From d348beaa63fa86d298e76d18c6699b14cbcc0f0f Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 17 May 2018 14:06:06 +0200 Subject: arm64: zynqmp: Show reset reason Read reset reason reg and show it in log and also save it as variable. Clearing reset reason when it is read to show only one status Signed-off-by: Michal Simek --- arch/arm/include/asm/arch-zynqmp/hardware.h | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/include/asm/arch-zynqmp/hardware.h b/arch/arm/include/asm/arch-zynqmp/hardware.h index acc6825..f317250 100644 --- a/arch/arm/include/asm/arch-zynqmp/hardware.h +++ b/arch/arm/include/asm/arch-zynqmp/hardware.h @@ -30,6 +30,14 @@ #define PS_MODE2 BIT(2) #define PS_MODE3 BIT(3) +#define RESET_REASON_DEBUG_SYS BIT(6) +#define RESET_REASON_SOFT BIT(5) +#define RESET_REASON_SRST BIT(4) +#define RESET_REASON_PSONLY BIT(3) +#define RESET_REASON_PMU BIT(2) +#define RESET_REASON_INTERNAL BIT(1) +#define RESET_REASON_EXTERNAL BIT(0) + struct crlapb_regs { u32 reserved0[36]; u32 cpu_r5_ctrl; /* 0x90 */ @@ -37,7 +45,9 @@ struct crlapb_regs { u32 timestamp_ref_ctrl; /* 0x128 */ u32 reserved2[53]; u32 boot_mode; /* 0x200 */ - u32 reserved3[14]; + u32 reserved3_0[7]; + u32 reset_reason; /* 0x220 */ + u32 reserved3_1[6]; u32 rst_lpd_top; /* 0x23C */ u32 reserved4[4]; u32 boot_pin_ctrl; /* 0x250 */ -- cgit v1.1 From 8dd94a8fe5d344208a170080a388f0cf4e9ae2ef Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 14 May 2018 15:33:22 +0200 Subject: arm64: zynqmp: Get rid of emulation platforms ZynqMP emulation platforms are no longer tested and supported that's why remove macros and code around. Signed-off-by: Michal Simek --- arch/arm/cpu/armv8/zynqmp/clk.c | 10 +--------- arch/arm/cpu/armv8/zynqmp/cpu.c | 4 ---- arch/arm/include/asm/arch-zynqmp/hardware.h | 2 -- 3 files changed, 1 insertion(+), 15 deletions(-) (limited to 'arch') diff --git a/arch/arm/cpu/armv8/zynqmp/clk.c b/arch/arm/cpu/armv8/zynqmp/clk.c index 13e1977..0593b63 100644 --- a/arch/arm/cpu/armv8/zynqmp/clk.c +++ b/arch/arm/cpu/armv8/zynqmp/clk.c @@ -16,10 +16,6 @@ unsigned long zynqmp_get_system_timer_freq(void) u32 ver = zynqmp_get_silicon_version(); switch (ver) { - case ZYNQMP_CSU_VERSION_VELOCE: - return 10000; - case ZYNQMP_CSU_VERSION_EP108: - return 4000000; case ZYNQMP_CSU_VERSION_QEMU: return 50000000; } @@ -40,11 +36,7 @@ int set_cpu_clk_info(void) { gd->cpu_clk = get_tbclk(); - /* Support Veloce to show at least 1MHz via bdi */ - if (gd->cpu_clk > 1000000) - gd->bd->bi_arm_freq = gd->cpu_clk / 1000000; - else - gd->bd->bi_arm_freq = 1; + gd->bd->bi_arm_freq = gd->cpu_clk / 1000000; gd->bd->bi_dsp_freq = 0; diff --git a/arch/arm/cpu/armv8/zynqmp/cpu.c b/arch/arm/cpu/armv8/zynqmp/cpu.c index 2748d65..792a3e1 100644 --- a/arch/arm/cpu/armv8/zynqmp/cpu.c +++ b/arch/arm/cpu/armv8/zynqmp/cpu.c @@ -135,12 +135,8 @@ unsigned int zynqmp_get_silicon_version(void) gd->cpu_clk = get_tbclk(); switch (gd->cpu_clk) { - case 0 ... 1000000: - return ZYNQMP_CSU_VERSION_VELOCE; case 50000000: return ZYNQMP_CSU_VERSION_QEMU; - case 4000000: - return ZYNQMP_CSU_VERSION_EP108; } return ZYNQMP_CSU_VERSION_SILICON; diff --git a/arch/arm/include/asm/arch-zynqmp/hardware.h b/arch/arm/include/asm/arch-zynqmp/hardware.h index f317250..8a505ed 100644 --- a/arch/arm/include/asm/arch-zynqmp/hardware.h +++ b/arch/arm/include/asm/arch-zynqmp/hardware.h @@ -130,8 +130,6 @@ struct apu_regs { /* Board version value */ #define ZYNQMP_CSU_BASEADDR 0xFFCA0000 #define ZYNQMP_CSU_VERSION_SILICON 0x0 -#define ZYNQMP_CSU_VERSION_EP108 0x1 -#define ZYNQMP_CSU_VERSION_VELOCE 0x2 #define ZYNQMP_CSU_VERSION_QEMU 0x3 #define ZYNQMP_CSU_VERSION_EMPTY_SHIFT 20 -- cgit v1.1 From 6189f76ae8fb3549349443d1d702d3d652d1244b Mon Sep 17 00:00:00 2001 From: Rajan Vaja Date: Wed, 7 Feb 2018 06:49:21 -0800 Subject: soc: zynqmp: Update required API version to 1.0 Existing EEMI version is to as 1.0 (available from xilinx v2018.1 version). Update required API version to match with EEMI API version. New PMUFW version is required for operations with programmable logic. Signed-off-by: Rajan Vaja Signed-off-by: Michal Simek --- arch/arm/cpu/armv8/zynqmp/cpu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/cpu/armv8/zynqmp/cpu.c b/arch/arm/cpu/armv8/zynqmp/cpu.c index 792a3e1..e122be5 100644 --- a/arch/arm/cpu/armv8/zynqmp/cpu.c +++ b/arch/arm/cpu/armv8/zynqmp/cpu.c @@ -173,8 +173,8 @@ int __maybe_unused invoke_smc(u32 pm_api_id, u32 arg0, u32 arg1, u32 arg2, #define ZYNQMP_SIP_SVC_GET_API_VERSION 0xC2000001 -#define ZYNQMP_PM_VERSION_MAJOR 0 -#define ZYNQMP_PM_VERSION_MINOR 3 +#define ZYNQMP_PM_VERSION_MAJOR 1 +#define ZYNQMP_PM_VERSION_MINOR 0 #define ZYNQMP_PM_VERSION_MAJOR_SHIFT 16 #define ZYNQMP_PM_VERSION_MINOR_MASK 0xFFFF -- cgit v1.1 From 7483969c550a931aa7b2441025a99c2fc878582e Mon Sep 17 00:00:00 2001 From: Ibai Erkiaga Date: Tue, 22 May 2018 17:03:04 +0100 Subject: arm: zynq: Add initial support for Avnet MiniZed Initial support for Avnet MiniZed board. Tested UART1 (serial console), QSPI(Flash), SDHCI1 (eMMC), USB. Signed-off-by: Ibai Erkiaga Signed-off-by: Michal Simek --- arch/arm/dts/Makefile | 1 + arch/arm/dts/zynq-minized.dts | 106 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 107 insertions(+) create mode 100644 arch/arm/dts/zynq-minized.dts (limited to 'arch') diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index a0349a8..197639c 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -130,6 +130,7 @@ dtb-$(CONFIG_ARCH_ZYNQ) += \ zynq-cc108.dtb \ zynq-cse-qspi-single.dtb \ zynq-microzed.dtb \ + zynq-minized.dtb \ zynq-picozed.dtb \ zynq-syzygy-hub.dtb \ zynq-topic-miami.dtb \ diff --git a/arch/arm/dts/zynq-minized.dts b/arch/arm/dts/zynq-minized.dts new file mode 100644 index 0000000..525921e --- /dev/null +++ b/arch/arm/dts/zynq-minized.dts @@ -0,0 +1,106 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * dts file for Avnet MiniZed board + * + * (C) Copyright 2017 - 2018, Xilinx, Inc. + * + * Ibai Erkiaga + */ + +/dts-v1/; +#include "zynq-7000.dtsi" + +/ { + model = "Avnet Zynq MiniZed Development Board"; + compatible = "avnet,minized", "xlnx,zynq-7000"; + + aliases { + serial0 = &uart1; + serial1 = &uart0; + spi0 = &qspi; + mmc0 = &sdhci0; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x20000000>; + }; + + chosen { + bootargs = ""; + stdout-path = "serial0:115200n8"; + }; + + usb_phy0: phy0 { + compatible = "usb-nop-xceiv"; + #phy-cells = <0>; + }; +}; + +&qspi { + status = "okay"; + is-dual = <0>; + num-cs = <1>; + flash@0 { + compatible = "micron,m25p128"; + reg = <0x0>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + spi-max-frequency = <50000000>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "boot"; + reg = <0x0 0xff0000>; + }; + + partition@270000 { + label = "kernel"; + reg = <0x270000 0xd80000>; + }; + + partition@ff0000 { + label = "bootenv"; + reg = <0xff0000 0x10000>; + }; + + partition@1000000 { + label = "spare"; + reg = <0x1000000 0x0>; + }; + }; + }; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&usb0 { + status = "okay"; + dr_mode = "host"; + usb-phy = <&usb_phy0>; + usb-reset = <&gpio0 7 0>; /* USB_RST_N-MIO7 */ +}; + +&sdhci1 { + status = "okay"; + non-removable; + bus-width = <4>; + max-frequency = <12000000>; + + #address-cells = <1>; + #size-cells = <0>; + mmccard: mmccard@0 { + compatible = "mmc-card"; + reg = <0>; + broken-hpi; + }; +}; -- cgit v1.1 From c66f5620e6a63b1912c017781c7eec6400dde292 Mon Sep 17 00:00:00 2001 From: Ezequiel Garcia Date: Fri, 12 Jan 2018 12:33:50 -0300 Subject: arm: zynq: Add support for Bitmain Antminer S9 control board This is control board on Bitmain Antminer S9. There are 3 board variables with 256MB, 512MB and 1024MB DDR. DDR memory is automatically detected with using get_with using get_ram_size(). Bitmain is using 16MB space for FPGA which is handled via reserved-memory. Also U-Boot is allocating 16B for storing bootcounts. Watchdog is started but never service in U-Boot. SPL MMC is working. SPL NAND is not working because it is not supported as of now. Signed-off-by: Ezequiel Garcia Signed-off-by: Michal Simek Signed-off-by: Michal Simek --- arch/arm/dts/bitmain-antminer-s9.dts | 78 ++++++++++++++++++++++++++++++++++++ 1 file changed, 78 insertions(+) create mode 100644 arch/arm/dts/bitmain-antminer-s9.dts (limited to 'arch') diff --git a/arch/arm/dts/bitmain-antminer-s9.dts b/arch/arm/dts/bitmain-antminer-s9.dts new file mode 100644 index 0000000..7362ad4 --- /dev/null +++ b/arch/arm/dts/bitmain-antminer-s9.dts @@ -0,0 +1,78 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Bitmain Antminer S9 board DTS + * + * Copyright (C) 2018 Michal Simek + * Copyright (C) 2018 VanguardiaSur + */ +/dts-v1/; +#include "zynq-7000.dtsi" + +/ { + model = "Bitmain Antminer S9 Board"; + compatible = "bitmain,antminer-s9", "xlnx,zynq-7000"; + + aliases { + ethernet0 = &gem0; + serial0 = &uart1; + mmc0 = &sdhci0; + gpio0 = &gpio0; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x40000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + bootcount@efffff0 { + reg = <0xefffff0 0x10>; + no-map; + }; + + fpga_space@f000000 { + reg = <0xf000000 0x1000000>; + no-map; + }; + }; + + chosen { + bootargs = "earlycon"; + stdout-path = "serial0:115200n8"; + }; +}; + +&clkc { + ps-clk-frequency = <33333333>; +}; + +&gem0 { + status = "okay"; + phy-mode = "rgmii-id"; + phy-handle = <ðernet_phy>; + + /* 0362/5e62 */ + ethernet_phy: ethernet-phy@1 { + reg = <1>; + }; +}; + +&sdhci0 { + u-boot,dm-pre-reloc; + status = "okay"; + disable-wp; +}; + +&uart1 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&watchdog0 { + reset-on-timeout; + timeout-sec = <200>; +}; -- cgit v1.1 From 3705dae164f807bf4fb993c5fe2eae3c86f95b9e Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 29 May 2018 14:45:13 +0200 Subject: arm64: zynqmp: Add ina226 to zcu104 revC Add new ina226 chip present on i2c bus which wasn't on revA. Signed-off-by: Michal Simek --- arch/arm/dts/zynqmp-zcu104-revC.dts | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/dts/zynqmp-zcu104-revC.dts b/arch/arm/dts/zynqmp-zcu104-revC.dts index 6e3cf5a..f3ab99a 100644 --- a/arch/arm/dts/zynqmp-zcu104-revC.dts +++ b/arch/arm/dts/zynqmp-zcu104-revC.dts @@ -145,10 +145,15 @@ }; }; - i2c@4 { + i2c@3 { #address-cells = <1>; #size-cells = <0>; - reg = <4>; + reg = <3>; + ina226@40 { /* u183 */ + compatible = "ti,ina226"; + reg = <0x40>; + shunt-resistor = <5000>; + }; }; i2c@5 { @@ -163,7 +168,7 @@ reg = <7>; }; - /* 3, 6 not connected */ + /* 4, 6 not connected */ }; }; -- cgit v1.1 From ce236dce56a826805bcf83f9ef2efcb7cf6eeb5b Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 29 May 2018 15:28:43 +0200 Subject: arm64: zynqmp: Fix address for tca6416_u97 chip on zcu104 I2c address is not 0x21 but 0x20. This patch is fixing both revA and revC boards. Signed-off-by: Michal Simek --- arch/arm/dts/zynqmp-zcu104-revA.dts | 4 ++-- arch/arm/dts/zynqmp-zcu104-revC.dts | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/arm/dts/zynqmp-zcu104-revA.dts b/arch/arm/dts/zynqmp-zcu104-revA.dts index a0e13d8..6a4b701 100644 --- a/arch/arm/dts/zynqmp-zcu104-revA.dts +++ b/arch/arm/dts/zynqmp-zcu104-revA.dts @@ -130,9 +130,9 @@ #address-cells = <1>; #size-cells = <0>; reg = <4>; - tca6416_u97: gpio@21 { + tca6416_u97: gpio@20 { compatible = "ti,tca6416"; - reg = <0x21>; + reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* diff --git a/arch/arm/dts/zynqmp-zcu104-revC.dts b/arch/arm/dts/zynqmp-zcu104-revC.dts index f3ab99a..fe742b8 100644 --- a/arch/arm/dts/zynqmp-zcu104-revC.dts +++ b/arch/arm/dts/zynqmp-zcu104-revC.dts @@ -74,9 +74,9 @@ status = "okay"; clock-frequency = <400000>; - tca6416_u97: gpio@21 { + tca6416_u97: gpio@20 { compatible = "ti,tca6416"; - reg = <0x21>; + reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* -- cgit v1.1 From 3e98a9c4167299cc3c6a608681a8b48e4a5bdefa Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 28 May 2018 15:19:02 +0200 Subject: arm64: zynqmp: Remove broken-cd from zcu100-revC Card detect bit was broken on revA and it is working fine with revC board that's why this property can be removed. Signed-off-by: Michal Simek --- arch/arm/dts/zynqmp-zcu100-revC.dts | 1 - 1 file changed, 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/dts/zynqmp-zcu100-revC.dts b/arch/arm/dts/zynqmp-zcu100-revC.dts index bcd9c39..c6aaa08 100644 --- a/arch/arm/dts/zynqmp-zcu100-revC.dts +++ b/arch/arm/dts/zynqmp-zcu100-revC.dts @@ -252,7 +252,6 @@ &sdhci0 { status = "okay"; no-1-8-v; - broken-cd; /* CD has to be enabled by default */ disable-wp; xlnx,mio_bank = <0>; }; -- cgit v1.1 From f0d56145d934b560ee9ef8ba6b4655a214696b75 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 4 Apr 2018 14:08:24 +0200 Subject: arm64: zynqmp: Disable WP on zcu111 On this board there is SD slot without WP connected. Signed-off-by: Michal Simek --- arch/arm/dts/zynqmp-zcu111-revA.dts | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/arm/dts/zynqmp-zcu111-revA.dts b/arch/arm/dts/zynqmp-zcu111-revA.dts index 4002d78..aa9055b 100644 --- a/arch/arm/dts/zynqmp-zcu111-revA.dts +++ b/arch/arm/dts/zynqmp-zcu111-revA.dts @@ -500,6 +500,7 @@ &sdhci1 { status = "okay"; no-1-8-v; + disable-wp; xlnx,mio_bank = <1>; }; -- cgit v1.1 From ecb4d7481e78af2f0ae67236f82f091b87112180 Mon Sep 17 00:00:00 2001 From: Rajan Vaja Date: Wed, 25 Apr 2018 05:34:04 -0700 Subject: arm64: zynqmp: Add TTC clocks PS clock(LPD_APB_CLK) is default clock for TTC. Add this clock entry in TTC nodes. Signed-off-by: Rajan Vaja Signed-off-by: Michal Simek --- arch/arm/dts/zynqmp-clk-ccf.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'arch') diff --git a/arch/arm/dts/zynqmp-clk-ccf.dtsi b/arch/arm/dts/zynqmp-clk-ccf.dtsi index b18d8d1..247a35f 100644 --- a/arch/arm/dts/zynqmp-clk-ccf.dtsi +++ b/arch/arm/dts/zynqmp-clk-ccf.dtsi @@ -248,6 +248,22 @@ clocks = <&clkc 59>, <&clkc 31>; }; +&ttc0 { + clocks = <&clkc 31>; +}; + +&ttc1 { + clocks = <&clkc 31>; +}; + +&ttc2 { + clocks = <&clkc 31>; +}; + +&ttc3 { + clocks = <&clkc 31>; +}; + &uart0 { clocks = <&clkc 56>, <&clkc 31>; }; -- cgit v1.1 From a18d09ea384fb66105fbfa24fd2d1288754b8f07 Mon Sep 17 00:00:00 2001 From: Siva Durga Prasad Paladugu Date: Thu, 31 May 2018 15:10:23 +0530 Subject: fpga: zynqmp: Add secure bitstream loading for ZynqMP This patch adds support for loading secure bitstreams on ZynqMP platforms. The secure bitstream images has to be generated using Xilinx bootgen tool. Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek --- arch/arm/include/asm/arch-zynqmp/sys_proto.h | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch') diff --git a/arch/arm/include/asm/arch-zynqmp/sys_proto.h b/arch/arm/include/asm/arch-zynqmp/sys_proto.h index 6056bc6..773b930 100644 --- a/arch/arm/include/asm/arch-zynqmp/sys_proto.h +++ b/arch/arm/include/asm/arch-zynqmp/sys_proto.h @@ -13,8 +13,14 @@ #define ZYNQMP_SIP_SVC_PM_SECURE_IMG_LOAD 0xC200002D #define KEY_PTR_LEN 32 +#define ZYNQMP_FPGA_BIT_AUTH_DDR 1 +#define ZYNQMP_FPGA_BIT_AUTH_OCM 2 +#define ZYNQMP_FPGA_BIT_ENC_USR_KEY 3 +#define ZYNQMP_FPGA_BIT_ENC_DEV_KEY 4 #define ZYNQMP_FPGA_BIT_NS 5 +#define ZYNQMP_FPGA_AUTH_DDR 1 + enum { IDCODE, VERSION, -- cgit v1.1