From 404339759ef5e0bcd4fa7768d1148b1ace2d2bb6 Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Mon, 27 Jan 2020 16:39:44 -0500 Subject: riscv: Remove unnecessary instruction The add instruction on risc-v can have any three sources and targets, so there is no need for an intermediate mov. Signed-off-by: Sean Anderson Reviewed-by: Rick Chen Reviewed-by: Bin Meng --- arch/riscv/cpu/start.S | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index f3dccdb..6b3ff99 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -359,9 +359,8 @@ relocate_secondary_harts: call_board_init_r: jal invalidate_icache_all jal flush_dcache_all - la t0, board_init_r - mv t4, t0 /* offset of board_init_r() */ - add t4, t4, t6 /* real address of board_init_r() */ + la t0, board_init_r /* offset of board_init_r() */ + add t4, t0, t6 /* real address of board_init_r() */ /* * setup parameters for board_init_r */ -- cgit v1.1