From 036f3f3379d56a4eb64d5154b47a8981a478fe3e Mon Sep 17 00:00:00 2001 From: Alison Wang Date: Thu, 12 Mar 2015 11:31:44 +0800 Subject: arm/ls102xa:Add support of conditional workaround implementation as per SoC ver For LS102xA, some workarounds are only used in VER1.0, so silicon version detection are added for QDS and TWR boards. Signed-off-by: Alison Wang Reviewed-by: York Sun --- arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch') diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h index 3a64afc..a8122c1 100644 --- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h @@ -17,6 +17,9 @@ #define SOC_VER_LS1021 0x11 #define SOC_VER_LS1022 0x12 +#define SOC_MAJOR_VER_1_0 0x1 +#define SOC_MAJOR_VER_2_0 0x2 + #define CCSR_BRR_OFFSET 0xe4 #define CCSR_SCRATCHRW1_OFFSET 0x200 -- cgit v1.1 From 98cb0efde8aaed200750e6d75fa8e5fc01dcd8f4 Mon Sep 17 00:00:00 2001 From: gaurav rana Date: Tue, 10 Mar 2015 14:08:50 +0530 Subject: Add bootscript support to esbc_validate. 1. Default environment will be used for secure boot flow which can't be edited or saved. 2. Command for secure boot is predefined in the default environment which will run on autoboot (and autoboot is the only option allowed in case of secure boot) and it looks like this: #define CONFIG_SECBOOT \ "setenv bs_hdraddr 0xe8e00000;" \ "esbc_validate $bs_hdraddr;" \ "source $img_addr;" \ "esbc_halt;" #endif 3. Boot Script can contain esbc_validate commands and bootm command. Uboot source command used in default secure boot command will run the bootscript. 4. Command esbc_halt added to ensure either bootm executes after validation of images or core should just spin. Signed-off-by: Ruchika Gupta Signed-off-by: Gaurav Rana Reviewed-by: York Sun --- arch/arm/include/asm/fsl_secure_boot.h | 25 +++++++++++++++++++++++++ arch/powerpc/include/asm/fsl_secure_boot.h | 19 +++++++++++++++++++ 2 files changed, 44 insertions(+) create mode 100644 arch/arm/include/asm/fsl_secure_boot.h (limited to 'arch') diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h new file mode 100644 index 0000000..f097c81 --- /dev/null +++ b/arch/arm/include/asm/fsl_secure_boot.h @@ -0,0 +1,25 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __FSL_SECURE_BOOT_H +#define __FSL_SECURE_BOOT_H + +#ifdef CONFIG_SECURE_BOOT +#ifndef CONFIG_FIT_SIGNATURE + +#define CONFIG_EXTRA_ENV \ + "setenv fdt_high 0xcfffffff;" \ + "setenv initrd_high 0xcfffffff;" \ + "setenv hwconfig \'fsl_ddr:ctlr_intlv=null,bank_intlv=null\';" + +/* The address needs to be modified according to NOR memory map */ +#define CONFIG_BOOTSCRIPT_HDR_ADDR 0x600a0000 + +#include +#endif +#endif + +#endif diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h index 49f6814..8f794ef 100644 --- a/arch/powerpc/include/asm/fsl_secure_boot.h +++ b/arch/powerpc/include/asm/fsl_secure_boot.h @@ -67,5 +67,24 @@ #define CONFIG_FSL_ISBC_KEY_EXT #endif +#ifndef CONFIG_FIT_SIGNATURE +/* The bootscript header address is different for B4860 because the NOR + * mapping is different on B4 due to reduced NOR size. + */ +#if defined(CONFIG_B4860QDS) +#define CONFIG_BOOTSCRIPT_HDR_ADDR 0xecc00000 +#elif defined(CONFIG_FSL_CORENET) +#define CONFIG_BOOTSCRIPT_HDR_ADDR 0xe8e00000 +#elif defined(CONFIG_BSC9132QDS) +#define CONFIG_BOOTSCRIPT_HDR_ADDR 0x88020000 +#elif defined(CONFIG_C29XPCIE) +#define CONFIG_BOOTSCRIPT_HDR_ADDR 0xec020000 +#else +#define CONFIG_BOOTSCRIPT_HDR_ADDR 0xee020000 +#endif + +#include +#endif + #endif #endif -- cgit v1.1 From d42bd3453af5dc81b6907be1b066b34ba0a0c979 Mon Sep 17 00:00:00 2001 From: Minghuan Lian Date: Thu, 12 Mar 2015 10:58:48 +0800 Subject: pci/layerscape: remove unnecessary pcie_layerscape.h The patch uses the common function name ft_pci_setup to replace ft_pcie_setup, then removes unnecessary pcie_layerscape.h because all the functions have been declared in common.h. Signed-off-by: Minghuan Lian Reviewed-by: Tom Rini Reviewed-by: York Sun --- arch/arm/include/asm/pcie_layerscape.h | 13 ------------- 1 file changed, 13 deletions(-) delete mode 100644 arch/arm/include/asm/pcie_layerscape.h (limited to 'arch') diff --git a/arch/arm/include/asm/pcie_layerscape.h b/arch/arm/include/asm/pcie_layerscape.h deleted file mode 100644 index fb08578..0000000 --- a/arch/arm/include/asm/pcie_layerscape.h +++ /dev/null @@ -1,13 +0,0 @@ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __PCIE_LAYERSCAPE_H_ -#define __PCIE_LAYERSCAPE_H_ - -void pci_init_board(void); -void ft_pcie_setup(void *blob, bd_t *bd); - -#endif -- cgit v1.1 From ae42eb035e86f2fca98adc5f5b59543a49797877 Mon Sep 17 00:00:00 2001 From: Zhao Qiang Date: Wed, 25 Mar 2015 17:02:59 +0800 Subject: QE/DeepSleep: add QE deepsleep support for mpc85xx Muram will power off during deepsleep, and the microcode of qe in muram will be lost, it should be reload when resume. Signed-off-by: Zhao Qiang Reviewed-by: York Sun --- arch/arm/include/asm/arch-ls102xa/config.h | 4 ---- 1 file changed, 4 deletions(-) (limited to 'arch') diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index 6561ce6..4dc528b 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -119,10 +119,6 @@ #define DCU_LAYER_MAX_NUM 16 -#define QE_MURAM_SIZE 0x6000UL -#define MAX_QE_RISC 1 -#define QE_NUM_OF_SNUM 28 - #define CONFIG_SYS_FSL_SRDS_1 #ifdef CONFIG_LS102XA -- cgit v1.1 From 422cb08acb1bc9a05ffa68ba68b4e196dad1af5b Mon Sep 17 00:00:00 2001 From: Bhupesh Sharma Date: Thu, 19 Mar 2015 09:20:43 -0700 Subject: armv8/fsl-lsch3: Add Freescale Debug Server driver The Debug Server driver is responsible for loading the Debug server FW on the Service Processor (Cortex-A5 core) on LS2085A like SoCs and then polling for the successful initialization of the same. TOP MEM HIDE is adjusted to ensure the space required by Debug Server FW is accounted for. MC uses the DDR area which is calculated as: MC DDR region start = Top of DDR - area reserved by Debug Server FW Signed-off-by: Bhupesh Sharma Reviewed-by: York Sun --- arch/arm/cpu/armv8/fsl-lsch3/cpu.c | 2 +- arch/arm/include/asm/arch-fsl-lsch3/config.h | 10 +++++++++- 2 files changed, 10 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c index 4997487..618fbc2 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c +++ b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include "cpu.h" #include "mp.h" @@ -384,7 +385,6 @@ int cpu_eth_init(bd_t *bis) return error; } - int arch_early_init_r(void) { int rv; diff --git a/arch/arm/include/asm/arch-fsl-lsch3/config.h b/arch/arm/include/asm/arch-fsl-lsch3/config.h index b140c1f..59d10bf 100644 --- a/arch/arm/include/asm/arch-fsl-lsch3/config.h +++ b/arch/arm/include/asm/arch-fsl-lsch3/config.h @@ -30,6 +30,15 @@ #define CONFIG_SYS_FSL_PMU_CLTBENR (CONFIG_SYS_FSL_PMU_ADDR + \ 0x18A0) +/* SP (Cortex-A5) related */ +#define CONFIG_SYS_FSL_SP_ADDR (CONFIG_SYS_IMMR + 0x00F00000) +#define CONFIG_SYS_FSL_SP_VSG_GIC_ADDR (CONFIG_SYS_FSL_SP_ADDR) +#define CONFIG_SYS_FSL_SP_VSG_GIC_VIGR1 (CONFIG_SYS_FSL_SP_ADDR) +#define CONFIG_SYS_FSL_SP_VSG_GIC_VIGR2 \ + (CONFIG_SYS_FSL_SP_ADDR + 0x0008) +#define CONFIG_SYS_FSL_SP_LOOPBACK_DUART \ + (CONFIG_SYS_FSL_SP_ADDR + 0x1000) + #define CONFIG_SYS_FSL_DCSR_DDR_ADDR 0x70012c000ULL #define CONFIG_SYS_FSL_DCSR_DDR2_ADDR 0x70012d000ULL #define CONFIG_SYS_FSL_DCSR_DDR3_ADDR 0x700132000ULL @@ -88,7 +97,6 @@ #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS2_DDR_BLOCK1_SIZE #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 - /* IFC */ #define CONFIG_SYS_FSL_IFC_LE -- cgit v1.1 From b7f57ac0d8a7ac16c893170b9b9a72bda138eb23 Mon Sep 17 00:00:00 2001 From: Bhupesh Sharma Date: Thu, 19 Mar 2015 09:20:44 -0700 Subject: fsl-ch3/README: Add description for NOR flash layout (firmware images) This patch adds description for NOR flash layout (firmware images) in the README file for LS2085A platforms. Signed-off-by: Bhupesh Sharma Reviewed-by: York Sun --- arch/arm/cpu/armv8/fsl-lsch3/README | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) (limited to 'arch') diff --git a/arch/arm/cpu/armv8/fsl-lsch3/README b/arch/arm/cpu/armv8/fsl-lsch3/README index cc47466..99fc39a 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/README +++ b/arch/arm/cpu/armv8/fsl-lsch3/README @@ -8,3 +8,28 @@ Freescale LayerScape with Chassis Generation 3 This architecture supports Freescale ARMv8 SoCs with Chassis generation 3, for example LS2085A. + +Flash Layout +============ +A typical layout of various images (including Linux and other firmware images) +is shown below considering a 32MB NOR flash device: + + ------------------------- + | linux | + ------------------------- ----> 0x0120_0000 + | Debug Server | + ------------------------- ----> 0x00C0_0000 + | AIOP SW | + ------------------------- ----> 0x0070_0000 + | MC FW | + ------------------------- ----> 0x006C_0000 + | MC Data Path Layout | + ------------------------- ----> 0x0020_0000 + | BootLoader | + ------------------------- ----> 0x0000_1000 + | PBI | + ------------------------- ----> 0x0000_0080 + | RCW | + ------------------------- ----> 0x0000_0000 + + 32-MB NOR flash layout -- cgit v1.1 From a2a55e518f81900ab1538656e5df8d2759ccb1fb Mon Sep 17 00:00:00 2001 From: Prabhakar Kushwaha Date: Thu, 19 Mar 2015 09:20:45 -0700 Subject: driver/fsl-mc: Add support of MC Flibs Freescale's Layerscape Management Complex (MC) provide support various objects like DPRC, DPNI, DPBP and DPIO. Where: DPRC: Place holdes for other MC objectes like DPNI, DPBP, DPIO DPBP: Management of buffer pool DPIO: Used for used to QBMan portal DPNI: Represents standard network interface These objects are used for DPAA ethernet drivers. Signed-off-by: J. German Rivera Signed-off-by: Lijun Pan Signed-off-by: Stuart Yoder Signed-off-by: Geoff Thorpe Signed-off-by: Haiying Wang Signed-off-by: Cristian Sovaiala Signed-off-by: pankaj chauhan Signed-off-by: Prabhakar Kushwaha Reviewed-by: York Sun --- arch/arm/cpu/armv8/fsl-lsch3/cpu.c | 2 +- arch/arm/include/asm/arch-fsl-lsch3/config.h | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c index 618fbc2..94fd147 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c +++ b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c @@ -380,7 +380,7 @@ int cpu_eth_init(bd_t *bis) int error = 0; #ifdef CONFIG_FSL_MC_ENET - error = mc_init(bis); + error = fsl_mc_ldpaa_init(bis); #endif return error; } diff --git a/arch/arm/include/asm/arch-fsl-lsch3/config.h b/arch/arm/include/asm/arch-fsl-lsch3/config.h index 59d10bf..0217582 100644 --- a/arch/arm/include/asm/arch-fsl-lsch3/config.h +++ b/arch/arm/include/asm/arch-fsl-lsch3/config.h @@ -8,6 +8,8 @@ #define _ASM_ARMV8_FSL_LSCH3_CONFIG_ #include + +#define CONFIG_SYS_PAGE_SIZE 0x10000 #define CONFIG_MP #define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */ /* Link Definitions */ -- cgit v1.1 From c517771ae745dbba59112b8d311e41d37c0fc032 Mon Sep 17 00:00:00 2001 From: Prabhakar Kushwaha Date: Thu, 19 Mar 2015 09:20:46 -0700 Subject: driver/ldpaa_eth: Add LDPAA Ethernet driver LDPAA Ethernet driver is a freescale's new ethernet driver based on Layerscape architecture. Every ethernet driver controls on DPNI object. Where all DPNIs share one common DPBP and DPIO object to support Rx and Tx flows. Signed-off-by: Prabhakar Kushwaha CC: Cristian Sovaiala CC: Bogdan Hamciuc CC: J. German Rivera [York Sun: s/NetReceive/net_process_received_packet] Reviewed-by: York Sun --- arch/arm/include/asm/arch-fsl-lsch3/config.h | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch') diff --git a/arch/arm/include/asm/arch-fsl-lsch3/config.h b/arch/arm/include/asm/arch-fsl-lsch3/config.h index 0217582..1d2a7fa 100644 --- a/arch/arm/include/asm/arch-fsl-lsch3/config.h +++ b/arch/arm/include/asm/arch-fsl-lsch3/config.h @@ -10,6 +10,12 @@ #include #define CONFIG_SYS_PAGE_SIZE 0x10000 + +#ifndef L1_CACHE_BYTES +#define L1_CACHE_SHIFT 6 +#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) +#endif + #define CONFIG_MP #define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */ /* Link Definitions */ -- cgit v1.1 From 060ef094600373ea2b25111006edc56c072d9bd7 Mon Sep 17 00:00:00 2001 From: York Sun Date: Fri, 20 Mar 2015 19:28:05 -0700 Subject: armv8/fsl-lsch3: Implement workaround for erratum A008585 Generic Timer may contain an erroneous value. The workaround is to read it twice until getting the same value. Signed-off-by: York Sun --- arch/arm/cpu/armv8/generic_timer.c | 11 +++++++++++ arch/arm/include/asm/arch-fsl-lsch3/config.h | 1 + 2 files changed, 12 insertions(+) (limited to 'arch') diff --git a/arch/arm/cpu/armv8/generic_timer.c b/arch/arm/cpu/armv8/generic_timer.c index 223b95e..8e60bae 100644 --- a/arch/arm/cpu/armv8/generic_timer.c +++ b/arch/arm/cpu/armv8/generic_timer.c @@ -25,7 +25,18 @@ unsigned long get_tbclk(void) unsigned long timer_read_counter(void) { unsigned long cntpct; +#ifdef CONFIG_SYS_FSL_ERRATUM_A008585 + /* This erratum number needs to be confirmed to match ARM document */ + unsigned long temp; +#endif isb(); asm volatile("mrs %0, cntpct_el0" : "=r" (cntpct)); +#ifdef CONFIG_SYS_FSL_ERRATUM_A008585 + asm volatile("mrs %0, cntpct_el0" : "=r" (temp)); + while (temp != cntpct) { + asm volatile("mrs %0, cntpct_el0" : "=r" (cntpct)); + asm volatile("mrs %0, cntpct_el0" : "=r" (temp)); + } +#endif return cntpct; } diff --git a/arch/arm/include/asm/arch-fsl-lsch3/config.h b/arch/arm/include/asm/arch-fsl-lsch3/config.h index 1d2a7fa..2d461d9 100644 --- a/arch/arm/include/asm/arch-fsl-lsch3/config.h +++ b/arch/arm/include/asm/arch-fsl-lsch3/config.h @@ -120,6 +120,7 @@ #ifdef CONFIG_LS2085A #define CONFIG_SYS_FSL_ERRATUM_A008336 #define CONFIG_SYS_FSL_ERRATUM_A008514 +#define CONFIG_SYS_FSL_ERRATUM_A008585 #endif #endif /* _ASM_ARMV8_FSL_LSCH3_CONFIG_ */ -- cgit v1.1 From f3f8c564a1cb745cef41c98dd2c29e3aad37dc4c Mon Sep 17 00:00:00 2001 From: Prabhakar Kushwaha Date: Fri, 20 Mar 2015 19:28:06 -0700 Subject: armv8/ls2085a: Update common header file ls2085a_common.h contains hard-coded information for NOR/NAND flash, I2C, DDR, etc. These are platform specific. Move them out of common header file and placed into respective board header files. Move TEXTBASE to 1MB offset to fit NOR flash with up to 1MB sector size. Enable command auto complete. Update prompt symbol. Set fdt_high to 0xa0000000 because Linux requires that the fdt be 8-byte aligned and below 512 MiB. Besides ensuring compliance with the 512 MiB limit, this avoids problems with the dtb being misaligned within the FIT image. Change the MC FW, MC DPL and Debug server NOR addresses in compliance with the NOR flash layouts for 128MB flash. Add PCIe macros. Enable "loadb" command. Disable debug server. Enable workaround for erratum A008511. Stop reset on panic for postmortem debugging. Signed-off-by: Prabhakar Kushwaha Signed-off-by: Scott Wood Signed-off-by: Bhupesh Sharma Signed-off-by: Minghuan Lian Signed-off-by: York Sun --- arch/arm/include/asm/arch-fsl-lsch3/config.h | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'arch') diff --git a/arch/arm/include/asm/arch-fsl-lsch3/config.h b/arch/arm/include/asm/arch-fsl-lsch3/config.h index 2d461d9..518e59c 100644 --- a/arch/arm/include/asm/arch-fsl-lsch3/config.h +++ b/arch/arm/include/asm/arch-fsl-lsch3/config.h @@ -108,6 +108,16 @@ /* IFC */ #define CONFIG_SYS_FSL_IFC_LE +/* PCIe */ +#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000) +#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000) +#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000) +#define CONFIG_SYS_PCIE4_ADDR (CONFIG_SYS_IMMR + 0x2700000) +#define CONFIG_SYS_PCIE1_PHYS_ADDR 0x1000000000ULL +#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x1200000000ULL +#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x1400000000ULL +#define CONFIG_SYS_PCIE4_PHYS_ADDR 0x1600000000ULL + #ifdef CONFIG_LS2085A #define CONFIG_MAX_CPUS 16 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 @@ -119,6 +129,7 @@ #ifdef CONFIG_LS2085A #define CONFIG_SYS_FSL_ERRATUM_A008336 +#define CONFIG_SYS_FSL_ERRATUM_A008511 #define CONFIG_SYS_FSL_ERRATUM_A008514 #define CONFIG_SYS_FSL_ERRATUM_A008585 #endif -- cgit v1.1 From 19f9175027b14f11b5a30df17ce76fb6f64dc724 Mon Sep 17 00:00:00 2001 From: York Sun Date: Fri, 20 Mar 2015 19:28:07 -0700 Subject: armv8/fsl-lsch3: Fix platform clock calculation Platform clock is half of platform PLL. There is an additional divisor in place. Clean up code copied from powerpc. Signed-off-by: York Sun --- arch/arm/cpu/armv8/fsl-lsch3/speed.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/arm/cpu/armv8/fsl-lsch3/speed.c b/arch/arm/cpu/armv8/fsl-lsch3/speed.c index 72cd999..2b140cd 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/speed.c +++ b/arch/arm/cpu/armv8/fsl-lsch3/speed.c @@ -86,6 +86,8 @@ void get_sys_info(struct sys_info *sys_info) sys_info->freq_systembus *= (in_le32(&gur->rcwsr[0]) >> FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_SHIFT) & FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_MASK; + /* Platform clock is half of platform PLL */ + sys_info->freq_systembus /= 2; sys_info->freq_ddrbus *= (in_le32(&gur->rcwsr[0]) >> FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT) & FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK; @@ -102,10 +104,7 @@ void get_sys_info(struct sys_info *sys_info) offsetof(struct ccsr_clk_cluster_group, pllngsr[i%3].gsr)); ratio[i] = (in_le32(offset) >> 1) & 0x3f; - if (ratio[i] > 4) - freq_c_pll[i] = sysclk * ratio[i]; - else - freq_c_pll[i] = sys_info->freq_systembus * ratio[i]; + freq_c_pll[i] = sysclk * ratio[i]; } for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) { -- cgit v1.1 From 207774b213caa3c72ebd6c9f6d1e4a3a666938b7 Mon Sep 17 00:00:00 2001 From: York Sun Date: Fri, 20 Mar 2015 19:28:08 -0700 Subject: armv8/ls2085a: Fix generic timer clock source The timer clock is system clock divided by 4, not fixed 12MHz. This is common to the SoC, not board specific. Primary core is fixed when u-boot still runs in board_f. Secondary cores are fixed by reading a variable set by u-boot. Signed-off-by: York Sun CC: Mark Rutland --- arch/arm/cpu/armv8/fsl-lsch3/cpu.c | 24 ++++++++++++++++++++++++ arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S | 6 ++++++ arch/arm/cpu/armv8/fsl-lsch3/mp.c | 7 +++++++ arch/arm/cpu/armv8/fsl-lsch3/mp.h | 1 + 4 files changed, 38 insertions(+) (limited to 'arch') diff --git a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c index 94fd147..e985181 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c +++ b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c @@ -395,3 +395,27 @@ int arch_early_init_r(void) return 0; } + +int timer_init(void) +{ + u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR; + u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR; +#ifdef COUNTER_FREQUENCY_REAL + unsigned long cntfrq = COUNTER_FREQUENCY_REAL; + + /* Update with accurate clock frequency */ + asm volatile("msr cntfrq_el0, %0" : : "r" (cntfrq) : "memory"); +#endif + + /* Enable timebase for all clusters. + * It is safe to do so even some clusters are not enabled. + */ + out_le32(cltbenr, 0xf); + + /* Enable clock for timer + * This is a global setting. + */ + out_le32(cntcr, 0x1); + + return 0; +} diff --git a/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S b/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S index 886576e..53bdb44 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S +++ b/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S @@ -224,6 +224,9 @@ ENTRY(secondary_boot_func) /* physical address of this cpus spin table element */ add x11, x1, x0 + ldr x0, =__real_cntfrq + ldr x0, [x0] + msr cntfrq_el0, x0 /* set with real frequency */ str x9, [x11, #16] /* LPID */ mov x4, #1 str x4, [x11, #8] /* STATUS */ @@ -275,6 +278,9 @@ ENDPROC(secondary_switch_to_el1) /* 64 bit alignment for elements accessed as data */ .align 4 + .global __real_cntfrq +__real_cntfrq: + .quad COUNTER_FREQUENCY .globl __secondary_boot_code_size .type __secondary_boot_code_size, %object /* Secondary Boot Code ends here */ diff --git a/arch/arm/cpu/armv8/fsl-lsch3/mp.c b/arch/arm/cpu/armv8/fsl-lsch3/mp.c index ce9c0c1..da7853a 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/mp.c +++ b/arch/arm/cpu/armv8/fsl-lsch3/mp.c @@ -31,6 +31,13 @@ int fsl_lsch3_wake_seconday_cores(void) int i, timeout = 10; u64 *table = get_spin_tbl_addr(); +#ifdef COUNTER_FREQUENCY_REAL + /* update for secondary cores */ + __real_cntfrq = COUNTER_FREQUENCY_REAL; + flush_dcache_range((unsigned long)&__real_cntfrq, + (unsigned long)&__real_cntfrq + 8); +#endif + cores = cpu_mask(); /* Clear spin table so that secondary processors * observe the correct value after waking up from wfe. diff --git a/arch/arm/cpu/armv8/fsl-lsch3/mp.h b/arch/arm/cpu/armv8/fsl-lsch3/mp.h index 66144d6..c985d6a 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/mp.h +++ b/arch/arm/cpu/armv8/fsl-lsch3/mp.h @@ -26,6 +26,7 @@ #define id_to_core(x) ((x & 3) | (x >> 6)) #ifndef __ASSEMBLY__ extern u64 __spin_table[]; +extern u64 __real_cntfrq; extern u64 *secondary_boot_code; extern size_t __secondary_boot_code_size; int fsl_lsch3_wake_seconday_cores(void); -- cgit v1.1 From 05d2e21be5e48185cf81389d12b1b8d0eceeae83 Mon Sep 17 00:00:00 2001 From: pankaj chauhan Date: Fri, 20 Mar 2015 19:28:09 -0700 Subject: armv8/ls2085a: Add support for reset request Add support for reset_cpu() by asserting RESET_REQ_B. Signed-off-by: pankaj chauhan Signed-off-by: York Sun --- arch/arm/cpu/armv8/fsl-lsch3/cpu.c | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'arch') diff --git a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c index e985181..0e5aa5c 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c +++ b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c @@ -419,3 +419,14 @@ int timer_init(void) return 0; } + +void reset_cpu(ulong addr) +{ + u32 __iomem *rstcr = (u32 *)CONFIG_SYS_FSL_RST_ADDR; + u32 val; + + /* Raise RESET_REQ_B */ + val = in_le32(rstcr); + val |= 0x02; + out_le32(rstcr, val); +} -- cgit v1.1 From 07c6600068da31d0f7c67ac3eb92dfc4270f4c07 Mon Sep 17 00:00:00 2001 From: Scott Wood Date: Fri, 20 Mar 2015 19:28:10 -0700 Subject: armv8/fsl-lsch3: Set nodes in DVM domain This is required for TLB invalidation broadcasts to work. Signed-off-by: Scott Wood Signed-off-by: York Sun --- arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S | 9 +++++++++ arch/arm/include/asm/arch-fsl-lsch3/config.h | 6 ++++++ 2 files changed, 15 insertions(+) (limited to 'arch') diff --git a/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S b/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S index 53bdb44..018c617 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S +++ b/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S @@ -15,6 +15,15 @@ ENTRY(lowlevel_init) mov x29, lr /* Save LR */ + /* Add fully-coherent masters to DVM domain */ + ldr x1, =CCI_MN_BASE + ldr x2, [x1, #CCI_MN_RNF_NODEID_LIST] + str x2, [x1, #CCI_MN_DVM_DOMAIN_CTL_SET] +1: ldr x3, [x1, #CCI_MN_DVM_DOMAIN_CTL_SET] + mvn x0, x3 + tst x0, x3 /* Wait for domain addition to complete */ + b.ne 1b + /* Set the SMMU page size in the sACR register */ ldr x1, =SMMU_BASE ldr w0, [x1, #0x10] diff --git a/arch/arm/include/asm/arch-fsl-lsch3/config.h b/arch/arm/include/asm/arch-fsl-lsch3/config.h index 518e59c..9121452 100644 --- a/arch/arm/include/asm/arch-fsl-lsch3/config.h +++ b/arch/arm/include/asm/arch-fsl-lsch3/config.h @@ -118,6 +118,12 @@ #define CONFIG_SYS_PCIE3_PHYS_ADDR 0x1400000000ULL #define CONFIG_SYS_PCIE4_PHYS_ADDR 0x1600000000ULL +/* Cache Coherent Interconnect */ +#define CCI_MN_BASE 0x04000000 +#define CCI_MN_RNF_NODEID_LIST 0x180 +#define CCI_MN_DVM_DOMAIN_CTL 0x200 +#define CCI_MN_DVM_DOMAIN_CTL_SET 0x210 + #ifdef CONFIG_LS2085A #define CONFIG_MAX_CPUS 16 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 -- cgit v1.1 From 12eaf31c0709840d6448d45ebfaecccadc34afa3 Mon Sep 17 00:00:00 2001 From: York Sun Date: Fri, 20 Mar 2015 19:28:11 -0700 Subject: armv8/fsl-lsch3: Update early MMU table During booting, IFC is mapped to low region. After booting up, IFC is remapped to high region for larger space. The environmental variables are also stored at high region. In order to read the variables during booting, a virtual mapping is required. Cache was enabled for entire IFC space before. Actually the first two entries are big enough (4MB) to cover the boot code and environmental variables. Remove extra entries. Move OCRAM entry out of ifdef. Signed-off-by: York Sun --- arch/arm/cpu/armv8/fsl-lsch3/cpu.c | 56 ++++++++++++++++++++++++++------------ 1 file changed, 39 insertions(+), 17 deletions(-) (limited to 'arch') diff --git a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c index 0e5aa5c..595dbd1 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c +++ b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c @@ -25,8 +25,9 @@ DECLARE_GLOBAL_DATA_PTR; * levels of translation tables here to cover 40-bit address space. * We use 4KB granule size, with 40 bits physical address, T0SZ=24 * Level 0 IA[39], table address @0 - * Level 1 IA[31:30], table address @01000, 0x2000 - * Level 2 IA[29:21], table address @0x3000 + * Level 1 IA[31:30], table address @0x1000, 0x2000 + * Level 2 IA[29:21], table address @0x3000, 0x4000 + * Address above 0x5000 is free for other purpose. */ #define SECTION_SHIFT_L0 39UL @@ -61,12 +62,12 @@ static inline void early_mmu_setup(void) { int el; u64 i; - u64 section_l1t0, section_l1t1, section_l2; + u64 section_l1t0, section_l1t1, section_l2t0, section_l2t1; u64 *level0_table = (u64 *)CONFIG_SYS_FSL_OCRAM_BASE; u64 *level1_table_0 = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x1000); u64 *level1_table_1 = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x2000); - u64 *level2_table = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x3000); - + u64 *level2_table_0 = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x3000); + u64 *level2_table_1 = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x4000); level0_table[0] = (u64)level1_table_0 | PMD_TYPE_TABLE; @@ -80,21 +81,25 @@ static inline void early_mmu_setup(void) */ section_l1t0 = 0; section_l1t1 = BLOCK_SIZE_L0; - section_l2 = 0; + section_l2t0 = 0; + section_l2t1 = CONFIG_SYS_FLASH_BASE; for (i = 0; i < 512; i++) { set_pgtable_section(level1_table_0, i, section_l1t0, MT_DEVICE_NGNRNE); set_pgtable_section(level1_table_1, i, section_l1t1, MT_NORMAL); - set_pgtable_section(level2_table, i, section_l2, + set_pgtable_section(level2_table_0, i, section_l2t0, + MT_DEVICE_NGNRNE); + set_pgtable_section(level2_table_1, i, section_l2t1, MT_DEVICE_NGNRNE); section_l1t0 += BLOCK_SIZE_L1; section_l1t1 += BLOCK_SIZE_L1; - section_l2 += BLOCK_SIZE_L2; + section_l2t0 += BLOCK_SIZE_L2; + section_l2t1 += BLOCK_SIZE_L2; } level1_table_0[0] = - (u64)level2_table | PMD_TYPE_TABLE; + (u64)level2_table_0 | PMD_TYPE_TABLE; level1_table_0[1] = 0x40000000 | PMD_SECT_AF | PMD_TYPE_SECT | PMD_ATTRINDX(MT_DEVICE_NGNRNE); @@ -105,17 +110,34 @@ static inline void early_mmu_setup(void) 0xc0000000 | PMD_SECT_AF | PMD_TYPE_SECT | PMD_ATTRINDX(MT_NORMAL); - /* Rewrite table to enable cache */ - set_pgtable_section(level2_table, + /* Rewerite table to enable cache for OCRAM */ + set_pgtable_section(level2_table_0, CONFIG_SYS_FSL_OCRAM_BASE >> SECTION_SHIFT_L2, CONFIG_SYS_FSL_OCRAM_BASE, MT_NORMAL); - for (i = CONFIG_SYS_IFC_BASE >> SECTION_SHIFT_L2; - i < (CONFIG_SYS_IFC_BASE + CONFIG_SYS_IFC_SIZE) - >> SECTION_SHIFT_L2; i++) { - section_l2 = i << SECTION_SHIFT_L2; - set_pgtable_section(level2_table, i, - section_l2, MT_NORMAL); + +#if defined(CONFIG_SYS_NOR0_CSPR_EARLY) && defined(CONFIG_SYS_NOR_AMASK_EARLY) + /* Rewrite table to enable cache for two entries (4MB) */ + section_l2t1 = CONFIG_SYS_IFC_BASE; + set_pgtable_section(level2_table_0, + section_l2t1 >> SECTION_SHIFT_L2, + section_l2t1, + MT_NORMAL); + section_l2t1 += BLOCK_SIZE_L2; + set_pgtable_section(level2_table_0, + section_l2t1 >> SECTION_SHIFT_L2, + section_l2t1, + MT_NORMAL); +#endif + + /* Create a mapping for 256MB IFC region to final flash location */ + level1_table_0[CONFIG_SYS_FLASH_BASE >> SECTION_SHIFT_L1] = + (u64)level2_table_1 | PMD_TYPE_TABLE; + section_l2t1 = CONFIG_SYS_IFC_BASE; + for (i = 0; i < 0x10000000 >> SECTION_SHIFT_L2; i++) { + set_pgtable_section(level2_table_1, i, + section_l2t1, MT_DEVICE_NGNRNE); + section_l2t1 += BLOCK_SIZE_L2; } el = current_el(); -- cgit v1.1 From b991b981e04eddb30c47fe97fbcfb05099b4fd88 Mon Sep 17 00:00:00 2001 From: Scott Wood Date: Fri, 20 Mar 2015 19:28:12 -0700 Subject: fsl-lsch3: Introduce place for common early SoC init Signed-off-by: Scott Wood Signed-off-by: York Sun --- arch/arm/cpu/armv8/fsl-lsch3/Makefile | 1 + arch/arm/cpu/armv8/fsl-lsch3/soc.c | 14 ++++++++++++++ arch/arm/include/asm/arch-fsl-lsch3/soc.h | 8 ++++++++ 3 files changed, 23 insertions(+) create mode 100644 arch/arm/cpu/armv8/fsl-lsch3/soc.c create mode 100644 arch/arm/include/asm/arch-fsl-lsch3/soc.h (limited to 'arch') diff --git a/arch/arm/cpu/armv8/fsl-lsch3/Makefile b/arch/arm/cpu/armv8/fsl-lsch3/Makefile index f920eeb..6542590 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/Makefile +++ b/arch/arm/cpu/armv8/fsl-lsch3/Makefile @@ -6,6 +6,7 @@ obj-y += cpu.o obj-y += lowlevel.o +obj-y += soc.o obj-y += speed.o obj-$(CONFIG_MP) += mp.o obj-$(CONFIG_OF_LIBFDT) += fdt.o diff --git a/arch/arm/cpu/armv8/fsl-lsch3/soc.c b/arch/arm/cpu/armv8/fsl-lsch3/soc.c new file mode 100644 index 0000000..242a865 --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-lsch3/soc.c @@ -0,0 +1,14 @@ +/* + * Copyright 2015 Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +void fsl_lsch3_early_init_f(void) +{ + init_early_memctl_regs(); /* tighten IFC timing */ +} diff --git a/arch/arm/include/asm/arch-fsl-lsch3/soc.h b/arch/arm/include/asm/arch-fsl-lsch3/soc.h new file mode 100644 index 0000000..16b723d --- /dev/null +++ b/arch/arm/include/asm/arch-fsl-lsch3/soc.h @@ -0,0 +1,8 @@ +/* + * Copyright 2015 Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +void fsl_lsch3_early_init_f(void); + -- cgit v1.1 From d746fef40653d17a64ff81a8ff57c55d122d8d5e Mon Sep 17 00:00:00 2001 From: Scott Wood Date: Fri, 20 Mar 2015 19:28:13 -0700 Subject: armv8/ls2085a: Add workaround for USB erratum A-008751 Without this "USB may not work" according to the erratum text, though I did not notice a problem without it. Signed-off-by: Scott Wood Signed-off-by: York Sun --- arch/arm/cpu/armv8/fsl-lsch3/soc.c | 11 +++++++++++ arch/arm/include/asm/arch-fsl-lsch3/config.h | 5 +++++ 2 files changed, 16 insertions(+) (limited to 'arch') diff --git a/arch/arm/cpu/armv8/fsl-lsch3/soc.c b/arch/arm/cpu/armv8/fsl-lsch3/soc.c index 242a865..17700ef 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/soc.c +++ b/arch/arm/cpu/armv8/fsl-lsch3/soc.c @@ -7,8 +7,19 @@ #include #include #include +#include + +static void erratum_a008751(void) +{ +#ifdef CONFIG_SYS_FSL_ERRATUM_A008751 + u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE; + + writel(0x27672b2a, scfg + SCFG_USB3PRM1CR / 4); +#endif +} void fsl_lsch3_early_init_f(void) { + erratum_a008751(); init_early_memctl_regs(); /* tighten IFC timing */ } diff --git a/arch/arm/include/asm/arch-fsl-lsch3/config.h b/arch/arm/include/asm/arch-fsl-lsch3/config.h index 9121452..a81e3ed 100644 --- a/arch/arm/include/asm/arch-fsl-lsch3/config.h +++ b/arch/arm/include/asm/arch-fsl-lsch3/config.h @@ -124,6 +124,10 @@ #define CCI_MN_DVM_DOMAIN_CTL 0x200 #define CCI_MN_DVM_DOMAIN_CTL_SET 0x210 +/* Supplemental Configuration */ +#define SCFG_BASE 0x01fc0000 +#define SCFG_USB3PRM1CR 0x000 + #ifdef CONFIG_LS2085A #define CONFIG_MAX_CPUS 16 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 @@ -138,6 +142,7 @@ #define CONFIG_SYS_FSL_ERRATUM_A008511 #define CONFIG_SYS_FSL_ERRATUM_A008514 #define CONFIG_SYS_FSL_ERRATUM_A008585 +#define CONFIG_SYS_FSL_ERRATUM_A008751 #endif #endif /* _ASM_ARMV8_FSL_LSCH3_CONFIG_ */ -- cgit v1.1 From 1e52835a89d8ba8a420ab8aaf947994bfe157b34 Mon Sep 17 00:00:00 2001 From: Scott Wood Date: Fri, 20 Mar 2015 19:28:14 -0700 Subject: armv8/fsl-lsch3: Use correct compatible for serial clock fixup The serial nodes in the fsl-lsch3 device trees have compatible = "fsl,ns16550", "ns16550a" -- so don't look for "ns16550". Signed-off-by: Scott Wood Signed-off-by: York Sun --- arch/arm/cpu/armv8/fsl-lsch3/fdt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/cpu/armv8/fsl-lsch3/fdt.c b/arch/arm/cpu/armv8/fsl-lsch3/fdt.c index 7eb9b6a..42c5b58 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/fdt.c +++ b/arch/arm/cpu/armv8/fsl-lsch3/fdt.c @@ -62,7 +62,7 @@ void ft_cpu_setup(void *blob, bd_t *bd) #endif #ifdef CONFIG_SYS_NS16550 - do_fixup_by_compat_u32(blob, "ns16550", + do_fixup_by_compat_u32(blob, "fsl,ns16550", "clock-frequency", CONFIG_SYS_NS16550_CLK, 1); #endif } -- cgit v1.1 From 31d34c6c4b4470b4cd2094693259fb48ec51e652 Mon Sep 17 00:00:00 2001 From: Minghuan Lian Date: Fri, 20 Mar 2015 19:28:16 -0700 Subject: armv8: Add SerDes framework for Layerscape Architecture Add support of SerDes framework for Layerscape Architecture. - Add support of 2 SerDes block - Add SerDes protocol parsing and detection - Create table of SerDes protocol supported by LS2085A Signed-off-by: Prabhakar Kushwaha Signed-off-by: Minghuan Lian Reviewed-by: York Sun --- arch/arm/cpu/armv8/fsl-lsch3/Makefile | 1 + arch/arm/cpu/armv8/fsl-lsch3/cpu.c | 4 + arch/arm/cpu/armv8/fsl-lsch3/fsl_lsch3_serdes.c | 110 ++++++++++++++++++++ arch/arm/cpu/armv8/fsl-lsch3/ls2085a_serdes.c | 117 ++++++++++++++++++++++ arch/arm/include/asm/arch-fsl-lsch3/config.h | 4 + arch/arm/include/asm/arch-fsl-lsch3/fsl_serdes.h | 67 +++++++++++++ arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h | 5 + 7 files changed, 308 insertions(+) create mode 100644 arch/arm/cpu/armv8/fsl-lsch3/fsl_lsch3_serdes.c create mode 100644 arch/arm/cpu/armv8/fsl-lsch3/ls2085a_serdes.c create mode 100644 arch/arm/include/asm/arch-fsl-lsch3/fsl_serdes.h (limited to 'arch') diff --git a/arch/arm/cpu/armv8/fsl-lsch3/Makefile b/arch/arm/cpu/armv8/fsl-lsch3/Makefile index 6542590..9f7815b 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/Makefile +++ b/arch/arm/cpu/armv8/fsl-lsch3/Makefile @@ -8,5 +8,6 @@ obj-y += cpu.o obj-y += lowlevel.o obj-y += soc.o obj-y += speed.o +obj-$(CONFIG_SYS_HAS_SERDES) += fsl_lsch3_serdes.o ls2085a_serdes.o obj-$(CONFIG_MP) += mp.o obj-$(CONFIG_OF_LIBFDT) += fdt.o diff --git a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c index 595dbd1..caa48f2 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c +++ b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c @@ -12,6 +12,7 @@ #include #include #include +#include #include "cpu.h" #include "mp.h" #include "speed.h" @@ -415,6 +416,9 @@ int arch_early_init_r(void) if (rv) printf("Did not wake secondary cores\n"); +#ifdef CONFIG_SYS_HAS_SERDES + fsl_serdes_init(); +#endif return 0; } diff --git a/arch/arm/cpu/armv8/fsl-lsch3/fsl_lsch3_serdes.c b/arch/arm/cpu/armv8/fsl-lsch3/fsl_lsch3_serdes.c new file mode 100644 index 0000000..78b9210 --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-lsch3/fsl_lsch3_serdes.c @@ -0,0 +1,110 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +#ifdef CONFIG_SYS_FSL_SRDS_1 +static u8 serdes1_prtcl_map[SERDES_PRCTL_COUNT]; +#endif +#ifdef CONFIG_SYS_FSL_SRDS_2 +static u8 serdes2_prtcl_map[SERDES_PRCTL_COUNT]; +#endif + +int is_serdes_configured(enum srds_prtcl device) +{ + int ret = 0; + +#ifdef CONFIG_SYS_FSL_SRDS_1 + ret |= serdes1_prtcl_map[device]; +#endif +#ifdef CONFIG_SYS_FSL_SRDS_2 + ret |= serdes2_prtcl_map[device]; +#endif + + return !!ret; +} + +int serdes_get_first_lane(u32 sd, enum srds_prtcl device) +{ + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + u32 cfg = in_le32(&gur->rcwsr[28]); + int i; + + switch (sd) { +#ifdef CONFIG_SYS_FSL_SRDS_1 + case FSL_SRDS_1: + cfg &= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK; + cfg >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT; + break; +#endif +#ifdef CONFIG_SYS_FSL_SRDS_2 + case FSL_SRDS_2: + cfg &= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK; + cfg >>= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT; + break; +#endif + default: + printf("invalid SerDes%d\n", sd); + break; + } + /* Is serdes enabled at all? */ + if (cfg == 0) + return -ENODEV; + + for (i = 0; i < SRDS_MAX_LANES; i++) { + if (serdes_get_prtcl(sd, cfg, i) == device) + return i; + } + + return -ENODEV; +} + +void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift, + u8 serdes_prtcl_map[SERDES_PRCTL_COUNT]) +{ + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + u32 cfg; + int lane; + + memset(serdes_prtcl_map, 0, sizeof(serdes_prtcl_map)); + + cfg = in_le32(&gur->rcwsr[28]) & sd_prctl_mask; + cfg >>= sd_prctl_shift; + printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg); + + if (!is_serdes_prtcl_valid(sd, cfg)) + printf("SERDES%d[PRTCL] = 0x%x is not valid\n", sd + 1, cfg); + + for (lane = 0; lane < SRDS_MAX_LANES; lane++) { + enum srds_prtcl lane_prtcl = serdes_get_prtcl(sd, cfg, lane); + if (unlikely(lane_prtcl >= SERDES_PRCTL_COUNT)) + debug("Unknown SerDes lane protocol %d\n", lane_prtcl); + else + serdes_prtcl_map[lane_prtcl] = 1; + } +} + +void fsl_serdes_init(void) +{ +#ifdef CONFIG_SYS_FSL_SRDS_1 + serdes_init(FSL_SRDS_1, + CONFIG_SYS_FSL_LSCH3_SERDES_ADDR, + FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK, + FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT, + serdes1_prtcl_map); +#endif +#ifdef CONFIG_SYS_FSL_SRDS_2 + serdes_init(FSL_SRDS_2, + CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + FSL_SRDS_2 * 0x10000, + FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK, + FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT, + serdes2_prtcl_map); +#endif +} diff --git a/arch/arm/cpu/armv8/fsl-lsch3/ls2085a_serdes.c b/arch/arm/cpu/armv8/fsl-lsch3/ls2085a_serdes.c new file mode 100644 index 0000000..098745b --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-lsch3/ls2085a_serdes.c @@ -0,0 +1,117 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +struct serdes_config { + u8 protocol; + u8 lanes[SRDS_MAX_LANES]; +}; + +static struct serdes_config serdes1_cfg_tbl[] = { + /* SerDes 1 */ + {0x03, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2 } }, + {0x05, {PCIE2, PCIE2, PCIE2, PCIE2, SGMII4, SGMII3, SGMII2, SGMII1 } }, + {0x07, {SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, SGMII2, + SGMII1 } }, + {0x09, {SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, SGMII2, + SGMII1 } }, + {0x0A, {SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, SGMII2, + SGMII1 } }, + {0x0C, {SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, SGMII2, + SGMII1 } }, + {0x0E, {SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, SGMII2, + SGMII1 } }, + {0x26, {SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, XFI2, XFI1 } }, + {0x28, {SGMII8, SGMII7, SGMII6, SGMII5, XFI4, XFI3, XFI2, XFI1 } }, + {0x2A, {XFI8, XFI7, XFI6, XFI5, XFI4, XFI3, XFI2, XFI1 } }, + {0x2B, {SGMII8, SGMII7, SGMII6, SGMII5, XAUI1, XAUI1, XAUI1, XAUI1 } }, + {0x32, {XAUI2, XAUI2, XAUI2, XAUI2, XAUI1, XAUI1, XAUI1, XAUI1 } }, + {0x33, {PCIE2, PCIE2, PCIE2, PCIE2, QSGMII_D, QSGMII_C, QSGMII_B, + QSGMII_A} }, + {0x35, {QSGMII_D, QSGMII_C, QSGMII_B, PCIE2, XFI4, XFI3, XFI2, XFI1 } }, + {} +}; +static struct serdes_config serdes2_cfg_tbl[] = { + /* SerDes 2 */ + {0x07, {SGMII9, SGMII10, SGMII11, SGMII12, SGMII13, SGMII14, SGMII15, + SGMII16 } }, + {0x09, {SGMII9, SGMII10, SGMII11, SGMII12, SGMII13, SGMII14, SGMII15, + SGMII16 } }, + {0x0A, {SGMII9, SGMII10, SGMII11, SGMII12, SGMII13, SGMII14, SGMII15, + SGMII16 } }, + {0x0C, {SGMII9, SGMII10, SGMII11, SGMII12, SGMII13, SGMII14, SGMII15, + SGMII16 } }, + {0x0E, {SGMII9, SGMII10, SGMII11, SGMII12, SGMII13, SGMII14, SGMII15, + SGMII16 } }, + {0x3D, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3 } }, + {0x3E, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3 } }, + {0x3F, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4 } }, + {0x40, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4 } }, + {0x41, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SATA1, SATA2 } }, + {0x42, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SATA1, SATA2 } }, + {0x43, {PCIE3, PCIE3, PCIE3, PCIE3, NONE, NONE, SATA1, SATA2 } }, + {0x44, {PCIE3, PCIE3, PCIE3, PCIE3, NONE, NONE, SATA1, SATA2 } }, + {0x45, {PCIE3, SGMII10, SGMII11, SGMII12, PCIE4, SGMII14, SGMII15, + SGMII16 } }, + {0x47, {SGMII9, SGMII10, SGMII11, SGMII12, PCIE4, PCIE4, PCIE4, + PCIE4 } }, + {0x49, {SGMII9, SGMII10, SGMII11, SGMII12, PCIE4, PCIE4, SATA1, + SATA2 } }, + {0x4A, {SGMII9, SGMII10, SGMII11, SGMII12, PCIE4, PCIE4, SATA1, + SATA2 } }, + {} +}; + +static struct serdes_config *serdes_cfg_tbl[] = { + serdes1_cfg_tbl, + serdes2_cfg_tbl, +}; + +enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane) +{ + struct serdes_config *ptr; + + if (serdes >= ARRAY_SIZE(serdes_cfg_tbl)) + return 0; + + ptr = serdes_cfg_tbl[serdes]; + while (ptr->protocol) { + if (ptr->protocol == cfg) + return ptr->lanes[lane]; + ptr++; + } + + return 0; +} + +int is_serdes_prtcl_valid(int serdes, u32 prtcl) +{ + int i; + struct serdes_config *ptr; + + if (serdes >= ARRAY_SIZE(serdes_cfg_tbl)) + return 0; + + ptr = serdes_cfg_tbl[serdes]; + while (ptr->protocol) { + if (ptr->protocol == prtcl) + break; + ptr++; + } + + if (!ptr->protocol) + return 0; + + for (i = 0; i < SRDS_MAX_LANES; i++) { + if (ptr->lanes[i] != NONE) + return 1; + } + + return 0; +} diff --git a/arch/arm/include/asm/arch-fsl-lsch3/config.h b/arch/arm/include/asm/arch-fsl-lsch3/config.h index a81e3ed..98db1ef 100644 --- a/arch/arm/include/asm/arch-fsl-lsch3/config.h +++ b/arch/arm/include/asm/arch-fsl-lsch3/config.h @@ -38,6 +38,8 @@ #define CONFIG_SYS_FSL_PMU_CLTBENR (CONFIG_SYS_FSL_PMU_ADDR + \ 0x18A0) +#define CONFIG_SYS_FSL_LSCH3_SERDES_ADDR (CONFIG_SYS_IMMR + 0xEA0000) + /* SP (Cortex-A5) related */ #define CONFIG_SYS_FSL_SP_ADDR (CONFIG_SYS_IMMR + 0x00F00000) #define CONFIG_SYS_FSL_SP_VSG_GIC_ADDR (CONFIG_SYS_FSL_SP_ADDR) @@ -133,6 +135,8 @@ #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 #define CONFIG_NUM_DDR_CONTROLLERS 3 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 } +#define CONFIG_SYS_FSL_SRDS_1 +#define CONFIG_SYS_FSL_SRDS_2 #else #error SoC not defined #endif diff --git a/arch/arm/include/asm/arch-fsl-lsch3/fsl_serdes.h b/arch/arm/include/asm/arch-fsl-lsch3/fsl_serdes.h new file mode 100644 index 0000000..2810f3f --- /dev/null +++ b/arch/arm/include/asm/arch-fsl-lsch3/fsl_serdes.h @@ -0,0 +1,67 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __FSL_SERDES_H +#define __FSL_SERDES_H + +#include + +#define SRDS_MAX_LANES 8 + +enum srds_prtcl { + NONE = 0, + PCIE1, + PCIE2, + PCIE3, + PCIE4, + SATA1, + SATA2, + XAUI1, + XAUI2, + XFI1, + XFI2, + XFI3, + XFI4, + XFI5, + XFI6, + XFI7, + XFI8, + SGMII1, + SGMII2, + SGMII3, + SGMII4, + SGMII5, + SGMII6, + SGMII7, + SGMII8, + SGMII9, + SGMII10, + SGMII11, + SGMII12, + SGMII13, + SGMII14, + SGMII15, + SGMII16, + QSGMII_A, /* A indicates MACs 1-4 */ + QSGMII_B, /* B indicates MACs 5-8 */ + QSGMII_C, /* C indicates MACs 9-12 */ + QSGMII_D, /* D indicates MACs 12-16 */ + SERDES_PRCTL_COUNT +}; + +enum srds { + FSL_SRDS_1 = 0, + FSL_SRDS_2 = 1, +}; + +int is_serdes_configured(enum srds_prtcl device); +void fsl_serdes_init(void); + +int serdes_get_first_lane(u32 sd, enum srds_prtcl device); +enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane); +int is_serdes_prtcl_valid(int serdes, u32 prtcl); + +#endif /* __FSL_SERDES_H */ diff --git a/arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h index dd11ef7..91cf68b 100644 --- a/arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h @@ -63,6 +63,11 @@ struct ccsr_gur { #define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK 0x3f #define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_SHIFT 18 #define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_MASK 0x3f +#define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK 0x00FF0000 +#define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT 16 +#define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK 0xFF000000 +#define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT 24 + u8 res_180[0x200-0x180]; u32 scratchrw[32]; /* Scratch Read/Write */ u8 res_280[0x300-0x280]; -- cgit v1.1 From 125e2bc1f24736291e752d78a769f7f942050be2 Mon Sep 17 00:00:00 2001 From: "J. German Rivera" Date: Fri, 20 Mar 2015 19:28:18 -0700 Subject: drivers/fsl-mc: Changed MC firmware loading for new boot architecture Changed MC firmware loading to comply with the new MC boot architecture. Flush D-cache hierarchy after loading MC images. Add environment variables "mcboottimeout" for MC boot timeout in milliseconds, "mcmemsize" for MC DRAM block size. Check MC boot status before calling flib functions. Signed-off-by: J. German Rivera Signed-off-by: York Sun --- arch/arm/cpu/armv8/fsl-lsch3/README | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch') diff --git a/arch/arm/cpu/armv8/fsl-lsch3/README b/arch/arm/cpu/armv8/fsl-lsch3/README index 99fc39a..f781620 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/README +++ b/arch/arm/cpu/armv8/fsl-lsch3/README @@ -33,3 +33,11 @@ is shown below considering a 32MB NOR flash device: ------------------------- ----> 0x0000_0000 32-MB NOR flash layout + +Environment Variables +===================== +mcboottimeout: MC boot timeout in milliseconds. If this variable is not defined + the value CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS will be assumed. + +mcmemsize: MC DRAM block size. If this variable is not defined, the value + CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE will be assumed. -- cgit v1.1 From cd348efa6c8c38cc95495a34d784f9ea159ca41d Mon Sep 17 00:00:00 2001 From: Shaohui Xie Date: Fri, 20 Mar 2015 19:28:19 -0700 Subject: net/memac_phy: reuse driver for little endian SoCs The memac for PHY management on little endian SoCs is similar on big endian SoCs, so we modify the driver by using I/O accessor function to handle the endianness, so the driver can be reused on little endian SoCs, we introduce CONFIG_SYS_MEMAC_LITTLE_ENDIAN for little endian SoCs, if the CONFIG_SYS_MEMAC_LITTLE_ENDIAN is defined, the I/O access is little endian, if not, the I/O access is big endian. Move fsl_memac.h out of powerpc include. Signed-off-by: Shaohui Xie Signed-off-by: York Sun --- arch/arm/include/asm/arch-fsl-lsch3/config.h | 1 + arch/powerpc/include/asm/fsl_memac.h | 264 --------------------------- 2 files changed, 1 insertion(+), 264 deletions(-) delete mode 100644 arch/powerpc/include/asm/fsl_memac.h (limited to 'arch') diff --git a/arch/arm/include/asm/arch-fsl-lsch3/config.h b/arch/arm/include/asm/arch-fsl-lsch3/config.h index 98db1ef..684c70f 100644 --- a/arch/arm/include/asm/arch-fsl-lsch3/config.h +++ b/arch/arm/include/asm/arch-fsl-lsch3/config.h @@ -109,6 +109,7 @@ /* IFC */ #define CONFIG_SYS_FSL_IFC_LE +#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN /* PCIe */ #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000) diff --git a/arch/powerpc/include/asm/fsl_memac.h b/arch/powerpc/include/asm/fsl_memac.h deleted file mode 100644 index bed2a40..0000000 --- a/arch/powerpc/include/asm/fsl_memac.h +++ /dev/null @@ -1,264 +0,0 @@ -/* - * Copyright 2012 Freescale Semiconductor, Inc. - * Roy Zang - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __MEMAC_H__ -#define __MEMAC_H__ - -#include - -struct memac { - /* memac general control and status registers */ - u32 res_0[2]; - u32 command_config; /* Control and configuration register */ - u32 mac_addr_0; /* Lower 32 bits of 48-bit MAC address */ - u32 mac_addr_1; /* Upper 16 bits of 48-bit MAC address */ - u32 maxfrm; /* Maximum frame length register */ - u32 res_18[5]; - u32 hashtable_ctrl; /* Hash table control register */ - u32 res_30[4]; - u32 ievent; /* Interrupt event register */ - u32 tx_ipg_length; /* Transmitter inter-packet-gap register */ - u32 res_48; - u32 imask; /* interrupt mask register */ - u32 res_50; - u32 cl_pause_quanta[4]; /* CL01-CL67 pause quanta register */ - u32 cl_pause_thresh[4]; /* CL01-CL67 pause thresh register */ - u32 rx_pause_status; /* Receive pause status register */ - u32 res_78[2]; - u32 mac_addr[14]; /* MAC address */ - u32 lpwake_timer; /* EEE low power wakeup timer register */ - u32 sleep_timer; /* Transmit EEE Low Power Timer register */ - u32 res_c0[8]; - u32 statn_config; /* Statistics configuration register */ - u32 res_e4[7]; - - /* memac statistics counter registers */ - u32 rx_eoct_l; /* Rx ethernet octests lower */ - u32 rx_eoct_u; /* Rx ethernet octests upper */ - u32 rx_oct_l; /* Rx octests lower */ - u32 rx_oct_u; /* Rx octests upper */ - u32 rx_align_err_l; /* Rx alignment error lower */ - u32 rx_align_err_u; /* Rx alignment error upper */ - u32 rx_pause_frame_l; /* Rx valid pause frame upper */ - u32 rx_pause_frame_u; /* Rx valid pause frame upper */ - u32 rx_frame_l; /* Rx frame counter lower */ - u32 rx_frame_u; /* Rx frame counter upper */ - u32 rx_frame_crc_err_l; /* Rx frame check sequence error lower */ - u32 rx_frame_crc_err_u; /* Rx frame check sequence error upper */ - u32 rx_vlan_l; /* Rx VLAN frame lower */ - u32 rx_vlan_u; /* Rx VLAN frame upper */ - u32 rx_err_l; /* Rx frame error lower */ - u32 rx_err_u; /* Rx frame error upper */ - u32 rx_uni_l; /* Rx unicast frame lower */ - u32 rx_uni_u; /* Rx unicast frame upper */ - u32 rx_multi_l; /* Rx multicast frame lower */ - u32 rx_multi_u; /* Rx multicast frame upper */ - u32 rx_brd_l; /* Rx broadcast frame lower */ - u32 rx_brd_u; /* Rx broadcast frame upper */ - u32 rx_drop_l; /* Rx dropped packets lower */ - u32 rx_drop_u; /* Rx dropped packets upper */ - u32 rx_pkt_l; /* Rx packets lower */ - u32 rx_pkt_u; /* Rx packets upper */ - u32 rx_undsz_l; /* Rx undersized packet lower */ - u32 rx_undsz_u; /* Rx undersized packet upper */ - u32 rx_64_l; /* Rx 64 oct packet lower */ - u32 rx_64_u; /* Rx 64 oct packet upper */ - u32 rx_127_l; /* Rx 65 to 127 oct packet lower */ - u32 rx_127_u; /* Rx 65 to 127 oct packet upper */ - u32 rx_255_l; /* Rx 128 to 255 oct packet lower */ - u32 rx_255_u; /* Rx 128 to 255 oct packet upper */ - u32 rx_511_l; /* Rx 256 to 511 oct packet lower */ - u32 rx_511_u; /* Rx 256 to 511 oct packet upper */ - u32 rx_1023_l; /* Rx 512 to 1023 oct packet lower */ - u32 rx_1023_u; /* Rx 512 to 1023 oct packet upper */ - u32 rx_1518_l; /* Rx 1024 to 1518 oct packet lower */ - u32 rx_1518_u; /* Rx 1024 to 1518 oct packet upper */ - u32 rx_1519_l; /* Rx 1519 to max oct packet lower */ - u32 rx_1519_u; /* Rx 1519 to max oct packet upper */ - u32 rx_oversz_l; /* Rx oversized packet lower */ - u32 rx_oversz_u; /* Rx oversized packet upper */ - u32 rx_jabber_l; /* Rx Jabber packet lower */ - u32 rx_jabber_u; /* Rx Jabber packet upper */ - u32 rx_frag_l; /* Rx Fragment packet lower */ - u32 rx_frag_u; /* Rx Fragment packet upper */ - u32 rx_cnp_l; /* Rx control packet lower */ - u32 rx_cnp_u; /* Rx control packet upper */ - u32 rx_drntp_l; /* Rx dripped not truncated packet lower */ - u32 rx_drntp_u; /* Rx dripped not truncated packet upper */ - u32 res_1d0[0xc]; - - u32 tx_eoct_l; /* Tx ethernet octests lower */ - u32 tx_eoct_u; /* Tx ethernet octests upper */ - u32 tx_oct_l; /* Tx octests lower */ - u32 tx_oct_u; /* Tx octests upper */ - u32 res_210[0x2]; - u32 tx_pause_frame_l; /* Tx valid pause frame lower */ - u32 tx_pause_frame_u; /* Tx valid pause frame upper */ - u32 tx_frame_l; /* Tx frame counter lower */ - u32 tx_frame_u; /* Tx frame counter upper */ - u32 tx_frame_crc_err_l; /* Tx frame check sequence error lower */ - u32 tx_frame_crc_err_u; /* Tx frame check sequence error upper */ - u32 tx_vlan_l; /* Tx VLAN frame lower */ - u32 tx_vlan_u; /* Tx VLAN frame upper */ - u32 tx_frame_err_l; /* Tx frame error lower */ - u32 tx_frame_err_u; /* Tx frame error upper */ - u32 tx_uni_l; /* Tx unicast frame lower */ - u32 tx_uni_u; /* Tx unicast frame upper */ - u32 tx_multi_l; /* Tx multicast frame lower */ - u32 tx_multi_u; /* Tx multicast frame upper */ - u32 tx_brd_l; /* Tx broadcast frame lower */ - u32 tx_brd_u; /* Tx broadcast frame upper */ - u32 res_258[0x2]; - u32 tx_pkt_l; /* Tx packets lower */ - u32 tx_pkt_u; /* Tx packets upper */ - u32 tx_undsz_l; /* Tx undersized packet lower */ - u32 tx_undsz_u; /* Tx undersized packet upper */ - u32 tx_64_l; /* Tx 64 oct packet lower */ - u32 tx_64_u; /* Tx 64 oct packet upper */ - u32 tx_127_l; /* Tx 65 to 127 oct packet lower */ - u32 tx_127_u; /* Tx 65 to 127 oct packet upper */ - u32 tx_255_l; /* Tx 128 to 255 oct packet lower */ - u32 tx_255_u; /* Tx 128 to 255 oct packet upper */ - u32 tx_511_l; /* Tx 256 to 511 oct packet lower */ - u32 tx_511_u; /* Tx 256 to 511 oct packet upper */ - u32 tx_1023_l; /* Tx 512 to 1023 oct packet lower */ - u32 tx_1023_u; /* Tx 512 to 1023 oct packet upper */ - u32 tx_1518_l; /* Tx 1024 to 1518 oct packet lower */ - u32 tx_1518_u; /* Tx 1024 to 1518 oct packet upper */ - u32 tx_1519_l; /* Tx 1519 to max oct packet lower */ - u32 tx_1519_u; /* Tx 1519 to max oct packet upper */ - u32 res_2a8[0x6]; - u32 tx_cnp_l; /* Tx control packet lower */ - u32 tx_cnp_u; /* Tx control packet upper */ - u32 res_2c8[0xe]; - - /* Line interface control register */ - u32 if_mode; /* interface mode control */ - u32 if_status; /* interface status */ - u32 res_308[0xe]; - - /* HiGig/2 Register */ - u32 hg_config; /* HiGig2 control and configuration */ - u32 res_344[0x3]; - u32 hg_pause_quanta; /* HiGig2 pause quanta */ - u32 res_354[0x3]; - u32 hg_pause_thresh; /* HiGig2 pause quanta threshold */ - u32 res_364[0x3]; - u32 hgrx_pause_status; /* HiGig2 rx pause quanta status */ - u32 hg_fifos_status; /* HiGig2 fifos status */ - u32 rhm; /* Rx HiGig2 message counter register */ - u32 thm;/* Tx HiGig2 message counter register */ - u32 res_380[0x320]; -}; - -/* COMMAND_CONFIG - command and configuration register */ -#define MEMAC_CMD_CFG_RX_EN 0x00000002 /* MAC Rx path enable */ -#define MEMAC_CMD_CFG_TX_EN 0x00000001 /* MAC Tx path enable */ -#define MEMAC_CMD_CFG_RXTX_EN (MEMAC_CMD_CFG_RX_EN | MEMAC_CMD_CFG_TX_EN) -#define MEMAC_CMD_CFG_NO_LEN_CHK 0x20000 /* Payload length check disable */ - -/* HASHTABLE_CTRL - Hashtable control register */ -#define HASHTABLE_CTRL_MCAST_EN 0x00000200 /* enable mulitcast Rx hash */ -#define HASHTABLE_CTRL_ADDR_MASK 0x000001ff - -/* TX_IPG_LENGTH - Transmit inter-packet gap length register */ -#define TX_IPG_LENGTH_IPG_LEN_MASK 0x000003ff - -/* IMASK - interrupt mask register */ -#define IMASK_MDIO_SCAN_EVENT 0x00010000 /* MDIO scan event mask */ -#define IMASK_MDIO_CMD_CMPL 0x00008000 /* MDIO cmd completion mask */ -#define IMASK_REM_FAULT 0x00004000 /* remote fault mask */ -#define IMASK_LOC_FAULT 0x00002000 /* local fault mask */ -#define IMASK_TX_ECC_ER 0x00001000 /* Tx frame ECC error mask */ -#define IMASK_TX_FIFO_UNFL 0x00000800 /* Tx FIFO underflow mask */ -#define IMASK_TX_ER 0x00000200 /* Tx frame error mask */ -#define IMASK_RX_FIFO_OVFL 0x00000100 /* Rx FIFO overflow mask */ -#define IMASK_RX_ECC_ER 0x00000080 /* Rx frame ECC error mask */ -#define IMASK_RX_JAB_FRM 0x00000040 /* Rx jabber frame mask */ -#define IMASK_RX_OVRSZ_FRM 0x00000020 /* Rx oversized frame mask */ -#define IMASK_RX_RUNT_FRM 0x00000010 /* Rx runt frame mask */ -#define IMASK_RX_FRAG_FRM 0x00000008 /* Rx fragment frame mask */ -#define IMASK_RX_LEN_ER 0x00000004 /* Rx payload length error mask */ -#define IMASK_RX_CRC_ER 0x00000002 /* Rx CRC error mask */ -#define IMASK_RX_ALIGN_ER 0x00000001 /* Rx alignment error mask */ - -#define IMASK_MASK_ALL 0x00000000 - -/* IEVENT - interrupt event register */ -#define IEVENT_MDIO_SCAN_EVENT 0x00010000 /* MDIO scan event */ -#define IEVENT_MDIO_CMD_CMPL 0x00008000 /* MDIO cmd completion */ -#define IEVENT_REM_FAULT 0x00004000 /* remote fault */ -#define IEVENT_LOC_FAULT 0x00002000 /* local fault */ -#define IEVENT_TX_ECC_ER 0x00001000 /* Tx frame ECC error */ -#define IEVENT_TX_FIFO_UNFL 0x00000800 /* Tx FIFO underflow */ -#define IEVENT_TX_ER 0x00000200 /* Tx frame error */ -#define IEVENT_RX_FIFO_OVFL 0x00000100 /* Rx FIFO overflow */ -#define IEVENT_RX_ECC_ER 0x00000080 /* Rx frame ECC error */ -#define IEVENT_RX_JAB_FRM 0x00000040 /* Rx jabber frame */ -#define IEVENT_RX_OVRSZ_FRM 0x00000020 /* Rx oversized frame */ -#define IEVENT_RX_RUNT_FRM 0x00000010 /* Rx runt frame */ -#define IEVENT_RX_FRAG_FRM 0x00000008 /* Rx fragment frame */ -#define IEVENT_RX_LEN_ER 0x00000004 /* Rx payload length error */ -#define IEVENT_RX_CRC_ER 0x00000002 /* Rx CRC error */ -#define IEVENT_RX_ALIGN_ER 0x00000001 /* Rx alignment error */ - -#define IEVENT_CLEAR_ALL 0xffffffff - -/* IF_MODE - Interface Mode Register */ -#define IF_MODE_EN_AUTO 0x00008000 /* 1 - Enable automatic speed selection */ -#define IF_MODE_SETSP_100M 0x00000000 /* 00 - 100Mbps RGMII */ -#define IF_MODE_SETSP_10M 0x00002000 /* 01 - 10Mbps RGMII */ -#define IF_MODE_SETSP_1000M 0x00004000 /* 10 - 1000Mbps RGMII */ -#define IF_MODE_SETSP_MASK 0x00006000 /* setsp mask bits */ -#define IF_MODE_XGMII 0x00000000 /* 00- XGMII(10) interface mode */ -#define IF_MODE_GMII 0x00000002 /* 10- GMII interface mode */ -#define IF_MODE_MASK 0x00000003 /* mask for mode interface mode */ -#define IF_MODE_RG 0x00000004 /* 1- RGMII */ -#define IF_MODE_RM 0x00000008 /* 1- RGMII */ - -#define IF_DEFAULT (IF_GMII) - -/* Internal PHY Registers - SGMII */ -#define PHY_SGMII_CR_PHY_RESET 0x8000 -#define PHY_SGMII_CR_RESET_AN 0x0200 -#define PHY_SGMII_CR_DEF_VAL 0x1140 -#define PHY_SGMII_DEV_ABILITY_SGMII 0x4001 -#define PHY_SGMII_IF_MODE_AN 0x0002 -#define PHY_SGMII_IF_MODE_SGMII 0x0001 - -struct memac_mdio_controller { - u32 res0[0xc]; - u32 mdio_stat; /* MDIO configuration and status */ - u32 mdio_ctl; /* MDIO control */ - u32 mdio_data; /* MDIO data */ - u32 mdio_addr; /* MDIO address */ -}; - -#define MDIO_STAT_CLKDIV(x) (((x>>1) & 0xff) << 8) -#define MDIO_STAT_BSY (1 << 0) -#define MDIO_STAT_RD_ER (1 << 1) -#define MDIO_STAT_PRE (1 << 5) -#define MDIO_STAT_ENC (1 << 6) -#define MDIO_STAT_HOLD_15_CLK (7 << 2) -#define MDIO_STAT_NEG (1 << 23) - -#define MDIO_CTL_DEV_ADDR(x) (x & 0x1f) -#define MDIO_CTL_PORT_ADDR(x) ((x & 0x1f) << 5) -#define MDIO_CTL_PRE_DIS (1 << 10) -#define MDIO_CTL_SCAN_EN (1 << 11) -#define MDIO_CTL_POST_INC (1 << 14) -#define MDIO_CTL_READ (1 << 15) - -#define MDIO_DATA(x) (x & 0xffff) -#define MDIO_DATA_BSY (1 << 31) - -struct fsl_enet_mac; - -void init_memac(struct fsl_enet_mac *mac, void *base, void *phyregs, - int max_rx_len); - -#endif -- cgit v1.1 From d27bf906dac9d85ca2426a7f42299d0560f4a968 Mon Sep 17 00:00:00 2001 From: Bhupesh Sharma Date: Fri, 20 Mar 2015 19:28:20 -0700 Subject: armv8/fsl-ch3: Add support to print RCW configuration This patch adds support to print out the Reset Configuration Word information. Signed-off-by: Bhupesh Sharma Signed-off-by: York Sun --- arch/arm/cpu/armv8/fsl-lsch3/cpu.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'arch') diff --git a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c index caa48f2..07064a3 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c +++ b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c @@ -371,6 +371,7 @@ u32 fsl_qoriq_core_to_type(unsigned int core) #ifdef CONFIG_DISPLAY_CPUINFO int print_cpuinfo(void) { + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); struct sys_info sysinfo; char buf[32]; unsigned int i, core; @@ -394,6 +395,19 @@ int print_cpuinfo(void) printf(" DP-DDR: %-4s MHz", strmhz(buf, sysinfo.freq_ddrbus2)); puts("\n"); + /* Display the RCW, so that no one gets confused as to what RCW + * we're actually using for this boot. + */ + puts("Reset Configuration Word (RCW):"); + for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) { + u32 rcw = in_le32(&gur->rcwsr[i]); + + if ((i % 4) == 0) + printf("\n %02x:", i * 4); + printf(" %08x", rcw); + } + puts("\n"); + return 0; } #endif -- cgit v1.1 From 9cc2c4713a822cccaa1c5872720a23675045dd42 Mon Sep 17 00:00:00 2001 From: Prabhakar Kushwaha Date: Fri, 20 Mar 2015 19:28:22 -0700 Subject: driver/ldpaa: Add support of WRIOP static data structure Wire rate IO Processor (WRIOP) provide support of receive and transmit ethernet frames from the ethernet MAC. Here Each WRIOP block supports upto 64 DPMACs. Create a house keeping data structure to support upto 16 DPMACs and store external phy related information. Signed-off-by: Prabhakar Kushwaha Signed-off-by: York Sun --- arch/arm/cpu/armv8/fsl-lsch3/fsl_lsch3_serdes.c | 7 ++++++- arch/arm/include/asm/arch-fsl-lsch3/config.h | 3 +++ arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h | 24 +++++++++++++++++++++++ 3 files changed, 33 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/cpu/armv8/fsl-lsch3/fsl_lsch3_serdes.c b/arch/arm/cpu/armv8/fsl-lsch3/fsl_lsch3_serdes.c index 78b9210..02ca126 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/fsl_lsch3_serdes.c +++ b/arch/arm/cpu/armv8/fsl-lsch3/fsl_lsch3_serdes.c @@ -9,6 +9,7 @@ #include #include #include +#include #ifdef CONFIG_SYS_FSL_SRDS_1 static u8 serdes1_prtcl_map[SERDES_PRCTL_COUNT]; @@ -86,8 +87,12 @@ void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift, enum srds_prtcl lane_prtcl = serdes_get_prtcl(sd, cfg, lane); if (unlikely(lane_prtcl >= SERDES_PRCTL_COUNT)) debug("Unknown SerDes lane protocol %d\n", lane_prtcl); - else + else { serdes_prtcl_map[lane_prtcl] = 1; +#ifdef CONFIG_FSL_MC_ENET + wriop_init_dpmac(sd, lane + 1, (int)lane_prtcl); +#endif + } } } diff --git a/arch/arm/include/asm/arch-fsl-lsch3/config.h b/arch/arm/include/asm/arch-fsl-lsch3/config.h index 684c70f..403b2ef 100644 --- a/arch/arm/include/asm/arch-fsl-lsch3/config.h +++ b/arch/arm/include/asm/arch-fsl-lsch3/config.h @@ -38,6 +38,9 @@ #define CONFIG_SYS_FSL_PMU_CLTBENR (CONFIG_SYS_FSL_PMU_ADDR + \ 0x18A0) +#define CONFIG_SYS_FSL_WRIOP1_ADDR (CONFIG_SYS_IMMR + 0x7B80000) +#define CONFIG_SYS_FSL_WRIOP1_MDIO1 (CONFIG_SYS_FSL_WRIOP1_ADDR + 0x16000) +#define CONFIG_SYS_FSL_WRIOP1_MDIO2 (CONFIG_SYS_FSL_WRIOP1_ADDR + 0x17000) #define CONFIG_SYS_FSL_LSCH3_SERDES_ADDR (CONFIG_SYS_IMMR + 0xEA0000) /* SP (Cortex-A5) related */ diff --git a/arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h index 91cf68b..d6bee60 100644 --- a/arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h @@ -47,6 +47,30 @@ struct ccsr_gur { u32 devdisr5; /* Device disable control 5 */ u32 devdisr6; /* Device disable control 6 */ u32 devdisr7; /* Device disable control 7 */ +#define FSL_CHASSIS3_DEVDISR2_DPMAC1 0x00000001 +#define FSL_CHASSIS3_DEVDISR2_DPMAC2 0x00000002 +#define FSL_CHASSIS3_DEVDISR2_DPMAC3 0x00000004 +#define FSL_CHASSIS3_DEVDISR2_DPMAC4 0x00000008 +#define FSL_CHASSIS3_DEVDISR2_DPMAC5 0x00000010 +#define FSL_CHASSIS3_DEVDISR2_DPMAC6 0x00000020 +#define FSL_CHASSIS3_DEVDISR2_DPMAC7 0x00000040 +#define FSL_CHASSIS3_DEVDISR2_DPMAC8 0x00000080 +#define FSL_CHASSIS3_DEVDISR2_DPMAC9 0x00000100 +#define FSL_CHASSIS3_DEVDISR2_DPMAC10 0x00000200 +#define FSL_CHASSIS3_DEVDISR2_DPMAC11 0x00000400 +#define FSL_CHASSIS3_DEVDISR2_DPMAC12 0x00000800 +#define FSL_CHASSIS3_DEVDISR2_DPMAC13 0x00001000 +#define FSL_CHASSIS3_DEVDISR2_DPMAC14 0x00002000 +#define FSL_CHASSIS3_DEVDISR2_DPMAC15 0x00004000 +#define FSL_CHASSIS3_DEVDISR2_DPMAC16 0x00008000 +#define FSL_CHASSIS3_DEVDISR2_DPMAC17 0x00010000 +#define FSL_CHASSIS3_DEVDISR2_DPMAC18 0x00020000 +#define FSL_CHASSIS3_DEVDISR2_DPMAC19 0x00040000 +#define FSL_CHASSIS3_DEVDISR2_DPMAC20 0x00080000 +#define FSL_CHASSIS3_DEVDISR2_DPMAC21 0x00100000 +#define FSL_CHASSIS3_DEVDISR2_DPMAC22 0x00200000 +#define FSL_CHASSIS3_DEVDISR2_DPMAC23 0x00400000 +#define FSL_CHASSIS3_DEVDISR2_DPMAC24 0x00800000 u8 res_08c[0x90-0x8c]; u32 coredisru; /* uppper portion for support of 64 cores */ u32 coredisrl; /* lower portion for support of 64 cores */ -- cgit v1.1 From 7288c2c2b0d4ea2475424ef9d00227a4b608234d Mon Sep 17 00:00:00 2001 From: York Sun Date: Fri, 20 Mar 2015 19:28:23 -0700 Subject: armv8/ls2085aqds: Add support of LS2085AQDS platform The LS2085AQDS is an evaluatoin platform that supports the LS2085A family SoCs. This patch add basic support of the platform. Signed-off-by: York Sun Signed-off-by: Prabhakar Kushwaha Signed-off-by: Bhupesh Sharma --- arch/arm/Kconfig | 11 ++++++ arch/arm/cpu/armv8/fsl-lsch3/README | 70 ++++++++++++++++++++++++++++++++----- 2 files changed, 73 insertions(+), 8 deletions(-) (limited to 'arch') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 3702bb0..f8ef5dc 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -711,6 +711,16 @@ config TARGET_LS2085A_SIMU select ARM64 select ARMV8_MULTIENTRY +config TARGET_LS2085AQDS + bool "Support ls2085aqds" + select ARM64 + select ARMV8_MULTIENTRY + help + Support for Freescale LS2085AQDS platform + The LS2085A Development System (QDS) is a high-performance + development platform that supports the QorIQ LS2085A + Layerscape Architecture processor. + config TARGET_LS1021AQDS bool "Support ls1021aqds" select CPU_V7 @@ -865,6 +875,7 @@ source "board/denx/m53evk/Kconfig" source "board/embest/mx6boards/Kconfig" source "board/esg/ima3-mx53/Kconfig" source "board/freescale/ls2085a/Kconfig" +source "board/freescale/ls2085aqds/Kconfig" source "board/freescale/ls1021aqds/Kconfig" source "board/freescale/ls1021atwr/Kconfig" source "board/freescale/mx23evk/Kconfig" diff --git a/arch/arm/cpu/armv8/fsl-lsch3/README b/arch/arm/cpu/armv8/fsl-lsch3/README index f781620..817ea1b 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/README +++ b/arch/arm/cpu/armv8/fsl-lsch3/README @@ -11,28 +11,82 @@ for example LS2085A. Flash Layout ============ -A typical layout of various images (including Linux and other firmware images) -is shown below considering a 32MB NOR flash device: + +(1) A typical layout of various images (including Linux and other firmware images) + is shown below considering a 32MB NOR flash device present on most + pre-silicon platforms (simulator and emulator): ------------------------- - | linux | + | FIT Image | + | (linux + DTB + RFS) | ------------------------- ----> 0x0120_0000 - | Debug Server | + | Debug Server FW | ------------------------- ----> 0x00C0_0000 - | AIOP SW | + | AIOP FW | ------------------------- ----> 0x0070_0000 | MC FW | ------------------------- ----> 0x006C_0000 - | MC Data Path Layout | + | MC DPL Blob | ------------------------- ----> 0x0020_0000 - | BootLoader | + | BootLoader + Env| ------------------------- ----> 0x0000_1000 | PBI | ------------------------- ----> 0x0000_0080 | RCW | ------------------------- ----> 0x0000_0000 - 32-MB NOR flash layout + 32-MB NOR flash layout for pre-silicon platforms (simulator and emulator) + +(2) A typical layout of various images (including Linux and other firmware images) + is shown below considering a 128MB NOR flash device present on QDS + boards: + ----------------------------------------- ----> 0x5_8800_0000 --- + | .. Unused .. (7M) | | + ----------------------------------------- ----> 0x5_8790_0000 | + | FIT Image (linux + DTB + RFS) (40M) | | + ----------------------------------------- ----> 0x5_8510_0000 | + | PHY firmware (2M) | | + ----------------------------------------- ----> 0x5_84F0_0000 | 64K + | Debug Server FW (2M) | | Alt + ----------------------------------------- ----> 0x5_84D0_0000 | Bank + | AIOP FW (4M) | | + ----------------------------------------- ----> 0x5_8490_0000 (vbank4) + | MC DPC Blob (1M) | | + ----------------------------------------- ----> 0x5_8480_0000 | + | MC DPL Blob (1M) | | + ----------------------------------------- ----> 0x5_8470_0000 | + | MC FW (4M) | | + ----------------------------------------- ----> 0x5_8430_0000 | + | BootLoader Environment (1M) | | + ----------------------------------------- ----> 0x5_8420_0000 | + | BootLoader (1M) | | + ----------------------------------------- ----> 0x5_8410_0000 | + | RCW and PBI (1M) | | + ----------------------------------------- ----> 0x5_8400_0000 --- + | .. Unused .. (7M) | | + ----------------------------------------- ----> 0x5_8390_0000 | + | FIT Image (linux + DTB + RFS) (40M) | | + ----------------------------------------- ----> 0x5_8110_0000 | + | PHY firmware (2M) | | + ----------------------------------------- ----> 0x5_80F0_0000 | 64K + | Debug Server FW (2M) | | Bank + ----------------------------------------- ----> 0x5_80D0_0000 | + | AIOP FW (4M) | | + ----------------------------------------- ----> 0x5_8090_0000 (vbank0) + | MC DPC Blob (1M) | | + ----------------------------------------- ----> 0x5_8080_0000 | + | MC DPL Blob (1M) | | + ----------------------------------------- ----> 0x5_8070_0000 | + | MC FW (4M) | | + ----------------------------------------- ----> 0x5_8030_0000 | + | BootLoader Environment (1M) | | + ----------------------------------------- ----> 0x5_8020_0000 | + | BootLoader (1M) | | + ----------------------------------------- ----> 0x5_8010_0000 | + | RCW and PBI (1M) | | + ----------------------------------------- ----> 0x5_8000_0000 --- + + 128-MB NOR flash layout for QDS board Environment Variables ===================== -- cgit v1.1 From e2b65ea975c2ddc67a958bf428e34ee3c543061a Mon Sep 17 00:00:00 2001 From: York Sun Date: Fri, 20 Mar 2015 19:28:24 -0700 Subject: armv8/ls2085ardb: Add support of LS2085ARDB platform The LS2085ARDB is a evaluation platform that supports LS2085A family SoCs. This patch add sbasic support for the platform. Signed-off-by: York Sun Signed-off-by: Prabhakar Kushwaha Signed-off-by: Bhupesh Sharma Signed-off-by: Scott Wood --- arch/arm/Kconfig | 11 +++++++++++ arch/arm/cpu/armv8/fsl-lsch3/README | 4 ++-- 2 files changed, 13 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index f8ef5dc..3d0828d 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -721,6 +721,16 @@ config TARGET_LS2085AQDS development platform that supports the QorIQ LS2085A Layerscape Architecture processor. +config TARGET_LS2085ARDB + bool "Support ls2085ardb" + select ARM64 + select ARMV8_MULTIENTRY + help + Support for Freescale LS2085ARDB platform. + The LS2085A Reference design board (RDB) is a high-performance + development platform that supports the QorIQ LS2085A + Layerscape Architecture processor. + config TARGET_LS1021AQDS bool "Support ls1021aqds" select CPU_V7 @@ -876,6 +886,7 @@ source "board/embest/mx6boards/Kconfig" source "board/esg/ima3-mx53/Kconfig" source "board/freescale/ls2085a/Kconfig" source "board/freescale/ls2085aqds/Kconfig" +source "board/freescale/ls2085ardb/Kconfig" source "board/freescale/ls1021aqds/Kconfig" source "board/freescale/ls1021atwr/Kconfig" source "board/freescale/mx23evk/Kconfig" diff --git a/arch/arm/cpu/armv8/fsl-lsch3/README b/arch/arm/cpu/armv8/fsl-lsch3/README index 817ea1b..4f36e2a 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/README +++ b/arch/arm/cpu/armv8/fsl-lsch3/README @@ -38,7 +38,7 @@ Flash Layout 32-MB NOR flash layout for pre-silicon platforms (simulator and emulator) (2) A typical layout of various images (including Linux and other firmware images) - is shown below considering a 128MB NOR flash device present on QDS + is shown below considering a 128MB NOR flash device present on QDS and RDB boards: ----------------------------------------- ----> 0x5_8800_0000 --- | .. Unused .. (7M) | | @@ -86,7 +86,7 @@ Flash Layout | RCW and PBI (1M) | | ----------------------------------------- ----> 0x5_8000_0000 --- - 128-MB NOR flash layout for QDS board + 128-MB NOR flash layout for QDS and RDB boards Environment Variables ===================== -- cgit v1.1 From 39b0bbbb23076a7109eeb20b6ae812edcd60ffc2 Mon Sep 17 00:00:00 2001 From: Jaiprakash Singh Date: Fri, 20 Mar 2015 19:28:27 -0700 Subject: driver/ifc: Add 64KB page support IFC has two register pages.Till IFC version 1.4 each register page is 4KB each.But IFC ver 2.0 register page size is 64KB each.IFC regiters structure is break into two viz FCM and RUNTIME.FCM(Flash control machine) registers are defined in PAGE0 and controls IFC generic functionality. RUNTIME registers are defined in PAGE1 and controls NAND and GPCM funcinality. FCM and RUNTIME structures defination is common for IFC version 1.4 and 2.0. Signed-off-by: Jaiprakash Singh Signed-off-by: York Sun --- arch/arm/cpu/armv7/ls102xa/clock.c | 4 ++-- arch/arm/cpu/armv8/fsl-lsch3/speed.c | 4 ++-- arch/powerpc/cpu/mpc85xx/cpu_init_early.c | 8 ++++---- arch/powerpc/cpu/mpc85xx/speed.c | 4 ++-- 4 files changed, 10 insertions(+), 10 deletions(-) (limited to 'arch') diff --git a/arch/arm/cpu/armv7/ls102xa/clock.c b/arch/arm/cpu/armv7/ls102xa/clock.c index 8f80c61..7a337e1 100644 --- a/arch/arm/cpu/armv7/ls102xa/clock.c +++ b/arch/arm/cpu/armv7/ls102xa/clock.c @@ -20,7 +20,7 @@ void get_sys_info(struct sys_info *sys_info) { struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); #ifdef CONFIG_FSL_IFC - struct fsl_ifc *ifc_regs = (void *)CONFIG_SYS_IFC_ADDR; + struct fsl_ifc ifc_regs = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL}; u32 ccr; #endif struct ccsr_clk *clk = (void *)(CONFIG_SYS_FSL_LS1_CLK_ADDR); @@ -74,7 +74,7 @@ void get_sys_info(struct sys_info *sys_info) } #if defined(CONFIG_FSL_IFC) - ccr = in_be32(&ifc_regs->ifc_ccr); + ccr = in_be32(&ifc_regs.gregs->ifc_ccr); ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1; sys_info->freq_localbus = sys_info->freq_systembus / ccr; diff --git a/arch/arm/cpu/armv8/fsl-lsch3/speed.c b/arch/arm/cpu/armv8/fsl-lsch3/speed.c index 2b140cd..cac4f92 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/speed.c +++ b/arch/arm/cpu/armv8/fsl-lsch3/speed.c @@ -26,7 +26,7 @@ void get_sys_info(struct sys_info *sys_info) { struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); #ifdef CONFIG_FSL_IFC - struct fsl_ifc *ifc_regs = (void *)CONFIG_SYS_IFC_ADDR; + struct fsl_ifc ifc_regs = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL}; u32 ccr; #endif struct ccsr_clk_cluster_group __iomem *clk_grp[2] = { @@ -118,7 +118,7 @@ void get_sys_info(struct sys_info *sys_info) } #if defined(CONFIG_FSL_IFC) - ccr = in_le32(&ifc_regs->ifc_ccr); + ccr = in_le32(&ifc_regs.gregs->ifc_ccr); ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1; sys_info->freq_localbus = sys_info->freq_systembus / ccr; diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c index 5ca9bf5..235a635 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c @@ -15,7 +15,7 @@ DECLARE_GLOBAL_DATA_PTR; #ifdef CONFIG_A003399_NOR_WORKAROUND void setup_ifc(void) { - struct fsl_ifc *ifc_regs = (void *)CONFIG_SYS_IFC_ADDR; + struct fsl_ifc ifc_regs = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL}; u32 _mas0, _mas1, _mas2, _mas3, _mas7; phys_addr_t flash_phys = CONFIG_SYS_FLASH_BASE_PHYS; @@ -70,9 +70,9 @@ void setup_ifc(void) #endif /* Change flash's physical address */ - ifc_out32(&(ifc_regs->cspr_cs[0].cspr), CONFIG_SYS_CSPR0); - ifc_out32(&(ifc_regs->csor_cs[0].csor), CONFIG_SYS_CSOR0); - ifc_out32(&(ifc_regs->amask_cs[0].amask), CONFIG_SYS_AMASK0); + ifc_out32(&(ifc_regs.gregs->cspr_cs[0].cspr), CONFIG_SYS_CSPR0); + ifc_out32(&(ifc_regs.gregs->csor_cs[0].csor), CONFIG_SYS_CSOR0); + ifc_out32(&(ifc_regs.gregs->amask_cs[0].amask), CONFIG_SYS_AMASK0); return ; } diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index e24b857..321ade2 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -28,7 +28,7 @@ void get_sys_info(sys_info_t *sys_info) { volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); #ifdef CONFIG_FSL_IFC - struct fsl_ifc *ifc_regs = (void *)CONFIG_SYS_IFC_ADDR; + struct fsl_ifc ifc_regs = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL}; u32 ccr; #endif #ifdef CONFIG_FSL_CORENET @@ -597,7 +597,7 @@ void get_sys_info(sys_info_t *sys_info) #endif #if defined(CONFIG_FSL_IFC) - ccr = ifc_in32(&ifc_regs->ifc_ccr); + ccr = ifc_in32(&ifc_regs.gregs->ifc_ccr); ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1; sys_info->freq_localbus = sys_info->freq_systembus / ccr; -- cgit v1.1 From b2d5ac59859fa946e47fb6ab1f4f3486d4988680 Mon Sep 17 00:00:00 2001 From: Scott Wood Date: Tue, 24 Mar 2015 13:25:02 -0700 Subject: armv8/ls2085aqds: NAND boot support This adds NAND boot support for LS2085AQDS, using SPL framework. Details of forming NAND image can be found in README. Signed-off-by: Scott Wood [York Sun: Remove +S from defconfig after commit 252ed872] Signed-off-by: York Sun --- arch/arm/Kconfig | 1 + arch/arm/cpu/armv8/fsl-lsch3/README | 38 ++++++++++++++ arch/arm/cpu/armv8/fsl-lsch3/soc.c | 48 +++++++++++++++++ arch/arm/cpu/armv8/u-boot-spl.lds | 77 ++++++++++++++++++++++++++++ arch/arm/include/asm/arch-fsl-lsch3/config.h | 9 ++++ arch/arm/lib/crt0_64.S | 7 +++ 6 files changed, 180 insertions(+) create mode 100644 arch/arm/cpu/armv8/u-boot-spl.lds (limited to 'arch') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 3d0828d..4b7761d 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -715,6 +715,7 @@ config TARGET_LS2085AQDS bool "Support ls2085aqds" select ARM64 select ARMV8_MULTIENTRY + select SUPPORT_SPL help Support for Freescale LS2085AQDS platform The LS2085A Development System (QDS) is a high-performance diff --git a/arch/arm/cpu/armv8/fsl-lsch3/README b/arch/arm/cpu/armv8/fsl-lsch3/README index 4f36e2a..15a1549 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/README +++ b/arch/arm/cpu/armv8/fsl-lsch3/README @@ -95,3 +95,41 @@ mcboottimeout: MC boot timeout in milliseconds. If this variable is not defined mcmemsize: MC DRAM block size. If this variable is not defined, the value CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE will be assumed. + +Booting from NAND +------------------- +Booting from NAND requires two images, RCW and u-boot-with-spl.bin. +The difference between NAND boot RCW image and NOR boot image is the PBI +command sequence. Below is one example for PBI commands for QDS which uses +NAND device with 2KB/page, block size 128KB. + +1) CCSR 4-byte write to 0x00e00404, data=0x00000000 +2) CCSR 4-byte write to 0x00e00400, data=0x1800a000 +The above two commands set bootloc register to 0x00000000_1800a000 where +the u-boot code will be running in OCRAM. + +3) Block Copy: SRC=0x0107, SRC_ADDR=0x00020000, DEST_ADDR=0x1800a000, +BLOCK_SIZE=0x00014000 +This command copies u-boot image from NAND device into OCRAM. The values need +to adjust accordingly. + +SRC should match the cfg_rcw_src, the reset config pins. It depends + on the NAND device. See reference manual for cfg_rcw_src. +SRC_ADDR is the offset of u-boot-with-spl.bin image in NAND device. In + the example above, 128KB. For easy maintenance, we put it at + the beginning of next block from RCW. +DEST_ADDR is fixed at 0x1800a000, matching bootloc set above. +BLOCK_SIZE is the size to be copied by PBI. + +RCW image should be written to the beginning of NAND device. Example of using +u-boot command + +nand write 0 + +To form the NAND image, build u-boot with NAND config, for example, +ls2085aqds_nand_defconfig. The image needed is u-boot-with-spl.bin. +The u-boot image should be written to match SRC_ADDR, in above example 0x20000. + +nand write 200000 + +With these two images in NAND device, the board can boot from NAND. diff --git a/arch/arm/cpu/armv8/fsl-lsch3/soc.c b/arch/arm/cpu/armv8/fsl-lsch3/soc.c index 17700ef..ca00108 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/soc.c +++ b/arch/arm/cpu/armv8/fsl-lsch3/soc.c @@ -6,8 +6,13 @@ #include #include +#include +#include #include #include +#include + +DECLARE_GLOBAL_DATA_PTR; static void erratum_a008751(void) { @@ -18,8 +23,51 @@ static void erratum_a008751(void) #endif } +static void erratum_rcw_src(void) +{ +#if defined(CONFIG_SPL) + u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE; + u32 __iomem *dcfg_dcsr = (u32 __iomem *)DCFG_DCSR_BASE; + u32 val; + + val = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4); + val &= ~DCFG_PORSR1_RCW_SRC; + val |= DCFG_PORSR1_RCW_SRC_NOR; + out_le32(dcfg_dcsr + DCFG_DCSR_PORCR1 / 4, val); +#endif +} + void fsl_lsch3_early_init_f(void) { erratum_a008751(); + erratum_rcw_src(); init_early_memctl_regs(); /* tighten IFC timing */ } + +#ifdef CONFIG_SPL_BUILD +void board_init_f(ulong dummy) +{ + /* Clear global data */ + memset((void *)gd, 0, sizeof(gd_t)); + + arch_cpu_init(); + board_early_init_f(); + timer_init(); + env_init(); + gd->baudrate = getenv_ulong("baudrate", 10, CONFIG_BAUDRATE); + + serial_init(); + console_init_f(); + dram_init(); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + board_init_r(NULL, 0); +} + +u32 spl_boot_device(void) +{ + return BOOT_DEVICE_NAND; +} +#endif diff --git a/arch/arm/cpu/armv8/u-boot-spl.lds b/arch/arm/cpu/armv8/u-boot-spl.lds new file mode 100644 index 0000000..4df339c --- /dev/null +++ b/arch/arm/cpu/armv8/u-boot-spl.lds @@ -0,0 +1,77 @@ +/* + * (C) Copyright 2013 + * David Feng + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * (C) Copyright 2010 + * Texas Instruments, + * Aneesh V + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE, + LENGTH = CONFIG_SPL_MAX_SIZE } +MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, + LENGTH = CONFIG_SPL_BSS_MAX_SIZE } + +OUTPUT_FORMAT("elf64-littleaarch64", "elf64-littleaarch64", "elf64-littleaarch64") +OUTPUT_ARCH(aarch64) +ENTRY(_start) +SECTIONS +{ + .text : { + . = ALIGN(8); + *(.__image_copy_start) + CPUDIR/start.o (.text*) + *(.text*) + } >.sram + + .rodata : { + . = ALIGN(8); + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) + } >.sram + + .data : { + . = ALIGN(8); + *(.data*) + } >.sram + + .u_boot_list : { + . = ALIGN(8); + KEEP(*(SORT(.u_boot_list*))); + } >.sram + + .image_copy_end : { + . = ALIGN(8); + *(.__image_copy_end) + } >.sram + + .end : { + . = ALIGN(8); + *(.__end) + } >.sram + + .bss_start : { + . = ALIGN(8); + KEEP(*(.__bss_start)); + } >.sdram + + .bss : { + *(.bss*) + . = ALIGN(8); + } >.sdram + + .bss_end : { + KEEP(*(.__bss_end)); + } >.sdram + + /DISCARD/ : { *(.dynsym) } + /DISCARD/ : { *(.dynstr*) } + /DISCARD/ : { *(.dynamic*) } + /DISCARD/ : { *(.plt*) } + /DISCARD/ : { *(.interp*) } + /DISCARD/ : { *(.gnu*) } +} diff --git a/arch/arm/include/asm/arch-fsl-lsch3/config.h b/arch/arm/include/asm/arch-fsl-lsch3/config.h index 403b2ef..77c20ab 100644 --- a/arch/arm/include/asm/arch-fsl-lsch3/config.h +++ b/arch/arm/include/asm/arch-fsl-lsch3/config.h @@ -130,6 +130,15 @@ #define CCI_MN_DVM_DOMAIN_CTL 0x200 #define CCI_MN_DVM_DOMAIN_CTL_SET 0x210 +/* Device Configuration */ +#define DCFG_BASE 0x01e00000 +#define DCFG_PORSR1 0x000 +#define DCFG_PORSR1_RCW_SRC 0xff800000 +#define DCFG_PORSR1_RCW_SRC_NOR 0x12f00000 + +#define DCFG_DCSR_BASE 0X700100000ULL +#define DCFG_DCSR_PORCR1 0x000 + /* Supplemental Configuration */ #define SCFG_BASE 0x01fc0000 #define SCFG_USB3PRM1CR 0x000 diff --git a/arch/arm/lib/crt0_64.S b/arch/arm/lib/crt0_64.S index 1654011..bc9c53c 100644 --- a/arch/arm/lib/crt0_64.S +++ b/arch/arm/lib/crt0_64.S @@ -61,7 +61,11 @@ ENTRY(_main) /* * Set up initial C runtime environment and call board_init_f(0). */ +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK) + ldr x0, =(CONFIG_SPL_STACK) +#else ldr x0, =(CONFIG_SYS_INIT_SP_ADDR) +#endif sub x18, x0, #GD_SIZE /* allocate one GD above SP */ bic x18, x18, #0x7 /* 8-byte alignment for GD */ zero_gd: @@ -77,6 +81,7 @@ zero_gd: mov x0, #0 bl board_init_f +#if !defined(CONFIG_SPL_BUILD) /* * Set up intermediate environment (new sp and gd) and call * relocate_code(addr_moni). Trick here is that we'll return @@ -119,4 +124,6 @@ clear_loop: /* NOTREACHED - board_init_r() does not return */ +#endif /* !CONFIG_SPL_BUILD */ + ENDPROC(_main) -- cgit v1.1 From 32eda7cc945212ba8df569e399b0361b32676ac2 Mon Sep 17 00:00:00 2001 From: Scott Wood Date: Tue, 24 Mar 2015 13:25:03 -0700 Subject: armv8/ls2085ardb: Enable NAND SPL support Enable NAND boot support using SPL framework. To boot from NAND, either use DIP switches on board, or "qixis_reset nand" command. Details of forming NAND image can be found in README. Signed-off-by: Scott Wood [York Sun: Remove +S from defconfig after commit 252ed872] Signed-off-by: York Sun --- arch/arm/Kconfig | 1 + arch/arm/cpu/armv8/fsl-lsch3/README | 13 +++++++++++++ 2 files changed, 14 insertions(+) (limited to 'arch') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 4b7761d..844b862 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -726,6 +726,7 @@ config TARGET_LS2085ARDB bool "Support ls2085ardb" select ARM64 select ARMV8_MULTIENTRY + select SUPPORT_SPL help Support for Freescale LS2085ARDB platform. The LS2085A Reference design board (RDB) is a high-performance diff --git a/arch/arm/cpu/armv8/fsl-lsch3/README b/arch/arm/cpu/armv8/fsl-lsch3/README index 15a1549..37f07fb 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/README +++ b/arch/arm/cpu/armv8/fsl-lsch3/README @@ -133,3 +133,16 @@ The u-boot image should be written to match SRC_ADDR, in above example 0x20000. nand write 200000 With these two images in NAND device, the board can boot from NAND. + +Another example for RDB boards, + +1) CCSR 4-byte write to 0x00e00404, data=0x00000000 +2) CCSR 4-byte write to 0x00e00400, data=0x1800a000 +3) Block Copy: SRC=0x0119, SRC_ADDR=0x00080000, DEST_ADDR=0x1800a000, +BLOCK_SIZE=0x00014000 + +nand write 0 +nand write 80000 + +Notice the difference from QDS is SRC, SRC_ADDR and the offset of u-boot image +to match board NAND device with 4KB/page, block size 512KB. -- cgit v1.1 From 8b06460e5518eeec449298c91fb1424b36c9b305 Mon Sep 17 00:00:00 2001 From: Yangbo Lu Date: Fri, 20 Mar 2015 19:28:31 -0700 Subject: ls2085a: esdhc: Add esdhc support for ls2085a This patch adds esdhc support for ls2085a. Signed-off-by: Yangbo Lu Signed-off-by: York Sun --- arch/arm/cpu/armv8/fsl-lsch3/cpu.c | 10 ++++++++++ arch/arm/cpu/armv8/fsl-lsch3/fdt.c | 7 +++++++ arch/arm/include/asm/arch-fsl-lsch3/config.h | 2 ++ 3 files changed, 19 insertions(+) (limited to 'arch') diff --git a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c index 07064a3..6714577 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c +++ b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c @@ -13,6 +13,9 @@ #include #include #include +#ifdef CONFIG_FSL_ESDHC +#include +#endif #include "cpu.h" #include "mp.h" #include "speed.h" @@ -412,6 +415,13 @@ int print_cpuinfo(void) } #endif +#ifdef CONFIG_FSL_ESDHC +int cpu_mmc_init(bd_t *bis) +{ + return fsl_esdhc_mmc_init(bis); +} +#endif + int cpu_eth_init(bd_t *bis) { int error = 0; diff --git a/arch/arm/cpu/armv8/fsl-lsch3/fdt.c b/arch/arm/cpu/armv8/fsl-lsch3/fdt.c index 42c5b58..d370023 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/fdt.c +++ b/arch/arm/cpu/armv8/fsl-lsch3/fdt.c @@ -7,6 +7,9 @@ #include #include #include +#ifdef CONFIG_FSL_ESDHC +#include +#endif #include "mp.h" #ifdef CONFIG_MP @@ -65,4 +68,8 @@ void ft_cpu_setup(void *blob, bd_t *bd) do_fixup_by_compat_u32(blob, "fsl,ns16550", "clock-frequency", CONFIG_SYS_NS16550_CLK, 1); #endif + +#if defined(CONFIG_FSL_ESDHC) + fdt_fixup_esdhc(blob, bd); +#endif } diff --git a/arch/arm/include/asm/arch-fsl-lsch3/config.h b/arch/arm/include/asm/arch-fsl-lsch3/config.h index 77c20ab..ca8d38c 100644 --- a/arch/arm/include/asm/arch-fsl-lsch3/config.h +++ b/arch/arm/include/asm/arch-fsl-lsch3/config.h @@ -31,6 +31,7 @@ #define CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR (CONFIG_SYS_IMMR + 0x00300000) #define CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR (CONFIG_SYS_IMMR + 0x00310000) #define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR (CONFIG_SYS_IMMR + 0x00370000) +#define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x01140000) #define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x01240000) #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011C0500) #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011C0600) @@ -110,6 +111,7 @@ #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS2_DDR_BLOCK1_SIZE #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 +#define CONFIG_SYS_FSL_ESDHC_LE /* IFC */ #define CONFIG_SYS_FSL_IFC_LE #define CONFIG_SYS_MEMAC_LITTLE_ENDIAN -- cgit v1.1 From ab10d73d2fc13bd5baf5024e54ad92641d238bdb Mon Sep 17 00:00:00 2001 From: York Sun Date: Mon, 23 Mar 2015 10:41:35 -0700 Subject: armv8/fsl-lsch3: Implement workaround for I2C erratum A009203 This erratum requires setting GLITCH_EN bit in debug register to enable digital filter to improve clock stability. Signed-off-by: York Sun CC: Heiko Schocher --- arch/arm/cpu/armv8/fsl-lsch3/soc.c | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) (limited to 'arch') diff --git a/arch/arm/cpu/armv8/fsl-lsch3/soc.c b/arch/arm/cpu/armv8/fsl-lsch3/soc.c index ca00108..2538001 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/soc.c +++ b/arch/arm/cpu/armv8/fsl-lsch3/soc.c @@ -37,11 +37,45 @@ static void erratum_rcw_src(void) #endif } +#define I2C_DEBUG_REG 0x6 +#define I2C_GLITCH_EN 0x8 +/* + * This erratum requires setting glitch_en bit to enable + * digital glitch filter to improve clock stability. + */ +static void erratum_a009203(void) +{ + u8 __iomem *ptr; +#ifdef CONFIG_SYS_I2C +#ifdef I2C1_BASE_ADDR + ptr = (u8 __iomem *)(I2C1_BASE_ADDR + I2C_DEBUG_REG); + + writeb(I2C_GLITCH_EN, ptr); +#endif +#ifdef I2C2_BASE_ADDR + ptr = (u8 __iomem *)(I2C2_BASE_ADDR + I2C_DEBUG_REG); + + writeb(I2C_GLITCH_EN, ptr); +#endif +#ifdef I2C3_BASE_ADDR + ptr = (u8 __iomem *)(I2C3_BASE_ADDR + I2C_DEBUG_REG); + + writeb(I2C_GLITCH_EN, ptr); +#endif +#ifdef I2C4_BASE_ADDR + ptr = (u8 __iomem *)(I2C4_BASE_ADDR + I2C_DEBUG_REG); + + writeb(I2C_GLITCH_EN, ptr); +#endif +#endif +} + void fsl_lsch3_early_init_f(void) { erratum_a008751(); erratum_rcw_src(); init_early_memctl_regs(); /* tighten IFC timing */ + erratum_a009203(); } #ifdef CONFIG_SPL_BUILD -- cgit v1.1