From 762a88ccf8540948fbf8c31b40a29d1e0684a25b Mon Sep 17 00:00:00 2001 From: Pierre Aubert Date: Thu, 19 Sep 2013 17:48:59 +0200 Subject: mx6: compute PLL PFD frequencies rather than using defines Signed-off-by: Pierre Aubert CC: Stefano Babic --- arch/arm/cpu/armv7/mx6/clock.c | 56 ++++++++++++++++++++++++-------- arch/arm/include/asm/arch-mx6/crm_regs.h | 11 ------- 2 files changed, 42 insertions(+), 25 deletions(-) (limited to 'arch') diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index df11678..3bf80e2 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -100,6 +100,32 @@ static u32 decode_pll(enum pll_clocks pll, u32 infreq) } /* NOTREACHED */ } +static u32 mxc_get_pll_pfd(enum pll_clocks pll, int pfd_num) +{ + u32 div; + u64 freq; + + switch (pll) { + case PLL_BUS: + if (pfd_num == 3) { + /* No PFD3 on PPL2 */ + return 0; + } + div = __raw_readl(&imx_ccm->analog_pfd_528); + freq = (u64)decode_pll(PLL_BUS, MXC_HCLK); + break; + case PLL_USBOTG: + div = __raw_readl(&imx_ccm->analog_pfd_480); + freq = (u64)decode_pll(PLL_USBOTG, MXC_HCLK); + break; + default: + /* No PFD on other PLL */ + return 0; + } + + return (freq * 18) / ((div & ANATOP_PFD_FRAC_MASK(pfd_num)) >> + ANATOP_PFD_FRAC_SHIFT(pfd_num)); +} static u32 get_mcu_main_clk(void) { @@ -144,13 +170,14 @@ u32 get_periph_clk(void) freq = decode_pll(PLL_BUS, MXC_HCLK); break; case 1: - freq = PLL2_PFD2_FREQ; + freq = mxc_get_pll_pfd(PLL_BUS, 2); break; case 2: - freq = PLL2_PFD0_FREQ; + freq = mxc_get_pll_pfd(PLL_BUS, 0); break; case 3: - freq = PLL2_PFD2_DIV_FREQ; + /* static / 2 divider */ + freq = mxc_get_pll_pfd(PLL_BUS, 2) / 2; break; default: break; @@ -184,7 +211,7 @@ static u32 get_ipg_per_clk(void) static u32 get_uart_clk(void) { u32 reg, uart_podf; - u32 freq = PLL3_80M; + u32 freq = decode_pll(PLL_USBOTG, MXC_HCLK) / 6; /* static divider */ reg = __raw_readl(&imx_ccm->cscdr1); #ifdef CONFIG_MX6SL if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL) @@ -204,7 +231,7 @@ static u32 get_cspi_clk(void) reg &= MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK; cspi_podf = reg >> MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET; - return PLL3_60M / (cspi_podf + 1); + return decode_pll(PLL_USBOTG, MXC_HCLK) / (8 * (cspi_podf + 1)); } static u32 get_axi_clk(void) @@ -217,9 +244,9 @@ static u32 get_axi_clk(void) if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) { if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL) - root_freq = PLL2_PFD2_FREQ; + root_freq = mxc_get_pll_pfd(PLL_BUS, 2); else - root_freq = PLL3_PFD1_FREQ; + root_freq = mxc_get_pll_pfd(PLL_USBOTG, 1); } else root_freq = get_periph_clk(); @@ -244,10 +271,10 @@ static u32 get_emi_slow_clk(void) root_freq = decode_pll(PLL_USBOTG, MXC_HCLK); break; case 2: - root_freq = PLL2_PFD2_FREQ; + root_freq = mxc_get_pll_pfd(PLL_BUS, 2); break; case 3: - root_freq = PLL2_PFD0_FREQ; + root_freq = mxc_get_pll_pfd(PLL_BUS, 0); break; } @@ -270,13 +297,14 @@ static u32 get_mmdc_ch0_clk(void) freq = decode_pll(PLL_BUS, MXC_HCLK); break; case 1: - freq = PLL2_PFD2_FREQ; + freq = mxc_get_pll_pfd(PLL_BUS, 2); break; case 2: - freq = PLL2_PFD0_FREQ; + freq = mxc_get_pll_pfd(PLL_BUS, 0); break; case 3: - freq = PLL2_PFD2_DIV_FREQ; + /* static / 2 divider */ + freq = mxc_get_pll_pfd(PLL_BUS, 2) / 2; } return freq / (podf + 1); @@ -359,9 +387,9 @@ static u32 get_usdhc_clk(u32 port) } if (clk_sel) - root_freq = PLL2_PFD0_FREQ; + root_freq = mxc_get_pll_pfd(PLL_BUS, 0); else - root_freq = PLL2_PFD2_FREQ; + root_freq = mxc_get_pll_pfd(PLL_BUS, 2); return root_freq / (usdhc_podf + 1); } diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h index 2813593..7202073 100644 --- a/arch/arm/include/asm/arch-mx6/crm_regs.h +++ b/arch/arm/include/asm/arch-mx6/crm_regs.h @@ -890,15 +890,4 @@ struct mxc_ccm_reg { #define BF_ANADIG_PFD_528_PFD0_FRAC(v) \ (((v) << 0) & BM_ANADIG_PFD_528_PFD0_FRAC) -#define PLL2_PFD0_FREQ 352000000 -#define PLL2_PFD1_FREQ 594000000 -#define PLL2_PFD2_FREQ 396000000 -#define PLL2_PFD2_DIV_FREQ 200000000 -#define PLL3_PFD0_FREQ 720000000 -#define PLL3_PFD1_FREQ 540000000 -#define PLL3_PFD2_FREQ 508200000 -#define PLL3_PFD3_FREQ 454700000 -#define PLL3_80M 80000000 -#define PLL3_60M 60000000 - #endif /*__ARCH_ARM_MACH_MX6_CCM_REGS_H__ */ -- cgit v1.1 From 6654f33c9b520bd4073c7f82a13044e79bc14898 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 24 Sep 2013 17:39:17 +0200 Subject: ARM: mxs: tools: Use mkimage for BootStream generation Now that mkimage can generate an BootStream for i.MX23 and i.MX28, use the mkimage as a default tool to generate the BootStreams instead of the elftosb tool. This cuts out another obscure dependency. Signed-off-by: Marek Vasut Cc: Fabio Estevam Cc: Otavio Salvador Cc: Stefano Babic --- arch/arm/cpu/arm926ejs/mxs/Makefile | 11 ++++++----- arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg | 4 ++-- arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg | 4 ++-- 3 files changed, 10 insertions(+), 9 deletions(-) (limited to 'arch') diff --git a/arch/arm/cpu/arm926ejs/mxs/Makefile b/arch/arm/cpu/arm926ejs/mxs/Makefile index 3d66892..ea397c7 100644 --- a/arch/arm/cpu/arm926ejs/mxs/Makefile +++ b/arch/arm/cpu/arm926ejs/mxs/Makefile @@ -25,14 +25,15 @@ $(LIB): $(OBJS) $(call cmd_link_o_target, $(OBJS)) # Specify the target for use in elftosb call -ELFTOSB_TARGET-$(CONFIG_MX23) = imx23 -ELFTOSB_TARGET-$(CONFIG_MX28) = imx28 +MKIMAGE_TARGET-$(CONFIG_MX23) = mx23 +MKIMAGE_TARGET-$(CONFIG_MX28) = mx28 -$(OBJTREE)/u-boot.bd: $(SRCTREE)/$(CPUDIR)/$(SOC)/u-boot-$(ELFTOSB_TARGET-y).bd +$(OBJTREE)/mxsimage.cfg: $(SRCTREE)/$(CPUDIR)/$(SOC)/mxsimage.$(MKIMAGE_TARGET-y).cfg sed "s@OBJTREE@$(OBJTREE)@g" $^ > $@ -$(OBJTREE)/u-boot.sb: $(OBJTREE)/u-boot.bin $(OBJTREE)/spl/u-boot-spl.bin $(OBJTREE)/u-boot.bd - elftosb -zf $(ELFTOSB_TARGET-y) -c $(OBJTREE)/u-boot.bd -o $(OBJTREE)/u-boot.sb +$(OBJTREE)/u-boot.sb: $(OBJTREE)/u-boot.bin $(OBJTREE)/spl/u-boot-spl.bin $(OBJTREE)/mxsimage.cfg + $(OBJTREE)/tools/mkimage -n $(OBJTREE)/mxsimage.cfg -T mxsimage $@ + ######################################################################### diff --git a/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg b/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg index 8118767..c9cf4b3 100644 --- a/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg +++ b/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg @@ -1,6 +1,6 @@ SECTION 0x0 BOOTABLE TAG LAST - LOAD 0x0 spl/u-boot-spl.bin + LOAD 0x0 OBJTREE/spl/u-boot-spl.bin CALL 0x14 0x0 - LOAD 0x40000100 u-boot.bin + LOAD 0x40000100 OBJTREE/u-boot.bin CALL 0x40000100 0x0 diff --git a/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg b/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg index ea772f0..676f5c8 100644 --- a/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg +++ b/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg @@ -1,8 +1,8 @@ SECTION 0x0 BOOTABLE TAG LAST - LOAD 0x0 spl/u-boot-spl.bin + LOAD 0x0 OBJTREE/spl/u-boot-spl.bin LOAD IVT 0x8000 0x14 CALL HAB 0x8000 0x0 - LOAD 0x40000100 u-boot.bin + LOAD 0x40000100 OBJTREE/u-boot.bin LOAD IVT 0x8000 0x40000100 CALL HAB 0x8000 0x0 -- cgit v1.1 From 77b0e2239a13fa83a745ea9b03994bf780a9738a Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 20 Sep 2013 01:36:44 +0200 Subject: ARM: mxs: Setup stack in JTAG mode In case the MX23/MX28 is switched into JTAG mode via the BootMode select switches, the BootROM bypasses the CPU core registers initialization. This in turn means that the Stack Pointer (SP) register is not set as it is in every other mode of operation, but instead is only zeroed out. To prevent U-Boot SPL from crashing in this obscure JTAG mode, configure the SP to point at the CONFIG_SYS_INIT_SP_ADDR if the SP is zeroed out. Note that in case the SP is already configured, we must preserve that exact SP value and must not modify it. This is important since in every other mode but the JTAG mode, the SPL returns into the BootROM and BootROM in turn loads U-Boot itself. If the SP were to be corrupted, the BootROM won't be able to continue it's operation after returned from SPL and the system would crash. Finally, add the JTAG mode switch identifier, so it's not recognised as Unknown mode. Signed-off-by: Marek Vasut Cc: Stefano Babic Cc: Fabio Estevam Cc: Otavio Salvador --- arch/arm/cpu/arm926ejs/mxs/start.S | 9 +++++++++ arch/arm/include/asm/arch-mxs/sys_proto.h | 2 ++ 2 files changed, 11 insertions(+) (limited to 'arch') diff --git a/arch/arm/cpu/arm926ejs/mxs/start.S b/arch/arm/cpu/arm926ejs/mxs/start.S index 3e454ae..5de2bad 100644 --- a/arch/arm/cpu/arm926ejs/mxs/start.S +++ b/arch/arm/cpu/arm926ejs/mxs/start.S @@ -150,6 +150,15 @@ IRQ_STACK_START_IN: _reset: /* + * If the CPU is configured in "Wait JTAG connection mode", the stack + * pointer is not configured and is zero. This will cause crash when + * trying to push data onto stack right below here. Load the SP and make + * it point to the end of OCRAM if the SP is zero. + */ + cmp sp, #0x00000000 + ldreq sp, =CONFIG_SYS_INIT_SP_ADDR + + /* * Store all registers on old stack pointer, this will allow us later to * return to the BootROM and let the BootROM load U-Boot into RAM. * diff --git a/arch/arm/include/asm/arch-mxs/sys_proto.h b/arch/arm/include/asm/arch-mxs/sys_proto.h index 43c7dd6..09dfc90 100644 --- a/arch/arm/include/asm/arch-mxs/sys_proto.h +++ b/arch/arm/include/asm/arch-mxs/sys_proto.h @@ -46,6 +46,7 @@ static const struct mxs_pair mxs_boot_modes[] = { { 0x02, 0x1f, "SSP SPI #1, master, NOR" }, { 0x03, 0x1f, "SSP SPI #2, master, NOR" }, { 0x04, 0x1f, "NAND" }, + { 0x06, 0x1f, "JTAG" }, { 0x08, 0x1f, "SSP SPI #3, master, EEPROM" }, { 0x09, 0x1f, "SSP SD/MMC #0" }, { 0x0a, 0x1f, "SSP SD/MMC #1" }, @@ -60,6 +61,7 @@ static const struct mxs_pair mxs_boot_modes[] = { { 0x13, 0x1f, "SSP SPI #3, master, 1V8 NOR" }, { 0x04, 0x1f, "NAND, 3V3" }, { 0x14, 0x1f, "NAND, 1V8" }, + { 0x06, 0x1f, "JTAG" }, { 0x08, 0x1f, "SSP SPI #3, master, 3V3 EEPROM" }, { 0x18, 0x1f, "SSP SPI #3, master, 1V8 EEPROM" }, { 0x09, 0x1f, "SSP SD/MMC #0, 3V3" }, -- cgit v1.1 From 4867b634b7c0e5ede258b4998fa4b2710e7daacf Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 30 Sep 2013 13:16:52 -0300 Subject: ARM: mx5: Enable L2 cache Enable L2 cache for improving the system performance. Signed-off-by: Fabio Estevam --- arch/arm/cpu/armv7/mx5/lowlevel_init.S | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch') diff --git a/arch/arm/cpu/armv7/mx5/lowlevel_init.S b/arch/arm/cpu/armv7/mx5/lowlevel_init.S index 25fadf6..97077fd 100644 --- a/arch/arm/cpu/armv7/mx5/lowlevel_init.S +++ b/arch/arm/cpu/armv7/mx5/lowlevel_init.S @@ -45,6 +45,12 @@ #endif mcr 15, 1, r0, c9, c0, 2 + + /* enable L2 cache */ + mrc 15, 0, r0, c1, c0, 1 + orr r0, r0, #2 + mcr 15, 0, r0, c1, c0, 1 + .endm /* init_l2cc */ /* AIPS setup - Only setup MPROTx registers. -- cgit v1.1 From 357efe69e9d70bd510d7a1720bf2d0084ec5e91e Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 30 Sep 2013 18:28:54 -0300 Subject: mx5: lowlevel_init: Remove unused macro setup_wdog macro is not used anywhere, so just remove it. Signed-off-by: Fabio Estevam Acked-by: Stefano Babic --- arch/arm/cpu/armv7/mx5/lowlevel_init.S | 6 ------ 1 file changed, 6 deletions(-) (limited to 'arch') diff --git a/arch/arm/cpu/armv7/mx5/lowlevel_init.S b/arch/arm/cpu/armv7/mx5/lowlevel_init.S index 97077fd..f5bc672 100644 --- a/arch/arm/cpu/armv7/mx5/lowlevel_init.S +++ b/arch/arm/cpu/armv7/mx5/lowlevel_init.S @@ -375,12 +375,6 @@ setup_pll_func: #endif /* CONFIG_MX53 */ .endm -.macro setup_wdog - ldr r0, =WDOG1_BASE_ADDR - mov r1, #0x30 - strh r1, [r0] -.endm - ENTRY(lowlevel_init) mov r10, lr mov r4, #0 /* Fix R4 to 0 */ -- cgit v1.1 From 0029bc47ad7bb2e61121335052fed88b0be1824d Mon Sep 17 00:00:00 2001 From: Otavio Salvador Date: Mon, 21 Oct 2013 21:34:57 -0200 Subject: mx6: Remove PAD_CTL_DSE_120ohm from i.MX6DL's IPU1_DI0_PIN4 pin This removes the PAD_CTL_DSE_120ohm as done for i.MX6Q's IPU1_DI0_PIN4 pin definition and makes it aligned with 3.0.35-4.1.0 and 3.12 mainline kernel. Signed-off-by: Otavio Salvador --- arch/arm/include/asm/arch-mx6/mx6dl_pins.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/include/asm/arch-mx6/mx6dl_pins.h b/arch/arm/include/asm/arch-mx6/mx6dl_pins.h index b5df68a..7373407 100644 --- a/arch/arm/include/asm/arch-mx6/mx6dl_pins.h +++ b/arch/arm/include/asm/arch-mx6/mx6dl_pins.h @@ -210,7 +210,7 @@ enum { MX6_PAD_DI0_PIN3__MMDC_MMDC_DEBUG_3 = IOMUX_PAD(0x03BC, 0x00A8, 6, 0x0000, 0, 0), MX6_PAD_DI0_PIN3__PL301_SIM_MX6DL_PER1_HADDR_10 = IOMUX_PAD(0x03BC, 0x00A8, 7, 0x0000, 0, 0), MX6_PAD_DI0_PIN3__LCDIF_CS = IOMUX_PAD(0x03BC, 0x00A8, 8, 0x0000, 0, 0), - MX6_PAD_DI0_PIN4__IPU1_DI0_PIN4 = IOMUX_PAD(0x03C0, 0x00AC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DI0_PIN4__IPU1_DI0_PIN4 = IOMUX_PAD(0x03C0, 0x00AC, 0, 0x0000, 0, 0), MX6_PAD_DI0_PIN4__LCDIF_BUSY = IOMUX_PAD(0x03C0, 0x00AC, 1, 0x08D8, 1, 0), MX6_PAD_DI0_PIN4__AUDMUX_AUD6_RXD = IOMUX_PAD(0x03C0, 0x00AC, 2, 0x0000, 0, 0), MX6_PAD_DI0_PIN4__USDHC1_WP = IOMUX_PAD(0x03C0, 0x00AC, 3, 0x092C, 0, 0), -- cgit v1.1 From a0f97610757d6370fc58849032b36a94b4167fdc Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 28 Oct 2013 12:29:30 +0100 Subject: ARM: mxs: Enable DCDC converter for battery boot In case the board detected sufficient voltage for battery boot, make sure the DCDC converter is ON and the board is not running only from linregs, otherwise an instability will be observed. Signed-off-by: Marek Vasut Cc: Stefano Babic Cc: Fabio Estevam --- arch/arm/cpu/arm926ejs/mxs/spl_power_init.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch') diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c index 8ea45be..d25019a 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c @@ -654,6 +654,8 @@ static void mxs_batt_boot(void) clrsetbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK, 0x8 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET); + + mxs_power_enable_4p2(); } /** -- cgit v1.1