From 6224dc9ba428a7b7f7433d2bfd7bdf070b5bf06f Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 24 Jan 2021 14:32:47 -0700 Subject: arm: Remove vital devices last Update announce_and_cleanup() to remove all devices, with the vital ones being removed last. This is an extra patch on top of the recent RFC: http://patchwork.ozlabs.org/project/uboot/list/?series=223280 Signed-off-by: Simon Glass --- arch/arm/lib/bootm.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch') diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c index 1206e30..f46d51d 100644 --- a/arch/arm/lib/bootm.c +++ b/arch/arm/lib/bootm.c @@ -119,6 +119,9 @@ static void announce_and_cleanup(int fake) * This may be useful for last-stage operations, like cancelling * of DMA operation or releasing device internal buffers. */ + dm_remove_devices_flags(DM_REMOVE_ACTIVE_ALL | DM_REMOVE_NON_VITAL); + + /* Remove all active vital devices next */ dm_remove_devices_flags(DM_REMOVE_ACTIVE_ALL); cleanup_before_linux(); -- cgit v1.1 From 85c714d8dcd56f63c2c0ae1b0f6a7e4a96c918a4 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Sun, 31 Jan 2021 20:35:57 +0800 Subject: riscv: Adjust board_get_usable_ram_top() for 32-bit When testing QEMU RISC-V 'virt' machine with a 2 GiB memory configuration, it was discovered gd->ram_top is assigned to value zero in setup_dest_addr(). While gd->ram_top should not be declared as type `unsigned long`, which will be updated in a future patch, the current logic in board_get_usable_ram_top() can be updated to cover both 64-bit and 32-bit RISC-V. Signed-off-by: Bin Meng --- arch/riscv/cpu/fu540/dram.c | 7 +++---- arch/riscv/cpu/generic/dram.c | 7 +++---- 2 files changed, 6 insertions(+), 8 deletions(-) (limited to 'arch') diff --git a/arch/riscv/cpu/fu540/dram.c b/arch/riscv/cpu/fu540/dram.c index 1dc77ef..259da65 100644 --- a/arch/riscv/cpu/fu540/dram.c +++ b/arch/riscv/cpu/fu540/dram.c @@ -22,7 +22,6 @@ int dram_init_banksize(void) ulong board_get_usable_ram_top(ulong total_size) { -#ifdef CONFIG_64BIT /* * Ensure that we run from first 4GB so that all * addresses used by U-Boot are 32bit addresses. @@ -31,8 +30,8 @@ ulong board_get_usable_ram_top(ulong total_size) * devices work fine because DMA mapping APIs will * provide 32bit DMA addresses only. */ - if (gd->ram_top > SZ_4G) - return SZ_4G; -#endif + if (gd->ram_top >= SZ_4G) + return SZ_4G - 1; + return gd->ram_top; } diff --git a/arch/riscv/cpu/generic/dram.c b/arch/riscv/cpu/generic/dram.c index 1dc77ef..259da65 100644 --- a/arch/riscv/cpu/generic/dram.c +++ b/arch/riscv/cpu/generic/dram.c @@ -22,7 +22,6 @@ int dram_init_banksize(void) ulong board_get_usable_ram_top(ulong total_size) { -#ifdef CONFIG_64BIT /* * Ensure that we run from first 4GB so that all * addresses used by U-Boot are 32bit addresses. @@ -31,8 +30,8 @@ ulong board_get_usable_ram_top(ulong total_size) * devices work fine because DMA mapping APIs will * provide 32bit DMA addresses only. */ - if (gd->ram_top > SZ_4G) - return SZ_4G; -#endif + if (gd->ram_top >= SZ_4G) + return SZ_4G - 1; + return gd->ram_top; } -- cgit v1.1 From 65f354cd8df614e1262fe05691543b1947e5091c Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Sun, 31 Jan 2021 20:35:58 +0800 Subject: arm: rockchip: Explicitly cast gd->ram_top in dram_init_banksize() The min() macro used in dram_init_banksize() requires two elements to compare have the same type. Let's explicitly cast gd->ram_top. Signed-off-by: Bin Meng --- arch/arm/mach-rockchip/sdram.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-rockchip/sdram.c b/arch/arm/mach-rockchip/sdram.c index 4c637b7..c3d5fed 100644 --- a/arch/arm/mach-rockchip/sdram.c +++ b/arch/arm/mach-rockchip/sdram.c @@ -37,7 +37,7 @@ struct tos_parameter_t { int dram_init_banksize(void) { size_t top = min((unsigned long)(gd->ram_size + CONFIG_SYS_SDRAM_BASE), - gd->ram_top); + (unsigned long)(gd->ram_top)); #ifdef CONFIG_ARM64 /* Reserve 0x200000 for ATF bl31 */ -- cgit v1.1 From 86c915628d582a36029ff1f6c4443b6e81e0d51f Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Sun, 31 Jan 2021 20:36:04 +0800 Subject: riscv: Change phys_addr_t and phys_size_t to 64-bit phys_addr_t and phys_size_t are currently defined as `unsigned long`, but RV32 supports 34-bit physical address, hence both phys_addr_t and phys_size_t should be defined to 64-bit using `unsigned long long`. Signed-off-by: Bin Meng --- arch/riscv/include/asm/types.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/riscv/include/asm/types.h b/arch/riscv/include/asm/types.h index b800b2d..49f7a5d 100644 --- a/arch/riscv/include/asm/types.h +++ b/arch/riscv/include/asm/types.h @@ -35,8 +35,8 @@ typedef u64 dma_addr_t; typedef u32 dma_addr_t; #endif -typedef unsigned long phys_addr_t; -typedef unsigned long phys_size_t; +typedef unsigned long long phys_addr_t; +typedef unsigned long long phys_size_t; #endif /* __KERNEL__ */ -- cgit v1.1 From 98592c7509278e73b2d56c5e307015d6f33c0f34 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Sun, 31 Jan 2021 20:36:05 +0800 Subject: bdinfo: Rename function names to be clearer At present we have bdinfo_print_num() to print unsigned long numbers. We also have print_phys_addr() which accept numbers that might be 64-bit on a 32-bit platform. Rename these 2 functions to be clearer: bdinfo_print_num() => bdinfo_print_num_l() print_phys_addr() => bdinfo_print_num_ll() While we are here, make bdinfo_print_num_ll() public so that it can be used outside cmd/bdinfo.c in the future. Signed-off-by: Bin Meng --- arch/arm/lib/bdinfo.c | 16 ++++++++-------- arch/m68k/lib/bdinfo.c | 2 +- arch/powerpc/lib/bdinfo.c | 4 ++-- 3 files changed, 11 insertions(+), 11 deletions(-) (limited to 'arch') diff --git a/arch/arm/lib/bdinfo.c b/arch/arm/lib/bdinfo.c index 25bc6e8..4a98cb7 100644 --- a/arch/arm/lib/bdinfo.c +++ b/arch/arm/lib/bdinfo.c @@ -15,23 +15,23 @@ void arch_print_bdinfo(void) { struct bd_info *bd = gd->bd; - bdinfo_print_num("arch_number", bd->bi_arch_number); + bdinfo_print_num_l("arch_number", bd->bi_arch_number); #ifdef CONFIG_SYS_MEM_RESERVE_SECURE if (gd->arch.secure_ram & MEM_RESERVE_SECURE_SECURED) { - bdinfo_print_num("Secure ram", - gd->arch.secure_ram & - MEM_RESERVE_SECURE_ADDR_MASK); + bdinfo_print_num_l("Secure ram", + gd->arch.secure_ram & + MEM_RESERVE_SECURE_ADDR_MASK); } #endif #ifdef CONFIG_RESV_RAM if (gd->arch.resv_ram) - bdinfo_print_num("Reserved ram", gd->arch.resv_ram); + bdinfo_print_num_l("Reserved ram", gd->arch.resv_ram); #endif #if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) - bdinfo_print_num("TLB addr", gd->arch.tlb_addr); + bdinfo_print_num_l("TLB addr", gd->arch.tlb_addr); #endif - bdinfo_print_num("irq_sp", gd->irq_sp); /* irq stack pointer */ - bdinfo_print_num("sp start ", gd->start_addr_sp); + bdinfo_print_num_l("irq_sp", gd->irq_sp); /* irq stack pointer */ + bdinfo_print_num_l("sp start ", gd->start_addr_sp); /* * TODO: Currently only support for davinci SOC's is added. * Remove this check once all the board implement this. diff --git a/arch/m68k/lib/bdinfo.c b/arch/m68k/lib/bdinfo.c index 404e5f1..92ea175 100644 --- a/arch/m68k/lib/bdinfo.c +++ b/arch/m68k/lib/bdinfo.c @@ -38,7 +38,7 @@ void arch_print_bdinfo(void) bdinfo_print_mhz("busfreq", bd->bi_busfreq); #if defined(CONFIG_SYS_MBAR) - bdinfo_print_num("mbar", bd->bi_mbar_base); + bdinfo_print_num_l("mbar", bd->bi_mbar_base); #endif bdinfo_print_mhz("cpufreq", bd->bi_intfreq); if (IS_ENABLED(CONFIG_PCI)) diff --git a/arch/powerpc/lib/bdinfo.c b/arch/powerpc/lib/bdinfo.c index 36c9c99..b14e75b 100644 --- a/arch/powerpc/lib/bdinfo.c +++ b/arch/powerpc/lib/bdinfo.c @@ -47,9 +47,9 @@ void arch_print_bdinfo(void) bdinfo_print_mhz("busfreq", bd->bi_busfreq); #if defined(CONFIG_MPC8xx) || defined(CONFIG_E500) - bdinfo_print_num("immr_base", bd->bi_immr_base); + bdinfo_print_num_l("immr_base", bd->bi_immr_base); #endif - bdinfo_print_num("bootflags", bd->bi_bootflags); + bdinfo_print_num_l("bootflags", bd->bi_bootflags); bdinfo_print_mhz("intfreq", bd->bi_intfreq); #ifdef CONFIG_ENABLE_36BIT_PHYS if (IS_ENABLED(CONFIG_PHYS_64BIT)) -- cgit v1.1 From 6424fba1bc4e80c43eb5eb69b9e66c0d89d1b1cf Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Sun, 31 Jan 2021 20:36:06 +0800 Subject: bdinfo: Change to use bdinfo_print_num_ll() where the number could be 64-bit There are some calls to bdinfo_print_num_l() with parameters that could be a 64-bit value on a 32-bit system. Change those calls to use bdinfo_print_num_ll() instead. Signed-off-by: Bin Meng Reviewed-by: Simon Glass --- arch/arm/lib/bdinfo.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/arm/lib/bdinfo.c b/arch/arm/lib/bdinfo.c index 4a98cb7..c905783 100644 --- a/arch/arm/lib/bdinfo.c +++ b/arch/arm/lib/bdinfo.c @@ -18,14 +18,14 @@ void arch_print_bdinfo(void) bdinfo_print_num_l("arch_number", bd->bi_arch_number); #ifdef CONFIG_SYS_MEM_RESERVE_SECURE if (gd->arch.secure_ram & MEM_RESERVE_SECURE_SECURED) { - bdinfo_print_num_l("Secure ram", - gd->arch.secure_ram & - MEM_RESERVE_SECURE_ADDR_MASK); + bdinfo_print_num_ll("Secure ram", + gd->arch.secure_ram & + MEM_RESERVE_SECURE_ADDR_MASK); } #endif #ifdef CONFIG_RESV_RAM if (gd->arch.resv_ram) - bdinfo_print_num_l("Reserved ram", gd->arch.resv_ram); + bdinfo_print_num_ll("Reserved ram", gd->arch.resv_ram); #endif #if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) bdinfo_print_num_l("TLB addr", gd->arch.tlb_addr); -- cgit v1.1