From 442e6305b5b02d689774a0bf73311643ffa0df6f Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Thu, 21 Jan 2021 13:57:07 -0700 Subject: x86: coral: Support TPM and RTC in SPL Update the devicetree so that the TPM and RTC can be used in SPL. Also enable the pins used for getting the memory configuration settings while we are here. Signed-off-by: Simon Glass --- arch/x86/dts/chromebook_coral.dts | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) (limited to 'arch/x86/dts') diff --git a/arch/x86/dts/chromebook_coral.dts b/arch/x86/dts/chromebook_coral.dts index 965f592..9319123 100644 --- a/arch/x86/dts/chromebook_coral.dts +++ b/arch/x86/dts/chromebook_coral.dts @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /dts-v1/; +#include #include /include/ "skeleton.dtsi" @@ -99,6 +100,7 @@ clk: clock { compatible = "intel,apl-clk"; #clock-cells = <1>; + u-boot,dm-pre-reloc; }; cpus { @@ -139,6 +141,7 @@ }; acpi_gpe: general-purpose-events { + u-boot,dm-pre-reloc; reg = ; compatible = "intel,acpi-gpe"; interrupt-controller; @@ -417,8 +420,10 @@ }; i2c_2: i2c2@16,2 { - compatible = "intel,apl-i2c"; + compatible = "intel,apl-i2c", "snps,designware-i2c-pci"; reg = <0x0200b210 0 0 0 0>; + early-regs = ; + u-boot,dm-pre-reloc; #address-cells = <1>; #size-cells = <0>; clock-frequency = <400000>; @@ -429,6 +434,7 @@ tpm: tpm@50 { reg = <0x50>; compatible = "google,cr50"; + u-boot,dm-pre-reloc; u-boot,i2c-offset-len = <0>; ready-gpios = <&gpio_n 28 GPIO_ACTIVE_LOW>; interrupts-extended = <&acpi_gpe GPIO_28_IRQ @@ -583,6 +589,7 @@ u-boot,dm-pre-reloc; cros_ec: cros-ec { u-boot,dm-pre-proper; + u-boot,dm-vpl; compatible = "google,cros-ec-lpc"; reg = <0x204 1 0x200 1 0x880 0x80>; @@ -658,6 +665,11 @@ PAD_CFG_NF(LPC_AD3, UP_20K, DEEP, NF1) /* LPC_AD3 */ PAD_CFG_NF(LPC_CLKRUNB, UP_20K, DEEP, NF1) /* LPC_CLKRUN_N */ PAD_CFG_NF(LPC_FRAMEB, NATIVE, DEEP, NF1) /* LPC_FRAME_N */ + + PAD_CFG_GPI(GPIO_101, NONE, DEEP) /* FST_IO2 -- MEM_CONFIG0 */ + PAD_CFG_GPI(GPIO_102, NONE, DEEP) /* FST_IO3 -- MEM_CONFIG1 */ + PAD_CFG_GPI(GPIO_38, NONE, DEEP) /* LPSS_UART0_RXD - MEM_CONFIG2*/ + PAD_CFG_GPI(GPIO_45, NONE, DEEP) /* LPSS_UART1_CTS - MEM_CONFIG3 */ >; }; @@ -1211,3 +1223,9 @@ PAD_CFG_GPI(GPIO_73, UP_20K, DEEP) /* GP_CAMERASB11 */ >; }; + +&rtc { + #address-cells = <1>; + #size-cells = <0>; + u-boot,dm-pre-reloc; +}; -- cgit v1.1