From 4cf56ec07f673f99c87862dbb7e72bc077685474 Mon Sep 17 00:00:00 2001 From: Suneel Garapati Date: Sat, 19 Oct 2019 17:10:20 -0700 Subject: pci: pci-uclass: Add multi entry support for memory regions Enable PCI memory regions in ranges property to be of multiple entry. This helps to add support for SoC's like OcteonTX/TX2 where every peripheral is on PCI bus. Signed-off-by: Suneel Garapati Cc: Simon Glass Cc: Bin Meng --- arch/sandbox/dts/test.dts | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'arch/sandbox') diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts index 1d8956a..9f45c48 100644 --- a/arch/sandbox/dts/test.dts +++ b/arch/sandbox/dts/test.dts @@ -666,8 +666,9 @@ bus-range = <0x00 0xff>; #address-cells = <3>; #size-cells = <2>; - ranges = <0x02000000 0 0x30000000 0x30000000 0 0x2000 - 0x01000000 0 0x40000000 0x40000000 0 0x2000>; + ranges = <0x02000000 0 0x30000000 0x30000000 0 0x2000 // MEM0 + 0x02000000 0 0x31000000 0x31000000 0 0x2000 // MEM1 + 0x01000000 0 0x40000000 0x40000000 0 0x2000>; sandbox,dev-info = <0x08 0x00 0x1234 0x5678 0x0c 0x00 0x1234 0x5678 0x10 0x00 0x1234 0x5678>; -- cgit v1.1