From dda00ae4ef357233a72c74e6c02d27b70c844422 Mon Sep 17 00:00:00 2001 From: Rick Chen Date: Tue, 2 Apr 2019 15:56:42 +0800 Subject: riscv: ax25: Andes specific cache shall only support in M-mode Limit the cache configuration only can be supported in M mode. It can not be manipulated in S mode. Signed-off-by: Rick Chen Cc: Greentime Hu Reviewed-by: Bin Meng Reviewed-by: Lukas Auer --- arch/riscv/cpu/ax25/Kconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/riscv') diff --git a/arch/riscv/cpu/ax25/Kconfig b/arch/riscv/cpu/ax25/Kconfig index 68bd4e9..6b4b92e 100644 --- a/arch/riscv/cpu/ax25/Kconfig +++ b/arch/riscv/cpu/ax25/Kconfig @@ -14,6 +14,7 @@ if RISCV_NDS config RISCV_NDS_CACHE bool "AndeStar V5 families specific cache support" + depends on RISCV_MMODE help Provide Andes Technology AndeStar V5 families specific cache support. -- cgit v1.1