From c1b88196807e1dd797aea6cc7ddb0dce02b4e898 Mon Sep 17 00:00:00 2001 From: Yu Chien Peter Lin Date: Mon, 6 Feb 2023 16:10:48 +0800 Subject: riscv: ae350: dts: Update L2 cache compatible string Update the compatible string of L2 cache. Signed-off-by: Yu Chien Peter Lin Reviewed-by: Leo Yu-Chi Liang Reviewed-by: Rick Chen --- arch/riscv/dts/ae350_32.dts | 2 +- arch/riscv/dts/ae350_64.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/riscv/dts') diff --git a/arch/riscv/dts/ae350_32.dts b/arch/riscv/dts/ae350_32.dts index 96ef8bd..61af6d5 100644 --- a/arch/riscv/dts/ae350_32.dts +++ b/arch/riscv/dts/ae350_32.dts @@ -112,7 +112,7 @@ }; L2: l2-cache@e0500000 { - compatible = "v5l2cache"; + compatible = "cache"; cache-level = <2>; cache-size = <0x40000>; reg = <0xe0500000 0x40000>; diff --git a/arch/riscv/dts/ae350_64.dts b/arch/riscv/dts/ae350_64.dts index cddbaec..8c7db29 100644 --- a/arch/riscv/dts/ae350_64.dts +++ b/arch/riscv/dts/ae350_64.dts @@ -112,7 +112,7 @@ }; L2: l2-cache@e0500000 { - compatible = "v5l2cache"; + compatible = "cache"; cache-level = <2>; cache-size = <0x40000>; reg = <0x0 0xe0500000 0x0 0x40000>; -- cgit v1.1 From 8900e2bbecd021b16eee7c344cd6ca0e1ee901f3 Mon Sep 17 00:00:00 2001 From: Leo Yu-Chi Liang Date: Tue, 14 Feb 2023 20:42:49 +0800 Subject: riscv: Rename Andes cpu and board names The current ae350-related defconfigs could also support newer Andes CPU IP, so modify the names of CPU from ax25 to andesv5, and board name from ax25-ae350 to ae350. Signed-off-by: Leo Yu-Chi Liang Reviewed-by: Yu Chien Peter Lin Reviewed-by: Rick Chen --- arch/riscv/dts/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/riscv/dts') diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile index 5c15a0f..c576c55 100644 --- a/arch/riscv/dts/Makefile +++ b/arch/riscv/dts/Makefile @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0+ -dtb-$(CONFIG_TARGET_AX25_AE350) += ae350_32.dtb ae350_64.dtb +dtb-$(CONFIG_TARGET_AE350) += ae350_32.dtb ae350_64.dtb dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += microchip-mpfs-icicle-kit.dtb dtb-$(CONFIG_TARGET_QEMU_VIRT) += qemu-virt32.dtb qemu-virt64.dtb dtb-$(CONFIG_TARGET_OPENPITON_RISCV64) += openpiton-riscv64.dtb -- cgit v1.1 From 7574b6476afc1fd76816be6567458f6ca4f44234 Mon Sep 17 00:00:00 2001 From: Rick Chen Date: Fri, 17 Feb 2023 16:57:01 +0800 Subject: riscv: binman: Add help message for missing blobs Add the 'missing-msg' for more detailed output on missing system firmware. Signed-off-by: Rick Chen Reviewed-by: Leo Yu-Chi Liang Reviewed-by: Yu Chien Peter Lin --- arch/riscv/dts/binman.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/riscv/dts') diff --git a/arch/riscv/dts/binman.dtsi b/arch/riscv/dts/binman.dtsi index b8fc8f7..156cb00 100644 --- a/arch/riscv/dts/binman.dtsi +++ b/arch/riscv/dts/binman.dtsi @@ -45,6 +45,7 @@ opensbi_blob: opensbi { filename = "fw_dynamic.bin"; + missing-msg = "opensbi"; }; }; -- cgit v1.1