From 1206c18403ff25814673a4dbfa071ae06bbefaef Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Thu, 13 Dec 2012 20:48:44 +0000 Subject: ppc: Move brg_clk to arch_global_data Move this field into arch_global_data and tidy up. Signed-off-by: Simon Glass --- arch/powerpc/cpu/mpc8260/commproc.c | 2 +- arch/powerpc/cpu/mpc8260/i2c.c | 2 +- arch/powerpc/cpu/mpc8260/speed.c | 4 ++-- arch/powerpc/cpu/mpc83xx/speed.c | 5 +++-- arch/powerpc/cpu/mpc85xx/commproc.c | 2 +- arch/powerpc/cpu/mpc85xx/speed.c | 4 ++-- arch/powerpc/cpu/mpc8xx/fdt.c | 2 +- arch/powerpc/cpu/mpc8xx/speed.c | 2 +- 8 files changed, 12 insertions(+), 11 deletions(-) (limited to 'arch/powerpc/cpu') diff --git a/arch/powerpc/cpu/mpc8260/commproc.c b/arch/powerpc/cpu/mpc8260/commproc.c index 082957e..e5bfed1 100644 --- a/arch/powerpc/cpu/mpc8260/commproc.c +++ b/arch/powerpc/cpu/mpc8260/commproc.c @@ -101,7 +101,7 @@ m8260_cpm_hostalloc(uint size, uint align) * Baud rate clocks are zero-based in the driver code (as that maps * to port numbers). Documentation uses 1-based numbering. */ -#define BRG_INT_CLK gd->brg_clk +#define BRG_INT_CLK gd->arch.brg_clk #define BRG_UART_CLK (BRG_INT_CLK / 16) /* This function is used by UARTs, or anything else that uses a 16x diff --git a/arch/powerpc/cpu/mpc8260/i2c.c b/arch/powerpc/cpu/mpc8260/i2c.c index 7382cba..b720b1f 100644 --- a/arch/powerpc/cpu/mpc8260/i2c.c +++ b/arch/powerpc/cpu/mpc8260/i2c.c @@ -259,7 +259,7 @@ void i2c_init(int speed, int slaveadd) * divide BRGCLK by 1) */ debug("[I2C] Setting rate...\n"); - i2c_setrate(gd->brg_clk, CONFIG_SYS_I2C_SPEED); + i2c_setrate(gd->arch.brg_clk, CONFIG_SYS_I2C_SPEED); /* Set I2C controller in master mode */ i2c->i2c_i2com = 0x01; diff --git a/arch/powerpc/cpu/mpc8260/speed.c b/arch/powerpc/cpu/mpc8260/speed.c index bb50dee..4ad1ec2 100644 --- a/arch/powerpc/cpu/mpc8260/speed.c +++ b/arch/powerpc/cpu/mpc8260/speed.c @@ -145,7 +145,7 @@ int get_clocks (void) gd->cpm_clk = gd->vco_out / 2; gd->bus_clk = clkin; gd->scc_clk = gd->vco_out / 4; - gd->brg_clk = gd->vco_out / (1 << (2 * (dfbrg + 1))); + gd->arch.brg_clk = gd->vco_out / (1 << (2 * (dfbrg + 1))); if (cp->b2c_mult > 0) { gd->cpu_clk = (clkin * cp->b2c_mult) / 2; @@ -231,7 +231,7 @@ int prt_8260_clks (void) plldf, pllmf, pcidf); printf (" - vco_out %10ld, scc_clk %10ld, brg_clk %10ld\n", - gd->vco_out, gd->scc_clk, gd->brg_clk); + gd->vco_out, gd->scc_clk, gd->arch.brg_clk); printf (" - cpu_clk %10ld, cpm_clk %10ld, bus_clk %10ld\n", gd->cpu_clk, gd->cpm_clk, gd->bus_clk); diff --git a/arch/powerpc/cpu/mpc83xx/speed.c b/arch/powerpc/cpu/mpc83xx/speed.c index b8c05d1..21e8b0a 100644 --- a/arch/powerpc/cpu/mpc83xx/speed.c +++ b/arch/powerpc/cpu/mpc83xx/speed.c @@ -496,7 +496,7 @@ int get_clocks(void) #endif #if defined(CONFIG_QE) gd->qe_clk = qe_clk; - gd->brg_clk = brg_clk; + gd->arch.brg_clk = brg_clk; #endif #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \ defined(CONFIG_MPC837x) @@ -540,7 +540,8 @@ static int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) printf(" Coherent System Bus: %-4s MHz\n", strmhz(buf, gd->csb_clk)); #if defined(CONFIG_QE) printf(" QE: %-4s MHz\n", strmhz(buf, gd->qe_clk)); - printf(" BRG: %-4s MHz\n", strmhz(buf, gd->brg_clk)); + printf(" BRG: %-4s MHz\n", + strmhz(buf, gd->arch.brg_clk)); #endif printf(" Local Bus Controller:%-4s MHz\n", strmhz(buf, gd->lbiu_clk)); printf(" Local Bus: %-4s MHz\n", strmhz(buf, gd->lclk_clk)); diff --git a/arch/powerpc/cpu/mpc85xx/commproc.c b/arch/powerpc/cpu/mpc85xx/commproc.c index 292b723..7f10476 100644 --- a/arch/powerpc/cpu/mpc85xx/commproc.c +++ b/arch/powerpc/cpu/mpc85xx/commproc.c @@ -110,7 +110,7 @@ m8560_cpm_hostalloc(uint size, uint align) * Baud rate clocks are zero-based in the driver code (as that maps * to port numbers). Documentation uses 1-based numbering. */ -#define BRG_INT_CLK gd->brg_clk +#define BRG_INT_CLK gd->arch.brg_clk #define BRG_UART_CLK ((BRG_INT_CLK + 15) / 16) /* This function is used by UARTS, or anything else that uses a 16x diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index 801ee07..8a581ef 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -395,7 +395,7 @@ int get_clocks (void) #ifdef CONFIG_QE gd->qe_clk = sys_info.freqQE; - gd->brg_clk = gd->qe_clk / 2; + gd->arch.brg_clk = gd->qe_clk / 2; #endif /* * The base clock for I2C depends on the actual SOC. Unfortunately, @@ -438,7 +438,7 @@ int get_clocks (void) gd->vco_out = 2*sys_info.freqSystemBus; gd->cpm_clk = gd->vco_out / 2; gd->scc_clk = gd->vco_out / 4; - gd->brg_clk = gd->vco_out / (1 << (2 * (dfbrg + 1))); + gd->arch.brg_clk = gd->vco_out / (1 << (2 * (dfbrg + 1))); #endif if(gd->cpu_clk != 0) return (0); diff --git a/arch/powerpc/cpu/mpc8xx/fdt.c b/arch/powerpc/cpu/mpc8xx/fdt.c index 7130983..7edd7e4 100644 --- a/arch/powerpc/cpu/mpc8xx/fdt.c +++ b/arch/powerpc/cpu/mpc8xx/fdt.c @@ -37,7 +37,7 @@ void ft_cpu_setup(void *blob, bd_t *bd) do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, "clock-frequency", bd->bi_intfreq, 1); do_fixup_by_compat_u32(blob, "fsl,cpm-brg", "clock-frequency", - gd->brg_clk, 1); + gd->arch.brg_clk, 1); /* Fixup ethernet MAC addresses */ fdt_fixup_ethernet(blob); diff --git a/arch/powerpc/cpu/mpc8xx/speed.c b/arch/powerpc/cpu/mpc8xx/speed.c index 6e13e5d..091b49f 100644 --- a/arch/powerpc/cpu/mpc8xx/speed.c +++ b/arch/powerpc/cpu/mpc8xx/speed.c @@ -192,7 +192,7 @@ void get_brgclk(uint sccr) divider = 64; break; } - gd->brg_clk = gd->cpu_clk/divider; + gd->arch.brg_clk = gd->cpu_clk/divider; } #if !defined(CONFIG_8xx_CPUCLK_DEFAULT) -- cgit v1.1