From 2eed3dca229e97aa03954ee5178457c4f2f8cfdb Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Thu, 14 May 2020 11:59:03 +0200 Subject: mips: cache: Allow using CONFIG_MIPS_L2_CACHE without CONFIG_MIPS_CM This patch enables the usage of CONFIG_MIPS_L2_CACHE without CONFIG_MIPS_CM, which is what is needed for the newly added Octeon platform. Signed-off-by: Stefan Roese --- arch/mips/include/asm/cm.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'arch/mips/include') diff --git a/arch/mips/include/asm/cm.h b/arch/mips/include/asm/cm.h index 3878171..99ddbcc 100644 --- a/arch/mips/include/asm/cm.h +++ b/arch/mips/include/asm/cm.h @@ -41,6 +41,7 @@ #include #include +#if CONFIG_IS_ENABLED(MIPS_CM) static inline void *mips_cm_base(void) { return (void *)CKSEG1ADDR(CONFIG_MIPS_CM_BASE); @@ -56,6 +57,17 @@ static inline unsigned long mips_cm_l2_line_size(void) line_sz &= GENMASK(GCR_L2_CONFIG_LINESZ_BITS - 1, 0); return line_sz ? (2 << line_sz) : 0; } +#else +static inline void *mips_cm_base(void) +{ + return NULL; +} + +static inline unsigned long mips_cm_l2_line_size(void) +{ + return 0; +} +#endif #endif /* !__ASSEMBLY__ */ -- cgit v1.1