From a8d0526133e542ea93a741fd18833e571e817775 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Wed, 19 Oct 2016 15:18:47 -0600 Subject: ARM: tegra186: call secure monitor for all cache-wide ops An SMC call is required for all cache-wide operations on Tegra186. This patch implements the two missing hooks now that U-Boot supports them, and fixes the mapping of "hook name" to SMC call code. Signed-off-by: Stephen Warren Signed-off-by: Tom Warren --- arch/arm/mach-tegra/tegra186/cache.S | 24 +++++++++++++++++++++--- 1 file changed, 21 insertions(+), 3 deletions(-) (limited to 'arch/arm/mach-tegra') diff --git a/arch/arm/mach-tegra/tegra186/cache.S b/arch/arm/mach-tegra/tegra186/cache.S index 3ca3f3c..3061dc2 100644 --- a/arch/arm/mach-tegra/tegra186/cache.S +++ b/arch/arm/mach-tegra/tegra186/cache.S @@ -9,10 +9,10 @@ #define SMC_SIP_INVOKE_MCE 0x82FFFF00 #define MCE_SMC_ROC_FLUSH_CACHE (SMC_SIP_INVOKE_MCE | 11) +#define MCE_SMC_ROC_FLUSH_CACHE_ONLY (SMC_SIP_INVOKE_MCE | 14) +#define MCE_SMC_ROC_CLEAN_CACHE_ONLY (SMC_SIP_INVOKE_MCE | 15) -ENTRY(__asm_flush_l3_dcache) - mov x0, #(MCE_SMC_ROC_FLUSH_CACHE & 0xffff) - movk x0, #(MCE_SMC_ROC_FLUSH_CACHE >> 16), lsl #16 +ENTRY(__asm_tegra_cache_smc) mov x1, #0 mov x2, #0 mov x3, #0 @@ -22,4 +22,22 @@ ENTRY(__asm_flush_l3_dcache) smc #0 mov x0, #0 ret +ENDPROC(__asm_invalidate_l3_dcache) + +ENTRY(__asm_invalidate_l3_dcache) + mov x0, #(MCE_SMC_ROC_FLUSH_CACHE_ONLY & 0xffff) + movk x0, #(MCE_SMC_ROC_FLUSH_CACHE_ONLY >> 16), lsl #16 + b __asm_tegra_cache_smc +ENDPROC(__asm_invalidate_l3_dcache) + +ENTRY(__asm_flush_l3_dcache) + mov x0, #(MCE_SMC_ROC_CLEAN_CACHE_ONLY & 0xffff) + movk x0, #(MCE_SMC_ROC_CLEAN_CACHE_ONLY >> 16), lsl #16 + b __asm_tegra_cache_smc ENDPROC(__asm_flush_l3_dcache) + +ENTRY(__asm_invalidate_l3_icache) + mov x0, #(MCE_SMC_ROC_FLUSH_CACHE & 0xffff) + movk x0, #(MCE_SMC_ROC_FLUSH_CACHE >> 16), lsl #16 + b __asm_tegra_cache_smc +ENDPROC(__asm_invalidate_l3_icache) -- cgit v1.1