From 01a701994b0590b6452516a7c67353359d053c94 Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Fri, 27 Oct 2023 16:43:04 +0200 Subject: stm32mp2: initial support Add initial support for STM32MP2 SoCs family. SoCs information are available here : https://www.st.com/content/st_com/en/campaigns/microprocessor-stm32mp2.html Migrate all MP1 related code into stm32mp1/ directory Create stm32mp2 directory dedicated for STM32MP2 SoCs. Common code to MP1, MP13 and MP25 is kept into arch/arm/mach-stm32/mach-stm32mp directory : - boot_params.c - bsec - cmd_stm32key - cmd_stm32prog - dram_init.c - syscon.c - ecdsa_romapi.c For STM32MP2, it also : - adds memory region description needed for ARMv8 MMU. - enables early data cache before relocation. During the transition before/after relocation, the MMU, initially setup at the beginning of DDR, must be setup again at a correct address after relocation. This is done in enables_caches() by disabling cache, force arch.tlb_fillptr to NULL which will force the MMU to be setup again but with a new value for gd->arch.tlb_addr. gd->arch.tlb_addr has been updated after relocation in arm_reserve_mmu(). Signed-off-by: Patrice Chotard Reviewed-by: Patrick Delaunay --- arch/arm/mach-stm32mp/include/mach/stm32.h | 141 +++++++++++++++---------- arch/arm/mach-stm32mp/include/mach/sys_proto.h | 26 +++++ 2 files changed, 111 insertions(+), 56 deletions(-) (limited to 'arch/arm/mach-stm32mp/include') diff --git a/arch/arm/mach-stm32mp/include/mach/stm32.h b/arch/arm/mach-stm32mp/include/mach/stm32.h index 1cdc5e3..ce9d795 100644 --- a/arch/arm/mach-stm32mp/include/mach/stm32.h +++ b/arch/arm/mach-stm32mp/include/mach/stm32.h @@ -8,12 +8,66 @@ #ifndef __ASSEMBLY__ #include + +enum boot_device { + BOOT_FLASH_SD = 0x10, + BOOT_FLASH_SD_1 = 0x11, + BOOT_FLASH_SD_2 = 0x12, + BOOT_FLASH_SD_3 = 0x13, + + BOOT_FLASH_EMMC = 0x20, + BOOT_FLASH_EMMC_1 = 0x21, + BOOT_FLASH_EMMC_2 = 0x22, + BOOT_FLASH_EMMC_3 = 0x23, + + BOOT_FLASH_NAND = 0x30, + BOOT_FLASH_NAND_FMC = 0x31, + + BOOT_FLASH_NOR = 0x40, + BOOT_FLASH_NOR_QSPI = 0x41, + + BOOT_SERIAL_UART = 0x50, + BOOT_SERIAL_UART_1 = 0x51, + BOOT_SERIAL_UART_2 = 0x52, + BOOT_SERIAL_UART_3 = 0x53, + BOOT_SERIAL_UART_4 = 0x54, + BOOT_SERIAL_UART_5 = 0x55, + BOOT_SERIAL_UART_6 = 0x56, + BOOT_SERIAL_UART_7 = 0x57, + BOOT_SERIAL_UART_8 = 0x58, + + BOOT_SERIAL_USB = 0x60, + BOOT_SERIAL_USB_OTG = 0x62, + + BOOT_FLASH_SPINAND = 0x70, + BOOT_FLASH_SPINAND_1 = 0x71, +}; + +#define TAMP_BOOT_MODE_MASK GENMASK(15, 8) +#define TAMP_BOOT_MODE_SHIFT 8 +#define TAMP_BOOT_DEVICE_MASK GENMASK(7, 4) +#define TAMP_BOOT_INSTANCE_MASK GENMASK(3, 0) +#define TAMP_BOOT_FORCED_MASK GENMASK(7, 0) +#define TAMP_BOOT_DEBUG_ON BIT(16) + +enum forced_boot_mode { + BOOT_NORMAL = 0x00, + BOOT_FASTBOOT = 0x01, + BOOT_RECOVERY = 0x02, + BOOT_STM32PROG = 0x03, + BOOT_UMS_MMC0 = 0x10, + BOOT_UMS_MMC1 = 0x11, + BOOT_UMS_MMC2 = 0x12, +}; + #endif /* * Peripheral memory map * only address used before device tree parsing */ + +#if defined(CONFIG_STM32MP15x) || defined(CONFIG_STM32MP13x) #define STM32_RCC_BASE 0x50000000 #define STM32_PWR_BASE 0x50001000 #define STM32_SYSCFG_BASE 0x50020000 @@ -58,12 +112,6 @@ #define STM32_DDR_SIZE SZ_1G #ifndef __ASSEMBLY__ -/* enumerated used to identify the SYSCON driver instance */ -enum { - STM32MP_SYSCON_UNKNOWN, - STM32MP_SYSCON_SYSCFG, -}; - /* * enumerated for boot interface from Bootrom, used in TAMP_BOOT_CONTEXT * - boot device = bit 8:4 @@ -74,40 +122,6 @@ enum { #define BOOT_INSTANCE_MASK 0x0F #define BOOT_INSTANCE_SHIFT 0 -enum boot_device { - BOOT_FLASH_SD = 0x10, - BOOT_FLASH_SD_1 = 0x11, - BOOT_FLASH_SD_2 = 0x12, - BOOT_FLASH_SD_3 = 0x13, - - BOOT_FLASH_EMMC = 0x20, - BOOT_FLASH_EMMC_1 = 0x21, - BOOT_FLASH_EMMC_2 = 0x22, - BOOT_FLASH_EMMC_3 = 0x23, - - BOOT_FLASH_NAND = 0x30, - BOOT_FLASH_NAND_FMC = 0x31, - - BOOT_FLASH_NOR = 0x40, - BOOT_FLASH_NOR_QSPI = 0x41, - - BOOT_SERIAL_UART = 0x50, - BOOT_SERIAL_UART_1 = 0x51, - BOOT_SERIAL_UART_2 = 0x52, - BOOT_SERIAL_UART_3 = 0x53, - BOOT_SERIAL_UART_4 = 0x54, - BOOT_SERIAL_UART_5 = 0x55, - BOOT_SERIAL_UART_6 = 0x56, - BOOT_SERIAL_UART_7 = 0x57, - BOOT_SERIAL_UART_8 = 0x58, - - BOOT_SERIAL_USB = 0x60, - BOOT_SERIAL_USB_OTG = 0x62, - - BOOT_FLASH_SPINAND = 0x70, - BOOT_FLASH_SPINAND_1 = 0x71, -}; - /* TAMP registers */ #define TAMP_BACKUP_REGISTER(x) (STM32_TAMP_BASE + 0x100 + 4 * x) @@ -123,7 +137,6 @@ enum boot_device { #define TAMP_FWU_BOOT_IDX_MASK GENMASK(3, 0) #define TAMP_FWU_BOOT_IDX_OFFSET 0 - #define TAMP_COPRO_STATE_OFF 0 #define TAMP_COPRO_STATE_INIT 1 #define TAMP_COPRO_STATE_CRUN 2 @@ -137,21 +150,23 @@ enum boot_device { #define TAMP_BOOT_CONTEXT TAMP_BACKUP_REGISTER(30) #endif -#define TAMP_BOOT_MODE_MASK GENMASK(15, 8) -#define TAMP_BOOT_MODE_SHIFT 8 -#define TAMP_BOOT_DEVICE_MASK GENMASK(7, 4) -#define TAMP_BOOT_INSTANCE_MASK GENMASK(3, 0) -#define TAMP_BOOT_FORCED_MASK GENMASK(7, 0) +#endif /* __ASSEMBLY__ */ +#endif /* CONFIG_STM32MP15X || CONFIG_STM32MP13X */ -enum forced_boot_mode { - BOOT_NORMAL = 0x00, - BOOT_FASTBOOT = 0x01, - BOOT_RECOVERY = 0x02, - BOOT_STM32PROG = 0x03, - BOOT_UMS_MMC0 = 0x10, - BOOT_UMS_MMC1 = 0x11, - BOOT_UMS_MMC2 = 0x12, -}; +#if CONFIG_STM32MP25X +#define STM32_RCC_BASE 0x44200000 +#define STM32_TAMP_BASE 0x46010000 + +#define STM32_DDR_BASE 0x80000000 + +#define STM32_DDR_SIZE SZ_4G + +/* TAMP registers x = 0 to 127 : hardcoded description, waiting NVMEM node in DT */ +#define TAMP_BACKUP_REGISTER(x) (STM32_TAMP_BASE + 0x100 + 4 * (x)) + +/* TAMP registers zone 3 RIF 1 (RW) at 96*/ +#define TAMP_BOOT_CONTEXT TAMP_BACKUP_REGISTER(96) +#endif /* STM32MP25X */ /* offset used for BSEC driver: misc_read and misc_write */ #define STM32_BSEC_SHADOW_OFFSET 0x0 @@ -175,6 +190,20 @@ enum forced_boot_mode { #define BSEC_OTP_MAC 57 #define BSEC_OTP_BOARD 60 #endif +#ifdef CONFIG_STM32MP25X +#define BSEC_OTP_SERIAL 5 +#define BSEC_OTP_RPN 9 +#define BSEC_OTP_PKG 246 +#endif + +#ifndef __ASSEMBLY__ +#include + +/* enumerated used to identify the SYSCON driver instance */ +enum { + STM32MP_SYSCON_UNKNOWN, + STM32MP_SYSCON_SYSCFG, +}; +#endif /* __ASSEMBLY__*/ -#endif /* __ASSEMBLY__ */ #endif /* _MACH_STM32_H_ */ diff --git a/arch/arm/mach-stm32mp/include/mach/sys_proto.h b/arch/arm/mach-stm32mp/include/mach/sys_proto.h index 83fb32a..7b2df09 100644 --- a/arch/arm/mach-stm32mp/include/mach/sys_proto.h +++ b/arch/arm/mach-stm32mp/include/mach/sys_proto.h @@ -30,11 +30,30 @@ #define CPU_STM32MP131Fxx 0x05010EC8 #define CPU_STM32MP131Dxx 0x05010EC9 +/* ID for STM32MP25x = Device Part Number (RPN) (bit31:0) */ +#define CPU_STM32MP257Cxx 0x00002000 +#define CPU_STM32MP255Cxx 0x00082000 +#define CPU_STM32MP253Cxx 0x000B2004 +#define CPU_STM32MP251Cxx 0x000B3065 +#define CPU_STM32MP257Axx 0x40002E00 +#define CPU_STM32MP255Axx 0x40082E00 +#define CPU_STM32MP253Axx 0x400B2E04 +#define CPU_STM32MP251Axx 0x400B3E65 +#define CPU_STM32MP257Fxx 0x80002000 +#define CPU_STM32MP255Fxx 0x80082000 +#define CPU_STM32MP253Fxx 0x800B2004 +#define CPU_STM32MP251Fxx 0x800B3065 +#define CPU_STM32MP257Dxx 0xC0002E00 +#define CPU_STM32MP255Dxx 0xC0082E00 +#define CPU_STM32MP253Dxx 0xC00B2E04 +#define CPU_STM32MP251Dxx 0xC00B3E65 + /* return CPU_STMP32MP...Xxx constants */ u32 get_cpu_type(void); #define CPU_DEV_STM32MP15 0x500 #define CPU_DEV_STM32MP13 0x501 +#define CPU_DEV_STM32MP25 0x505 /* return CPU_DEV constants */ u32 get_cpu_dev(void); @@ -59,6 +78,13 @@ u32 get_cpu_package(void); #define STM32MP15_PKG_AD_TFBGA257 1 #define STM32MP15_PKG_UNKNOWN 0 +/* package used for STM32MP25x */ +#define STM32MP25_PKG_CUSTOM 0 +#define STM32MP25_PKG_AL_TBGA361 3 +#define STM32MP25_PKG_AK_TBGA424 4 +#define STM32MP25_PKG_AI_TBGA436 5 +#define STM32MP25_PKG_UNKNOWN 7 + /* Get SOC name */ #define SOC_NAME_SIZE 20 void get_soc_name(char name[SOC_NAME_SIZE]); -- cgit v1.1