From 350b50eea31ac740e71f5d59b9a6a04b316c6d8d Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Sat, 25 Apr 2015 06:29:44 +0200 Subject: arm: armada-xp: Move SoC sources to mach-mvebu Move arch/arm/cpu/armv7armada-xp/* -> arch/arm/mach-mvebu/* Since this platform will be extended to support other Marvell SoC's as well, lets rename it directly to mvebu. This will be used by the upcoming Armada 38x suport (A38x). Signed-off-by: Stefan Roese Cc: Masahiro Yamada Tested-by: Kevin Smith Tested-by: Dirk Eibach --- arch/arm/mach-mvebu/lowlevel_spl.S | 61 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 61 insertions(+) create mode 100644 arch/arm/mach-mvebu/lowlevel_spl.S (limited to 'arch/arm/mach-mvebu/lowlevel_spl.S') diff --git a/arch/arm/mach-mvebu/lowlevel_spl.S b/arch/arm/mach-mvebu/lowlevel_spl.S new file mode 100644 index 0000000..69da7fe --- /dev/null +++ b/arch/arm/mach-mvebu/lowlevel_spl.S @@ -0,0 +1,61 @@ +/* + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +ENTRY(save_boot_params) + b save_boot_params_ret +ENDPROC(save_boot_params) + +/* + * cache_inv - invalidate Cache line + * r0 - dest + */ + .global cache_inv + .type cache_inv, %function + cache_inv: + + stmfd sp!, {r1-r12} + + mcr p15, 0, r0, c7, c6, 1 + + ldmfd sp!, {r1-r12} + bx lr + + +/* + * flush_l1_v6 - l1 cache clean invalidate + * r0 - dest + */ + .global flush_l1_v6 + .type flush_l1_v6, %function + flush_l1_v6: + + stmfd sp!, {r1-r12} + + mcr p15, 0, r0, c7, c10, 5 /* @ data memory barrier */ + mcr p15, 0, r0, c7, c14, 1 /* @ clean & invalidate D line */ + mcr p15, 0, r0, c7, c10, 4 /* @ data sync barrier */ + + ldmfd sp!, {r1-r12} + bx lr + + +/* + * flush_l1_v7 - l1 cache clean invalidate + * r0 - dest + */ + .global flush_l1_v7 + .type flush_l1_v7, %function + flush_l1_v7: + + stmfd sp!, {r1-r12} + + dmb /* @data memory barrier */ + mcr p15, 0, r0, c7, c14, 1 /* @ clean & invalidate D line */ + dsb /* @data sync barrier */ + + ldmfd sp!, {r1-r12} + bx lr -- cgit v1.1