From fdf6bbb260c36bb54826bffb4dd4d62b90c3cede Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 19 Sep 2022 21:37:07 +0200 Subject: ARM: imx: Deduplicate i.MX8M SNVS LPGPR unlock Pull this LPGPR unlock into common code, since it is used in multiple systems already. Signed-off-by: Marek Vasut --- arch/arm/include/asm/arch-imx8m/imx-regs.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm/include') diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h b/arch/arm/include/asm/arch-imx8m/imx-regs.h index ff3b9dd..29d5baa 100644 --- a/arch/arm/include/asm/arch-imx8m/imx-regs.h +++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h @@ -27,6 +27,7 @@ #define IOMUXC_GPR_BASE_ADDR 0x30340000 #define OCOTP_BASE_ADDR 0x30350000 #define ANATOP_BASE_ADDR 0x30360000 +#define SNVS_BASE_ADDR 0x30370000 #define CCM_BASE_ADDR 0x30380000 #define SRC_BASE_ADDR 0x30390000 #define GPC_BASE_ADDR 0x303A0000 @@ -113,6 +114,10 @@ #define SRC_DDR1_RCR_CORE_RESET_N_MASK BIT(1) #define SRC_DDR1_RCR_PRESET_N_MASK BIT(0) +#define SNVS_LPSR 0x4c +#define SNVS_LPLVDR 0x64 +#define SNVS_LPPGDR_INIT 0x41736166 + struct iomuxc_gpr_base_regs { u32 gpr[47]; }; -- cgit v1.1