From ae9996c806e15b68b97fe7a7242c44e713345269 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 18 Nov 2015 11:06:09 +0100 Subject: arm: socfpga: Add SoCFPGA SR1500 board The SR1500 board is a CycloneV based board, similar to the EBV SoCrates, equipped with the following devices: - SPI NOR - eMMC - Ethernet Signed-off-by: Stefan Roese Reviewed-by: Marek Vasut Cc: Pavel Machek Cc: Dinh Nguyen Acked-by: Pavel Machek --- arch/arm/dts/Makefile | 4 +- arch/arm/dts/socfpga_cyclone5_sr1500.dts | 101 +++++++++++++++++++++++++++++++ 2 files changed, 104 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/socfpga_cyclone5_sr1500.dts (limited to 'arch/arm/dts') diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 23e7b40..521aa4c 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -81,7 +81,9 @@ dtb-$(CONFIG_ARCH_SOCFPGA) += \ socfpga_cyclone5_socdk.dtb \ socfpga_cyclone5_de0_nano_soc.dtb \ socfpga_cyclone5_sockit.dtb \ - socfpga_cyclone5_socrates.dtb + socfpga_cyclone5_socrates.dtb \ + socfpga_cyclone5_sr1500.dtb + dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb dtb-$(CONFIG_TARGET_BEAGLE_X15) += am57xx-beagle-x15.dtb dtb-$(CONFIG_TARGET_STV0991) += stv0991.dtb diff --git a/arch/arm/dts/socfpga_cyclone5_sr1500.dts b/arch/arm/dts/socfpga_cyclone5_sr1500.dts new file mode 100644 index 0000000..3729ca0 --- /dev/null +++ b/arch/arm/dts/socfpga_cyclone5_sr1500.dts @@ -0,0 +1,101 @@ +/* + * Copyright (C) 2015 Stefan Roese + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include "socfpga_cyclone5.dtsi" + +/ { + model = "SoCFPGA Cyclone V SR1500"; + compatible = "anonymous,socfpga-sr1500", "altr,socfpga-cyclone5", "altr,socfpga"; + + chosen { + bootargs = "console=ttyS0,115200"; + }; + + aliases { + /* + * This allows the ethaddr uboot environmnet variable + * contents to be added to the gmac1 device tree blob. + */ + ethernet0 = &gmac1; + }; + + memory@0 { + name = "memory"; + device_type = "memory"; + reg = <0x0 0x40000000>; /* 1GB */ + }; + + soc { + u-boot,dm-pre-reloc; + }; +}; + +&gmac1 { + status = "okay"; + phy-mode = "rgmii"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + speed-mode = <0>; +}; + +&i2c1 { + status = "okay"; + speed-mode = <0>; +}; + +&mmc0 { + status = "okay"; + bus-width = <8>; + u-boot,dm-pre-reloc; +}; + +&uart0 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; + +&watchdog0 { + status = "okay"; +}; + +&qspi { + status = "okay"; + u-boot,dm-pre-reloc; + + flash0: n25q00@0 { + u-boot,dm-pre-reloc; + #address-cells = <1>; + #size-cells = <1>; + compatible = "n25q00", "spi-flash"; + reg = <0>; /* chip select */ + spi-max-frequency = <50000000>; + m25p,fast-read; + page-size = <256>; + block-size = <16>; /* 2^16, 64KB */ + read-delay = <4>; /* delay value in read data capture register */ + tshsl-ns = <50>; + tsd2d-ns = <50>; + tchsh-ns = <4>; + tslch-ns = <4>; + }; +}; -- cgit v1.1