From 860fbdd41f010348757926ca8f9c65dd00616d1e Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Thu, 18 Aug 2016 20:51:12 +0200 Subject: sunxi: Sync dts files with upstream kernel Sync dts files with the current (Aug 18th 2016) state of Maxime's linux/sunxi/for-next repo. Note this commit also updates configs/MSI_Primo81_defconfig, adding: "# CONFIG_REQUIRE_SERIAL_CONSOLE is not set", this is necessary because the tablet does not have a reachable uart so the dts sync drops its serial0 alias. Signed-off-by: Hans de Goede Acked-by: Ian Campbell --- arch/arm/dts/sun5i.dtsi | 92 +++++++++++++++++++++++-------------------------- 1 file changed, 43 insertions(+), 49 deletions(-) (limited to 'arch/arm/dts/sun5i.dtsi') diff --git a/arch/arm/dts/sun5i.dtsi b/arch/arm/dts/sun5i.dtsi index 87e5353..e374f4f 100644 --- a/arch/arm/dts/sun5i.dtsi +++ b/arch/arm/dts/sun5i.dtsi @@ -88,6 +88,15 @@ clock-output-names = "osc24M"; }; + osc3M: osc3M_clk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clock-div = <8>; + clock-mult = <1>; + clocks = <&osc24M>; + clock-output-names = "osc3M"; + }; + osc32k: clk@0 { #clock-cells = <0>; compatible = "fixed-clock"; @@ -112,6 +121,23 @@ "pll2-4x", "pll2-8x"; }; + pll3: clk@01c20010 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-pll3-clk"; + reg = <0x01c20010 0x4>; + clocks = <&osc3M>; + clock-output-names = "pll3"; + }; + + pll3x2: pll3x2_clk { + compatible = "allwinner,sun4i-a10-pll3-2x-clk", "fixed-factor-clock"; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <2>; + clocks = <&pll3>; + clock-output-names = "pll3-2x"; + }; + pll4: clk@01c20018 { #clock-cells = <0>; compatible = "allwinner,sun4i-a10-pll1-clk"; @@ -136,6 +162,23 @@ clock-output-names = "pll6_sata", "pll6_other", "pll6"; }; + pll7: clk@01c20030 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-pll3-clk"; + reg = <0x01c20030 0x4>; + clocks = <&osc3M>; + clock-output-names = "pll7"; + }; + + pll7x2: pll7x2_clk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <2>; + clocks = <&pll7>; + clock-output-names = "pll7-2x"; + }; + /* dummy is 200M */ cpu: cpu@01c20054 { #clock-cells = <0>; @@ -356,17 +399,6 @@ #dma-cells = <2>; }; - nfc: nand@01c03000 { - compatible = "allwinner,sun4i-a10-nand"; - reg = <0x01c03000 0x1000>; - interrupts = <37>; - clocks = <&ahb_gates 13>, <&nand_clk>; - clock-names = "ahb", "mod"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - spi0: spi@01c05000 { compatible = "allwinner,sun4i-a10-spi"; reg = <0x01c05000 0x1000>; @@ -559,44 +591,6 @@ allwinner,pull = ; }; - nand_pins_a: nand_base0@0 { - allwinner,pins = "PC0", "PC1", "PC2", - "PC5", "PC8", "PC9", "PC10", - "PC11", "PC12", "PC13", "PC14", - "PC15"; - allwinner,function = "nand0"; - allwinner,drive = <0>; - allwinner,pull = <0>; - }; - - nand_cs0_pins_a: nand_cs@0 { - allwinner,pins = "PC4"; - allwinner,function = "nand0"; - allwinner,drive = <0>; - allwinner,pull = <0>; - }; - - nand_cs1_pins_a: nand_cs@1 { - allwinner,pins = "PC3"; - allwinner,function = "nand0"; - allwinner,drive = <0>; - allwinner,pull = <0>; - }; - - nand_rb0_pins_a: nand_rb@0 { - allwinner,pins = "PC6"; - allwinner,function = "nand0"; - allwinner,drive = <0>; - allwinner,pull = <0>; - }; - - nand_rb1_pins_a: nand_rb@1 { - allwinner,pins = "PC7"; - allwinner,function = "nand0"; - allwinner,drive = <0>; - allwinner,pull = <0>; - }; - uart3_pins_a: uart3@0 { allwinner,pins = "PG9", "PG10"; allwinner,function = "uart3"; -- cgit v1.1