From 64501c669851e45dd47699349dae6b5798c075a3 Mon Sep 17 00:00:00 2001 From: Priyanka Jain Date: Tue, 2 Jul 2013 09:21:04 +0530 Subject: board/bsc9132qds: Add DSP side tlb and laws BSC9132QDS is a Freescale Reference Design Board for BSC9132 SoC which is a integrated device that contains two powerpc e500v2 cores and two DSP starcores. To support DSP starcore -Creating LAW and TLB for DSP-CCSR space. -Creating LAW for DSP-core subsystem M2 and M3 memory -Creating LAW for 1GB DDR which is connected exclusively to DSP-cores Signed-off-by: Manish Jaggi Signed-off-by: Priyanka Jain Acked-by: York Sun --- README | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'README') diff --git a/README b/README index 5fb4c75..3918807 100644 --- a/README +++ b/README @@ -406,10 +406,18 @@ The following options need to be configured: This is the value to write into CCSR offset 0x18600 according to the A004510 workaround. + CONFIG_SYS_FSL_DSP_DDR_ADDR + This value denotes start offset of DDR memory which is + connected exclusively to the DSP cores. + CONFIG_SYS_FSL_DSP_M2_RAM_ADDR This value denotes start offset of M2 memory which is directly connected to the DSP core. + CONFIG_SYS_FSL_DSP_M3_RAM_ADDR + This value denotes start offset of M3 memory which is directly + connected to the DSP core. + CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT This value denotes start offset of DSP CCSR space. -- cgit v1.1