From 9750a245cd4aca96ff01152929bf72004029545c Mon Sep 17 00:00:00 2001 From: Christophe Leroy Date: Tue, 4 Apr 2023 10:14:33 +0200 Subject: powerpc: mpc8xx: Migrate to CONFIG_SYS_CLK_FREQ 8xx has CONFIG_8xx_GCLK_FREQ which is similar to CONFIG_SYS_CLK_FREQ, and doesn't set CONFIG_SYS_CLK_FREQ. Due to that, get_board_sys_clk() returns 0. Remove CONFIG_8xx_GCLK_FREQ and use CONFIG_SYS_CLK_FREQ instead. Signed-off-by: Christophe Leroy --- arch/powerpc/cpu/mpc8xx/Kconfig | 3 --- arch/powerpc/cpu/mpc8xx/speed.c | 4 ++-- configs/CMPC885_defconfig | 2 +- configs/MCR3000_defconfig | 2 +- 4 files changed, 4 insertions(+), 7 deletions(-) diff --git a/arch/powerpc/cpu/mpc8xx/Kconfig b/arch/powerpc/cpu/mpc8xx/Kconfig index 628d361..a705014 100644 --- a/arch/powerpc/cpu/mpc8xx/Kconfig +++ b/arch/powerpc/cpu/mpc8xx/Kconfig @@ -30,9 +30,6 @@ config MPC885 endchoice -config 8xx_GCLK_FREQ - int "CPU GCLK Frequency" - comment "Specific commands" config CMD_IMMAP diff --git a/arch/powerpc/cpu/mpc8xx/speed.c b/arch/powerpc/cpu/mpc8xx/speed.c index ad3d3f9..1a882a3 100644 --- a/arch/powerpc/cpu/mpc8xx/speed.c +++ b/arch/powerpc/cpu/mpc8xx/speed.c @@ -14,7 +14,7 @@ DECLARE_GLOBAL_DATA_PTR; /* - * get_clocks() fills in gd->cpu_clock depending on CONFIG_8xx_GCLK_FREQ + * get_clocks() fills in gd->cpu_clk depending on CONFIG_SYS_CLK_FREQ */ int get_clocks(void) { @@ -28,7 +28,7 @@ int get_clocks(void) * (For example, the cogent CMA286-60 CPU module has no * separate oscillator for PITRTCLK) */ - gd->cpu_clk = CONFIG_8xx_GCLK_FREQ; + gd->cpu_clk = CONFIG_SYS_CLK_FREQ; if ((sccr & SCCR_EBDF11) == 0) { /* No Bus Divider active */ diff --git a/configs/CMPC885_defconfig b/configs/CMPC885_defconfig index 7dff6ff..484a81b 100644 --- a/configs/CMPC885_defconfig +++ b/configs/CMPC885_defconfig @@ -4,11 +4,11 @@ CONFIG_ENV_SECT_SIZE=0x2000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="cmpc885" CONFIG_SYS_PROMPT="S3K> " +CONFIG_SYS_CLK_FREQ=132000000 CONFIG_ENV_ADDR=0x40004000 CONFIG_MPC8xx=y CONFIG_TARGET_CMPC885=y CONFIG_MPC885=y -CONFIG_8xx_GCLK_FREQ=132000000 CONFIG_CMD_IMMAP=y CONFIG_SYS_SIUMCR=0x00620000 CONFIG_SYS_SYPCR=0xFFFFFF8F diff --git a/configs/MCR3000_defconfig b/configs/MCR3000_defconfig index f96e9f0..4b5ce40 100644 --- a/configs/MCR3000_defconfig +++ b/configs/MCR3000_defconfig @@ -4,11 +4,11 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x2000 CONFIG_DEFAULT_DEVICE_TREE="mcr3000" CONFIG_SYS_PROMPT="S3K> " +CONFIG_SYS_CLK_FREQ=132000000 CONFIG_SYS_LOAD_ADDR=0x200000 CONFIG_ENV_ADDR=0x4004000 CONFIG_MPC8xx=y CONFIG_TARGET_MCR3000=y -CONFIG_8xx_GCLK_FREQ=132000000 CONFIG_CMD_IMMAP=y CONFIG_SYS_SIUMCR=0x00600400 CONFIG_SYS_SYPCR=0xFFFFFF8F -- cgit v1.1 From 21eaade449e6e50f8c41ee65953126e2a1e5d683 Mon Sep 17 00:00:00 2001 From: Christophe Leroy Date: Mon, 3 Apr 2023 10:27:39 +0200 Subject: watchdog: mpc8xx: Rename it mpc8xxx mpc8xx, mpc83xx and mpc86xx have similar watchdog with almost same memory registers. Rename it mpc8xxx which is the generic name used for drivers supporting several mpc families. The driver will be made more generic in following patch. Signed-off-by: Christophe Leroy --- arch/powerpc/Kconfig | 2 +- drivers/watchdog/Kconfig | 6 ++-- drivers/watchdog/Makefile | 2 +- drivers/watchdog/mpc8xx_wdt.c | 75 ------------------------------------------ drivers/watchdog/mpc8xxx_wdt.c | 75 ++++++++++++++++++++++++++++++++++++++++++ 5 files changed, 80 insertions(+), 80 deletions(-) delete mode 100644 drivers/watchdog/mpc8xx_wdt.c create mode 100644 drivers/watchdog/mpc8xxx_wdt.c diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig index bee59c3..f20d58b 100644 --- a/arch/powerpc/Kconfig +++ b/arch/powerpc/Kconfig @@ -31,7 +31,7 @@ config MPC8xx select CREATE_ARCH_SYMLINK select BOARD_EARLY_INIT_F imply CMD_REGINFO - imply WDT_MPC8xx + imply WDT_MPC8xxx endchoice diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index b5ac8f7..f6554d5 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -184,12 +184,12 @@ config WDT_MESON_GXBB Select this to enable Meson watchdog timer, which can be found on some Amlogic platforms. -config WDT_MPC8xx - bool "MPC8xx watchdog timer support" +config WDT_MPC8xxx + bool "MPC8xxx watchdog timer support" depends on WDT && MPC8xx select HW_WATCHDOG help - Select this to enable mpc8xx watchdog timer + Select this to enable mpc8xxx watchdog timer config WDT_MT7620 bool "MediaTek MT7620 watchdog timer support" diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index 446d961..aba1df2 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -29,7 +29,7 @@ obj-$(CONFIG_WDT_CDNS) += cdns_wdt.o obj-$(CONFIG_WDT_GPIO) += gpio_wdt.o obj-$(CONFIG_WDT_MAX6370) += max6370_wdt.o obj-$(CONFIG_WDT_MESON_GXBB) += meson_gxbb_wdt.o -obj-$(CONFIG_WDT_MPC8xx) += mpc8xx_wdt.o +obj-$(CONFIG_WDT_MPC8xxx) += mpc8xxx_wdt.o obj-$(CONFIG_WDT_MT7620) += mt7620_wdt.o obj-$(CONFIG_WDT_MT7621) += mt7621_wdt.o obj-$(CONFIG_WDT_MTK) += mtk_wdt.o diff --git a/drivers/watchdog/mpc8xx_wdt.c b/drivers/watchdog/mpc8xx_wdt.c deleted file mode 100644 index c8b104d..0000000 --- a/drivers/watchdog/mpc8xx_wdt.c +++ /dev/null @@ -1,75 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2017 CS Systemes d'Information - */ - -#include -#include -#include -#include -#include -#include -#include - -void hw_watchdog_reset(void) -{ - immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR; - - out_be16(&immap->im_siu_conf.sc_swsr, 0x556c); /* write magic1 */ - out_be16(&immap->im_siu_conf.sc_swsr, 0xaa39); /* write magic2 */ -} - -static int mpc8xx_wdt_start(struct udevice *dev, u64 timeout, ulong flags) -{ - immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR; - u32 val = CONFIG_SYS_SYPCR; - const char *mode = env_get("watchdog_mode"); - - if (strcmp(mode, "off") == 0) - val = val & ~(SYPCR_SWE | SYPCR_SWRI); - else if (strcmp(mode, "nmi") == 0) - val = (val & ~SYPCR_SWRI) | SYPCR_SWE; - - out_be32(&immap->im_siu_conf.sc_sypcr, val); - - if (!(in_be32(&immap->im_siu_conf.sc_sypcr) & SYPCR_SWE)) - return -EBUSY; - return 0; - -} - -static int mpc8xx_wdt_stop(struct udevice *dev) -{ - immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR; - - out_be32(&immap->im_siu_conf.sc_sypcr, CONFIG_SYS_SYPCR & ~SYPCR_SWE); - - if (in_be32(&immap->im_siu_conf.sc_sypcr) & SYPCR_SWE) - return -EBUSY; - return 0; -} - -static int mpc8xx_wdt_reset(struct udevice *dev) -{ - hw_watchdog_reset(); - - return 0; -} - -static const struct wdt_ops mpc8xx_wdt_ops = { - .start = mpc8xx_wdt_start, - .reset = mpc8xx_wdt_reset, - .stop = mpc8xx_wdt_stop, -}; - -static const struct udevice_id mpc8xx_wdt_ids[] = { - { .compatible = "fsl,pq1-wdt" }, - {} -}; - -U_BOOT_DRIVER(wdt_mpc8xx) = { - .name = "wdt_mpc8xx", - .id = UCLASS_WDT, - .of_match = mpc8xx_wdt_ids, - .ops = &mpc8xx_wdt_ops, -}; diff --git a/drivers/watchdog/mpc8xxx_wdt.c b/drivers/watchdog/mpc8xxx_wdt.c new file mode 100644 index 0000000..ffca3ec --- /dev/null +++ b/drivers/watchdog/mpc8xxx_wdt.c @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2017 CS Systemes d'Information + */ + +#include +#include +#include +#include +#include +#include +#include + +void hw_watchdog_reset(void) +{ + immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR; + + out_be16(&immap->im_siu_conf.sc_swsr, 0x556c); /* write magic1 */ + out_be16(&immap->im_siu_conf.sc_swsr, 0xaa39); /* write magic2 */ +} + +static int mpc8xxx_wdt_start(struct udevice *dev, u64 timeout, ulong flags) +{ + immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR; + u32 val = CONFIG_SYS_SYPCR; + const char *mode = env_get("watchdog_mode"); + + if (strcmp(mode, "off") == 0) + val = val & ~(SYPCR_SWE | SYPCR_SWRI); + else if (strcmp(mode, "nmi") == 0) + val = (val & ~SYPCR_SWRI) | SYPCR_SWE; + + out_be32(&immap->im_siu_conf.sc_sypcr, val); + + if (!(in_be32(&immap->im_siu_conf.sc_sypcr) & SYPCR_SWE)) + return -EBUSY; + return 0; + +} + +static int mpc8xxx_wdt_stop(struct udevice *dev) +{ + immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR; + + out_be32(&immap->im_siu_conf.sc_sypcr, CONFIG_SYS_SYPCR & ~SYPCR_SWE); + + if (in_be32(&immap->im_siu_conf.sc_sypcr) & SYPCR_SWE) + return -EBUSY; + return 0; +} + +static int mpc8xxx_wdt_reset(struct udevice *dev) +{ + hw_watchdog_reset(); + + return 0; +} + +static const struct wdt_ops mpc8xxx_wdt_ops = { + .start = mpc8xxx_wdt_start, + .reset = mpc8xxx_wdt_reset, + .stop = mpc8xxx_wdt_stop, +}; + +static const struct udevice_id mpc8xxx_wdt_ids[] = { + { .compatible = "fsl,pq1-wdt" }, + {} +}; + +U_BOOT_DRIVER(wdt_mpc8xxx) = { + .name = "wdt_mpc8xxx", + .id = UCLASS_WDT, + .of_match = mpc8xxx_wdt_ids, + .ops = &mpc8xxx_wdt_ops, +}; -- cgit v1.1 From 26e8ebcd7cb7eabe2d62384b22d3ed9a235cb60e Mon Sep 17 00:00:00 2001 From: Christophe Leroy Date: Mon, 3 Apr 2023 10:27:39 +0200 Subject: watchdog: mpc8xxx: Make it generic mpc8xx, mpc83xx and mpc86xx have similar watchdog with almost same memory registers. Refactor the driver to get the register addresses from the device tree and use the compatible to know the prescale factor. Calculate the watchdog setup value from the provided timeout. Don't declare it anymore as an HW_WATCHDOG, u-boot will start servicing the watchdog early enough. On mpc8xx the watchdog configuration register is also used for configuring the bus monitor. So add it as an option to the watchdog when it is mpc8xx. When watchdog is not selected, leave the configuration of the initial SYPCR from Kconfig. Signed-off-by: Christophe Leroy --- arch/powerpc/cpu/mpc8xx/Kconfig | 3 +- arch/powerpc/cpu/mpc8xx/cpu_init.c | 5 ++- arch/powerpc/dts/cmpc885.dts | 12 ++++--- arch/powerpc/dts/mcr3000.dts | 20 +++++++++-- board/cssi/mcr3000/mcr3000.c | 14 -------- configs/CMPC885_defconfig | 2 +- configs/MCR3000_defconfig | 3 +- drivers/watchdog/Kconfig | 18 +++++++++- drivers/watchdog/mpc8xxx_wdt.c | 72 ++++++++++++++++++++++++++++---------- 9 files changed, 102 insertions(+), 47 deletions(-) diff --git a/arch/powerpc/cpu/mpc8xx/Kconfig b/arch/powerpc/cpu/mpc8xx/Kconfig index a705014..bfd903b 100644 --- a/arch/powerpc/cpu/mpc8xx/Kconfig +++ b/arch/powerpc/cpu/mpc8xx/Kconfig @@ -48,7 +48,8 @@ config SYS_SIUMCR SIU Module Configuration (11-6) config SYS_SYPCR - hex "SYPCR register" + hex "SYPCR register" if !WDT_MPC8xxx + default 0 help System Protection Control (11-9) diff --git a/arch/powerpc/cpu/mpc8xx/cpu_init.c b/arch/powerpc/cpu/mpc8xx/cpu_init.c index 86b08a6..feef792 100644 --- a/arch/powerpc/cpu/mpc8xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc8xx/cpu_init.c @@ -26,10 +26,9 @@ void cpu_init_f(immap_t __iomem *immr) /* SYPCR - contains watchdog control (11-9) */ -#ifndef CONFIG_HW_WATCHDOG /* deactivate watchdog if not enabled in config */ - out_be32(&immr->im_siu_conf.sc_sypcr, CONFIG_SYS_SYPCR & ~SYPCR_SWE); -#endif + if (!IS_ENABLED(CONFIG_WDT_MPC8xxx)) + out_be32(&immr->im_siu_conf.sc_sypcr, CONFIG_SYS_SYPCR & ~SYPCR_SWE); schedule(); diff --git a/arch/powerpc/dts/cmpc885.dts b/arch/powerpc/dts/cmpc885.dts index adda0f3..7b9566a 100644 --- a/arch/powerpc/dts/cmpc885.dts +++ b/arch/powerpc/dts/cmpc885.dts @@ -18,11 +18,6 @@ stdout-path = &SERIAL; }; - WDT: watchdog@0 { - device_type = "watchdog"; - compatible = "fsl,pq1-wdt"; - }; - SERIAL: serial { compatible = "fsl,pq1-smc"; }; @@ -43,6 +38,13 @@ ranges = <0 0xff000000 0x4000>; reg = <0xff000000 0x00000200>; + WDT: watchdog@0 { + compatible = "fsl,pq1-wdt"; + reg = <0x0 0x10>; + timeout-sec = <2>; + hw_margin_ms = <1000>; + }; + CPM1_PIO_B: gpio-controller@ab8 { #gpio-cells = <2>; compatible = "fsl,cpm1-pario-bank-b"; diff --git a/arch/powerpc/dts/mcr3000.dts b/arch/powerpc/dts/mcr3000.dts index 5f32d8a..c4d7737 100644 --- a/arch/powerpc/dts/mcr3000.dts +++ b/arch/powerpc/dts/mcr3000.dts @@ -9,9 +9,25 @@ /dts-v1/; / { - WDT: watchdog@0 { - compatible = "fsl,pq1-wdt"; + #address-cells = <1>; + #size-cells = <1>; + + soc: immr@ff000000 { + #address-cells = <1>; + #size-cells = <1>; + device-type = "soc"; + compatible = "simple-bus"; + ranges = <0 0xff000000 0x4000>; + reg = <0xff000000 0x00000200>; + + WDT: watchdog@0 { + compatible = "fsl,pq1-wdt"; + reg = <0x0 0x10>; + timeout-sec = <2>; + hw_margin_ms = <1000>; + }; }; + SERIAL: smc@0 { compatible = "fsl,pq1-smc"; }; diff --git a/board/cssi/mcr3000/mcr3000.c b/board/cssi/mcr3000/mcr3000.c index 7b3ab12..3514f67 100644 --- a/board/cssi/mcr3000/mcr3000.c +++ b/board/cssi/mcr3000/mcr3000.c @@ -138,17 +138,3 @@ int board_early_init_f(void) return 0; } - -int board_early_init_r(void) -{ - struct udevice *watchdog_dev = NULL; - - if (uclass_get_device(UCLASS_WDT, 0, &watchdog_dev)) { - puts("Cannot find watchdog!\n"); - } else { - puts("Enabling watchdog.\n"); - wdt_start(watchdog_dev, 0xffff, 0); - } - - return 0; -} diff --git a/configs/CMPC885_defconfig b/configs/CMPC885_defconfig index 484a81b..1fe67d0 100644 --- a/configs/CMPC885_defconfig +++ b/configs/CMPC885_defconfig @@ -11,7 +11,6 @@ CONFIG_TARGET_CMPC885=y CONFIG_MPC885=y CONFIG_CMD_IMMAP=y CONFIG_SYS_SIUMCR=0x00620000 -CONFIG_SYS_SYPCR=0xFFFFFF8F CONFIG_SYS_TBSCR=0x00C3 CONFIG_SYS_PISCR=0x0000 CONFIG_SYS_PLPRCR_BOOL=y @@ -106,5 +105,6 @@ CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_MPC8XX_SPI=y CONFIG_WDT=y +CONFIG_WDT_MPC8xxx_BME=y # CONFIG_REGEX is not set CONFIG_LZMA=y diff --git a/configs/MCR3000_defconfig b/configs/MCR3000_defconfig index 4b5ce40..fc2bf5b 100644 --- a/configs/MCR3000_defconfig +++ b/configs/MCR3000_defconfig @@ -11,7 +11,6 @@ CONFIG_MPC8xx=y CONFIG_TARGET_MCR3000=y CONFIG_CMD_IMMAP=y CONFIG_SYS_SIUMCR=0x00600400 -CONFIG_SYS_SYPCR=0xFFFFFF8F CONFIG_SYS_TBSCR=0x00C3 CONFIG_SYS_PISCR=0x0000 CONFIG_SYS_PLPRCR_BOOL=y @@ -29,7 +28,6 @@ CONFIG_AUTOBOOT_PROMPT="\nEnter password - autoboot in %d sec...\n" CONFIG_AUTOBOOT_DELAY_STR="root" CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="run flashboot" -CONFIG_BOARD_EARLY_INIT_R=y # CONFIG_HWCONFIG is not set CONFIG_MISC_INIT_R=y CONFIG_HUSH_PARSER=y @@ -102,4 +100,5 @@ CONFIG_MPC8XX_FEC=y # CONFIG_PCI is not set CONFIG_DM_SERIAL=y CONFIG_WDT=y +CONFIG_WDT_MPC8xxx_BME=y CONFIG_LZMA=y diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index f6554d5..f7fbb28 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -187,10 +187,26 @@ config WDT_MESON_GXBB config WDT_MPC8xxx bool "MPC8xxx watchdog timer support" depends on WDT && MPC8xx - select HW_WATCHDOG help Select this to enable mpc8xxx watchdog timer +config WDT_MPC8xxx_BME + bool "Enable MPC8xx Bus Monitoring" + depends on WDT_MPC8xxx && MPC8xx + help + Select this to enable mpc8xx Bus Monitor. + +config WDT_MPC8xxx_BMT + int "MPC8xx Bus Monitor Timing" if WDT_MPC8xxx_BME + range 0 255 + default 255 + depends on WDT_MPC8xxx + help + Bus monitor timing. Defines the timeout period, in 8 system clock + resolution, for the bus monitor. + + Maximum timeout is 2,040 clocks (255 x 8). + config WDT_MT7620 bool "MediaTek MT7620 watchdog timer support" depends on WDT && SOC_MT7620 diff --git a/drivers/watchdog/mpc8xxx_wdt.c b/drivers/watchdog/mpc8xxx_wdt.c index ffca3ec..9a29938 100644 --- a/drivers/watchdog/mpc8xxx_wdt.c +++ b/drivers/watchdog/mpc8xxx_wdt.c @@ -7,32 +7,61 @@ #include #include #include -#include -#include +#include #include -void hw_watchdog_reset(void) +struct mpc8xxx_wdt { + __be32 res0; + __be32 swcrr; /* System watchdog control register */ +#define SWCRR_SWTC 0xFFFF0000 /* Software Watchdog Time Count. */ +#define SWCRR_BME 0x00000080 /* Bus monitor enable (mpc8xx) */ +#define SWCRR_SWF 0x00000008 /* Software Watchdog Freeze (mpc8xx). */ +#define SWCRR_SWEN 0x00000004 /* Watchdog Enable bit. */ +#define SWCRR_SWRI 0x00000002 /* Software Watchdog Reset/Interrupt Select bit.*/ +#define SWCRR_SWPR 0x00000001 /* Software Watchdog Counter Prescale bit. */ + __be32 swcnr; /* System watchdog count register */ + u8 res1[2]; + __be16 swsrr; /* System watchdog service register */ + u8 res2[0xf0]; +}; + +struct mpc8xxx_wdt_priv { + struct mpc8xxx_wdt __iomem *base; +}; + +static int mpc8xxx_wdt_reset(struct udevice *dev) { - immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR; + struct mpc8xxx_wdt_priv *priv = dev_get_priv(dev); + + out_be16(&priv->base->swsrr, 0x556c); /* write magic1 */ + out_be16(&priv->base->swsrr, 0xaa39); /* write magic2 */ - out_be16(&immap->im_siu_conf.sc_swsr, 0x556c); /* write magic1 */ - out_be16(&immap->im_siu_conf.sc_swsr, 0xaa39); /* write magic2 */ + return 0; } static int mpc8xxx_wdt_start(struct udevice *dev, u64 timeout, ulong flags) { - immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR; - u32 val = CONFIG_SYS_SYPCR; + struct mpc8xxx_wdt_priv *priv = dev_get_priv(dev); const char *mode = env_get("watchdog_mode"); + ulong prescaler = dev_get_driver_data(dev); + u16 swtc = min_t(u16, timeout * get_board_sys_clk() / 1000 / prescaler, U16_MAX); + u32 val; + + mpc8xxx_wdt_reset(dev); if (strcmp(mode, "off") == 0) - val = val & ~(SYPCR_SWE | SYPCR_SWRI); + val = (swtc << 16) | SWCRR_SWPR; else if (strcmp(mode, "nmi") == 0) - val = (val & ~SYPCR_SWRI) | SYPCR_SWE; + val = (swtc << 16) | SWCRR_SWPR | SWCRR_SWEN; + else + val = (swtc << 16) | SWCRR_SWPR | SWCRR_SWEN | SWCRR_SWRI; + + if (IS_ENABLED(CONFIG_WDT_MPC8xxx_BME)) + val |= (CONFIG_WDT_MPC8xxx_BMT << 8) | SWCRR_BME; - out_be32(&immap->im_siu_conf.sc_sypcr, val); + out_be32(&priv->base->swcrr, val); - if (!(in_be32(&immap->im_siu_conf.sc_sypcr) & SYPCR_SWE)) + if (!(in_be32(&priv->base->swcrr) & SWCRR_SWEN)) return -EBUSY; return 0; @@ -40,18 +69,23 @@ static int mpc8xxx_wdt_start(struct udevice *dev, u64 timeout, ulong flags) static int mpc8xxx_wdt_stop(struct udevice *dev) { - immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR; + struct mpc8xxx_wdt_priv *priv = dev_get_priv(dev); - out_be32(&immap->im_siu_conf.sc_sypcr, CONFIG_SYS_SYPCR & ~SYPCR_SWE); + clrbits_be32(&priv->base->swcrr, SWCRR_SWEN); - if (in_be32(&immap->im_siu_conf.sc_sypcr) & SYPCR_SWE) + if (in_be32(&priv->base->swcrr) & SWCRR_SWEN) return -EBUSY; return 0; } -static int mpc8xxx_wdt_reset(struct udevice *dev) +static int mpc8xxx_wdt_of_to_plat(struct udevice *dev) { - hw_watchdog_reset(); + struct mpc8xxx_wdt_priv *priv = dev_get_priv(dev); + + priv->base = (void __iomem *)devfdt_remap_addr(dev); + + if (!priv->base) + return -EINVAL; return 0; } @@ -63,7 +97,7 @@ static const struct wdt_ops mpc8xxx_wdt_ops = { }; static const struct udevice_id mpc8xxx_wdt_ids[] = { - { .compatible = "fsl,pq1-wdt" }, + { .compatible = "fsl,pq1-wdt", .data = 0x800 }, {} }; @@ -72,4 +106,6 @@ U_BOOT_DRIVER(wdt_mpc8xxx) = { .id = UCLASS_WDT, .of_match = mpc8xxx_wdt_ids, .ops = &mpc8xxx_wdt_ops, + .of_to_plat = mpc8xxx_wdt_of_to_plat, + .priv_auto = sizeof(struct mpc8xxx_wdt_priv), }; -- cgit v1.1 From 0fd79138dc2394ea7820f583f8abfa06be0155f9 Mon Sep 17 00:00:00 2001 From: Christophe Leroy Date: Mon, 3 Apr 2023 10:39:59 +0200 Subject: watchdog: mpc8xxx: Add support for mpc83xx Introduce a new compatible "fsl,pq2pro-wdt" On mpc83xx, the prescaling factor is 0x10000. Don't write the watchdog configuration register in start.S as it can be written only once. Signed-off-by: Christophe Leroy --- arch/powerpc/cpu/mpc83xx/cpu.c | 2 +- arch/powerpc/cpu/mpc83xx/start.S | 2 ++ drivers/watchdog/Kconfig | 2 +- drivers/watchdog/mpc8xxx_wdt.c | 1 + 4 files changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/cpu/mpc83xx/cpu.c b/arch/powerpc/cpu/mpc83xx/cpu.c index a6c0635..f6ffe29 100644 --- a/arch/powerpc/cpu/mpc83xx/cpu.c +++ b/arch/powerpc/cpu/mpc83xx/cpu.c @@ -165,7 +165,7 @@ unsigned long get_tbclk(void) } #endif -#if defined(CONFIG_WATCHDOG) +#if defined(CONFIG_WATCHDOG) && !defined(CONFIG_WDT) void watchdog_reset (void) { int re_enable = disable_interrupts(); diff --git a/arch/powerpc/cpu/mpc83xx/start.S b/arch/powerpc/cpu/mpc83xx/start.S index e3878e4..4329b17 100644 --- a/arch/powerpc/cpu/mpc83xx/start.S +++ b/arch/powerpc/cpu/mpc83xx/start.S @@ -483,6 +483,7 @@ init_e300_core: /* time t 10 */ lis r3, CONFIG_SYS_IMMR@h +#ifndef CONFIG_WDT_MPC8xxx #if defined(CONFIG_WATCHDOG) /* Initialise the Watchdog values and reset it (if req) */ /*------------------------------------------------------*/ @@ -508,6 +509,7 @@ init_e300_core: /* time t 10 */ stw r4, SWCRR(r3) 1: #endif /* CONFIG_WATCHDOG */ +#endif #if defined(CONFIG_MASK_AER_AO) /* Write the Arbiter Event Enable to mask Address Only traps. */ diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index f7fbb28..f776759 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -186,7 +186,7 @@ config WDT_MESON_GXBB config WDT_MPC8xxx bool "MPC8xxx watchdog timer support" - depends on WDT && MPC8xx + depends on WDT && (MPC8xx || MPC83xx) help Select this to enable mpc8xxx watchdog timer diff --git a/drivers/watchdog/mpc8xxx_wdt.c b/drivers/watchdog/mpc8xxx_wdt.c index 9a29938..f28636c 100644 --- a/drivers/watchdog/mpc8xxx_wdt.c +++ b/drivers/watchdog/mpc8xxx_wdt.c @@ -98,6 +98,7 @@ static const struct wdt_ops mpc8xxx_wdt_ops = { static const struct udevice_id mpc8xxx_wdt_ids[] = { { .compatible = "fsl,pq1-wdt", .data = 0x800 }, + { .compatible = "fsl,pq2pro-wdt", .data = 0x10000 }, {} }; -- cgit v1.1 From 6792e85ee643e412d7c61fe3699326498260ece7 Mon Sep 17 00:00:00 2001 From: Christophe Leroy Date: Thu, 2 Mar 2023 10:48:58 +0100 Subject: powerpc: mpc832x: Fix reset word According to the reference manual, the Reset Configuration Word Low Register bits 2-3 must be set to 0b10. Signed-off-by: Christophe Leroy --- arch/powerpc/cpu/mpc83xx/hrcw/Kconfig | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/powerpc/cpu/mpc83xx/hrcw/Kconfig b/arch/powerpc/cpu/mpc83xx/hrcw/Kconfig index b67ccd6..44f66cd 100644 --- a/arch/powerpc/cpu/mpc83xx/hrcw/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/hrcw/Kconfig @@ -539,8 +539,7 @@ config DDR_MC_CLOCK_MODE config SYSTEM_PLL_VCO_DIV int - default 0 if ARCH_MPC832X - default 2 if ARCH_MPC8313 + default 2 if ARCH_MPC8313 || ARCH_MPC832X default 0 if SYSTEM_PLL_VCO_DIV_2 && !ARCH_MPC8360 && !ARCH_MPC837X default 1 if SYSTEM_PLL_VCO_DIV_4 && !ARCH_MPC8360 && !ARCH_MPC837X default 2 if SYSTEM_PLL_VCO_DIV_8 && !ARCH_MPC8360 && !ARCH_MPC837X -- cgit v1.1 From 8886a819615eac220aba1de77b996a6da0b68155 Mon Sep 17 00:00:00 2001 From: Christophe Leroy Date: Tue, 4 Apr 2023 15:09:18 +0200 Subject: powerpc: mpc83xx: Fix soc.h There are helpers included in soc.h Declare them static inline so that soc.h can be included in several places. Signed-off-by: Christophe Leroy --- arch/powerpc/include/asm/arch-mpc83xx/soc.h | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/powerpc/include/asm/arch-mpc83xx/soc.h b/arch/powerpc/include/asm/arch-mpc83xx/soc.h index 39bf7d5..ce54f9b 100644 --- a/arch/powerpc/include/asm/arch-mpc83xx/soc.h +++ b/arch/powerpc/include/asm/arch-mpc83xx/soc.h @@ -18,14 +18,14 @@ enum soc_type { SOC_MPC8379, }; -bool mpc83xx_has_sdhc(int type) +static inline bool mpc83xx_has_sdhc(int type) { return (type == SOC_MPC8308) || (type == SOC_MPC8309) || (type == SOC_MPC8379); } -bool mpc83xx_has_tsec(int type) +static inline bool mpc83xx_has_tsec(int type) { return (type == SOC_MPC8308) || (type == SOC_MPC8313) || @@ -34,37 +34,37 @@ bool mpc83xx_has_tsec(int type) (type == SOC_MPC8379); } -bool mpc83xx_has_pcie1(int type) +static inline bool mpc83xx_has_pcie1(int type) { return (type == SOC_MPC8308) || (type == SOC_MPC8315) || (type == SOC_MPC8379); } -bool mpc83xx_has_pcie2(int type) +static inline bool mpc83xx_has_pcie2(int type) { return (type == SOC_MPC8315) || (type == SOC_MPC8379); } -bool mpc83xx_has_sata(int type) +static inline bool mpc83xx_has_sata(int type) { return (type == SOC_MPC8315) || (type == SOC_MPC8379); } -bool mpc83xx_has_pci(int type) +static inline bool mpc83xx_has_pci(int type) { return type != SOC_MPC8308; } -bool mpc83xx_has_second_i2c(int type) +static inline bool mpc83xx_has_second_i2c(int type) { return (type != SOC_MPC8315) && (type != SOC_MPC832X); } -bool mpc83xx_has_quicc_engine(int type) +static inline bool mpc83xx_has_quicc_engine(int type) { return (type == SOC_MPC8309) || (type == SOC_MPC832X) || -- cgit v1.1 From b20db903c80906c0ba4a2da708c398413a9f9845 Mon Sep 17 00:00:00 2001 From: Christophe Leroy Date: Wed, 18 Jan 2023 20:52:38 +0100 Subject: powerpc: mpc83xx: Don't activate MMU when not necessary At startup, some RAM is needed (for instance for stack) before DRAM is initialised. One way to offer such RAM, used by mpc83xx, is to lock some entries in the cache. To do that, MMU needs to be activated. On mpc83xx having a QUICC Engine an alternative is to user some part of from the Multi User RAM, like done on mpc8xx for instance. For that, the MMU is not needed. Activating the MMU is problematic because exception vectors are not setup yet so in case of ISI or DSI that CPU will crash and reboot. At the time being, MMU is activated regardless. Only activate it when locking cache entries to provide initial RAM. Signed-off-by: Christophe Leroy --- arch/powerpc/cpu/mpc83xx/start.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/powerpc/cpu/mpc83xx/start.S b/arch/powerpc/cpu/mpc83xx/start.S index 4329b17..6749263 100644 --- a/arch/powerpc/cpu/mpc83xx/start.S +++ b/arch/powerpc/cpu/mpc83xx/start.S @@ -215,6 +215,7 @@ in_flash: * gt-regs BAT can be reused after board_init_f calls * board_early_init_f (EVB only). */ +#ifdef CONFIG_SYS_INIT_RAM_LOCK /* enable address translation */ bl enable_addr_trans sync @@ -222,7 +223,6 @@ in_flash: /* enable the data cache */ bl dcache_enable sync -#ifdef CONFIG_SYS_INIT_RAM_LOCK bl lock_ram_in_cache sync #endif -- cgit v1.1 From 34ae2b2abb950e62e64721b14c6ee8c8794c1ca4 Mon Sep 17 00:00:00 2001 From: Christophe Leroy Date: Mon, 3 Apr 2023 14:16:56 +0200 Subject: clk: mpc83xx: Fix clocks for mpc832x gd->arch.sdhc_clk only exists when CONFIG_FSL_ESDHC is set, so enclose it inside ifdefs. gd->arch.qe_clk and gd->arch.brg_clk must be populated when CONFIG_QE is set. Signed-off-by: Christophe Leroy --- drivers/clk/mpc83xx_clk.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/clk/mpc83xx_clk.c b/drivers/clk/mpc83xx_clk.c index 0255cca..cc73445 100644 --- a/drivers/clk/mpc83xx_clk.c +++ b/drivers/clk/mpc83xx_clk.c @@ -346,8 +346,10 @@ static int mpc83xx_clk_probe(struct udevice *dev) type = dev_get_driver_data(dev); +#ifdef CONFIG_FSL_ESDHC if (mpc83xx_has_sdhc(type)) gd->arch.sdhc_clk = priv->speed[MPC83XX_CLK_SDHC]; +#endif gd->arch.core_clk = priv->speed[MPC83XX_CLK_CORE]; gd->arch.i2c1_clk = priv->speed[MPC83XX_CLK_I2C1]; @@ -362,6 +364,11 @@ static int mpc83xx_clk_probe(struct udevice *dev) gd->cpu_clk = priv->speed[MPC83XX_CLK_CORE]; gd->bus_clk = priv->speed[MPC83XX_CLK_CSB]; +#ifdef CONFIG_QE + gd->arch.qe_clk = priv->speed[MPC83XX_CLK_QE]; + gd->arch.brg_clk = priv->speed[MPC83XX_CLK_BRG]; +#endif + return 0; } -- cgit v1.1 From e1fff66079d29ef59521771cf0aaa5ac4a834b50 Mon Sep 17 00:00:00 2001 From: Christophe Leroy Date: Tue, 21 Feb 2023 19:31:11 +0100 Subject: gpio: Add QUICC Engine GPIOs driver The mpc832x has GPIOs handled by the QUICC Engine. The registers are different from the one for the non QE mpc83xx GPIOs. Implement a GPIO driver for those. Signed-off-by: Christophe Leroy --- arch/powerpc/include/asm/arch-mpc83xx/gpio.h | 5 + drivers/gpio/Kconfig | 18 +++ drivers/gpio/Makefile | 1 + drivers/gpio/qe_gpio.c | 170 +++++++++++++++++++++++++++ 4 files changed, 194 insertions(+) create mode 100644 drivers/gpio/qe_gpio.c diff --git a/arch/powerpc/include/asm/arch-mpc83xx/gpio.h b/arch/powerpc/include/asm/arch-mpc83xx/gpio.h index 19c2506..df95d22 100644 --- a/arch/powerpc/include/asm/arch-mpc83xx/gpio.h +++ b/arch/powerpc/include/asm/arch-mpc83xx/gpio.h @@ -22,6 +22,11 @@ struct mpc8xxx_gpio_plat { uint ngpios; }; +struct qe_gpio_plat { + ulong addr; + unsigned long size; +}; + #ifndef DM_GPIO void mpc83xx_gpio_init_f(void); void mpc83xx_gpio_init_r(void); diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 7d5ddbd..9bf6e42 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -547,6 +547,24 @@ config MPC8XXX_GPIO value setting, the open-drain feature, which can configure individual GPIOs to work as open-drain outputs, is supported. +config QE_GPIO + bool "Freescale QUICC ENGINE GPIO driver" + depends on DM_GPIO + depends on QE + help + This driver supports the QUICC Engine GPIOs of MPC83XX CPUs. + Each GPIO bank is identified by its own entry in the device tree, + i.e. + + qe_pio_a: gpio-controller@1400 { + compatible = "fsl,mpc8323-qe-pario-bank"; + reg = <0x1400 0x18>; + gpio-controller; + #gpio-cells = <2>; + }; + + Each bank has 32 GPIOs. + config MPC8XX_GPIO bool "Freescale MPC8XX GPIO driver" depends on DM_GPIO diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 1e81e36..64a36c4 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -38,6 +38,7 @@ obj-$(CONFIG_TEGRA186_GPIO) += tegra186_gpio.o obj-$(CONFIG_DA8XX_GPIO) += da8xx_gpio.o obj-$(CONFIG_ALTERA_PIO) += altera_pio.o obj-$(CONFIG_MPC8XXX_GPIO) += mpc8xxx_gpio.o +obj-$(CONFIG_QE_GPIO) += qe_gpio.o obj-$(CONFIG_MPC8XX_GPIO) += mpc8xx_gpio.o obj-$(CONFIG_MPC83XX_SPISEL_BOOT) += mpc83xx_spisel_boot.o obj-$(CONFIG_SH_GPIO_PFC) += sh_pfc.o diff --git a/drivers/gpio/qe_gpio.c b/drivers/gpio/qe_gpio.c new file mode 100644 index 0000000..16e8d1e --- /dev/null +++ b/drivers/gpio/qe_gpio.c @@ -0,0 +1,170 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2023 CR GROUP France + * Christophe Leroy + */ + +#include +#include +#include +#include +#include +#include +#include + +#define QE_DIR_NONE 0 +#define QE_DIR_OUT 1 +#define QE_DIR_IN 2 +#define QE_DIR_IN_OUT 3 + +struct qe_gpio_data { + /* The bank's register base in memory */ + struct gpio_n __iomem *base; + /* The address of the registers; used to identify the bank */ + phys_addr_t addr; +}; + +static inline u32 gpio_mask(uint gpio) +{ + return 1U << (31 - (gpio)); +} + +static inline u32 gpio_mask2(uint gpio) +{ + return 1U << (30 - ((gpio & 15) << 1)); +} + +static int qe_gpio_direction_input(struct udevice *dev, uint gpio) +{ + struct qe_gpio_data *data = dev_get_priv(dev); + struct gpio_n __iomem *base = data->base; + u32 mask2 = gpio_mask2(gpio); + + if (gpio < 16) + clrsetbits_be32(&base->dir1, mask2 * QE_DIR_OUT, mask2 * QE_DIR_IN); + else + clrsetbits_be32(&base->dir2, mask2 * QE_DIR_OUT, mask2 * QE_DIR_IN); + + return 0; +} + +static int qe_gpio_set_value(struct udevice *dev, uint gpio, int value) +{ + struct qe_gpio_data *data = dev_get_priv(dev); + struct gpio_n __iomem *base = data->base; + u32 mask = gpio_mask(gpio); + u32 mask2 = gpio_mask2(gpio); + + if (gpio < 16) + clrsetbits_be32(&base->dir1, mask2 * QE_DIR_IN, mask2 * QE_DIR_OUT); + else + clrsetbits_be32(&base->dir2, mask2 * QE_DIR_IN, mask2 * QE_DIR_OUT); + + if (value) + setbits_be32(&base->pdat, mask); + else + clrbits_be32(&base->pdat, mask); + + return 0; +} + +static int qe_gpio_get_value(struct udevice *dev, uint gpio) +{ + struct qe_gpio_data *data = dev_get_priv(dev); + struct gpio_n __iomem *base = data->base; + u32 mask = gpio_mask(gpio); + + return !!(in_be32(&base->pdat) & mask); +} + +static int qe_gpio_get_function(struct udevice *dev, uint gpio) +{ + struct qe_gpio_data *data = dev_get_priv(dev); + struct gpio_n __iomem *base = data->base; + u32 mask2 = gpio_mask2(gpio); + int dir; + + if (gpio < 16) + dir = in_be32(&base->dir1); + else + dir = in_be32(&base->dir2); + + if ((dir & (mask2 * QE_DIR_IN_OUT)) == (mask2 & QE_DIR_IN)) + return GPIOF_INPUT; + else if ((dir & (mask2 * QE_DIR_IN_OUT)) == (mask2 & QE_DIR_OUT)) + return GPIOF_OUTPUT; + else + return GPIOF_UNKNOWN; +} + +static int qe_gpio_of_to_plat(struct udevice *dev) +{ + struct qe_gpio_plat *plat = dev_get_plat(dev); + + plat->addr = dev_read_addr_size_index(dev, 0, (fdt_size_t *)&plat->size); + + return 0; +} + +static int qe_gpio_plat_to_priv(struct udevice *dev) +{ + struct qe_gpio_data *priv = dev_get_priv(dev); + struct qe_gpio_plat *plat = dev_get_plat(dev); + unsigned long size = plat->size; + + if (size == 0) + size = sizeof(struct gpio_n); + + priv->addr = plat->addr; + priv->base = (void __iomem *)plat->addr; + + if (!priv->base) + return -ENOMEM; + + return 0; +} + +static int qe_gpio_probe(struct udevice *dev) +{ + struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); + struct qe_gpio_data *data = dev_get_priv(dev); + char name[32], *str; + + qe_gpio_plat_to_priv(dev); + + snprintf(name, sizeof(name), "QE@%.8llx", + (unsigned long long)data->addr); + str = strdup(name); + + if (!str) + return -ENOMEM; + + uc_priv->bank_name = str; + uc_priv->gpio_count = 32; + + return 0; +} + +static const struct dm_gpio_ops gpio_qe_ops = { + .direction_input = qe_gpio_direction_input, + .direction_output = qe_gpio_set_value, + .get_value = qe_gpio_get_value, + .set_value = qe_gpio_set_value, + .get_function = qe_gpio_get_function, +}; + +static const struct udevice_id qe_gpio_ids[] = { + { .compatible = "fsl,mpc8323-qe-pario-bank"}, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(gpio_qe) = { + .name = "gpio_qe", + .id = UCLASS_GPIO, + .ops = &gpio_qe_ops, + .of_to_plat = qe_gpio_of_to_plat, + .plat_auto = sizeof(struct qe_gpio_plat), + .of_match = qe_gpio_ids, + .probe = qe_gpio_probe, + .priv_auto = sizeof(struct qe_gpio_data), +}; -- cgit v1.1 From 83945efacff3ee4ed15457b2b9b627aab9814eba Mon Sep 17 00:00:00 2001 From: Christophe Leroy Date: Thu, 2 Mar 2023 16:26:26 +0100 Subject: spi: mpc8xxx: Add support for SPI on mpc832x On mpc832x, SPI can be either handled by CPU or QE. In order to work in CPU mode, bit 17 of SPMODE has to be set to 1, that bit is called OP. Also, data is located at a different place than the one expected by the driver today. In 8 bits mode with REV set, data to be transmitted is located in the most significant byte while received data is located in second byte. So perform the necessary shifts. In order to differentiate with other CPUs, a new compatible is added for mpc832x: fsl,mpc832x-spi Signed-off-by: Christophe Leroy Cc: Rasmus Villemoes --- arch/powerpc/include/asm/mpc8xxx_spi.h | 1 + drivers/spi/mpc8xxx_spi.c | 13 +++++++++++++ 2 files changed, 14 insertions(+) diff --git a/arch/powerpc/include/asm/mpc8xxx_spi.h b/arch/powerpc/include/asm/mpc8xxx_spi.h index 83cfe23..8e9411a 100644 --- a/arch/powerpc/include/asm/mpc8xxx_spi.h +++ b/arch/powerpc/include/asm/mpc8xxx_spi.h @@ -12,6 +12,7 @@ #if defined(CONFIG_ARCH_MPC8308) || \ defined(CONFIG_ARCH_MPC8313) || \ + defined(CONFIG_ARCH_MPC832X) || \ defined(CONFIG_ARCH_MPC834X) || \ defined(CONFIG_ARCH_MPC837X) diff --git a/drivers/spi/mpc8xxx_spi.c b/drivers/spi/mpc8xxx_spi.c index 6869d60..7889217 100644 --- a/drivers/spi/mpc8xxx_spi.c +++ b/drivers/spi/mpc8xxx_spi.c @@ -16,6 +16,7 @@ #include #include #include +#include enum { SPI_EV_NE = BIT(31 - 22), /* Receiver Not Empty */ @@ -30,6 +31,7 @@ enum { SPI_MODE_REV = BIT(31 - 5), /* Reverse mode - MSB first */ SPI_MODE_MS = BIT(31 - 6), /* Always master */ SPI_MODE_EN = BIT(31 - 7), /* Enable interface */ + SPI_MODE_OP = BIT(31 - 17), /* CPU Mode, QE otherwise */ SPI_MODE_LEN_MASK = 0xf00000, SPI_MODE_LEN_SHIFT = 20, @@ -89,6 +91,9 @@ static int mpc8xxx_spi_probe(struct udevice *dev) */ out_be32(&priv->spi->mode, SPI_MODE_REV | SPI_MODE_MS); + if (dev_get_driver_data(dev) == SOC_MPC832X) + setbits_be32(&priv->spi->mode, SPI_MODE_OP); + /* set len to 8 bits */ setbits_be32(&spi->mode, (8 - 1) << SPI_MODE_LEN_SHIFT); @@ -130,6 +135,7 @@ static int mpc8xxx_spi_xfer(struct udevice *dev, uint bitlen, u32 tmpdin = 0, tmpdout = 0, n; const u8 *cout = dout; u8 *cin = din; + ulong type = dev_get_driver_data(bus); debug("%s: slave %s:%u dout %08X din %08X bitlen %u\n", __func__, bus->name, plat->cs, (uint)dout, (uint)din, bitlen); @@ -157,6 +163,9 @@ static int mpc8xxx_spi_xfer(struct udevice *dev, uint bitlen, if (cout) tmpdout = *cout++; + if (type == SOC_MPC832X) + tmpdout <<= 24; + /* Write the data out */ out_be32(&spi->tx, tmpdout); @@ -179,6 +188,9 @@ static int mpc8xxx_spi_xfer(struct udevice *dev, uint bitlen, tmpdin = in_be32(&spi->rx); setbits_be32(&spi->event, SPI_EV_NE); + if (type == SOC_MPC832X) + tmpdin >>= 16; + if (cin) *cin++ = tmpdin; @@ -271,6 +283,7 @@ static const struct dm_spi_ops mpc8xxx_spi_ops = { static const struct udevice_id mpc8xxx_spi_ids[] = { { .compatible = "fsl,spi" }, + { .compatible = "fsl,mpc832x-spi", .data = SOC_MPC832X }, { } }; -- cgit v1.1 From 71e94640fb9b57fd1109898a7f2cb5de4a116620 Mon Sep 17 00:00:00 2001 From: Christophe Leroy Date: Fri, 28 Apr 2023 17:42:33 +0200 Subject: board: cssi: Migrate to hashed password Use a hashed password instead of clear text in order to improve board security. Signed-off-by: Christophe Leroy --- configs/CMPC885_defconfig | 5 ++++- configs/MCR3000_defconfig | 5 ++++- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/configs/CMPC885_defconfig b/configs/CMPC885_defconfig index 1fe67d0..b1df954 100644 --- a/configs/CMPC885_defconfig +++ b/configs/CMPC885_defconfig @@ -23,8 +23,11 @@ CONFIG_FIT=y CONFIG_OF_BOARD_SETUP=y CONFIG_BOOTDELAY=5 CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_FLUSH_STDIN=y CONFIG_AUTOBOOT_PROMPT="\nEnter password - autoboot in %d sec...\n" -CONFIG_AUTOBOOT_DELAY_STR="root" +CONFIG_AUTOBOOT_ENCRYPTION=y +CONFIG_AUTOBOOT_STOP_STR_ENABLE=y +CONFIG_AUTOBOOT_STOP_STR_SHA256="4813494d137e1631bba301d5acab6e7bb7aa74ce1185d456565ef51d737677b2" CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="run flashboot" CONFIG_BOARD_EARLY_INIT_R=y diff --git a/configs/MCR3000_defconfig b/configs/MCR3000_defconfig index fc2bf5b..d113ffe 100644 --- a/configs/MCR3000_defconfig +++ b/configs/MCR3000_defconfig @@ -24,8 +24,11 @@ CONFIG_OF_BOARD_SETUP=y CONFIG_SYS_MONITOR_BASE=0x04000000 CONFIG_BOOTDELAY=5 CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_FLUSH_STDIN=y CONFIG_AUTOBOOT_PROMPT="\nEnter password - autoboot in %d sec...\n" -CONFIG_AUTOBOOT_DELAY_STR="root" +CONFIG_AUTOBOOT_ENCRYPTION=y +CONFIG_AUTOBOOT_STOP_STR_ENABLE=y +CONFIG_AUTOBOOT_STOP_STR_SHA256="4813494d137e1631bba301d5acab6e7bb7aa74ce1185d456565ef51d737677b2" CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="run flashboot" # CONFIG_HWCONFIG is not set -- cgit v1.1 From 3155b0af4eab045b145681a53ebec04bd836b17c Mon Sep 17 00:00:00 2001 From: Christophe Leroy Date: Tue, 4 Apr 2023 12:42:15 +0200 Subject: board: cssi: Create dedicated file for common sources In preparation of the new cssi board called cmpcpro which we be introduce in a future patch, move common functions into a dedicated file in a common directory. Signed-off-by: Christophe Leroy --- board/cssi/cmpc885/Makefile | 2 +- board/cssi/cmpc885/cmpc885.c | 54 ++------------------------------------ board/cssi/common/common.c | 62 ++++++++++++++++++++++++++++++++++++++++++++ board/cssi/common/common.h | 8 ++++++ 4 files changed, 73 insertions(+), 53 deletions(-) create mode 100644 board/cssi/common/common.c create mode 100644 board/cssi/common/common.h diff --git a/board/cssi/cmpc885/Makefile b/board/cssi/cmpc885/Makefile index 6c05509..baf9e5a 100644 --- a/board/cssi/cmpc885/Makefile +++ b/board/cssi/cmpc885/Makefile @@ -5,6 +5,6 @@ # Christophe Leroy # -obj-y += cmpc885.o +obj-y += cmpc885.o ../common/common.o obj-y += sdram.o obj-$(CONFIG_CMD_NAND) += nand.o diff --git a/board/cssi/cmpc885/cmpc885.c b/board/cssi/cmpc885/cmpc885.c index 5233c24..689d573 100644 --- a/board/cssi/cmpc885/cmpc885.c +++ b/board/cssi/cmpc885/cmpc885.c @@ -22,9 +22,10 @@ #include #include #include - #include +#include "../common/common.h" + DECLARE_GLOBAL_DATA_PTR; #define BOARD_CMPC885 "cmpc885" @@ -59,57 +60,6 @@ DECLARE_GLOBAL_DATA_PTR; #define R_RESET_STATUS 0x0400 #define R_RST_STATUS 0x0004 -static int fdt_set_node_and_value(void *blob, char *node, const char *prop, - void *var, int size) -{ - int ret, off; - - off = fdt_path_offset(blob, node); - - if (off < 0) { - printf("Cannot find %s node err:%s\n", node, fdt_strerror(off)); - - return off; - } - - ret = fdt_setprop(blob, off, prop, var, size); - - if (ret < 0) - printf("Cannot set %s/%s prop err: %s\n", node, prop, fdt_strerror(ret)); - - return ret; -} - -/* Checks front/rear id and remove unneeded nodes from the blob */ -static void ft_cleanup(void *blob, uint32_t id, const char *prop, const char *compatible) -{ - int off; - - off = fdt_node_offset_by_compatible(blob, -1, compatible); - - while (off != -FDT_ERR_NOTFOUND) { - const struct fdt_property *ids; - int nb_ids, idx; - int tmp = -1; - - ids = fdt_get_property(blob, off, prop, &nb_ids); - - for (idx = 0; idx < nb_ids; idx += 4) { - if (*((uint32_t *)&ids->data[idx]) == id) - break; - } - - if (idx >= nb_ids) - fdt_del_node(blob, off); - else - tmp = off; - - off = fdt_node_offset_by_compatible(blob, tmp, compatible); - } - - fdt_set_node_and_value(blob, "/", prop, &id, sizeof(uint32_t)); -} - int ft_board_setup(void *blob, struct bd_info *bd) { u8 fav_id, far_id; diff --git a/board/cssi/common/common.c b/board/cssi/common/common.c new file mode 100644 index 0000000..71b35cc --- /dev/null +++ b/board/cssi/common/common.c @@ -0,0 +1,62 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2010-2020 CS Group + * Charles Frey + * Florent Trinh Thai + * Christophe Leroy + * + * Common specific routines for the CS Group boards + */ + +#include + +static int fdt_set_node_and_value(void *blob, char *node, const char *prop, + void *var, int size) +{ + int ret, off; + + off = fdt_path_offset(blob, node); + + if (off < 0) { + printf("Cannot find %s node err:%s\n", node, fdt_strerror(off)); + + return off; + } + + ret = fdt_setprop(blob, off, prop, var, size); + + if (ret < 0) + printf("Cannot set %s/%s prop err: %s\n", node, prop, fdt_strerror(ret)); + + return ret; +} + +/* Checks front/rear id and remove unneeded nodes from the blob */ +void ft_cleanup(void *blob, unsigned long id, const char *prop, const char *compatible) +{ + int off; + + off = fdt_node_offset_by_compatible(blob, -1, compatible); + + while (off != -FDT_ERR_NOTFOUND) { + const struct fdt_property *ids; + int nb_ids, idx; + int tmp = -1; + + ids = fdt_get_property(blob, off, prop, &nb_ids); + + for (idx = 0; idx < nb_ids; idx += 4) { + if (*((uint32_t *)&ids->data[idx]) == id) + break; + } + + if (idx >= nb_ids) + fdt_del_node(blob, off); + else + tmp = off; + + off = fdt_node_offset_by_compatible(blob, tmp, compatible); + } + + fdt_set_node_and_value(blob, "/", prop, &id, sizeof(uint32_t)); +} diff --git a/board/cssi/common/common.h b/board/cssi/common/common.h new file mode 100644 index 0000000..16852b6 --- /dev/null +++ b/board/cssi/common/common.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef _BOARD_CSSI_COMMON_H +#define _BOARD_CSSI_COMMON_H + +void ft_cleanup(void *blob, unsigned long id, const char *prop, const char *compatible); + +#endif /* _BOARD_CSSI_COMMON_H */ -- cgit v1.1 From 4b6a5388da774e68e0f6381faefc7a3b402c468a Mon Sep 17 00:00:00 2001 From: Christophe Leroy Date: Wed, 5 Apr 2023 16:05:36 +0200 Subject: board: cssi: Refactor EEPROM read On cmpc885 board, the ethernet addresses are stored in an EEPROM that is accessed through SPI. A 3 bytes command is sent to the chip then the content gets read. At the time being a single block access is performed, ignoring the first 3 bytes read. Reword the SPI transfer to first send 3 bytes then receive the content of the EEPROM so that there don't be 3 dummy bytes at the beginning of the buffer. And move the function into common.c so that it can be reused by the board that will be added in a future patch. Signed-off-by: Christophe Leroy --- board/cssi/cmpc885/cmpc885.c | 35 ++++------------------------------- board/cssi/common/common.c | 35 +++++++++++++++++++++++++++++++++++ board/cssi/common/common.h | 1 + 3 files changed, 40 insertions(+), 31 deletions(-) diff --git a/board/cssi/cmpc885/cmpc885.c b/board/cssi/cmpc885/cmpc885.c index 689d573..8f67f9f 100644 --- a/board/cssi/cmpc885/cmpc885.c +++ b/board/cssi/cmpc885/cmpc885.c @@ -147,55 +147,28 @@ int checkboard(void) return 0; } -#define SPI_EEPROM_READ 0x03 #define MAX_SPI_BYTES 0x20 -#define EE_OFF_MAC1 0x13 -#define EE_OFF_MAC2 0x19 +#define EE_OFF_MAC1 0x10 +#define EE_OFF_MAC2 0x16 /* Reads MAC addresses from SPI EEPROM */ static int setup_mac(void) { - struct udevice *eeprom; - struct spi_slave *slave; - char name[30], *str; uchar din[MAX_SPI_BYTES]; - uchar dout[MAX_SPI_BYTES] = {SPI_EEPROM_READ, 0, 0}; - int bitlen = 256, cs = 0, mode = 0, bus = 0, ret; + int ret; unsigned long ident = 0x08005120; - snprintf(name, sizeof(name), "generic_%d:%d", bus, cs); - - str = strdup(name); - if (!str) - return -1; - - ret = uclass_get_device(UCLASS_SPI, 0, &eeprom); - if (ret) { - printf("Could not enable Serial Peripheral Interface (SPI).\n"); - return -1; - } - - ret = _spi_get_bus_and_cs(bus, cs, 1000000, mode, "spi_generic_drv", str, &eeprom, &slave); + ret = read_eeprom(din, sizeof(din)); if (ret) return ret; - ret = spi_claim_bus(slave); - - ret = spi_xfer(slave, bitlen, dout, din, SPI_XFER_BEGIN | SPI_XFER_END); - if (ret) { - printf("Error %d during SPI transaction\n", ret); - return ret; - } - if (memcmp(din + EE_OFF_MAC1, &ident, sizeof(ident)) == 0) eth_env_set_enetaddr("ethaddr", din + EE_OFF_MAC1); if (memcmp(din + EE_OFF_MAC2, &ident, sizeof(ident)) == 0) eth_env_set_enetaddr("eth1addr", din + EE_OFF_MAC2); - spi_release_bus(slave); - return 0; } diff --git a/board/cssi/common/common.c b/board/cssi/common/common.c index 71b35cc..de68e23 100644 --- a/board/cssi/common/common.c +++ b/board/cssi/common/common.c @@ -8,7 +8,11 @@ * Common specific routines for the CS Group boards */ +#include #include +#include + +#define SPI_EEPROM_READ 0x03 static int fdt_set_node_and_value(void *blob, char *node, const char *prop, void *var, int size) @@ -60,3 +64,34 @@ void ft_cleanup(void *blob, unsigned long id, const char *prop, const char *comp fdt_set_node_and_value(blob, "/", prop, &id, sizeof(uint32_t)); } + +int read_eeprom(u8 *din, int len) +{ + struct udevice *eeprom; + struct spi_slave *slave; + uchar dout[3] = {SPI_EEPROM_READ, 0, 0}; + int ret; + + ret = uclass_get_device(UCLASS_SPI, 0, &eeprom); + if (ret) + return ret; + + ret = _spi_get_bus_and_cs(0, 0, 1000000, 0, "spi_generic_drv", + "generic_0:0", &eeprom, &slave); + if (ret) + return ret; + + ret = spi_claim_bus(slave); + + ret = spi_xfer(slave, sizeof(dout) << 3, dout, NULL, SPI_XFER_BEGIN); + if (ret) + return ret; + + ret = spi_xfer(slave, len << 3, NULL, din, SPI_XFER_END); + if (ret) + return ret; + + spi_release_bus(slave); + + return 0; +} diff --git a/board/cssi/common/common.h b/board/cssi/common/common.h index 16852b6..9660898 100644 --- a/board/cssi/common/common.h +++ b/board/cssi/common/common.h @@ -4,5 +4,6 @@ #define _BOARD_CSSI_COMMON_H void ft_cleanup(void *blob, unsigned long id, const char *prop, const char *compatible); +int read_eeprom(u8 *din, int len); #endif /* _BOARD_CSSI_COMMON_H */ -- cgit v1.1 From 78ba7b61da1271d982ff9c87b879d197ef911776 Mon Sep 17 00:00:00 2001 From: Christophe Leroy Date: Wed, 5 Apr 2023 18:50:23 +0200 Subject: board: cssi: Move all mother board code into common.c All the code used to manage the mother boards will be common to soon to come CPU board. Move all that code into common.c Signed-off-by: Christophe Leroy --- board/cssi/cmpc885/cmpc885.c | 152 ++++++------------------------------------- board/cssi/common/common.c | 124 ++++++++++++++++++++++++++++++++++- board/cssi/common/common.h | 8 ++- include/configs/cmpc885.h | 6 ++ 4 files changed, 157 insertions(+), 133 deletions(-) diff --git a/board/cssi/cmpc885/cmpc885.c b/board/cssi/cmpc885/cmpc885.c index 8f67f9f..540b9d3 100644 --- a/board/cssi/cmpc885/cmpc885.c +++ b/board/cssi/cmpc885/cmpc885.c @@ -28,33 +28,15 @@ DECLARE_GLOBAL_DATA_PTR; -#define BOARD_CMPC885 "cmpc885" -#define BOARD_MCR3000_2G "mcr3k_2g" -#define BOARD_VGOIP "vgoip" -#define BOARD_MIAE "miae" - -#define TYPE_MCR 0x22 -#define TYPE_MIAE 0x23 - -#define FAR_CASRSA 2 -#define FAR_VGOIP 4 -#define FAV_CLA 7 -#define FAV_SRSA 8 - #define ADDR_CPLD_R_RESET ((unsigned short __iomem *)CONFIG_CPLD_BASE) #define ADDR_CPLD_R_ETAT ((unsigned short __iomem *)(CONFIG_CPLD_BASE + 2)) #define ADDR_CPLD_R_TYPE ((unsigned char __iomem *)(CONFIG_CPLD_BASE + 3)) -#define ADDR_FPGA_R_BASE ((unsigned char __iomem *)CONFIG_FPGA_BASE) -#define ADDR_FPGA_R_ALARMES_IN ((unsigned char __iomem *)CONFIG_FPGA_BASE + 0x31) -#define ADDR_FPGA_R_FAV ((unsigned char __iomem *)CONFIG_FPGA_BASE + 0x44) - #define PATH_PHY2 "/soc@ff000000/mdio@e00/ethernet-phy@2" #define PATH_PHY3 "/soc@ff000000/mdio@e00/ethernet-phy@3" #define PATH_ETH1 "/soc@ff000000/ethernet@1e00" #define FIBER_PHY PATH_PHY2 -#define FPGA_R_ACQ_AL_FAV 0x04 #define R_ETAT_PRES_BASE 0x0040 #define R_RESET_STATUS 0x0400 @@ -62,8 +44,6 @@ DECLARE_GLOBAL_DATA_PTR; int ft_board_setup(void *blob, struct bd_info *bd) { - u8 fav_id, far_id; - const char *sync = "receive"; ft_cpu_setup(blob, bd); @@ -87,32 +67,19 @@ int ft_board_setup(void *blob, struct bd_info *bd) do_fixup_by_path(blob, "/localbus/e1", "rising-edge-sync-pulse", sync, strlen(sync), 1); /* MIAE only */ - if (!(in_be16(ADDR_CPLD_R_ETAT) & R_ETAT_PRES_BASE) || in_8(ADDR_FPGA_R_BASE) != TYPE_MIAE) + if (!(in_be16(ADDR_CPLD_R_ETAT) & R_ETAT_PRES_BASE)) return 0; - far_id = in_8(ADDR_FPGA_R_BASE + 0x43) >> 5; - ft_cleanup(blob, (u32)far_id, "far-id", "cs,mia-far"); - - /* - * special case, with CASRSA (far_id: 2) - * FAV-SRSA register itself as FAV-CLA - */ - fav_id = in_8(ADDR_FPGA_R_BASE + 0x44) >> 5; - - if (far_id == FAR_CASRSA && fav_id == FAV_CLA) - fav_id = FAV_SRSA; - - ft_cleanup(blob, (u32)fav_id, "fav-id", "cs,mia-fav"); - - if (far_id == FAR_CASRSA) { - /* switch to phy3 with gpio, we'll only use phy3 */ - immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR; - cpm8xx_t __iomem *cp = (cpm8xx_t __iomem *)&immr->im_cpm; + return ft_board_setup_common(blob); +} - setbits_be32(&cp->cp_pedat, 0x00002000); - } +void ft_board_setup_phy3(void) +{ + /* switch to phy3 with gpio, we'll only use phy3 */ + immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR; + cpm8xx_t __iomem *cp = (cpm8xx_t __iomem *)&immr->im_cpm; - return 0; + setbits_be32(&cp->cp_pedat, 0x00002000); } int checkboard(void) @@ -120,30 +87,11 @@ int checkboard(void) serial_puts("Board: "); /* Is a motherboard present ? */ - if (in_be16(ADDR_CPLD_R_ETAT) & R_ETAT_PRES_BASE) { - switch (in_8(ADDR_FPGA_R_BASE)) { - int far_id; - case TYPE_MCR: - printf("MCR3000_2G (CS GROUP)\n"); - break; - case TYPE_MIAE: - far_id = in_8(ADDR_FPGA_R_BASE + 0x43) >> 5; - - if (far_id == FAR_VGOIP) - printf("VGoIP (CS GROUP)\n"); - else - printf("MIAE (CS GROUP)\n"); - - break; - default: - printf("Unknown\n"); - for (;;) - ; - break; - } - } else { - printf("CMPC885 (CS GROUP)\n"); - } + if (in_be16(ADDR_CPLD_R_ETAT) & R_ETAT_PRES_BASE) + return checkboard_common(); + + printf("CMPC885 (CS GROUP)\n"); + return 0; } @@ -174,57 +122,12 @@ static int setup_mac(void) int misc_init_r(void) { - u8 val, tmp, far_id; - int count = 3; - - val = in_8(ADDR_FPGA_R_BASE); - /* Verify mother board presence */ if (in_be16(ADDR_CPLD_R_ETAT) & R_ETAT_PRES_BASE) { - /* identify the type of mother board */ - switch (val) { - case TYPE_MCR: - /* if at boot alarm button is pressed, delay boot */ - if ((in_8(ADDR_FPGA_R_ALARMES_IN) & FPGA_R_ACQ_AL_FAV) == 0) - env_set("bootdelay", "60"); - - env_set("config", BOARD_MCR3000_2G); - env_set("hostname", BOARD_MCR3000_2G); - break; - - case TYPE_MIAE: - do { - tmp = in_8(ADDR_FPGA_R_BASE + 0x41); - count--; - mdelay(10); /* 10msec wait */ - } while (count && tmp != in_8(ADDR_FPGA_R_BASE + 0x41)); - - if (!count) { - printf("Cannot read the reset factory switch position\n"); - hang(); - } - - if (tmp & 0x1) - env_set_default("Factory settings switch ON", 0); - - env_set("config", BOARD_MIAE); - far_id = in_8(ADDR_FPGA_R_BASE + 0x43) >> 5; - - if (far_id == FAR_VGOIP) - env_set("hostname", BOARD_VGOIP); - else - env_set("hostname", BOARD_MIAE); - break; - - default: - env_set("config", BOARD_CMPC885); - env_set("hostname", BOARD_CMPC885); - break; - } + misc_init_r_common(); } else { - printf("no mother board detected"); - env_set("config", BOARD_CMPC885); - env_set("hostname", BOARD_CMPC885); + env_set("config", CFG_BOARD_CMPCXXX); + env_set("hostname", CFG_BOARD_CMPCXXX); } if (setup_mac()) @@ -236,7 +139,7 @@ int misc_init_r(void) return 0; } -static void iop_setup_mcr(void) +void iop_setup_mcr(void) { immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR; iop8xx_t __iomem *iop = &immr->im_ioport; @@ -539,7 +442,7 @@ static void iop_setup_cmpc885(void) clrbits_be32(&cp->cp_peso, 0x00031980); } -static void iop_setup_miae(void) +void iop_setup_miae(void) { immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR; iop8xx_t __iomem *iop = &immr->im_ioport; @@ -549,7 +452,7 @@ static void iop_setup_miae(void) udelay(100); /* Set the front panel LED color to red */ - clrbits_8(ADDR_FPGA_R_FAV, 0x02); + clrbits_8((unsigned char __iomem *)CONFIG_FPGA_BASE + 0x44, 0x02); /* We must initialize data before changing direction */ setbits_be16(&iop->iop_pcdat, 0x0888); @@ -1007,20 +910,7 @@ int board_early_init_r(void) mdelay(200); } - /* Identify the type of mother board */ - switch (in_8(ADDR_FPGA_R_BASE)) { - case TYPE_MCR: - iop_setup_mcr(); - break; - - case TYPE_MIAE: - iop_setup_miae(); - break; - - default: - break; - } - /* CMPC885 board alone */ + iop_setup_common(); } else { iop_setup_cmpc885(); } diff --git a/board/cssi/common/common.c b/board/cssi/common/common.c index de68e23..7ecf772 100644 --- a/board/cssi/common/common.c +++ b/board/cssi/common/common.c @@ -9,8 +9,26 @@ */ #include +#include #include +#include #include +#include +#include + +#include "common.h" + +#define ADDR_FPGA_R_BASE ((unsigned char __iomem *)CONFIG_FPGA_BASE) + +#define FPGA_R_ACQ_AL_FAV 0x04 + +#define TYPE_MCR 0x22 +#define TYPE_MIAE 0x23 + +#define FAR_CASRSA 2 +#define FAR_VGOIP 4 +#define FAV_CLA 7 +#define FAV_SRSA 8 #define SPI_EEPROM_READ 0x03 @@ -36,7 +54,7 @@ static int fdt_set_node_and_value(void *blob, char *node, const char *prop, } /* Checks front/rear id and remove unneeded nodes from the blob */ -void ft_cleanup(void *blob, unsigned long id, const char *prop, const char *compatible) +static void ft_cleanup(void *blob, unsigned long id, const char *prop, const char *compatible) { int off; @@ -95,3 +113,107 @@ int read_eeprom(u8 *din, int len) return 0; } + +int ft_board_setup_common(void *blob) +{ + u8 far_id, fav_id; + + if (in_8(ADDR_FPGA_R_BASE) != TYPE_MIAE) + return 0; + + far_id = in_8(ADDR_FPGA_R_BASE + 0x43) >> 5; + ft_cleanup(blob, far_id, "far-id", "cs,mia-far"); + + fav_id = in_8(ADDR_FPGA_R_BASE + 0x44) >> 5; + + if (far_id == FAR_CASRSA && fav_id == FAV_CLA) + fav_id = FAV_SRSA; + + ft_cleanup(blob, fav_id, "fav-id", "cs,mia-fav"); + + if (far_id == FAR_CASRSA) + ft_board_setup_phy3(); + + return 0; +} + +int checkboard_common(void) +{ + switch (in_8(ADDR_FPGA_R_BASE)) { + int far_id; + case TYPE_MCR: + printf("MCR3000_2G (CS GROUP)\n"); + break; + case TYPE_MIAE: + far_id = in_8(ADDR_FPGA_R_BASE + 0x43) >> 5; + + if (far_id == FAR_VGOIP) + printf("VGoIP (CS GROUP)\n"); + else + printf("MIAE (CS GROUP)\n"); + + break; + default: + printf("Unknown\n"); + for (;;) + ; + break; + } + return 0; +} + +void misc_init_r_common(void) +{ + u8 tmp, far_id; + int count = 3; + + switch (in_8(ADDR_FPGA_R_BASE)) { + case TYPE_MCR: + /* if at boot alarm button is pressed, delay boot */ + if ((in_8(ADDR_FPGA_R_BASE + 0x31) & FPGA_R_ACQ_AL_FAV) == 0) + env_set("bootdelay", "60"); + + env_set("config", CFG_BOARD_MCR3000_2G); + env_set("hostname", CFG_BOARD_MCR3000_2G); + break; + + case TYPE_MIAE: + do { + tmp = in_8(ADDR_FPGA_R_BASE + 0x41); + count--; + mdelay(10); /* 10msec wait */ + } while (count && tmp != in_8(ADDR_FPGA_R_BASE + 0x41)); + + if (!count) { + printf("Cannot read the reset factory switch position\n"); + hang(); + } + + if (tmp & 0x1) + env_set_default("Factory settings switch ON", 0); + + env_set("config", CFG_BOARD_MIAE); + far_id = in_8(ADDR_FPGA_R_BASE + 0x43) >> 5; + + if (far_id == FAR_VGOIP) + env_set("hostname", CFG_BOARD_VGOIP); + else + env_set("hostname", CFG_BOARD_MIAE); + break; + + default: + env_set("config", CFG_BOARD_CMPCXXX); + env_set("hostname", CFG_BOARD_CMPCXXX); + break; + } +} + +void iop_setup_common(void) +{ + u8 type = in_8(ADDR_FPGA_R_BASE); + + if (type == TYPE_MCR) + iop_setup_mcr(); + else if (type == TYPE_MIAE) + iop_setup_miae(); +} diff --git a/board/cssi/common/common.h b/board/cssi/common/common.h index 9660898..c5ecb03 100644 --- a/board/cssi/common/common.h +++ b/board/cssi/common/common.h @@ -3,7 +3,13 @@ #ifndef _BOARD_CSSI_COMMON_H #define _BOARD_CSSI_COMMON_H -void ft_cleanup(void *blob, unsigned long id, const char *prop, const char *compatible); int read_eeprom(u8 *din, int len); +int ft_board_setup_common(void *blob); +void ft_board_setup_phy3(void); +int checkboard_common(void); +void misc_init_r_common(void); +void iop_setup_common(void); +void iop_setup_mcr(void); +void iop_setup_miae(void); #endif /* _BOARD_CSSI_COMMON_H */ diff --git a/include/configs/cmpc885.h b/include/configs/cmpc885.h index 4ce580c..b76230e 100644 --- a/include/configs/cmpc885.h +++ b/include/configs/cmpc885.h @@ -26,4 +26,10 @@ /* NAND configuration part */ #define CFG_SYS_NAND_BASE 0xC0000000 +/* Board names */ +#define CFG_BOARD_CMPCXXX "cmpc885" +#define CFG_BOARD_MCR3000_2G "mcr3k_2g" +#define CFG_BOARD_VGOIP "vgoip" +#define CFG_BOARD_MIAE "miae" + #endif /* __CONFIG_H */ -- cgit v1.1 From 4d0c8db74d83e43dec4e7481b2d1e194f51d907b Mon Sep 17 00:00:00 2001 From: Christophe Leroy Date: Tue, 4 Apr 2023 13:09:36 +0200 Subject: board: cssi: Add CPU board CMPCPRO CSSI has another CPU board, similar to the CMPC885 board that get plugged on the two base boards MCR3000_2G and MIAE. That CPU board is called CMPCPRO because it has a MPC8321E CPU, also known as Power QUICC II PRO. Signed-off-by: Christophe Leroy --- arch/powerpc/cpu/mpc83xx/Kconfig | 5 + arch/powerpc/dts/Makefile | 1 + arch/powerpc/dts/cmpcpro.dts | 189 ++++++++++++++++++ board/cssi/MAINTAINERS | 2 + board/cssi/cmpcpro/Kconfig | 26 +++ board/cssi/cmpcpro/Makefile | 8 + board/cssi/cmpcpro/cmpcpro.c | 404 +++++++++++++++++++++++++++++++++++++++ board/cssi/cmpcpro/cmpcpro.env | 8 + board/cssi/cmpcpro/nand.c | 43 +++++ configs/CMPCPRO_defconfig | 209 ++++++++++++++++++++ include/configs/cmpcpro.h | 99 ++++++++++ 11 files changed, 994 insertions(+) create mode 100644 arch/powerpc/dts/cmpcpro.dts create mode 100644 board/cssi/cmpcpro/Kconfig create mode 100644 board/cssi/cmpcpro/Makefile create mode 100644 board/cssi/cmpcpro/cmpcpro.c create mode 100644 board/cssi/cmpcpro/cmpcpro.env create mode 100644 board/cssi/cmpcpro/nand.c create mode 100644 configs/CMPCPRO_defconfig create mode 100644 include/configs/cmpcpro.h diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig index b695c7e..582e141 100644 --- a/arch/powerpc/cpu/mpc83xx/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/Kconfig @@ -20,6 +20,10 @@ choice prompt "Target select" optional +config TARGET_CMPCPRO + bool "Support CMPCPRO board from CSSI" + select ARCH_MPC832X + config TARGET_MPC837XERDB bool "Support MPC837XERDB" select ARCH_MPC837X @@ -205,5 +209,6 @@ config NEVER_ASSERT_ODT_TO_CPU source "board/freescale/mpc837xerdb/Kconfig" source "board/gdsys/mpc8308/Kconfig" +source "board/cssi/cmpcpro/Kconfig" endmenu diff --git a/arch/powerpc/dts/Makefile b/arch/powerpc/dts/Makefile index 26b592b..bb436f0 100644 --- a/arch/powerpc/dts/Makefile +++ b/arch/powerpc/dts/Makefile @@ -30,6 +30,7 @@ dtb-$(CONFIG_TARGET_TUXX1) += kmtuxa1.dtb dtb-$(CONFIG_TARGET_MCR3000) += mcr3000.dtb dtb-$(CONFIG_TARGET_GAZERBEAM) += gazerbeam.dtb dtb-$(CONFIG_TARGET_CMPC885) += cmpc885.dtb +dtb-$(CONFIG_TARGET_CMPCPRO) += cmpcpro.dtb include $(srctree)/scripts/Makefile.dts diff --git a/arch/powerpc/dts/cmpcpro.dts b/arch/powerpc/dts/cmpcpro.dts new file mode 100644 index 0000000..c27d9db --- /dev/null +++ b/arch/powerpc/dts/cmpcpro.dts @@ -0,0 +1,189 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * CMPC885 Device Tree Source + * + * Copyright 2020 CS GROUP France + * + */ + +/dts-v1/; + +#include + +/ { + model = "CMPCPRO"; + compatible = "fsl, cmpc85xx", "fsl,mod85xx", "CMPCPRO", "MPC8321E", "fsl,cmpcpro"; + #address-cells = <1>; + #size-cells = <1>; + + chosen { + stdout-path = &serial0; + }; + WDT: watchdog@0 { + device_type = "watchdog"; + compatible = "fsl,pq1-wdt"; + }; + + aliases { + ethernet0 = ð0; + etehrnet1 = ð1; + serial0 = &serial0; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + PowerPC,8321@0 { + device_type = "cpu"; + reg = <0x0>; + d-cache-line-size = <0x20>; // 32 bytes + i-cache-line-size = <0x20>; // 32 bytes + d-cache-size = <16384>; // L1, 16K + i-cache-size = <16384>; // L1, 16K + timebase-frequency = <0>; + bus-frequency = <0>; + clock-frequency = <0>; + }; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x20000000>; + }; + + soc8321@b0000000 { + #address-cells = <1>; + #size-cells = <1>; + device_type = "soc"; + compatible = "simple-bus"; + ranges = <0x0 0xb0000000 0x00100000>; + reg = <0xb0000000 0x00000200>; + bus-frequency = <0>; + pmc: power@b00 { + compatible = "fsl,mpc8323-pmc", "fsl,mpc8349-pmc"; + reg = <0xb00 0x100 0xa00 0x100>; + interrupts = <80 0x8>; + interrupt-parent = <&ipic>; + }; + serial0: serial@4500 { + clocks = <&socclocks MPC83XX_CLK_CSB>; + cell-index = <0>; + device_type = "serial"; + compatible = "fsl,ns16550", "ns16550"; + reg = <0x4500 0x100>; + clock-frequency = <0>; + interrupts = <9 0x8>; + interrupt-parent = <&ipic>; + }; + ipic:pic@700 { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <2>; + reg = <0x700 0x100>; + device_type = "ipic"; + }; + par_io@1400 { + #address-cells = <1>; + #size-cells = <1>; + reg = <0x1400 0x100>; + ranges; + compatible = "fsl,mpc8323-qe-pario","simple-bus"; + device_type = "par_io"; + num-ports = <7>; + qe_pio_a: gpio-controller@1400 { + #gpio-cells = <2>; + compatible = "fsl,mpc8323-qe-pario-bank","fsl,mpc8308-gpio"; + reg = <0x1400 0x18>; + gpio-controller; + }; + qe_pio_b: gpio-controller@1418 { + #gpio-cells = <2>; + compatible = "fsl,mpc8323-qe-pario-bank","fsl,mpc8308-gpio"; + reg = <0x1418 0x18>; + gpio-controller; + }; + qe_pio_c: gpio-controller@1430 { + #gpio-cells = <2>; + compatible = "fsl,mpc8323-qe-pario-bank","fsl,mpc8308-gpio"; + reg = <0x1430 0x18>; + gpio-controller; + }; + qe_pio_d: gpio-controller@1448 { + #gpio-cells = <2>; + compatible = "fsl,mpc8323-qe-pario-bank","fsl,mpc8308-gpio"; + reg = <0x1448 0x18>; + gpio-controller; + }; + }; + }; + socclocks: clocks { + bootph-all; + compatible = "fsl,mpc832x-clk"; + #clock-cells = <1>; + }; + qe@b0100000 { + #address-cells = <1>; + #size-cells = <1>; + device_type = "qe"; + compatible = "fsl,qe","simple-bus"; + ranges = <0x0 0xb0100000 0x00100000>; + reg = <0xb0100000 0x480>; + brg-frequency = <0>; + bus-frequency = <198000000>; + fsl,qe-num-riscs = <1>; + fsl,qe-num-snums = <28>; + spi@4c0 { + clocks = <&socclocks MPC83XX_CLK_CSB>; + #address-cells = <1>; + #size-cells = <0>; + cell-index = <0>; + compatible = "fsl,mpc832x-spi"; + reg = <0x4c0 0x40>; + mode = "cpu"; + gpios = <&qe_pio_d 3 1>; + clock-frequency = <0>; + eeprom@3 { + compatible = "atmel,at25", "cs,eeprom"; + cell-index = <1>; + }; + }; + eth0: ucc@3000 { + device_type = "network"; + compatible = "ucc_geth"; + cell-index = <2>; + reg = <0x3000 0x200>; + rx-clock-name = "clk17"; + tx-clock-name = "clk17"; + phy-handle = <&phy1>; + phy-connection-type = "rmii"; + }; + eth1: ucc@2200 { + device_type = "network"; + compatible = "ucc_geth"; + cell-index = <3>; + reg = <0x2200 0x200>; + rx-clock-name = "clk12"; + tx-clock-name = "clk12"; + phy-handle = <&phy2>; + phy-connection-type = "rmii"; + }; + mdio@3120 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3120 0x18>; + compatible = "fsl,ucc-mdio"; + phy1:ethernet-phy@1 { + interrupt-parent = <&ipic>; + reg = <0x1>; + interrupts = <17 8>; + device_type = "ethernet-phy"; + }; + phy2:ethernet-phy@2 { + interrupt-parent = <&ipic>; + reg = <0x2>; + interrupts = <17 8>; + device_type = "ethernet-phy"; + }; + }; + }; +}; diff --git a/board/cssi/MAINTAINERS b/board/cssi/MAINTAINERS index d8e7b5e..f82dd3b 100644 --- a/board/cssi/MAINTAINERS +++ b/board/cssi/MAINTAINERS @@ -6,3 +6,5 @@ F: include/configs/mcr3000.h F: configs/MCR3000_defconfig F: include/configs/cmpc885.h F: configs/CMPC885_defconfig +F: include/configs/cmpcpro.h +F: configs/CMPCPRO_defconfig diff --git a/board/cssi/cmpcpro/Kconfig b/board/cssi/cmpcpro/Kconfig new file mode 100644 index 0000000..b5d998a --- /dev/null +++ b/board/cssi/cmpcpro/Kconfig @@ -0,0 +1,26 @@ +if TARGET_CMPCPRO + +config SYS_BOARD + default "cmpcpro" + +config SYS_VENDOR + default "cssi" + +config SYS_CONFIG_NAME + default "cmpcpro" + +config TEXT_BASE + default 0x40000000 + +config CPLD_BASE + hex + default 0x90000000 + +config FPGA_BASE + hex + default 0x80000000 + +config PCI + default no + +endif diff --git a/board/cssi/cmpcpro/Makefile b/board/cssi/cmpcpro/Makefile new file mode 100644 index 0000000..73ff451 --- /dev/null +++ b/board/cssi/cmpcpro/Makefile @@ -0,0 +1,8 @@ +# +# (C) Copyright 2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += cmpcpro.o nand.o ../common/common.o diff --git a/board/cssi/cmpcpro/cmpcpro.c b/board/cssi/cmpcpro/cmpcpro.c new file mode 100644 index 0000000..3e9ba6a --- /dev/null +++ b/board/cssi/cmpcpro/cmpcpro.c @@ -0,0 +1,404 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2006-2023 CS GROUP France + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include +#include +#include + +#include + +#include "../common/common.h" + +DECLARE_GLOBAL_DATA_PTR; + +#define ADDR_FPGA_BASE ((unsigned char __iomem *)CONFIG_CPLD_BASE) +#define ADDR_FPGA_RESET_G (ADDR_FPGA_BASE + 0x40) +#define ADDR_FPGA_REG_ETAT (ADDR_FPGA_BASE + 0x42) + +#define R_ETAT_PRES_BASE 0x01 +#define RESET_G_OK 0x08 + +/* SPI EEPROM parameters */ +#define MAX_SPI_BYTES 0x28 +#define EE_OFF_MAC1 0x10 +#define EE_OFF_MAC2 0x16 +#define EE_OFF_MAC3 0x1C + +static uint upma_table[] = { + /* Read Single-Beat (RSS) */ + 0x00AC0C00, 0x00FC1C40, 0x30FCE045, 0xFFFF0C00, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* Read Burst (RBS) */ + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* Write Single-Beat (WSS) */ + 0x00A30C00, 0x00F31C40, 0x3FF3C045, 0xFFFF0C00, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* Write Burst (WBS) */ + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* Refresh Timer (RTS) */ + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* Exception Condition (EXS) */ + 0xFFFF0C01, 0xFFFF0C01, 0xFFFF0C01, 0xFFFF0C01, +}; + +const qe_iop_conf_t qe_iop_conf_tab[] = { + /* ETH3 */ + {1, 0, 1, 0, 1}, /* TxD0 */ + {1, 1, 1, 0, 1}, /* TxD1 */ + {1, 2, 1, 0, 1}, /* TxD2 */ + {1, 3, 1, 0, 1}, /* TxD3 */ + {1, 9, 1, 0, 1}, /* TxER */ + {1, 12, 1, 0, 1}, /* TxEN */ + {3, 24, 2, 0, 1}, /* TxCLK->CLK10 */ + + {1, 4, 2, 0, 1}, /* RxD0 */ + {1, 5, 2, 0, 1}, /* RxD1 */ + {1, 6, 2, 0, 1}, /* RxD2 */ + {1, 7, 2, 0, 1}, /* RxD3 */ + {1, 8, 2, 0, 1}, /* RxER */ + {1, 10, 2, 0, 1}, /* RxDV */ + {0, 13, 2, 0, 1}, /* RxCLK->CLK9 */ + {1, 11, 2, 0, 1}, /* COL */ + {1, 13, 2, 0, 1}, /* CRS */ + + /* ETH4 */ + {1, 18, 1, 0, 1}, /* TxD0 */ + {1, 19, 1, 0, 1}, /* TxD1 */ + {1, 20, 1, 0, 1}, /* TxD2 */ + {1, 21, 1, 0, 1}, /* TxD3 */ + {1, 27, 1, 0, 1}, /* TxER */ + {1, 30, 1, 0, 1}, /* TxEN */ + {3, 6, 2, 0, 1}, /* TxCLK->CLK8 */ + + {1, 22, 2, 0, 1}, /* RxD0 */ + {1, 23, 2, 0, 1}, /* RxD1 */ + {1, 24, 2, 0, 1}, /* RxD2 */ + {1, 25, 2, 0, 1}, /* RxD3 */ + {1, 26, 1, 0, 1}, /* RxER */ + {1, 28, 2, 0, 1}, /* Rx_DV */ + {3, 31, 2, 0, 1}, /* RxCLK->CLK7 */ + {1, 29, 2, 0, 1}, /* COL */ + {1, 31, 2, 0, 1}, /* CRS */ + + {3, 4, 3, 0, 2}, /* MDIO */ + {3, 5, 1, 0, 2}, /* MDC */ + + {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */ +}; + +void iop_setup_miae(void) +{ + immap_t __iomem *im = (immap_t *)CONFIG_SYS_IMMR; + + /* PORTA configuration */ + out_be32(&im->qepio.ioport[0].pdat, 0x00808000); + out_be32(&im->qepio.ioport[0].podr, 0x00008000); + out_be32(&im->qepio.ioport[0].dir1, 0x40800968); + out_be32(&im->qepio.ioport[0].dir2, 0x650A0896); + out_be32(&im->qepio.ioport[0].ppar1, 0x40400204); + out_be32(&im->qepio.ioport[0].ppar2, 0x05050464); + + /* PORTB configuration */ + out_be32(&im->qepio.ioport[1].pdat, 0x00018000); + out_be32(&im->qepio.ioport[1].podr, 0x00000000); + out_be32(&im->qepio.ioport[1].dir1, 0x50A08949); + out_be32(&im->qepio.ioport[1].dir2, 0x5C0C6890); + out_be32(&im->qepio.ioport[1].ppar1, 0x50504644); + out_be32(&im->qepio.ioport[1].ppar2, 0x080800A0); + + /* PORTC configuration */ + out_be32(&im->qepio.ioport[2].pdat, 0x3D000108); + out_be32(&im->qepio.ioport[2].podr, 0x00000000); + out_be32(&im->qepio.ioport[2].dir1, 0x45518000); + out_be32(&im->qepio.ioport[2].dir2, 0xA8119561); + out_be32(&im->qepio.ioport[2].ppar1, 0x80008000); + out_be32(&im->qepio.ioport[2].ppar2, 0x00000000); + + /* PORTD configuration */ + out_be32(&im->qepio.ioport[3].pdat, 0x1000E000); + out_be32(&im->qepio.ioport[3].podr, 0x0000E000); + out_be32(&im->qepio.ioport[3].dir1, 0xFDD20800); + out_be32(&im->qepio.ioport[3].dir2, 0x54155228); + out_be32(&im->qepio.ioport[3].ppar1, 0x54A30C00); + out_be32(&im->qepio.ioport[3].ppar2, 0x00000100); +} + +void iop_setup_mcr(void) +{ + immap_t __iomem *im = (immap_t *)CONFIG_SYS_IMMR; + + /* PORTA configuration */ + out_be32(&im->qepio.ioport[0].pdat, 0x00808004); + out_be32(&im->qepio.ioport[0].podr, 0x00000000); + out_be32(&im->qepio.ioport[0].dir1, 0x40800A68); + out_be32(&im->qepio.ioport[0].dir2, 0x650A0896); + out_be32(&im->qepio.ioport[0].ppar1, 0x40400004); + out_be32(&im->qepio.ioport[0].ppar2, 0x05050444); + + /* PORTB configuration */ + out_be32(&im->qepio.ioport[1].pdat, 0x00008000); + out_be32(&im->qepio.ioport[1].podr, 0x00000004); + out_be32(&im->qepio.ioport[1].dir1, 0x50A08A4A); + out_be32(&im->qepio.ioport[1].dir2, 0x5C0C6890); + out_be32(&im->qepio.ioport[1].ppar1, 0x50504444); + out_be32(&im->qepio.ioport[1].ppar2, 0x08080080); + + /* PORTC configuration */ + out_be32(&im->qepio.ioport[2].pdat, 0x3D000018); + out_be32(&im->qepio.ioport[2].podr, 0x00000400); + out_be32(&im->qepio.ioport[2].dir1, 0x45518000); + out_be32(&im->qepio.ioport[2].dir2, 0xA8129561); + out_be32(&im->qepio.ioport[2].ppar1, 0x80008000); + out_be32(&im->qepio.ioport[2].ppar2, 0x00000000); + + /* PORTD configuration */ + out_be32(&im->qepio.ioport[3].pdat, 0x1000E000); + out_be32(&im->qepio.ioport[3].podr, 0x0000E000); + out_be32(&im->qepio.ioport[3].dir1, 0xFDD20800); + out_be32(&im->qepio.ioport[3].dir2, 0x54155228); + out_be32(&im->qepio.ioport[3].ppar1, 0x54A30C00); + out_be32(&im->qepio.ioport[3].ppar2, 0x00000100); +} + +static void iop_setup_cmpcpro(void) +{ + immap_t __iomem *im = (immap_t *)CONFIG_SYS_IMMR; + + /* PORTA configuration */ + out_be32(&im->qepio.ioport[0].pdat, 0x00000000); + out_be32(&im->qepio.ioport[0].podr, 0x00000000); + out_be32(&im->qepio.ioport[0].dir1, 0x50A84020); + out_be32(&im->qepio.ioport[0].dir2, 0x00000000); + out_be32(&im->qepio.ioport[0].ppar1, 0xF0FCC000); + out_be32(&im->qepio.ioport[0].ppar2, 0x00000000); + + /* PORTB configuration */ + out_be32(&im->qepio.ioport[1].pdat, 0x00000000); + out_be32(&im->qepio.ioport[1].podr, 0x00000000); + out_be32(&im->qepio.ioport[1].dir1, 0x00000000); + out_be32(&im->qepio.ioport[1].dir2, 0x00006800); + out_be32(&im->qepio.ioport[1].ppar1, 0x00000000); + out_be32(&im->qepio.ioport[1].ppar2, 0x00000000); + + /* PORTC configuration */ + out_be32(&im->qepio.ioport[2].pdat, 0x19000000); + out_be32(&im->qepio.ioport[2].podr, 0x00000000); + out_be32(&im->qepio.ioport[2].dir1, 0x01410000); + out_be32(&im->qepio.ioport[2].dir2, 0xA8009400); + out_be32(&im->qepio.ioport[2].ppar1, 0x00000000); + out_be32(&im->qepio.ioport[2].ppar2, 0x00000000); + + /* PORTD configuration */ + out_be32(&im->qepio.ioport[3].pdat, 0x1000E000); + out_be32(&im->qepio.ioport[3].podr, 0x0000E000); + out_be32(&im->qepio.ioport[3].dir1, 0xFD020000); + out_be32(&im->qepio.ioport[3].dir2, 0x54055000); + out_be32(&im->qepio.ioport[3].ppar1, 0x54030000); + out_be32(&im->qepio.ioport[3].ppar2, 0x00000000); +} + +int board_early_init_r(void) +{ + immap_t __iomem *im = (immap_t *)CONFIG_SYS_IMMR; + fsl_lbc_t *lbus = &im->im_lbc; + + upmconfig(UPMA, upma_table, ARRAY_SIZE(upma_table)); + + out_be32(&lbus->mamr, 0x00044440); + + /* configure LBCR register */ + out_be32(&lbus->lbcr, 0x00000500); + sync(); + + if (in_8(ADDR_FPGA_REG_ETAT) & R_ETAT_PRES_BASE) { + int i; + + /* Initialize signal PROG_FPGA_FIRMWARE */ + setbits_be32(&im->qepio.ioport[0].pdat, 0x00008000); + setbits_be32(&im->qepio.ioport[0].dir2, 0x60000002); + setbits_be32(&im->qepio.ioport[0].podr, 0x00008000); + + mdelay(1); + + /* Now read CPDATA[31] to check if FPGA is loaded */ + if (!in_be32(&im->qepio.ioport[0].pdat) & 0x00000001) { + printf("Reloading FPGA firmware.\n"); + + clrbits_be32(&im->qepio.ioport[0].pdat, 0x00008000); + udelay(1); + setbits_be32(&im->qepio.ioport[0].pdat, 0x00008000); + + /* Wait 200 msec and check DONE_FPGA_FIRMWARE */ + mdelay(200); + if (!(in_be32(&im->qepio.ioport[0].pdat) & 0x00000001)) { + for (;;) { + printf("error loading firmware.\n"); + mdelay(500); + } + } + + /* Send a reset signal and wait for 20 msec */ + out_8(ADDR_FPGA_RESET_G, in_8(ADDR_FPGA_RESET_G) | RESET_G_OK); + mdelay(20); + out_8(ADDR_FPGA_RESET_G, in_8(ADDR_FPGA_RESET_G) & ~RESET_G_OK); + } + + /* Wait 300 msec and check the reset state */ + mdelay(300); + for (i = 0; !(in_8(ADDR_FPGA_REG_ETAT) & RESET_G_OK); i++) { + for (;;) { + printf("Could not reset FPGA.\n"); + mdelay(500); + } + } + + iop_setup_common(); + + /* clocks configuration */ + out_be32(&qe_immr->qmx.cmxsi1cr_l, 0x00040004); + out_be32(&qe_immr->qmx.cmxsi1syr, 0x00000000); + } else { + iop_setup_cmpcpro(); + } + + return 0; +} + +int dram_init(int board_type) +{ + immap_t __iomem *im = (immap_t __iomem *)CONFIG_SYS_IMMR; + + out_be32(&im->sysconf.ddrlaw[0].bar, CFG_SYS_DDR_SDRAM_BASE & LAWBAR_BAR); + out_be32(&im->sysconf.ddrlaw[0].ar, LAWAR_EN | ((ilog2(SZ_512M) - 1) & LAWAR_SIZE)); + + out_be32(&im->ddr.sdram_clk_cntl, CFG_SYS_DDR_CLK_CNTL); + out_be32(&im->ddr.csbnds[0].csbnds, CFG_SYS_DDR_CS0_BNDS); + out_be32(&im->ddr.cs_config[0], CFG_SYS_DDR_CS0_CONFIG); + + out_be32(&im->ddr.timing_cfg_0, CFG_SYS_DDR_TIMING_0); + out_be32(&im->ddr.timing_cfg_1, CFG_SYS_DDR_TIMING_1); + out_be32(&im->ddr.timing_cfg_2, CFG_SYS_DDR_TIMING_2); + out_be32(&im->ddr.timing_cfg_3, CFG_SYS_DDR_TIMING_3); + out_be32(&im->ddr.sdram_cfg, CFG_SYS_DDR_SDRAM_CFG); + out_be32(&im->ddr.sdram_cfg2, CFG_SYS_DDR_SDRAM_CFG2); + out_be32(&im->ddr.sdram_mode, CFG_SYS_DDR_MODE); + out_be32(&im->ddr.sdram_mode2, CFG_SYS_DDR_MODE2); + out_be32(&im->ddr.sdram_interval, CFG_SYS_DDR_INTERVAL); + udelay(200); + + setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN); + + gd->ram_size = SZ_512M; + + return 0; +} + +int checkboard(void) +{ + printf("Board: "); + + /* Is a motherboard present ? */ + if (in_8(ADDR_FPGA_REG_ETAT) & R_ETAT_PRES_BASE) + return checkboard_common(); + + printf("CMPCPRO (CS GROUP)\n"); + + return 0; +} + +/* Reads MAC addresses from SPI EEPROM */ +static int setup_mac(void) +{ + uchar din[MAX_SPI_BYTES]; + int ret; + unsigned long ident = 0x08005120; + + ret = read_eeprom(din, sizeof(din)); + if (ret) + return ret; + + if (memcmp(din + EE_OFF_MAC1, &ident, sizeof(ident)) == 0) { + eth_env_set_enetaddr("ethaddr", din + EE_OFF_MAC1); + eth_env_set_enetaddr("eth3addr", din + EE_OFF_MAC1); + } + + if (memcmp(din + EE_OFF_MAC2, &ident, sizeof(ident)) == 0) + eth_env_set_enetaddr("eth1addr", din + EE_OFF_MAC2); + + if (memcmp(din + EE_OFF_MAC3, &ident, sizeof(ident)) == 0) + eth_env_set_enetaddr("eth2addr", din + EE_OFF_MAC3); + + return 0; +} + +int misc_init_r(void) +{ + /* we do not modify environment variable area if CRC is false */ + /* Verify if mother board is present */ + if (in_8(ADDR_FPGA_REG_ETAT) & R_ETAT_PRES_BASE) { + misc_init_r_common(); + } else { + env_set("config", CFG_BOARD_CMPCXXX); + env_set("hostname", CFG_BOARD_CMPCXXX); + } + + if (setup_mac()) + printf("Error retrieving mac addresses\n"); + + return 0; +} + +int ft_board_setup(void *blob, struct bd_info *bd) +{ + ft_cpu_setup(blob, bd); + + /* MIAE only */ + if (!(in_8(ADDR_FPGA_REG_ETAT) & R_ETAT_PRES_BASE)) + return 0; + + return ft_board_setup_common(blob); +} + +void ft_board_setup_phy3(void) +{ + /* switch to phy3 with gpio, we'll only use phy3 */ + immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; + + setbits_be32(&immr->qepio.ioport[2].pdat, 0x00000400); +} + +#define ADDR_FPGA_R_BASE ((unsigned char __iomem *)CONFIG_FPGA_BASE) +#define ADDR_FPGA_R_ALARMES_IN ((unsigned char __iomem *)CONFIG_FPGA_BASE + 0x31) +#define ADDR_FPGA_R_FAV ((unsigned char __iomem *)CONFIG_FPGA_BASE + 0x44) + diff --git a/board/cssi/cmpcpro/cmpcpro.env b/board/cssi/cmpcpro/cmpcpro.env new file mode 100644 index 0000000..7394b83 --- /dev/null +++ b/board/cssi/cmpcpro/cmpcpro.env @@ -0,0 +1,8 @@ +loadaddr=0x1a00000 +filename=cmpcpro.itb +netdev=eth0 +console_args=console=ttyS0,115200N8 +loadkernel=ubi part nand0;ubifsmount ubi0; ubifsload ${loadaddr} /boot/${filename}; ubifsumount; ubi detach +flashboot=mw.w 90000040 0x000E 1; setenv bootargs ${console_args} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:eth0:off ${ofl_args}; run loadkernel; bootm $loadaddr#$config +tftpboot=mw.w 90000040 0x000E 1; setenv bootargs ${console_args} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:eth0:off ${ofl_args}; tftp ${loadaddr} ${filename}; bootm $loadaddr#$config +update=echo 'Updating ubi image'; mw.w 90000040 0x000E 1; if tftp $loadaddr $ubifile; then nand erase.chip; nand write $loadaddr 0x00 $filesize; fi; diff --git a/board/cssi/cmpcpro/nand.c b/board/cssi/cmpcpro/nand.c new file mode 100644 index 0000000..d8b4197 --- /dev/null +++ b/board/cssi/cmpcpro/nand.c @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2010-2023 CS GROUP France + * Florent TRINH THAI (florent.trinh-thai@csgroup.eu) + * Stephane FRANJOU (stephane.franjou@csgroup.eu) + */ + +#include +#include +#include +#include +#include + +#define BIT_CLE BIT(6) +#define BIT_ALE BIT(5) + +static u32 nand_mask(unsigned int ctrl) +{ + return ((ctrl & NAND_CLE) ? BIT_CLE : 0) | + ((ctrl & NAND_ALE) ? BIT_ALE : 0); +} + +static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl) +{ + immap_t __iomem *immr = (immap_t *)CONFIG_SYS_IMMR; + struct nand_chip *chip = mtd_to_nand(mtdinfo); + + if (ctrl & NAND_CTRL_CHANGE) + clrsetbits_be32(&immr->qepio.ioport[2].pdat, + BIT_CLE | BIT_ALE, nand_mask(ctrl)); + + if (cmd != NAND_CMD_NONE) + out_8(chip->IO_ADDR_W, cmd); +} + +int board_nand_init(struct nand_chip *nand) +{ + nand->chip_delay = 60; + nand->ecc.mode = NAND_ECC_SOFT; + nand->cmd_ctrl = nand_hwcontrol; + + return 0; +} diff --git a/configs/CMPCPRO_defconfig b/configs/CMPCPRO_defconfig new file mode 100644 index 0000000..7313715 --- /dev/null +++ b/configs/CMPCPRO_defconfig @@ -0,0 +1,209 @@ +CONFIG_PPC=y +CONFIG_SYS_IMMR=0xB0000000 +CONFIG_SYS_MALLOC_F_LEN=0x1000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="cmpcpro" +CONFIG_SYS_PROMPT="MPC_PRO> " +CONFIG_SYS_CLK_FREQ=66666667 +CONFIG_ENV_ADDR=0x400e0000 +CONFIG_MPC83xx=y +CONFIG_HIGH_BATS=y +CONFIG_TARGET_CMPCPRO=y +CONFIG_CORE_PLL_RATIO_25_1=y +CONFIG_QUICC_MULT_FACTOR_3=y +CONFIG_PCI_HOST_MODE_ENABLE=y +CONFIG_BOOT_MEMORY_SPACE_LOW=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_BAT0=y +CONFIG_BAT0_NAME="FLASH" +CONFIG_BAT0_BASE=0x40000000 +CONFIG_BAT0_LENGTH_64_MBYTES=y +CONFIG_BAT0_ACCESS_RW=y +CONFIG_BAT0_ICACHE_WRITETHROUGH=y +CONFIG_BAT0_DCACHE_WRITETHROUGH=y +CONFIG_BAT0_USER_MODE_VALID=y +CONFIG_BAT0_SUPERVISOR_MODE_VALID=y +CONFIG_BAT1=y +CONFIG_BAT1_NAME="DDR" +CONFIG_BAT1_BASE=0x00000000 +CONFIG_BAT1_LENGTH_256_MBYTES=y +CONFIG_BAT1_ACCESS_RW=y +CONFIG_BAT1_USER_MODE_VALID=y +CONFIG_BAT1_SUPERVISOR_MODE_VALID=y +CONFIG_BAT2=y +CONFIG_BAT2_NAME="DDR2" +CONFIG_BAT2_BASE=0x10000000 +CONFIG_BAT2_LENGTH_256_MBYTES=y +CONFIG_BAT2_ACCESS_RW=y +CONFIG_BAT2_USER_MODE_VALID=y +CONFIG_BAT2_SUPERVISOR_MODE_VALID=y +CONFIG_BAT3=y +CONFIG_BAT3_NAME="BCSR" +CONFIG_BAT3_BASE=0xA0000000 +CONFIG_BAT3_ACCESS_RW=y +CONFIG_BAT3_ICACHE_GUARDED=y +CONFIG_BAT3_DCACHE_WRITETHROUGH=y +CONFIG_BAT3_DCACHE_INHIBITED=y +CONFIG_BAT3_DCACHE_GUARDED=y +CONFIG_BAT3_SUPERVISOR_MODE_VALID=y +CONFIG_BAT4=y +CONFIG_BAT4_NAME="PERIPHETH" +CONFIG_BAT4_BASE=0x90000000 +CONFIG_BAT4_LENGTH_64_MBYTES=y +CONFIG_BAT4_ACCESS_RW=y +CONFIG_BAT4_ICACHE_GUARDED=y +CONFIG_BAT4_DCACHE_WRITETHROUGH=y +CONFIG_BAT4_DCACHE_INHIBITED=y +CONFIG_BAT4_DCACHE_GUARDED=y +CONFIG_BAT4_SUPERVISOR_MODE_VALID=y +CONFIG_BAT5=y +CONFIG_BAT5_NAME="CARTEBASE" +CONFIG_BAT5_BASE=0x80000000 +CONFIG_BAT5_LENGTH_64_MBYTES=y +CONFIG_BAT5_ACCESS_RW=y +CONFIG_BAT5_ICACHE_GUARDED=y +CONFIG_BAT5_DCACHE_WRITETHROUGH=y +CONFIG_BAT5_DCACHE_INHIBITED=y +CONFIG_BAT5_DCACHE_GUARDED=y +CONFIG_BAT5_SUPERVISOR_MODE_VALID=y +CONFIG_BAT6=y +CONFIG_BAT6_NAME="IMMRBAR" +CONFIG_BAT6_BASE=0xB0000000 +CONFIG_BAT6_LENGTH_4_MBYTES=y +CONFIG_BAT6_ACCESS_RW=y +CONFIG_BAT6_ICACHE_GUARDED=y +CONFIG_BAT6_DCACHE_INHIBITED=y +CONFIG_BAT6_DCACHE_GUARDED=y +CONFIG_BAT6_USER_MODE_VALID=y +CONFIG_BAT6_SUPERVISOR_MODE_VALID=y +CONFIG_BAT7=y +CONFIG_BAT7_NAME="STACK" +CONFIG_BAT7_BASE=0xE6000000 +CONFIG_BAT7_ACCESS_RW=y +CONFIG_BAT7_USER_MODE_VALID=y +CONFIG_BAT7_SUPERVISOR_MODE_VALID=y +CONFIG_LBLAW0=y +CONFIG_LBLAW0_BASE=0x40000000 +CONFIG_LBLAW0_LENGTH_64_MBYTES=y +CONFIG_LBLAW1=y +CONFIG_LBLAW1_BASE=0xA0000000 +CONFIG_LBLAW2=y +CONFIG_LBLAW2_BASE=0x90000000 +CONFIG_LBLAW2_LENGTH_64_MBYTES=y +CONFIG_LBLAW3=y +CONFIG_LBLAW3_BASE=0x80000000 +CONFIG_LBLAW3_LENGTH_64_MBYTES=y +CONFIG_HID0_FINAL_EMCP=y +CONFIG_HID0_FINAL_ICE=y +CONFIG_HID2_IFEB=y +CONFIG_HID2_EBPX=y +CONFIG_HID2_HBE=y +CONFIG_ACR_PIPE_DEP_3=y +CONFIG_ACR_RPTCNT_3=y +CONFIG_SPCR_OPT_SPEC_READ=y +CONFIG_LCRR_EADC_1=y +CONFIG_LCRR_CLKDIV_2=y +CONFIG_SYS_MONITOR_LEN=393216 +CONFIG_FIT=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_BOOTDELAY=5 +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_FLUSH_STDIN=y +CONFIG_AUTOBOOT_PROMPT="\nEnter password - autoboot in %d sec...\n" +CONFIG_AUTOBOOT_ENCRYPTION=y +CONFIG_AUTOBOOT_STOP_STR_ENABLE=y +CONFIG_AUTOBOOT_STOP_STR_SHA256="4813494d137e1631bba301d5acab6e7bb7aa74ce1185d456565ef51d737677b2" +CONFIG_USE_BOOTCOMMAND=y +CONFIG_BOOTCOMMAND="run flashboot" +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_BOARD_EARLY_INIT_R=y +CONFIG_MISC_INIT_R=y +CONFIG_HUSH_PARSER=y +# CONFIG_CMD_BDI is not set +# CONFIG_CMD_CONSOLE is not set +# CONFIG_BOOTM_PLAN9 is not set +# CONFIG_BOOTM_RTEMS is not set +# CONFIG_BOOTM_VXWORKS is not set +CONFIG_SYS_BOOTM_LEN=0x10000000 +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_GO is not set +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_XIMG is not set +CONFIG_CMD_ASKENV=y +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MTD=y +CONFIG_CMD_NAND=y +CONFIG_CMD_DHCP=y +CONFIG_BOOTP_BOOTFILESIZE=y +# CONFIG_CMD_NFS is not set +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +# CONFIG_CMD_SLEEP is not set +CONFIG_CMD_MTDPARTS=y +CONFIG_CMD_UBI=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_USE_ETHPRIME=y +CONFIG_ETHPRIME="UEC0" +CONFIG_USE_HOSTNAME=y +CONFIG_HOSTNAME="cmpcpro" +CONFIG_USE_IPADDR=y +CONFIG_IPADDR="192.168.0.3" +CONFIG_USE_NETMASK=y +CONFIG_NETMASK="255.255.255.0" +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.168.0.1" +# CONFIG_DM_DEVICE_REMOVE is not set +CONFIG_CLK=y +CONFIG_CPU=y +CONFIG_CPU_MPC83XX=y +CONFIG_SYS_BR0_PRELIM_BOOL=y +CONFIG_SYS_BR0_PRELIM=0x40001001 +CONFIG_SYS_OR0_PRELIM=0xFC001080 +CONFIG_SYS_BR1_PRELIM_BOOL=y +CONFIG_SYS_BR1_PRELIM=0xA0000801 +CONFIG_SYS_OR1_PRELIM=0xFFFF9030 +CONFIG_SYS_BR2_PRELIM_BOOL=y +CONFIG_SYS_BR2_PRELIM=0x90001001 +CONFIG_SYS_OR2_PRELIM=0xfc001090 +CONFIG_SYS_BR3_PRELIM_BOOL=y +CONFIG_SYS_BR3_PRELIM=0x80001081 +CONFIG_SYS_OR3_PRELIM=0xfc000100 +CONFIG_MPC8XXX_GPIO=y +CONFIG_QE_GPIO=y +# CONFIG_I2C is not set +# CONFIG_MMC is not set +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_CFI_DRIVER=y +CONFIG_SYS_FLASH_CFI=y +CONFIG_MTD_RAW_NAND=y +CONFIG_PHYLIB=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ90X1=y +CONFIG_DM_MDIO=y +CONFIG_DM_ETH_PHY=y +CONFIG_MII=y +CONFIG_RMII=y +CONFIG_QE_UEC=y +CONFIG_QE=y +CONFIG_U_QE=y +CONFIG_SPECIFY_CONSOLE_INDEX=y +CONFIG_DM_SERIAL=y +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_MPC8XXX_SPI=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_MPC83XX=y +CONFIG_WDT=y +CONFIG_WDT_MPC8xxx=y +# CONFIG_REGEX is not set +CONFIG_LZMA=y diff --git a/include/configs/cmpcpro.h b/include/configs/cmpcpro.h new file mode 100644 index 0000000..24e62df --- /dev/null +++ b/include/configs/cmpcpro.h @@ -0,0 +1,99 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2006-2023 CS GROUP France + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +/* + * System IO Config + */ +#define CFG_SYS_SICRL 0x00000000 + +#define CFG_SYS_DDR_SDRAM_BASE 0x00000000 + +#define CFG_SYS_DDRCDR 0x73000002 /* DDR II voltage is 1.8V */ + +/* + * Manually set up DDR parameters + */ + +/* DDR 512 M */ +#define CFG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_ODT_WR_CFG | CSCONFIG_BANK_BIT_3 | \ + CSCONFIG_ROW_BIT_14 | CSCONFIG_COL_BIT_10) +/* 0x80840102 */ +#define CFG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) | \ + (0 << TIMING_CFG0_WRT_SHIFT) | \ + (0 << TIMING_CFG0_RRT_SHIFT) | \ + (0 << TIMING_CFG0_WWT_SHIFT) | \ + (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \ + (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ + (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ + (2 << TIMING_CFG0_MRS_CYC_SHIFT)) +/* 0x00220802 */ +#define CFG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) | \ + (6 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ + (2 << TIMING_CFG1_ACTTORW_SHIFT) | \ + (5 << TIMING_CFG1_CASLAT_SHIFT) | \ + (27 << TIMING_CFG1_REFREC_SHIFT) | \ + (2 << TIMING_CFG1_WRREC_SHIFT) | \ + (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ + (2 << TIMING_CFG1_WRTORD_SHIFT)) +/* 0x3935D322 */ +#define CFG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) | \ + (31 << TIMING_CFG2_CPO_SHIFT) | \ + (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ + (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ + (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ + (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ + (7 << TIMING_CFG2_FOUR_ACT_SHIFT)) +/* 0x0F9048CA */ +#define CFG_SYS_DDR_TIMING_3 0x00000000 +#define CFG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 +/* 0x02000000 */ +#define CFG_SYS_DDR_MODE ((0x4440 << SDRAM_MODE_ESD_SHIFT) | (0x0232 << SDRAM_MODE_SD_SHIFT)) +/* 0x44400232 */ +#define CFG_SYS_DDR_MODE2 0x8000c000 +#define CFG_SYS_DDR_INTERVAL ((800 << SDRAM_INTERVAL_REFINT_SHIFT) | \ + (100 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) +#define CFG_SYS_DDR_CS0_BNDS (CFG_SYS_DDR_SDRAM_BASE >> 8 | 0x0000001F) + +#define CFG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN | SDRAM_CFG_SDRAM_TYPE_DDR2 | SDRAM_CFG_32_BE) +/* 0x43080000 */ +#define CFG_SYS_DDR_SDRAM_CFG2 0x00401000 + +/* + * Initial RAM Base Address Setup + */ +#define CFG_SYS_INIT_RAM_ADDR (CONFIG_SYS_IMMR + 0x110000) +#define CFG_SYS_INIT_RAM_SIZE 0x4000 + +/* + * FLASH on the Local Bus + */ +#define CFG_SYS_FLASH_BASE 0x40000000 /* FLASH base address */ +#define CFG_SYS_FLASH_SIZE 64 /* FLASH size is 64M */ + +/* + * NAND + */ +#define CFG_SYS_NAND_BASE 0xa0000000 + +/* + * For booting Linux, the board info and command line data + * have to be in the first 256 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ + /* Initial Memory map for Linux */ +#define CFG_SYS_BOOTMAPSZ SZ_256M + +/* Board names */ +#define CFG_BOARD_CMPCXXX "cmpcpro" +#define CFG_BOARD_MCR3000_2G "mcrpro" +#define CFG_BOARD_VGOIP "vgoippro" +#define CFG_BOARD_MIAE "miaepro" + +#endif /* __CONFIG_H */ -- cgit v1.1