From 008468fa35f8e3fd4b2a5885d1c5cc61a251f87e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Tue, 3 May 2022 11:13:24 +0200 Subject: cmd: mvebu: Hide bubt specific options when bubt is disabled MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit CONFIG_MVEBU_NAND_BOOT, CONFIG_MVEBU_SPI_BOOT, CONFIG_MVEBU_MMC_BOOT and CONFIG_MVEBU_UBOOT_DFLT_NAME are unused when CONFIG_CMD_MVEBU_BUBT is not enabled. So hide them. Signed-off-by: Pali Rohár Reviewed-by: Stefan Roese --- cmd/mvebu/Kconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/cmd/mvebu/Kconfig b/cmd/mvebu/Kconfig index ac8b0af..39963db 100644 --- a/cmd/mvebu/Kconfig +++ b/cmd/mvebu/Kconfig @@ -9,6 +9,8 @@ config CMD_MVEBU_BUBT For details about bubt command please see the documentation in doc/mvebu/cmd/bubt.txt +if CMD_MVEBU_BUBT + choice prompt "Flash for image" default MVEBU_SPI_BOOT @@ -49,6 +51,8 @@ config MVEBU_UBOOT_DFLT_NAME This option should contain a default file name to be used with MVEBU "bubt" command if the source file name is omitted +endif + config CMD_MVEBU_COMPHY_RX_TRAINING bool "mvebu_comphy_rx_training" depends on ARMADA_8K -- cgit v1.1 From 1001a0ab46ee3be2bb5f0017afdaf135df5e6f6d Mon Sep 17 00:00:00 2001 From: Chris Packham Date: Thu, 5 May 2022 14:09:34 +1200 Subject: arm: mvebu: Remove unused ARMADA_64BIT Nothing selects ARMADA_64BIT. Instead the 64-bit SoCs just select ARM64 directly. Remove the unused config item. Signed-off-by: Chris Packham Reviewed-by: Stefan Roese --- arch/arm/mach-mvebu/Kconfig | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig index a3f273f..c764439 100644 --- a/arch/arm/mach-mvebu/Kconfig +++ b/arch/arm/mach-mvebu/Kconfig @@ -17,10 +17,6 @@ config ARMADA_32BIT select TRANSLATION_OFFSET select SPL_SYS_NO_VECTOR_TABLE if SPL -config ARMADA_64BIT - bool - select ARM64 - # ARMv7 SoCs... config ARMADA_375 bool -- cgit v1.1 From 948da7773e340fe76d4d1b9c635d724bf8661d30 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Fri, 6 May 2022 11:05:13 +0200 Subject: arm: Add new config option ARCH_VERY_EARLY_INIT MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When this option is set then ARM _main() function would call arch_very_early_init() function at the beginning. It would be before calling any other functions like debug_uart_init() and also before initializing C runtime environment. Signed-off-by: Pali Rohár Reviewed-by: Stefan Roese --- arch/arm/Kconfig | 6 ++++++ arch/arm/lib/crt0.S | 5 +++++ 2 files changed, 11 insertions(+) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 0afec51..9898c7d 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -401,6 +401,12 @@ config SYS_ARM_CACHE_WRITEALLOC write is performed. endchoice +config ARCH_VERY_EARLY_INIT + bool + +config SPL_ARCH_VERY_EARLY_INIT + bool + config ARCH_CPU_INIT bool "Enable ARCH_CPU_INIT" help diff --git a/arch/arm/lib/crt0.S b/arch/arm/lib/crt0.S index ba31290..612a2d5 100644 --- a/arch/arm/lib/crt0.S +++ b/arch/arm/lib/crt0.S @@ -90,6 +90,11 @@ clbss_l:cmp r0, r1 /* while not at end of BSS */ ENTRY(_main) +/* Call arch_very_early_init before initializing C runtime environment. */ +#if CONFIG_IS_ENABLED(ARCH_VERY_EARLY_INIT) + bl arch_very_early_init +#endif + /* * Set up initial C runtime environment and call board_init_f(0). */ -- cgit v1.1 From 5bb2c550b11eb087437740b2a0d1fe780be5aec3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Fri, 6 May 2022 11:05:14 +0200 Subject: arm: mvebu: Move internal registers in arch_very_early_init() function MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Moving of internal registers from INTREG_BASE_ADDR_REG to SOC_REGS_PHY_BASE needs to be done very early, prior calling any function which may touch internal registers, like debug_uart_init(). So do it earlier in arch_very_early_init() instead of arch_cpu_init(). Movement is done in proper U-Boot, not in SPL. SPL may return to bootrom and bootrom requires internal registers at (old) expected location. Signed-off-by: Pali Rohár Reviewed-by: Stefan Roese --- arch/arm/mach-mvebu/Kconfig | 1 + arch/arm/mach-mvebu/Makefile | 1 + arch/arm/mach-mvebu/cpu.c | 31 ------------------------------- arch/arm/mach-mvebu/lowlevel.S | 27 +++++++++++++++++++++++++++ 4 files changed, 29 insertions(+), 31 deletions(-) create mode 100644 arch/arm/mach-mvebu/lowlevel.S diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig index c764439..a81b8e2 100644 --- a/arch/arm/mach-mvebu/Kconfig +++ b/arch/arm/mach-mvebu/Kconfig @@ -16,6 +16,7 @@ config ARMADA_32BIT select SUPPORT_SPL select TRANSLATION_OFFSET select SPL_SYS_NO_VECTOR_TABLE if SPL + select ARCH_VERY_EARLY_INIT # ARMv7 SoCs... config ARMADA_375 diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile index 1b45188..8bd2246 100644 --- a/arch/arm/mach-mvebu/Makefile +++ b/arch/arm/mach-mvebu/Makefile @@ -21,6 +21,7 @@ else # CONFIG_ARCH_KIRKWOOD obj-y = cpu.o obj-y += dram.o +obj-y += lowlevel.o obj-$(CONFIG_DM_RESET) += system-controller.o ifndef CONFIG_SPL_BUILD obj-$(CONFIG_ARMADA_375) += ../../../drivers/ddr/marvell/axp/xor.o diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c index 1e89377..173d95a 100644 --- a/arch/arm/mach-mvebu/cpu.c +++ b/arch/arm/mach-mvebu/cpu.c @@ -413,20 +413,7 @@ static void update_sdram_window_sizes(void) } } -void mmu_disable(void) -{ - asm volatile( - "mrc p15, 0, r0, c1, c0, 0\n" - "bic r0, #1\n" - "mcr p15, 0, r0, c1, c0, 0\n"); -} - #ifdef CONFIG_ARCH_CPU_INIT -static void set_cbar(u32 addr) -{ - asm("mcr p15, 4, %0, c15, c0" : : "r" (addr)); -} - #define MV_USB_PHY_BASE (MVEBU_AXP_USB_BASE + 0x800) #define MV_USB_PHY_PLL_REG(reg) (MV_USB_PHY_BASE | (((reg) & 0xF) << 2)) #define MV_USB_X3_BASE(addr) (MVEBU_AXP_USB_BASE | BIT(11) | \ @@ -476,24 +463,6 @@ int arch_cpu_init(void) struct pl310_regs *const pl310 = (struct pl310_regs *)CONFIG_SYS_PL310_BASE; - /* - * Only with disabled MMU its possible to switch the base - * register address on Armada 38x. Without this the SDRAM - * located at >= 0x4000.0000 is also not accessible, as its - * still locked to cache. - */ - mmu_disable(); - - /* Linux expects the internal registers to be at 0xf1000000 */ - writel(SOC_REGS_PHY_BASE, INTREG_BASE_ADDR_REG); - set_cbar(SOC_REGS_PHY_BASE + 0xC000); - - /* - * From this stage on, the SoC detection is working. As we have - * configured the internal register base to the value used - * in the macros / defines in the U-Boot header (soc.h). - */ - if (mvebu_soc_family() == MVEBU_SOC_A38X) { /* * To fully release / unlock this area from cache, we need diff --git a/arch/arm/mach-mvebu/lowlevel.S b/arch/arm/mach-mvebu/lowlevel.S new file mode 100644 index 0000000..2491310 --- /dev/null +++ b/arch/arm/mach-mvebu/lowlevel.S @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#include +#include + +ENTRY(arch_very_early_init) +#ifdef CONFIG_ARMADA_38X + /* + * Only with disabled MMU its possible to switch the base + * register address on Armada 38x. Without this the SDRAM + * located at >= 0x4000.0000 is also not accessible, as its + * still locked to cache. + */ + mrc p15, 0, r0, c1, c0, 0 + bic r0, #1 + mcr p15, 0, r0, c1, c0, 0 +#endif + + /* Move internal registers from INTREG_BASE_ADDR_REG to SOC_REGS_PHY_BASE */ + ldr r0, =SOC_REGS_PHY_BASE + ldr r1, =INTREG_BASE_ADDR_REG + str r0, [r1] + add r0, r0, #0xC000 + mcr p15, 4, r0, c15, c0 + + bx lr +ENDPROC(arch_very_early_init) -- cgit v1.1 From 9f971ff71498a34f533e341a7e0d00ec75d9fc5b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Fri, 6 May 2022 11:05:15 +0200 Subject: serial: Add new config option SPL_DEBUG_UART_BASE MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit SPL_DEBUG_UART_BASE is same as DEBUG_UART_BASE, but applies only for SPL. In some cases base address of UART is different in SPL and proper U-Boot. Signed-off-by: Pali Rohár Reviewed-by: Stefan Roese --- drivers/serial/Kconfig | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 26fa498..46726d7 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -508,6 +508,13 @@ config DEBUG_UART_BASE A default should be provided by your board, but if not you will need to use the correct value here. +config SPL_DEBUG_UART_BASE + hex "Base address of UART for SPL" + depends on SPL && DEBUG_UART + default DEBUG_UART_BASE + help + This is the base address of your UART for memory-mapped UARTs for SPL. + config DEBUG_UART_CLOCK int "UART input clock" depends on DEBUG_UART -- cgit v1.1 From 958789f026c23d9bfea9d31fe78745ef32b0bd7b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Mon, 16 May 2022 18:49:09 +0200 Subject: serial: Add new config option TPL_DEBUG_UART_BASE MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit TPL_DEBUG_UART_BASE is same as DEBUG_UART_BASE, but applies only for TPL. Signed-off-by: Pali Rohár Signed-off-by: Stefan Roese --- drivers/serial/Kconfig | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 46726d7..f6425a5 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -515,6 +515,13 @@ config SPL_DEBUG_UART_BASE help This is the base address of your UART for memory-mapped UARTs for SPL. +config TPL_DEBUG_UART_BASE + hex "Base address of UART for TPL" + depends on TPL && DEBUG_UART + default DEBUG_UART_BASE + help + This is the base address of your UART for memory-mapped UARTs for TPL. + config DEBUG_UART_CLOCK int "UART input clock" depends on DEBUG_UART -- cgit v1.1 From d293759d55cce9c3efccf96ca8423008c9d0293b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Fri, 6 May 2022 11:05:16 +0200 Subject: serial: ns16550: Add support for SPL_DEBUG_UART_BASE MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use CONFIG_VAL(DEBUG_UART_BASE) instead of CONFIG_DEBUG_UART_BASE, so proper config value (CONFIG_DEBUG_UART_BASE or CONFIG_SPL_DEBUG_UART_BASE) is used based on building target. Signed-off-by: Pali Rohár Reviewed-by: Stefan Roese --- drivers/serial/ns16550.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c index a4220fd..78bfe62 100644 --- a/drivers/serial/ns16550.c +++ b/drivers/serial/ns16550.c @@ -325,7 +325,7 @@ int ns16550_tstc(struct ns16550 *com_port) static inline void _debug_uart_init(void) { - struct ns16550 *com_port = (struct ns16550 *)CONFIG_DEBUG_UART_BASE; + struct ns16550 *com_port = (struct ns16550 *)CONFIG_VAL(DEBUG_UART_BASE); int baud_divisor; /* @@ -360,7 +360,7 @@ static inline int NS16550_read_baud_divisor(struct ns16550 *com_port) static inline void _debug_uart_putc(int ch) { - struct ns16550 *com_port = (struct ns16550 *)CONFIG_DEBUG_UART_BASE; + struct ns16550 *com_port = (struct ns16550 *)CONFIG_VAL(DEBUG_UART_BASE); while (!(serial_din(&com_port->lsr) & UART_LSR_THRE)) { #ifdef CONFIG_DEBUG_UART_NS16550_CHECK_ENABLED -- cgit v1.1 From 2418c1f56f0f39b86e81defb391d7d05bfc43ba4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Fri, 6 May 2022 11:05:17 +0200 Subject: arm: mvebu: turris_omnia: Fix DEBUG_UART_BASE MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Internal registers in SPL are at address 0xd0000000 and in proper U-Boot at address 0xf1000000. UART base address is located in internal registers. Fix DEBUG_UART_BASE option to correct value for both SPL and proper U-Boot. This change fixes hangup of proper U-Boot when it is trying to print something via debug UART. Signed-off-by: Pali Rohár Reviewed-by: Stefan Roese --- configs/turris_omnia_defconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/configs/turris_omnia_defconfig b/configs/turris_omnia_defconfig index 217e260..62c9be2 100644 --- a/configs/turris_omnia_defconfig +++ b/configs/turris_omnia_defconfig @@ -18,7 +18,7 @@ CONFIG_DEFAULT_DEVICE_TREE="armada-385-turris-omnia" CONFIG_SPL_TEXT_BASE=0x40000030 CONFIG_SPL_SERIAL=y CONFIG_SPL=y -CONFIG_DEBUG_UART_BASE=0xd0012000 +CONFIG_DEBUG_UART_BASE=0xf1012000 CONFIG_DEBUG_UART_CLOCK=250000000 CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_DEBUG_UART=y @@ -93,6 +93,7 @@ CONFIG_PCI_MVEBU=y CONFIG_DM_RTC=y CONFIG_RTC_ARMADA38X=y CONFIG_SCSI=y +CONFIG_SPL_DEBUG_UART_BASE=0xd0012000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550=y CONFIG_KIRKWOOD_SPI=y -- cgit v1.1 From 5be172819fc870f949c182dbdf7cfd54d0651cb3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Mon, 9 May 2022 20:17:07 +0200 Subject: arm: mvebu: Fix DEBUG_UART_BASE for all 32-bit boards MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit UART base address is located in internal registers. Internal registers for 32-bit mvebu boards in SPL are at address 0xd0000000 and in proper U-Boot at address 0xf1000000. Fix DEBUG_UART_BASE option for all 32-bit mvebu boards. Signed-off-by: Pali Rohár Reviewed-by: Stefan Roese --- configs/clearfog_defconfig | 3 ++- configs/controlcenterdc_defconfig | 3 ++- configs/db-88f6820-amc_defconfig | 3 ++- configs/db-88f6820-gp_defconfig | 3 ++- configs/db-mv784mp-gp_defconfig | 3 ++- configs/ds414_defconfig | 3 ++- configs/helios4_defconfig | 3 ++- configs/maxbcm_defconfig | 3 ++- configs/theadorable_debug_defconfig | 3 ++- configs/x530_defconfig | 3 ++- 10 files changed, 20 insertions(+), 10 deletions(-) diff --git a/configs/clearfog_defconfig b/configs/clearfog_defconfig index a7b6508..9f744d0 100644 --- a/configs/clearfog_defconfig +++ b/configs/clearfog_defconfig @@ -13,7 +13,7 @@ CONFIG_DEFAULT_DEVICE_TREE="armada-388-clearfog" CONFIG_SPL_TEXT_BASE=0x40000030 CONFIG_SPL_SERIAL=y CONFIG_SPL=y -CONFIG_DEBUG_UART_BASE=0xd0012000 +CONFIG_DEBUG_UART_BASE=0xf1012000 CONFIG_DEBUG_UART_CLOCK=250000000 CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_DEBUG_UART=y @@ -66,6 +66,7 @@ CONFIG_MVMDIO=y CONFIG_PCI=y CONFIG_PCI_MVEBU=y CONFIG_SCSI=y +CONFIG_SPL_DEBUG_UART_BASE=0xd0012000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550=y CONFIG_KIRKWOOD_SPI=y diff --git a/configs/controlcenterdc_defconfig b/configs/controlcenterdc_defconfig index df38b2c..c366db4 100644 --- a/configs/controlcenterdc_defconfig +++ b/configs/controlcenterdc_defconfig @@ -16,7 +16,7 @@ CONFIG_DEFAULT_DEVICE_TREE="armada-38x-controlcenterdc" CONFIG_SPL_TEXT_BASE=0x40000030 CONFIG_SPL_SERIAL=y CONFIG_SPL=y -CONFIG_DEBUG_UART_BASE=0xd0012000 +CONFIG_DEBUG_UART_BASE=0xf1012000 CONFIG_DEBUG_UART_CLOCK=250000000 CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_DEBUG_UART=y @@ -84,6 +84,7 @@ CONFIG_PCI_MVEBU=y CONFIG_SCSI=y CONFIG_SCSI_AHCI_PLAT=y CONFIG_SYS_SCSI_MAX_SCSI_ID=2 +CONFIG_SPL_DEBUG_UART_BASE=0xd0012000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550=y CONFIG_KIRKWOOD_SPI=y diff --git a/configs/db-88f6820-amc_defconfig b/configs/db-88f6820-amc_defconfig index 9b77b4a..be4ee79 100644 --- a/configs/db-88f6820-amc_defconfig +++ b/configs/db-88f6820-amc_defconfig @@ -13,7 +13,7 @@ CONFIG_DEFAULT_DEVICE_TREE="armada-385-db-88f6820-amc" CONFIG_SPL_TEXT_BASE=0x40000030 CONFIG_SPL_SERIAL=y CONFIG_SPL=y -CONFIG_DEBUG_UART_BASE=0xd0012000 +CONFIG_DEBUG_UART_BASE=0xf1012000 CONFIG_DEBUG_UART_CLOCK=200000000 CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_DEBUG_UART=y @@ -70,6 +70,7 @@ CONFIG_MII=y CONFIG_MVMDIO=y CONFIG_PCI=y CONFIG_PCI_MVEBU=y +CONFIG_SPL_DEBUG_UART_BASE=0xd0012000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550=y CONFIG_KIRKWOOD_SPI=y diff --git a/configs/db-88f6820-gp_defconfig b/configs/db-88f6820-gp_defconfig index f56d1fb..55ebb57 100644 --- a/configs/db-88f6820-gp_defconfig +++ b/configs/db-88f6820-gp_defconfig @@ -13,7 +13,7 @@ CONFIG_DEFAULT_DEVICE_TREE="armada-388-gp" CONFIG_SPL_TEXT_BASE=0x40000030 CONFIG_SPL_SERIAL=y CONFIG_SPL=y -CONFIG_DEBUG_UART_BASE=0xd0012000 +CONFIG_DEBUG_UART_BASE=0xf1012000 CONFIG_DEBUG_UART_CLOCK=250000000 CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_DEBUG_UART=y @@ -66,6 +66,7 @@ CONFIG_MVMDIO=y CONFIG_PCI=y CONFIG_PCI_MVEBU=y CONFIG_SCSI=y +CONFIG_SPL_DEBUG_UART_BASE=0xd0012000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550=y CONFIG_KIRKWOOD_SPI=y diff --git a/configs/db-mv784mp-gp_defconfig b/configs/db-mv784mp-gp_defconfig index 5683f11..2c1d3b4 100644 --- a/configs/db-mv784mp-gp_defconfig +++ b/configs/db-mv784mp-gp_defconfig @@ -13,7 +13,7 @@ CONFIG_DEFAULT_DEVICE_TREE="armada-xp-gp" CONFIG_SPL_TEXT_BASE=0x40004030 CONFIG_SPL_SERIAL=y CONFIG_SPL=y -CONFIG_DEBUG_UART_BASE=0xd0012000 +CONFIG_DEBUG_UART_BASE=0xf1012000 CONFIG_DEBUG_UART_CLOCK=250000000 CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_DEBUG_UART=y @@ -68,6 +68,7 @@ CONFIG_MII=y CONFIG_MVMDIO=y CONFIG_PCI=y CONFIG_PCI_MVEBU=y +CONFIG_SPL_DEBUG_UART_BASE=0xd0012000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550=y CONFIG_KIRKWOOD_SPI=y diff --git a/configs/ds414_defconfig b/configs/ds414_defconfig index a83fe07..81a767c 100644 --- a/configs/ds414_defconfig +++ b/configs/ds414_defconfig @@ -19,7 +19,7 @@ CONFIG_DEFAULT_DEVICE_TREE="armada-xp-synology-ds414" CONFIG_SPL_TEXT_BASE=0x40004030 CONFIG_SPL_SERIAL=y CONFIG_SPL=y -CONFIG_DEBUG_UART_BASE=0xd0012000 +CONFIG_DEBUG_UART_BASE=0xf1012000 CONFIG_DEBUG_UART_CLOCK=250000000 CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_DEBUG_UART=y @@ -68,6 +68,7 @@ CONFIG_MII=y CONFIG_MVMDIO=y CONFIG_PCI=y CONFIG_PCI_MVEBU=y +CONFIG_SPL_DEBUG_UART_BASE=0xd0012000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550=y CONFIG_KIRKWOOD_SPI=y diff --git a/configs/helios4_defconfig b/configs/helios4_defconfig index c2130ba..4dc9e3b 100644 --- a/configs/helios4_defconfig +++ b/configs/helios4_defconfig @@ -13,7 +13,7 @@ CONFIG_DEFAULT_DEVICE_TREE="armada-388-helios4" CONFIG_SPL_TEXT_BASE=0x40000030 CONFIG_SPL_SERIAL=y CONFIG_SPL=y -CONFIG_DEBUG_UART_BASE=0xd0012000 +CONFIG_DEBUG_UART_BASE=0xf1012000 CONFIG_DEBUG_UART_CLOCK=250000000 CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_DEBUG_UART=y @@ -67,6 +67,7 @@ CONFIG_MVMDIO=y CONFIG_PCI=y CONFIG_PCI_MVEBU=y CONFIG_SCSI=y +CONFIG_SPL_DEBUG_UART_BASE=0xd0012000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550=y CONFIG_KIRKWOOD_SPI=y diff --git a/configs/maxbcm_defconfig b/configs/maxbcm_defconfig index 40f79d4..c325dd7 100644 --- a/configs/maxbcm_defconfig +++ b/configs/maxbcm_defconfig @@ -13,7 +13,7 @@ CONFIG_DEFAULT_DEVICE_TREE="armada-xp-maxbcm" CONFIG_SPL_TEXT_BASE=0x40004030 CONFIG_SPL_SERIAL=y CONFIG_SPL=y -CONFIG_DEBUG_UART_BASE=0xd0012000 +CONFIG_DEBUG_UART_BASE=0xf1012000 CONFIG_DEBUG_UART_CLOCK=250000000 CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_DEBUG_UART=y @@ -48,6 +48,7 @@ CONFIG_PHY_GIGE=y CONFIG_MVNETA=y CONFIG_MII=y CONFIG_MVMDIO=y +CONFIG_SPL_DEBUG_UART_BASE=0xd0012000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550=y CONFIG_KIRKWOOD_SPI=y diff --git a/configs/theadorable_debug_defconfig b/configs/theadorable_debug_defconfig index 111392d..9e8523d 100644 --- a/configs/theadorable_debug_defconfig +++ b/configs/theadorable_debug_defconfig @@ -14,7 +14,7 @@ CONFIG_DEFAULT_DEVICE_TREE="armada-xp-theadorable" CONFIG_SPL_TEXT_BASE=0x40004030 CONFIG_SPL_SERIAL=y CONFIG_SPL=y -CONFIG_DEBUG_UART_BASE=0xd0012000 +CONFIG_DEBUG_UART_BASE=0xf1012000 CONFIG_DEBUG_UART_CLOCK=250000000 CONFIG_SYS_MEM_TOP_HIDE=0x80000 CONFIG_SYS_LOAD_ADDR=0x800000 @@ -74,6 +74,7 @@ CONFIG_MVMDIO=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCI_MVEBU=y +CONFIG_SPL_DEBUG_UART_BASE=0xd0012000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550=y CONFIG_KIRKWOOD_SPI=y diff --git a/configs/x530_defconfig b/configs/x530_defconfig index 77d2249..860cb22 100644 --- a/configs/x530_defconfig +++ b/configs/x530_defconfig @@ -14,7 +14,7 @@ CONFIG_DEFAULT_DEVICE_TREE="armada-385-atl-x530" CONFIG_SPL_TEXT_BASE=0x40000030 CONFIG_SPL_SERIAL=y CONFIG_SPL=y -CONFIG_DEBUG_UART_BASE=0xd0012000 +CONFIG_DEBUG_UART_BASE=0xf1012000 CONFIG_DEBUG_UART_CLOCK=250000000 CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_ENV_ADDR=0x100000 @@ -72,6 +72,7 @@ CONFIG_PCI_MVEBU=y CONFIG_DM_RTC=y CONFIG_RTC_DS1307=y CONFIG_SPECIFY_CONSOLE_INDEX=y +CONFIG_SPL_DEBUG_UART_BASE=0xd0012000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550=y CONFIG_KIRKWOOD_SPI=y -- cgit v1.1 From 29dd6e475a1551d8dab6231147c7120547099392 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Mon, 9 May 2022 11:12:46 +0200 Subject: arm: mvebu: turris_{omnia,mox}: Enable CONFIG_NETCONSOLE MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This allows to use U-Boot console on Turris devices via network. Signed-off-by: Pali Rohár Reviewed-by: Stefan Roese --- configs/turris_mox_defconfig | 1 + configs/turris_omnia_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/configs/turris_mox_defconfig b/configs/turris_mox_defconfig index bcd3699..c1bd1de 100644 --- a/configs/turris_mox_defconfig +++ b/configs/turris_mox_defconfig @@ -56,6 +56,7 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ARP_TIMEOUT=200 CONFIG_NET_RETRY_COUNT=50 +CONFIG_NETCONSOLE=y CONFIG_SCSI_AHCI=y CONFIG_AHCI_PCI=y CONFIG_BUTTON=y diff --git a/configs/turris_omnia_defconfig b/configs/turris_omnia_defconfig index 62c9be2..da94ca7 100644 --- a/configs/turris_omnia_defconfig +++ b/configs/turris_omnia_defconfig @@ -68,6 +68,7 @@ CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="ethernet@34000" CONFIG_ARP_TIMEOUT=200 CONFIG_NET_RETRY_COUNT=50 +CONFIG_NETCONSOLE=y CONFIG_SPL_OF_TRANSLATE=y CONFIG_AHCI_PCI=y CONFIG_AHCI_MVEBU=y -- cgit v1.1 From c7111e6ffd4b4f8fefd31044d2e042f910f54775 Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Fri, 6 May 2022 13:54:43 +0200 Subject: mvebu: uDPU: include fixed-phy support uDPU relies on using fixed-phy for the SFP support, and since the fixed-phy parsing was moved to the generic driver instead of mvneta networking stopped working on uDPU with: uDPU>> dhcp dm_eth_phy_connect failed This is due to the conversion commit not enabling fixed-phy support in defconfig like it did for other boards. Fixes: 77fcf3cf1251 ("net: mvneta: Convert to use PHY_FIXED for fixed-link") Signed-off-by: Robert Marko Reviewed-by: Stefan Roese --- configs/uDPU_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/uDPU_defconfig b/configs/uDPU_defconfig index f2852ad..f7cd1a0 100644 --- a/configs/uDPU_defconfig +++ b/configs/uDPU_defconfig @@ -70,6 +70,7 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_MTD=y CONFIG_PHYLIB_10G=y CONFIG_PHY_MARVELL=y +CONFIG_PHY_FIXED=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MVNETA=y -- cgit v1.1 From f9ec791b5e24378b71590877499f8683d5f54dac Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Fri, 6 May 2022 20:01:39 +0200 Subject: pinctrl: probe pinctrl drivers during post-bind MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Currently, pinctrl drivers only get probed if pinconf is actually being used, however on SoC-s like Armada 3720 pinctrl driver is a also the GPIO driver. So, if the pinctrl driver doesn't get probed GPIO-s won't get registered and thus they cannot be used. This is a problem on the Methode eDPU as it just uses SB pins as GPIO-s and without them being registered networking won't work as it only has one SFP slot and the TX disable GPIO is on the SB controller. So, probe the pinctrl drivers using DM_FLAG_PROBE_AFTER_BIND like LED uclass does. Signed-off-by: Robert Marko Reviewed-by: Pali Rohár Reviewed-by: Stefan Roese --- drivers/pinctrl/pinctrl-uclass.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/pinctrl/pinctrl-uclass.c b/drivers/pinctrl/pinctrl-uclass.c index 4462ed2..38ce2b5 100644 --- a/drivers/pinctrl/pinctrl-uclass.c +++ b/drivers/pinctrl/pinctrl-uclass.c @@ -402,6 +402,13 @@ static int __maybe_unused pinctrl_post_bind(struct udevice *dev) { const struct pinctrl_ops *ops = pinctrl_get_ops(dev); + /* + * Make sure that the pinctrl driver gets probed after binding + * as some pinctrl drivers also register the GPIO driver during + * probe, and if they are not probed GPIO-s are not registered. + */ + dev_or_flags(dev, DM_FLAG_PROBE_AFTER_BIND); + if (!ops) { dev_dbg(dev, "ops is not set. Do not bind.\n"); return -EINVAL; -- cgit v1.1