From 83a8e27062d2c24e001426c4c35859e133e2f1d5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Thu, 3 Feb 2022 17:50:46 +0100 Subject: tools/mrvl_uart.sh: Remove script MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit There are two tools for sending images over UART to Marvell SoCs: kwboot and mrvl_uart.sh. kwboot received lot of new features and improvements in last few months. There is no need to maintain two tools in U-Boot, so remove old mrvl_uart.sh tool. Signed-off-by: Pali Rohár Reviewed-by: Marek Behún Reviewed-by: Marcel Ziswiler Tested-by: Marcel Ziswiler Reviewed-by: Tony Dinh --- tools/mrvl_uart.sh | 119 ----------------------------------------------------- 1 file changed, 119 deletions(-) delete mode 100755 tools/mrvl_uart.sh diff --git a/tools/mrvl_uart.sh b/tools/mrvl_uart.sh deleted file mode 100755 index a46411f..0000000 --- a/tools/mrvl_uart.sh +++ /dev/null @@ -1,119 +0,0 @@ -#!/bin/bash -# SPDX-License-Identifier: GPL-2.0 -# -###################################################### -# Copyright (C) 2016 Marvell International Ltd. -# -# https://spdx.org/licenses -# -# Author: Konstantin Porotchkin kostap@marvell.com -# -# Version 0.3 -# -# UART recovery downloader for Armada SoCs -# -###################################################### - -port=$1 -file=$2 -speed=$3 - -pattern_repeat=1500 -default_baudrate=115200 -tmpfile=/tmp/xmodem.pattern -tools=( dd stty sx minicom ) - -case "$3" in - 2) - fast_baudrate=230400 - prefix="\xF2" - ;; - 4) - fast_baudrate=460800 - prefix="\xF4" - ;; - 8) - fast_baudrate=921600 - prefix="\xF8" - ;; - *) - fast_baudrate=$default_baudrate - prefix="\xBB" -esac - -if [[ -z "$port" || -z "$file" ]] -then - echo -e "\nMarvell recovery image downloader for Armada SoC family." - echo -e "Command syntax:" - echo -e "\t$(basename $0) [2|4|8]" - echo -e "\tport - serial port the target board is connected to" - echo -e "\tfile - recovery boot image for target download" - echo -e "\t2|4|8 - times to increase the default serial port speed by" - echo -e "For example - load the image over ttyUSB0 @ 460800 baud:" - echo -e "$(basename $0) /dev/ttyUSB0 /tmp/flash-image.bin 4\n" - echo -e "=====WARNING=====" - echo -e "- The speed-up option is not available in SoC families prior to A8K+" - echo -e "- This utility is not compatible with Armada 37xx SoC family\n" -fi - -# Sanity checks -if [ -c "$port" ] -then - echo -e "Using device connected on serial port \"$port\"" -else - echo "Wrong serial port name!" - exit 1 -fi - -if [ -f "$file" ] -then - echo -e "Loading flash image file \"$file\"" -else - echo "File $file does not exist!" - exit 1 -fi - -# Verify required tools installation -for tool in ${tools[@]} -do - toolname=`which $tool` - if [ -z "$toolname" ] - then - echo -e "Missing installation of \"$tool\" --> Exiting" - exit 1 - fi -done - - -echo -e "Recovery will run at $fast_baudrate baud" -echo -e "========================================" - -if [ -f "$tmpfile" ] -then - rm -f $tmpfile -fi - -# Send the escape sequence to target board using default debug port speed -stty -F $port raw ignbrk time 5 $default_baudrate -counter=0 -while [ $counter -lt $pattern_repeat ]; do - echo -n -e "$prefix\x11\x22\x33\x44\x55\x66\x77" >> $tmpfile - let counter=counter+1 -done - -echo -en "Press the \"Reset\" button on the target board and " -echo -en "the \"Enter\" key on the host keyboard simultaneously" -read -dd if=$tmpfile of=$port &>/dev/null - -# Speed up the binary image transfer -stty -F $port raw ignbrk time 5 $fast_baudrate -sx -vv $file > $port < $port -#sx-at91 $port $file - -# Return the port to the default speed -stty -F $port raw ignbrk time 5 $default_baudrate - -# Optional - fire up Minicom -minicom -D $port -b $default_baudrate - -- cgit v1.1 From a37b68820c432ff9b0b3dab597d94f7bbfa5d1e2 Mon Sep 17 00:00:00 2001 From: Rogier Stam Date: Wed, 9 Feb 2022 00:27:00 +0100 Subject: arm: mvebu: Fix Espressobin build for configs where ENV is not in SPI MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When storing the UBoot Environment in for example EXT4, the U-Boot build is broken for several reasons: 1. armada-385-turris-omnia-u-boot.dtsi will not allow CONFIG_ENV_OFFSET and CONFIG_ENV_SIZE to be undefined 2. armada-37xx/board.c ft_board_setup function does not exist if CONFIG_ENV_IS_IN_SPI_FLASH is not defined This commit changes these files so that selecting a different location for the environment is possible. Signed-off-by: Rogier Stam Reviewed-by: Pali Rohár --- arch/arm/dts/armada-385-turris-omnia-u-boot.dtsi | 2 ++ board/Marvell/mvebu_armada-37xx/board.c | 4 +++- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm/dts/armada-385-turris-omnia-u-boot.dtsi b/arch/arm/dts/armada-385-turris-omnia-u-boot.dtsi index 3ff76c9..008787e 100644 --- a/arch/arm/dts/armada-385-turris-omnia-u-boot.dtsi +++ b/arch/arm/dts/armada-385-turris-omnia-u-boot.dtsi @@ -38,6 +38,7 @@ }; }; +#ifdef CONFIG_ENV_IS_IN_SPI_FLASH &spi0 { u-boot,dm-pre-reloc; @@ -56,6 +57,7 @@ }; }; }; +#endif &uart0 { u-boot,dm-pre-reloc; diff --git a/board/Marvell/mvebu_armada-37xx/board.c b/board/Marvell/mvebu_armada-37xx/board.c index 6bfec0c..98e1b36 100644 --- a/board/Marvell/mvebu_armada-37xx/board.c +++ b/board/Marvell/mvebu_armada-37xx/board.c @@ -328,9 +328,10 @@ int board_network_enable(struct mii_dev *bus) return 0; } -#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_ENV_IS_IN_SPI_FLASH) +#ifdef CONFIG_OF_BOARD_SETUP int ft_board_setup(void *blob, struct bd_info *bd) { +#ifdef CONFIG_ENV_IS_IN_SPI_FLASH int ret; int spi_off; int parts_off; @@ -424,6 +425,7 @@ int ft_board_setup(void *blob, struct bd_info *bd) return 0; } +#endif return 0; } #endif -- cgit v1.1 From 10154b81def9b66e7ad45d6e295e5ea640d79f1e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Wed, 23 Feb 2022 14:15:45 +0100 Subject: arm: mvebu: a37xx: Add support for reading NB and SB fuse OTP value MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Implement reading NB and SB fuses of Armada 37xx SOC via U-Boot fuse API. Banks 0-43 are reserved for accessing Security OTP (not implemented yet). Bank 44 is used for accessing North Bridge OTP (69 bits via words 0-2). Bank 45 is used for accessing South Bridge OTP (97 bits via words 0-3). Write support is not implemented yet because it looks like that both North and South Bridge OTPs are already burned in factory with some data. The meaning of some bits of North Bridge is documented in WTMI source code. The meaning of bits in South Bridge is unknown. Signed-off-by: Pali Rohár Reviewed-by: Marek Behún Reviewed-by: Stefan Roese --- arch/arm/mach-mvebu/Kconfig | 1 + arch/arm/mach-mvebu/Makefile | 3 + arch/arm/mach-mvebu/armada3700/Makefile | 1 + arch/arm/mach-mvebu/armada3700/efuse.c | 136 ++++++++++++++++++++++++++++++++ 4 files changed, 141 insertions(+) create mode 100644 arch/arm/mach-mvebu/armada3700/efuse.c diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig index 21d9db2..ccdb624 100644 --- a/arch/arm/mach-mvebu/Kconfig +++ b/arch/arm/mach-mvebu/Kconfig @@ -44,6 +44,7 @@ config ARMADA_XP config ARMADA_3700 bool select ARM64 + select HAVE_MVEBU_EFUSE # Armada 7K and 8K are very similar - use only one Kconfig symbol for both config ARMADA_8K diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile index a5a2087..1b45188 100644 --- a/arch/arm/mach-mvebu/Makefile +++ b/arch/arm/mach-mvebu/Makefile @@ -27,7 +27,10 @@ obj-$(CONFIG_ARMADA_375) += ../../../drivers/ddr/marvell/axp/xor.o obj-$(CONFIG_ARMADA_38X) += ../../../drivers/ddr/marvell/a38x/xor.o obj-$(CONFIG_ARMADA_XP) += ../../../drivers/ddr/marvell/axp/xor.o obj-$(CONFIG_ARMADA_MSYS) += ../../../drivers/ddr/marvell/axp/xor.o + +ifdef CONFIG_ARMADA_38X obj-$(CONFIG_MVEBU_EFUSE) += efuse.o +endif extra-y += kwbimage.cfg diff --git a/arch/arm/mach-mvebu/armada3700/Makefile b/arch/arm/mach-mvebu/armada3700/Makefile index 031b3e8..cd74726 100644 --- a/arch/arm/mach-mvebu/armada3700/Makefile +++ b/arch/arm/mach-mvebu/armada3700/Makefile @@ -3,3 +3,4 @@ # Copyright (C) 2016 Stefan Roese obj-y = cpu.o +obj-$(CONFIG_MVEBU_EFUSE) += efuse.o diff --git a/arch/arm/mach-mvebu/armada3700/efuse.c b/arch/arm/mach-mvebu/armada3700/efuse.c new file mode 100644 index 0000000..03778f1 --- /dev/null +++ b/arch/arm/mach-mvebu/armada3700/efuse.c @@ -0,0 +1,136 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) 2017 Marvell International Ltd. + * (C) 2021 Pali Rohár + */ + +#include +#include +#include +#include +#include + +#define OTP_NB_REG_BASE ((void __iomem *)MVEBU_REGISTER(0x12600)) +#define OTP_SB_REG_BASE ((void __iomem *)MVEBU_REGISTER(0x1A200)) + +#define OTP_CONTROL_OFF 0x00 +#define OTP_MODE_BIT BIT(15) +#define OTP_RPTR_RST_BIT BIT(14) +#define OTP_POR_B_BIT BIT(13) +#define OTP_PRDT_BIT BIT(3) +#define OTP_READ_PORT_OFF 0x04 +#define OTP_READ_POINTER_OFF 0x08 +#define OTP_PTR_INC_BIT BIT(8) + +static void otp_read_parallel(void __iomem *base, u32 *data, u32 count) +{ + u32 regval; + + /* 1. Clear OTP_MODE_NB to parallel mode */ + regval = readl(base + OTP_CONTROL_OFF); + regval &= ~OTP_MODE_BIT; + writel(regval, base + OTP_CONTROL_OFF); + + /* 2. Set OTP_POR_B_NB enter normal operation */ + regval = readl(base + OTP_CONTROL_OFF); + regval |= OTP_POR_B_BIT; + writel(regval, base + OTP_CONTROL_OFF); + + /* 3. Set OTP_PTR_INC_NB to auto-increment pointer after each read */ + regval = readl(base + OTP_READ_POINTER_OFF); + regval |= OTP_PTR_INC_BIT; + writel(regval, base + OTP_READ_POINTER_OFF); + + /* 4. Set OTP_RPTR_RST_NB, then clear the same field */ + regval = readl(base + OTP_CONTROL_OFF); + regval |= OTP_RPTR_RST_BIT; + writel(regval, base + OTP_CONTROL_OFF); + + regval = readl(base + OTP_CONTROL_OFF); + regval &= ~OTP_RPTR_RST_BIT; + writel(regval, base + OTP_CONTROL_OFF); + + /* 5. Toggle OTP_PRDT_NB + * a. Set OTP_PRDT_NB to 1. + * b. Clear OTP_PRDT_NB to 0. + * c. Wait for a minimum of 100 ns. + * d. Set OTP_PRDT_NB to 1 + */ + regval = readl(base + OTP_CONTROL_OFF); + regval |= OTP_PRDT_BIT; + writel(regval, base + OTP_CONTROL_OFF); + + regval = readl(base + OTP_CONTROL_OFF); + regval &= ~OTP_PRDT_BIT; + writel(regval, base + OTP_CONTROL_OFF); + + ndelay(100); + + regval = readl(base + OTP_CONTROL_OFF); + regval |= OTP_PRDT_BIT; + writel(regval, base + OTP_CONTROL_OFF); + + while (count-- > 0) { + /* 6. Read the content of OTP 32-bits at a time */ + ndelay(100000); + *(data++) = readl(base + OTP_READ_PORT_OFF); + } +} + +/* + * Banks 0-43 are used for accessing Security OTP (44 rows with 67 bits via 44 banks and words 0-2) + * Bank 44 is used for accessing North Bridge OTP (69 bits via words 0-2) + * Bank 45 is used for accessing South Bridge OTP (97 bits via words 0-3) + */ + +#define RWTM_ROWS 44 +#define RWTM_MAX_BANK (RWTM_ROWS - 1) +#define RWTM_ROW_WORDS 3 +#define OTP_NB_BANK RWTM_ROWS +#define OTP_NB_WORDS 3 +#define OTP_SB_BANK (RWTM_ROWS + 1) +#define OTP_SB_WORDS 4 + +int fuse_read(u32 bank, u32 word, u32 *val) +{ + if (bank <= RWTM_MAX_BANK) { + if (word >= RWTM_ROW_WORDS) + return -EINVAL; + /* TODO: not implemented yet */ + return -ENOSYS; + } else if (bank == OTP_NB_BANK) { + u32 data[OTP_NB_WORDS]; + if (word >= OTP_NB_WORDS) + return -EINVAL; + otp_read_parallel(OTP_NB_REG_BASE, data, OTP_NB_WORDS); + *val = data[word]; + return 0; + } else if (bank == OTP_SB_BANK) { + u32 data[OTP_SB_WORDS]; + if (word >= OTP_SB_WORDS) + return -EINVAL; + otp_read_parallel(OTP_SB_REG_BASE, data, OTP_SB_WORDS); + *val = data[word]; + return 0; + } else { + return -EINVAL; + } +} + +int fuse_prog(u32 bank, u32 word, u32 val) +{ + /* TODO: not implemented yet */ + return -ENOSYS; +} + +int fuse_sense(u32 bank, u32 word, u32 *val) +{ + /* not supported */ + return -ENOSYS; +} + +int fuse_override(u32 bank, u32 word, u32 val) +{ + /* not supported */ + return -ENOSYS; +} -- cgit v1.1 From 122dae90844719d2bc5c64f602e840f7e2babad9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Wed, 23 Feb 2022 14:15:46 +0100 Subject: arm: mvebu: a37xx: Enable fuse command on all Armada 3720 boards MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Allow to read OTP bits via U-Boot fuse command on all Armada 3720 boards. Signed-off-by: Pali Rohár Reviewed-by: Marek Behún Reviewed-by: Stefan Roese --- configs/mvebu_db-88f3720_defconfig | 2 ++ configs/mvebu_espressobin-88f3720_defconfig | 2 ++ configs/turris_mox_defconfig | 2 ++ configs/uDPU_defconfig | 2 ++ 4 files changed, 8 insertions(+) diff --git a/configs/mvebu_db-88f3720_defconfig b/configs/mvebu_db-88f3720_defconfig index 2756b08..ff89115 100644 --- a/configs/mvebu_db-88f3720_defconfig +++ b/configs/mvebu_db-88f3720_defconfig @@ -4,6 +4,7 @@ CONFIG_ARCH_MVEBU=y CONFIG_SYS_TEXT_BASE=0x00000000 CONFIG_NR_DRAM_BANKS=1 CONFIG_TARGET_MVEBU_ARMADA_37XX=y +CONFIG_MVEBU_EFUSE=y CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0x3f0000 CONFIG_ENV_SECT_SIZE=0x10000 @@ -23,6 +24,7 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_ARCH_EARLY_INIT_R=y CONFIG_BOARD_EARLY_INIT_F=y # CONFIG_CMD_FLASH is not set +CONFIG_CMD_FUSE=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/mvebu_espressobin-88f3720_defconfig b/configs/mvebu_espressobin-88f3720_defconfig index 8fd9cbd..ff05630 100644 --- a/configs/mvebu_espressobin-88f3720_defconfig +++ b/configs/mvebu_espressobin-88f3720_defconfig @@ -4,6 +4,7 @@ CONFIG_ARCH_MVEBU=y CONFIG_SYS_TEXT_BASE=0x00000000 CONFIG_NR_DRAM_BANKS=1 CONFIG_TARGET_MVEBU_ARMADA_37XX=y +CONFIG_MVEBU_EFUSE=y CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0x3F0000 CONFIG_ENV_SECT_SIZE=0x10000 @@ -25,6 +26,7 @@ CONFIG_ARCH_EARLY_INIT_R=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_LATE_INIT=y # CONFIG_CMD_FLASH is not set +CONFIG_CMD_FUSE=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y diff --git a/configs/turris_mox_defconfig b/configs/turris_mox_defconfig index e8fc2c7..9a76a11 100644 --- a/configs/turris_mox_defconfig +++ b/configs/turris_mox_defconfig @@ -4,6 +4,7 @@ CONFIG_ARCH_MVEBU=y CONFIG_SYS_TEXT_BASE=0x00000000 CONFIG_NR_DRAM_BANKS=2 CONFIG_TARGET_TURRIS_MOX=y +CONFIG_MVEBU_EFUSE=y CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0x180000 CONFIG_ENV_SECT_SIZE=0x10000 @@ -30,6 +31,7 @@ CONFIG_MISC_INIT_R=y CONFIG_CMD_SHA1SUM=y CONFIG_CMD_CLK=y # CONFIG_CMD_FLASH is not set +CONFIG_CMD_FUSE=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y diff --git a/configs/uDPU_defconfig b/configs/uDPU_defconfig index dbc736e..43c4bdf 100644 --- a/configs/uDPU_defconfig +++ b/configs/uDPU_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_MVEBU=y CONFIG_SYS_TEXT_BASE=0x00000000 CONFIG_TARGET_MVEBU_ARMADA_37XX=y +CONFIG_MVEBU_EFUSE=y CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0x180000 CONFIG_ENV_SECT_SIZE=0x10000 @@ -28,6 +29,7 @@ CONFIG_SYS_PROMPT="uDPU>> " # CONFIG_CMD_IMI is not set # CONFIG_CMD_XIMG is not set # CONFIG_CMD_FLASH is not set +CONFIG_CMD_FUSE=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y -- cgit v1.1 From 46ce9c78a99814639763d8ea9ac1bf7354b6ea8d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Wed, 23 Feb 2022 14:15:47 +0100 Subject: arm: mvebu: a37xx: Move generic mbox code to arch/arm/mach-mvebu MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Generic A3720 mbox code is currently in Turris Mox specific board file board/CZ.NIC/turris_mox/mox_sp.c. Move it to board independent arch file arch/arm/mach-mvebu/armada3700/mbox.c. Signed-off-by: Pali Rohár Reviewed-by: Marek Behún Reviewed-by: Stefan Roese --- arch/arm/mach-mvebu/armada3700/Makefile | 2 +- arch/arm/mach-mvebu/armada3700/mbox.c | 67 ++++++++++++++++++++++++++++++++ arch/arm/mach-mvebu/include/mach/mbox.h | 23 +++++++++++ board/CZ.NIC/turris_mox/mox_sp.c | 69 +-------------------------------- 4 files changed, 92 insertions(+), 69 deletions(-) create mode 100644 arch/arm/mach-mvebu/armada3700/mbox.c create mode 100644 arch/arm/mach-mvebu/include/mach/mbox.h diff --git a/arch/arm/mach-mvebu/armada3700/Makefile b/arch/arm/mach-mvebu/armada3700/Makefile index cd74726..98350a4 100644 --- a/arch/arm/mach-mvebu/armada3700/Makefile +++ b/arch/arm/mach-mvebu/armada3700/Makefile @@ -2,5 +2,5 @@ # # Copyright (C) 2016 Stefan Roese -obj-y = cpu.o +obj-y = cpu.o mbox.o obj-$(CONFIG_MVEBU_EFUSE) += efuse.o diff --git a/arch/arm/mach-mvebu/armada3700/mbox.c b/arch/arm/mach-mvebu/armada3700/mbox.c new file mode 100644 index 0000000..cb86b96 --- /dev/null +++ b/arch/arm/mach-mvebu/armada3700/mbox.c @@ -0,0 +1,67 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Marek Behun + */ + +#include +#include +#include +#include +#include +#include + +#define RWTM_BASE (MVEBU_REGISTER(0xb0000)) +#define RWTM_CMD_PARAM(i) (size_t)(RWTM_BASE + (i) * 4) +#define RWTM_CMD (RWTM_BASE + 0x40) +#define RWTM_CMD_RETSTATUS (RWTM_BASE + 0x80) +#define RWTM_CMD_STATUS(i) (size_t)(RWTM_BASE + 0x84 + (i) * 4) + +#define RWTM_HOST_INT_RESET (RWTM_BASE + 0xc8) +#define RWTM_HOST_INT_MASK (RWTM_BASE + 0xcc) +#define SP_CMD_COMPLETE BIT(0) + +#define MBOX_STS_SUCCESS (0x0 << 30) +#define MBOX_STS_FAIL (0x1 << 30) +#define MBOX_STS_BADCMD (0x2 << 30) +#define MBOX_STS_LATER (0x3 << 30) +#define MBOX_STS_ERROR(s) ((s) & (3 << 30)) +#define MBOX_STS_VALUE(s) (((s) >> 10) & 0xfffff) +#define MBOX_STS_CMD(s) ((s) & 0x3ff) + +int mbox_do_cmd(enum mbox_cmd cmd, u32 *out, int nout) +{ + const int tries = 50; + int i; + u32 status; + + clrbits_le32(RWTM_HOST_INT_MASK, SP_CMD_COMPLETE); + + writel(cmd, RWTM_CMD); + + for (i = 0; i < tries; ++i) { + mdelay(10); + if (readl(RWTM_HOST_INT_RESET) & SP_CMD_COMPLETE) + break; + } + + if (i == tries) { + /* if timed out, don't read status */ + setbits_le32(RWTM_HOST_INT_RESET, SP_CMD_COMPLETE); + return -ETIMEDOUT; + } + + for (i = 0; i < nout; ++i) + out[i] = readl(RWTM_CMD_STATUS(i)); + status = readl(RWTM_CMD_RETSTATUS); + + setbits_le32(RWTM_HOST_INT_RESET, SP_CMD_COMPLETE); + + if (MBOX_STS_CMD(status) != cmd) + return -EIO; + else if (MBOX_STS_ERROR(status) == MBOX_STS_FAIL) + return -(int)MBOX_STS_VALUE(status); + else if (MBOX_STS_ERROR(status) != MBOX_STS_SUCCESS) + return -EIO; + else + return MBOX_STS_VALUE(status); +} diff --git a/arch/arm/mach-mvebu/include/mach/mbox.h b/arch/arm/mach-mvebu/include/mach/mbox.h new file mode 100644 index 0000000..9812049 --- /dev/null +++ b/arch/arm/mach-mvebu/include/mach/mbox.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2018 Marek Behun + */ + +#ifndef _MVEBU_MBOX_H +#define _MVEBU_MBOX_H + +enum mbox_cmd { + MBOX_CMD_GET_RANDOM = 1, + MBOX_CMD_BOARD_INFO, + MBOX_CMD_ECDSA_PUB_KEY, + MBOX_CMD_HASH, + MBOX_CMD_SIGN, + MBOX_CMD_VERIFY, + + MBOX_CMD_OTP_READ, + MBOX_CMD_OTP_WRITE, +}; + +int mbox_do_cmd(enum mbox_cmd cmd, u32 *in, int nout); + +#endif diff --git a/board/CZ.NIC/turris_mox/mox_sp.c b/board/CZ.NIC/turris_mox/mox_sp.c index cc57b9f..4de067b 100644 --- a/board/CZ.NIC/turris_mox/mox_sp.c +++ b/board/CZ.NIC/turris_mox/mox_sp.c @@ -8,74 +8,7 @@ #include #include #include - -#define RWTM_BASE (MVEBU_REGISTER(0xb0000)) -#define RWTM_CMD_PARAM(i) (size_t)(RWTM_BASE + (i) * 4) -#define RWTM_CMD (RWTM_BASE + 0x40) -#define RWTM_CMD_RETSTATUS (RWTM_BASE + 0x80) -#define RWTM_CMD_STATUS(i) (size_t)(RWTM_BASE + 0x84 + (i) * 4) - -#define RWTM_HOST_INT_RESET (RWTM_BASE + 0xc8) -#define RWTM_HOST_INT_MASK (RWTM_BASE + 0xcc) -#define SP_CMD_COMPLETE BIT(0) - -#define MBOX_STS_SUCCESS (0x0 << 30) -#define MBOX_STS_FAIL (0x1 << 30) -#define MBOX_STS_BADCMD (0x2 << 30) -#define MBOX_STS_LATER (0x3 << 30) -#define MBOX_STS_ERROR(s) ((s) & (3 << 30)) -#define MBOX_STS_VALUE(s) (((s) >> 10) & 0xfffff) -#define MBOX_STS_CMD(s) ((s) & 0x3ff) - -enum mbox_cmd { - MBOX_CMD_GET_RANDOM = 1, - MBOX_CMD_BOARD_INFO, - MBOX_CMD_ECDSA_PUB_KEY, - MBOX_CMD_HASH, - MBOX_CMD_SIGN, - MBOX_CMD_VERIFY, - - MBOX_CMD_OTP_READ, - MBOX_CMD_OTP_WRITE -}; - -static int mbox_do_cmd(enum mbox_cmd cmd, u32 *out, int nout) -{ - const int tries = 50; - int i; - u32 status; - - clrbits_le32(RWTM_HOST_INT_MASK, SP_CMD_COMPLETE); - - writel(cmd, RWTM_CMD); - - for (i = 0; i < tries; ++i) { - mdelay(10); - if (readl(RWTM_HOST_INT_RESET) & SP_CMD_COMPLETE) - break; - } - - if (i == tries) { - /* if timed out, don't read status */ - setbits_le32(RWTM_HOST_INT_RESET, SP_CMD_COMPLETE); - return -ETIMEDOUT; - } - - for (i = 0; i < nout; ++i) - out[i] = readl(RWTM_CMD_STATUS(i)); - status = readl(RWTM_CMD_RETSTATUS); - - setbits_le32(RWTM_HOST_INT_RESET, SP_CMD_COMPLETE); - - if (MBOX_STS_CMD(status) != cmd) - return -EIO; - else if (MBOX_STS_ERROR(status) == MBOX_STS_FAIL) - return -(int)MBOX_STS_VALUE(status); - else if (MBOX_STS_ERROR(status) != MBOX_STS_SUCCESS) - return -EIO; - else - return MBOX_STS_VALUE(status); -} +#include const char *mox_sp_get_ecdsa_public_key(void) { -- cgit v1.1 From 85df8f9a211610d4406e644061220b5e2fd221c7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Wed, 23 Feb 2022 14:15:48 +0100 Subject: arm: mvebu: a37xx: Extend mbox_do_cmd() code MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Allow to specify input parameters, define all available mbox commands supported by CZ.NIC's secure firmware and also Marvell's fuse.bin firmware and fix parsing response from Marvell OTP commands. Signed-off-by: Pali Rohár Reviewed-by: Marek Behún Reviewed-by: Stefan Roese --- arch/arm/mach-mvebu/armada3700/mbox.c | 20 ++++++++++++++++++-- arch/arm/mach-mvebu/include/mach/mbox.h | 19 ++++++++++++++++++- board/CZ.NIC/turris_mox/mox_sp.c | 4 ++-- 3 files changed, 38 insertions(+), 5 deletions(-) diff --git a/arch/arm/mach-mvebu/armada3700/mbox.c b/arch/arm/mach-mvebu/armada3700/mbox.c index cb86b96..eb1f828 100644 --- a/arch/arm/mach-mvebu/armada3700/mbox.c +++ b/arch/arm/mach-mvebu/armada3700/mbox.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2018 Marek Behun + * Copyright (C) 2021 Pali Rohár */ #include @@ -15,6 +16,7 @@ #define RWTM_CMD (RWTM_BASE + 0x40) #define RWTM_CMD_RETSTATUS (RWTM_BASE + 0x80) #define RWTM_CMD_STATUS(i) (size_t)(RWTM_BASE + 0x84 + (i) * 4) +#define MAX_ARGS 16 #define RWTM_HOST_INT_RESET (RWTM_BASE + 0xc8) #define RWTM_HOST_INT_MASK (RWTM_BASE + 0xcc) @@ -27,15 +29,27 @@ #define MBOX_STS_ERROR(s) ((s) & (3 << 30)) #define MBOX_STS_VALUE(s) (((s) >> 10) & 0xfffff) #define MBOX_STS_CMD(s) ((s) & 0x3ff) +#define MBOX_STS_MARVELL_ERROR(s) ((s) == 0 ? 0 : \ + (s) == 2 ? ETIMEDOUT : \ + (s) == 3 ? EINVAL : \ + (s) == 4 ? ENOSYS : \ + EIO) -int mbox_do_cmd(enum mbox_cmd cmd, u32 *out, int nout) +int mbox_do_cmd(enum mbox_cmd cmd, u32 *in, int nin, u32 *out, int nout) { const int tries = 50; int i; u32 status; + if (nin > MAX_ARGS || nout > MAX_ARGS) + return -EINVAL; + clrbits_le32(RWTM_HOST_INT_MASK, SP_CMD_COMPLETE); + for (i = 0; i < nin; i++) + writel(in[i], RWTM_CMD_PARAM(i)); + for (; i < MAX_ARGS; i++) + writel(0x0, RWTM_CMD_PARAM(i)); writel(cmd, RWTM_CMD); for (i = 0; i < tries; ++i) { @@ -57,9 +71,11 @@ int mbox_do_cmd(enum mbox_cmd cmd, u32 *out, int nout) setbits_le32(RWTM_HOST_INT_RESET, SP_CMD_COMPLETE); if (MBOX_STS_CMD(status) != cmd) - return -EIO; + return -MBOX_STS_MARVELL_ERROR(status); else if (MBOX_STS_ERROR(status) == MBOX_STS_FAIL) return -(int)MBOX_STS_VALUE(status); + else if (MBOX_STS_ERROR(status) == MBOX_STS_BADCMD) + return -ENOSYS; else if (MBOX_STS_ERROR(status) != MBOX_STS_SUCCESS) return -EIO; else diff --git a/arch/arm/mach-mvebu/include/mach/mbox.h b/arch/arm/mach-mvebu/include/mach/mbox.h index 9812049..f1cb55f 100644 --- a/arch/arm/mach-mvebu/include/mach/mbox.h +++ b/arch/arm/mach-mvebu/include/mach/mbox.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright (C) 2018 Marek Behun + * Copyright (C) 2021 Pali Rohár */ #ifndef _MVEBU_MBOX_H @@ -16,8 +17,24 @@ enum mbox_cmd { MBOX_CMD_OTP_READ, MBOX_CMD_OTP_WRITE, + + MBOX_CMD_REBOOT, + + /* OTP read commands supported by Marvell fuse.bin firmware */ + MBOX_CMD_OTP_READ_1B = 257, + MBOX_CMD_OTP_READ_8B, + MBOX_CMD_OTP_READ_32B, + MBOX_CMD_OTP_READ_64B, + MBOX_CMD_OTP_READ_256B, + + /* OTP write commands supported by Marvell fuse.bin firmware */ + MBOX_CMD_OTP_WRITE_1B = 513, + MBOX_CMD_OTP_WRITE_8B, + MBOX_CMD_OTP_WRITE_32B, + MBOX_CMD_OTP_WRITE_64B, + MBOX_CMD_OTP_WRITE_256B, }; -int mbox_do_cmd(enum mbox_cmd cmd, u32 *in, int nout); +int mbox_do_cmd(enum mbox_cmd cmd, u32 *in, int nin, u32 *out, int nout); #endif diff --git a/board/CZ.NIC/turris_mox/mox_sp.c b/board/CZ.NIC/turris_mox/mox_sp.c index 4de067b..93e96b0 100644 --- a/board/CZ.NIC/turris_mox/mox_sp.c +++ b/board/CZ.NIC/turris_mox/mox_sp.c @@ -19,7 +19,7 @@ const char *mox_sp_get_ecdsa_public_key(void) if (public_key[0]) return public_key; - res = mbox_do_cmd(MBOX_CMD_ECDSA_PUB_KEY, out, 16); + res = mbox_do_cmd(MBOX_CMD_ECDSA_PUB_KEY, NULL, 0, out, 16); if (res < 0) return NULL; @@ -47,7 +47,7 @@ int mbox_sp_get_board_info(u64 *sn, u8 *mac1, u8 *mac2, int *bv, int *ram) u32 out[8]; int res; - res = mbox_do_cmd(MBOX_CMD_BOARD_INFO, out, 8); + res = mbox_do_cmd(MBOX_CMD_BOARD_INFO, NULL, 0, out, 8); if (res < 0) return res; -- cgit v1.1 From c8b00da69504dae6b768c1fd46fbe63641f99dd1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Wed, 23 Feb 2022 14:15:49 +0100 Subject: arm: mvebu: a37xx: Add support for reading Security OTP values MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit It is not possible for the A53 core (on which U-Boot is running) to read it directly. For this purpose Marvell defined mbox API for sending OTP commands between CM3 and A53 cores. Implement these Marvell fuse reading mbox commands via U-Boot fuse API. Banks 0-43 are used for accessing Security OTP (44 rows with 67 bits via 44 banks and words 0-2). Note that of the 67 bits, the 3 upper bits are: 1 lock bit and 2 auxiliary bits (meant for testing during the manufacture of the SOC, as I understand it). Also note that the lock bit and the auxiliary bits are not readable via Marvell commands. With CZ.NIC's commands the lock bit is readable. Write support is not implemented yet. Signed-off-by: Pali Rohár Reviewed-by: Marek Behún Reviewed-by: Stefan Roese --- arch/arm/mach-mvebu/armada3700/efuse.c | 39 ++++++++++++++++++++++++++++++++-- 1 file changed, 37 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-mvebu/armada3700/efuse.c b/arch/arm/mach-mvebu/armada3700/efuse.c index 03778f1..50c73f3 100644 --- a/arch/arm/mach-mvebu/armada3700/efuse.c +++ b/arch/arm/mach-mvebu/armada3700/efuse.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #define OTP_NB_REG_BASE ((void __iomem *)MVEBU_REGISTER(0x12600)) @@ -77,6 +78,41 @@ static void otp_read_parallel(void __iomem *base, u32 *data, u32 count) } } +static int rwtm_otp_read(u8 row, u32 word, u32 *data) +{ + u32 out[3]; + u32 in[2]; + int res = -EINVAL; + + if (word < 2) { + /* + * MBOX_CMD_OTP_READ_32B command is supported by Marvell + * fuse.bin firmware and also by new CZ.NIC wtmi firmware. + * This command returns raw bits without ECC corrections. + * It does not provide access to the lock bit. + */ + in[0] = row; + in[1] = word * 32; + res = mbox_do_cmd(MBOX_CMD_OTP_READ_32B, in, 2, out, 1); + if (!res) + *data = out[0]; + } else if (word == 2) { + /* + * MBOX_CMD_OTP_READ command is supported only by new CZ.NIC + * wtmi firmware and provides access to all bits, including + * lock bit without doing ECC corrections. For compatibility + * with Marvell fuse.bin firmware, use this command only for + * accessing lock bit. + */ + in[0] = row; + res = mbox_do_cmd(MBOX_CMD_OTP_READ, in, 1, out, 3); + if (!res) + *data = out[2]; + } + + return res; +} + /* * Banks 0-43 are used for accessing Security OTP (44 rows with 67 bits via 44 banks and words 0-2) * Bank 44 is used for accessing North Bridge OTP (69 bits via words 0-2) @@ -96,8 +132,7 @@ int fuse_read(u32 bank, u32 word, u32 *val) if (bank <= RWTM_MAX_BANK) { if (word >= RWTM_ROW_WORDS) return -EINVAL; - /* TODO: not implemented yet */ - return -ENOSYS; + return rwtm_otp_read(bank, word, val); } else if (bank == OTP_NB_BANK) { u32 data[OTP_NB_WORDS]; if (word >= OTP_NB_WORDS) -- cgit v1.1 From 9b02de852578ffdfb363c657da08ba26e96582ac Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Thu, 24 Mar 2022 10:57:36 +0100 Subject: arm: mvebu: dts: uDPU: update DTS Update the uDPU DTS to the version that is pending upstream [1][2]. [1] https://patchwork.kernel.org/project/linux-arm-kernel/patch/20220322105857.1107016-1-robert.marko@sartura.hr/ [2] https://patchwork.kernel.org/project/linux-arm-kernel/patch/20220322105857.1107016-2-robert.marko@sartura.hr/ Signed-off-by: Robert Marko Reviewed-by: Stefan Roese --- arch/arm/dts/armada-3720-uDPU.dts | 21 +++++++++++++-------- 1 file changed, 13 insertions(+), 8 deletions(-) diff --git a/arch/arm/dts/armada-3720-uDPU.dts b/arch/arm/dts/armada-3720-uDPU.dts index 95d46e8..1f534c0 100644 --- a/arch/arm/dts/armada-3720-uDPU.dts +++ b/arch/arm/dts/armada-3720-uDPU.dts @@ -99,7 +99,7 @@ pinctrl-names = "default"; pinctrl-0 = <&spi_quad_pins>; - m25p80@0 { + spi-flash@0 { compatible = "jedec,spi-nor"; reg = <0>; spi-max-frequency = <54000000>; @@ -108,10 +108,15 @@ compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; - /* only bootloader is located on the SPI */ + partition@0 { - label = "uboot"; - reg = <0 0x400000>; + label = "firmware"; + reg = <0x0 0x180000>; + }; + + partition@180000 { + label = "u-boot-env"; + reg = <0x180000 0x10000>; }; }; }; @@ -148,15 +153,15 @@ scl-gpios = <&gpionb 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpionb 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - lm75@48 { + nct375@48 { status = "okay"; - compatible = "lm75"; + compatible = "ti,tmp75c"; reg = <0x48>; }; - lm75@49 { + nct375@49 { status = "okay"; - compatible = "lm75"; + compatible = "ti,tmp75c"; reg = <0x49>; }; }; -- cgit v1.1 From 2b7beb9c0950ff032ab504a3adcabddae7bb9a01 Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Thu, 24 Mar 2022 10:57:37 +0100 Subject: net: mvneta: add SFP TX disable handling MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add support for handling SFP TX disable for MVNETA in the same fashion as to what MVPP2 is doing in order to enable using SFP-s. This allows using ethernet on SFP only boards. Signed-off-by: Robert Marko Reviewed-by: Marek Behún Reviewed-by: Ramon Fried Reviewed-by: Stefan Roese --- drivers/net/mvneta.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/net/mvneta.c b/drivers/net/mvneta.c index e2ac4d8..15dc714 100644 --- a/drivers/net/mvneta.c +++ b/drivers/net/mvneta.c @@ -286,6 +286,7 @@ struct mvneta_port { struct phy_device *phydev; #if CONFIG_IS_ENABLED(DM_GPIO) struct gpio_desc phy_reset_gpio; + struct gpio_desc sfp_tx_disable_gpio; #endif struct mii_dev *bus; }; @@ -1693,6 +1694,9 @@ static int mvneta_probe(struct udevice *dev) { struct eth_pdata *pdata = dev_get_plat(dev); struct mvneta_port *pp = dev_get_priv(dev); +#if CONFIG_IS_ENABLED(DM_GPIO) + struct ofnode_phandle_args sfp_args; +#endif void *blob = (void *)gd->fdt_blob; int node = dev_of_offset(dev); struct mii_dev *bus; @@ -1767,6 +1771,11 @@ static int mvneta_probe(struct udevice *dev) return ret; #if CONFIG_IS_ENABLED(DM_GPIO) + ret = dev_read_phandle_with_args(dev, "sfp", NULL, 0, 0, &sfp_args); + if (!ret && ofnode_is_enabled(sfp_args.node)) + gpio_request_by_name_nodev(sfp_args.node, "tx-disable-gpio", 0, + &pp->sfp_tx_disable_gpio, GPIOD_IS_OUT); + gpio_request_by_name(dev, "phy-reset-gpios", 0, &pp->phy_reset_gpio, GPIOD_IS_OUT); @@ -1775,6 +1784,9 @@ static int mvneta_probe(struct udevice *dev) mdelay(10); dm_gpio_set_value(&pp->phy_reset_gpio, 0); } + + if (dm_gpio_is_valid(&pp->sfp_tx_disable_gpio)) + dm_gpio_set_value(&pp->sfp_tx_disable_gpio, 0); #endif return board_network_enable(bus); -- cgit v1.1 From 9e778c7ffc3184bd538f2ff73d395df608d907e5 Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Thu, 24 Mar 2022 10:57:38 +0100 Subject: arm: mvebu: dts: uDPU: fix non-working networking uDPU is a bit of a specific device in that it does not have any copper ports nor any ethernet PHY-s but 2 SFP ports. This is an issue since MVNETA requires a PHY phandle or a fixed-link to be defined under its node. Since U-boot has no SFP support this is reasonable in order to know how to configure the MAC. However this also means that networking does not work on uDPU at all currently, and fails with: uDPU>> dhcp Could not get PHY for neta@30000: addr 0 phy_connect failed Could not get PHY for neta@40000: addr 1 phy_connect failed So, to provide working networking using only SFP-s let add the fixed-link at 1G which is much more common than 2.5G SFP-s as well as disable the TX_DISABLE pins like done on Armada 7040 and 8040 platforms. Since uDPU is not using any of the GPIO-s on the SB controller for any purpose other than GPIO, a call to the pinctrl must be made in order for it to get probed and thus register the SB GPIO bank, otherwise SB GPIO-s are not registered at all. Signed-off-by: Robert Marko Reviewed-by: Stefan Roese --- arch/arm/dts/armada-3720-uDPU-u-boot.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm/dts/armada-3720-uDPU-u-boot.dtsi b/arch/arm/dts/armada-3720-uDPU-u-boot.dtsi index cf8ae44..47d87d4 100644 --- a/arch/arm/dts/armada-3720-uDPU-u-boot.dtsi +++ b/arch/arm/dts/armada-3720-uDPU-u-boot.dtsi @@ -31,3 +31,27 @@ &sdhci0 { u-boot,dm-pre-reloc; }; + +&pinctrl_sb { + sfp_pin: sfp-pin { + groups = "pcie1_clkreq"; + function = "gpio"; + }; +}; + +ð0 { + pinctrl-names = "default"; + pinctrl-0 = <&sfp_pin>; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +ð1 { + fixed-link { + speed = <1000>; + full-duplex; + }; +}; -- cgit v1.1 From 7001ea3ec408cbc801fc21054927ca1f4840ff79 Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Thu, 24 Mar 2022 10:57:39 +0100 Subject: mvebu: uDPU: update defconfig Update the current uDPU defconfig with following changes: * Disable CONFIG_SPI_BOOT, its not needed for booting and the device boots from eMMC anyway. * Disable CONFIG_SYS_CONSOLE_INFO_QUIET, there is no need to diverge from other boards by not priting the console device * Enable CONFIG_CMD_MTD in order to allow use of the MTD tool * Disable CONFIG_CMD_MTDPARTS, with MTD now being able to parse partitions from DTS there is no need for it, the default MTDPARTS were incorrect anyway * Enable CONFIG_MMC_HS200_SUPPORT, the eMMC used support both HS200 and HS400 modes, so enable at least HS200 because Xenon driver does not support HS400 currently * Replace CONFIG_SPI_FLASH_BAR with CONFIG_SPI_FLASH_SFDP_SUPPORT Utilize SFDP parsing instead of relying on the extended address registers Signed-off-by: Robert Marko Reviewed-by: Stefan Roese --- configs/uDPU_defconfig | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/configs/uDPU_defconfig b/configs/uDPU_defconfig index 43c4bdf..c07bad5 100644 --- a/configs/uDPU_defconfig +++ b/configs/uDPU_defconfig @@ -16,9 +16,8 @@ CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_FIT=y -CONFIG_SPI_BOOT=y +CONFIG_FIT_VERBOSE=y CONFIG_USE_PREBOOT=y -CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y @@ -33,6 +32,7 @@ CONFIG_CMD_FUSE=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y CONFIG_CMD_PCI=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y @@ -42,9 +42,6 @@ CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y CONFIG_CMD_MVEBU_BUBT=y CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nor0=spi0" -CONFIG_MTDPARTS_DEFAULT="mtdparts=spi0:4m(uboot),-(rootfs)" CONFIG_MAC_PARTITION=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y @@ -59,12 +56,13 @@ CONFIG_DM_I2C=y CONFIG_DM_I2C_GPIO=y CONFIG_SYS_I2C_MV=y CONFIG_MISC=y +CONFIG_MMC_HS200_SUPPORT=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_XENON=y CONFIG_MTD=y CONFIG_DM_MTD=y -CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_SFDP_SUPPORT=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y -- cgit v1.1 From 8b3d7ecdfec30d63684d86bd76632929b72d8a84 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Wed, 6 Apr 2022 14:18:18 +0200 Subject: arm: mvebu: Add support for reading LD0 and LD1 eFuse MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Armada 385 contains 64 lines of HD eFuse and 2 lines of LD eFuse. HD eFuse is used for secure boot and each line is 64 bits long + 1 lock bit. LD eFuse lines are 256 bits long + 1 lock bit. LD 0 line is reserved for Marvell Internal Use and LD 1 line is for General Purpose Data. U-Boot already contains HD eFuse reading and programming support. This patch implements LD eFuse reading support. LD 0 line is mapped to U-Boot fuse bank 64 and LD 1 line to fuse bank 65. LD 0 Marvell Internal Use line seems that was burned in factory with some data and can be read by U-Boot fuse command: => fuse read 64 0 9 LD 1 General Purpose Data line is by default empty and can be read by U-Boot fuse command: => fuse read 65 0 9 Signed-off-by: Pali Rohár Reviewed-by: Marek Behún --- arch/arm/mach-mvebu/efuse.c | 28 ++++++++++++++++++++++++++++ arch/arm/mach-mvebu/include/mach/efuse.h | 5 +++++ 2 files changed, 33 insertions(+) diff --git a/arch/arm/mach-mvebu/efuse.c b/arch/arm/mach-mvebu/efuse.c index c79eee9..80318c3 100644 --- a/arch/arm/mach-mvebu/efuse.c +++ b/arch/arm/mach-mvebu/efuse.c @@ -27,6 +27,7 @@ enum { MVEBU_EFUSE_CTRL_PROGRAM_ENABLE = (1 << 31), + MVEBU_EFUSE_LD1_SELECT = (1 << 6), }; struct mvebu_hd_efuse { @@ -39,8 +40,10 @@ struct mvebu_hd_efuse { #ifndef DRY_RUN static struct mvebu_hd_efuse *efuses = (struct mvebu_hd_efuse *)(MBUS_EFUSE_BASE + 0xF9000); +static u32 *ld_efuses = (void *)MBUS_EFUSE_BASE + 0xF8F00; #else static struct mvebu_hd_efuse efuses[EFUSE_LINE_MAX + 1]; +static u32 ld_efuses[EFUSE_LD_WORDS]; #endif static int efuse_initialised; @@ -169,6 +172,21 @@ int mvebu_read_efuse(int nr, struct efuse_val *val) return 0; } +void mvebu_read_ld_efuse(int ld1, u32 *line) +{ + int i; + +#ifndef DRY_RUN + if (ld1) + setbits_le32(MVEBU_EFUSE_CONTROL, MVEBU_EFUSE_LD1_SELECT); + else + clrbits_le32(MVEBU_EFUSE_CONTROL, MVEBU_EFUSE_LD1_SELECT); +#endif + + for (i = 0; i < EFUSE_LD_WORDS; i++) + line[i] = readl(ld_efuses + i); +} + int mvebu_write_efuse(int nr, struct efuse_val *val) { return prog_efuse(nr, val, ~0, ~0); @@ -199,8 +217,18 @@ static int valid_prog_words; int fuse_read(u32 bank, u32 word, u32 *val) { struct efuse_val fuse_line; + u32 ld_line[EFUSE_LD_WORDS]; int res; + if ((bank == EFUSE_LD0_LINE || bank == EFUSE_LD1_LINE) && word < EFUSE_LD_WORDS) { + res = mvebu_efuse_init_hw(); + if (res) + return res; + mvebu_read_ld_efuse(bank == EFUSE_LD1_LINE, ld_line); + *val = ld_line[word]; + return 0; + } + if (bank < EFUSE_LINE_MIN || bank > EFUSE_LINE_MAX || word > 2) return -EINVAL; diff --git a/arch/arm/mach-mvebu/include/mach/efuse.h b/arch/arm/mach-mvebu/include/mach/efuse.h index bbc5844..122e735 100644 --- a/arch/arm/mach-mvebu/include/mach/efuse.h +++ b/arch/arm/mach-mvebu/include/mach/efuse.h @@ -53,8 +53,13 @@ enum efuse_line { EFUSE_LINE_MIN = 0, EFUSE_LINE_MAX = 63, + + EFUSE_LD0_LINE = 64, + EFUSE_LD1_LINE = 65, }; +#define EFUSE_LD_WORDS 9 + #endif int mvebu_efuse_init_hw(void); -- cgit v1.1 From a339d6c464dd9e2c952bbdc5baa450149da9d6a3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Wed, 6 Apr 2022 15:18:59 +0200 Subject: tools: kwboot: Replace fstat()+st_size by lseek()+SEEK_END MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit fstat()'s st_size works only for regular files. lseek() with SEEK_END works also for block or MTD devices. This replacement allows kwboot to load kwbimage from /dev/mtd0 for booting another device over /dev/ttyS0. Signed-off-by: Pali Rohár Reviewed-by: Marek Behún --- tools/kwboot.c | 19 +++++++++++-------- 1 file changed, 11 insertions(+), 8 deletions(-) diff --git a/tools/kwboot.c b/tools/kwboot.c index 9f2dd2d..b697d3b 100644 --- a/tools/kwboot.c +++ b/tools/kwboot.c @@ -1591,8 +1591,8 @@ static void * kwboot_read_image(const char *path, size_t *size, size_t reserve) { int rc, fd; - struct stat st; void *img; + off_t len; off_t tot; rc = -1; @@ -1602,31 +1602,34 @@ kwboot_read_image(const char *path, size_t *size, size_t reserve) if (fd < 0) goto out; - rc = fstat(fd, &st); - if (rc) + len = lseek(fd, 0, SEEK_END); + if (len == (off_t)-1) + goto out; + + if (lseek(fd, 0, SEEK_SET) == (off_t)-1) goto out; - img = malloc(st.st_size + reserve); + img = malloc(len + reserve); if (!img) goto out; tot = 0; - while (tot < st.st_size) { - ssize_t rd = read(fd, img + tot, st.st_size - tot); + while (tot < len) { + ssize_t rd = read(fd, img + tot, len - tot); if (rd < 0) goto out; tot += rd; - if (!rd && tot < st.st_size) { + if (!rd && tot < len) { errno = EIO; goto out; } } rc = 0; - *size = st.st_size; + *size = len; out: if (rc && img) { free(img); -- cgit v1.1 From 372779abc3efe869aaa3c61c4bf6e2fcbaa46b57 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Wed, 6 Apr 2022 16:20:18 +0200 Subject: arm: Introduce new CONFIG_SPL_SYS_NO_VECTOR_TABLE option MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Move OMAP4 specific option for disabling overwriting vector table into config option CONFIG_SPL_SYS_NO_VECTOR_TABLE. Signed-off-by: Pali Rohár --- arch/arm/Kconfig | 4 ++++ arch/arm/cpu/armv7/start.S | 4 +--- arch/arm/mach-omap2/Kconfig | 1 + 3 files changed, 6 insertions(+), 3 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index efe33a5..10726ea 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -57,6 +57,10 @@ config SYS_INIT_SP_BSS_OFFSET that the early malloc region, global data (gd), and early stack usage do not overlap any appended DTB. +config SPL_SYS_NO_VECTOR_TABLE + depends on SPL + bool + config LINUX_KERNEL_IMAGE_HEADER depends on ARM64 bool diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index af87a54..3703612 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -97,12 +97,10 @@ switch_to_hypervisor_ret: orr r0, r0, #0xc0 @ disable FIQ and IRQ msr cpsr,r0 +#if !CONFIG_IS_ENABLED(SYS_NO_VECTOR_TABLE) /* * Setup vector: - * (OMAP4 spl TEXT_BASE is not 32 byte aligned. - * Continue to use ROM code vector only in OMAP4 spl) */ -#if !(defined(CONFIG_OMAP44XX) && defined(CONFIG_SPL_BUILD)) /* Set V=0 in CP15 SCTLR register - for VBAR to point to vector */ mrc p15, 0, r0, c1, c0, 0 @ Read CP15 SCTLR Register bic r0, #CR_V @ V = 0 diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index 2631426..e1b9180 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -32,6 +32,7 @@ config OMAP34XX config OMAP44XX bool "OMAP44XX SoC" select SPL_USE_TINY_PRINTF + select SPL_SYS_NO_VECTOR_TABLE if SPL imply NAND_OMAP_ELM imply NAND_OMAP_GPMC imply SPL_DISPLAY_PRINT -- cgit v1.1 From 5165d2a04a777a9b636d6a3fe6d23f9c5086ff62 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Wed, 6 Apr 2022 16:20:19 +0200 Subject: arm: Do not compile vector table when SYS_NO_VECTOR_TABLE is enabled MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Vector table is not used when SYS_NO_VECTOR_TABLE is enabled. So do not compile it and reduce image size. Signed-off-by: Pali Rohár --- arch/arm/lib/vectors.S | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/lib/vectors.S b/arch/arm/lib/vectors.S index 56f3681..a54c84b 100644 --- a/arch/arm/lib/vectors.S +++ b/arch/arm/lib/vectors.S @@ -24,6 +24,7 @@ #else b reset #endif +#if !CONFIG_IS_ENABLED(SYS_NO_VECTOR_TABLE) ldr pc, _undefined_instruction ldr pc, _software_interrupt ldr pc, _prefetch_abort @@ -31,6 +32,7 @@ ldr pc, _not_used ldr pc, _irq ldr pc, _fiq +#endif .endm @@ -87,6 +89,7 @@ _start: ARM_VECTORS #endif /* !defined(CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK) */ +#if !CONFIG_IS_ENABLED(SYS_NO_VECTOR_TABLE) /* ************************************************************************* * @@ -118,6 +121,7 @@ _irq: .word irq _fiq: .word fiq .balignl 16,0xdeadbeef +#endif /* ************************************************************************* @@ -131,6 +135,7 @@ _fiq: .word fiq #ifdef CONFIG_SPL_BUILD +#if !CONFIG_IS_ENABLED(SYS_NO_VECTOR_TABLE) .align 5 undefined_instruction: software_interrupt: @@ -141,6 +146,7 @@ irq: fiq: 1: b 1b /* hang and never return */ +#endif #else /* !CONFIG_SPL_BUILD */ -- cgit v1.1 From 2975bba6dfdd3c190a473686765e9a936938c394 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Wed, 6 Apr 2022 16:20:20 +0200 Subject: arm: mvebu: Enable CONFIG_SPL_SYS_NO_VECTOR_TABLE for 32-bit mvebu MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit U-Boot SPL is on 32-bit mvebu executed by the BootROM. And BootROM expects that U-Boot SPL returns execution back to the BootROM. Vectors during execution of U-Boot SPL should not be changed as BootROM does not expect it and uses its own vectors. So do not overwrite vectors in SPL build. Signed-off-by: Pali Rohár --- arch/arm/mach-mvebu/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig index ccdb624..a3f273f 100644 --- a/arch/arm/mach-mvebu/Kconfig +++ b/arch/arm/mach-mvebu/Kconfig @@ -15,6 +15,7 @@ config ARMADA_32BIT select SPL_SIMPLE_BUS if SPL select SUPPORT_SPL select TRANSLATION_OFFSET + select SPL_SYS_NO_VECTOR_TABLE if SPL config ARMADA_64BIT bool -- cgit v1.1 From 1d71bbca45b03eb5ba6cabbb2859047b8cb80229 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Thu, 7 Apr 2022 11:32:10 +0200 Subject: arm: mvebu: a37xx: Add support for writing Security OTP values MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Implement write support for Security OTP values via mailbox API commands MBOX_CMD_OTP_WRITE_32B and MBOX_CMD_OTP_WRITE. Write support for North and South Bridge OTPs are not implemented as these OTPs are already burned in factory with some data. Signed-off-by: Pali Rohár Reviewed-by: Marek Behún --- arch/arm/mach-mvebu/armada3700/efuse.c | 50 ++++++++++++++++++++++++++++++++-- 1 file changed, 48 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-mvebu/armada3700/efuse.c b/arch/arm/mach-mvebu/armada3700/efuse.c index 50c73f3..07d5f39 100644 --- a/arch/arm/mach-mvebu/armada3700/efuse.c +++ b/arch/arm/mach-mvebu/armada3700/efuse.c @@ -113,6 +113,41 @@ static int rwtm_otp_read(u8 row, u32 word, u32 *data) return res; } +static int rwtm_otp_write(u8 row, u32 word, u32 data) +{ + u32 in[4]; + int res = -EINVAL; + + if (word < 2) { + /* + * MBOX_CMD_OTP_WRITE_32B command is supported by Marvell + * fuse.bin firmware and also by new CZ.NIC wtmi firmware. + * This command writes only selected bits to OTP and does + * not calculate ECC bits. It does not allow to write the + * lock bit. + */ + in[0] = row; + in[1] = word * 32; + in[2] = data; + res = mbox_do_cmd(MBOX_CMD_OTP_WRITE_32B, in, 3, NULL, 0); + } else if (word == 2 && !(data & ~0x1)) { + /* + * MBOX_CMD_OTP_WRITE command is supported only by new CZ.NIC + * wtmi firmware and allows to write any bit to OTP, including + * the lock bit. It does not calculate or write ECC bits too. + * For compatibility with Marvell fuse.bin firmware, use this + * command only for writing the lock bit. + */ + in[0] = row; + in[1] = 0; + in[2] = 0; + in[3] = data; + res = mbox_do_cmd(MBOX_CMD_OTP_WRITE, in, 4, NULL, 0); + } + + return res; +} + /* * Banks 0-43 are used for accessing Security OTP (44 rows with 67 bits via 44 banks and words 0-2) * Bank 44 is used for accessing North Bridge OTP (69 bits via words 0-2) @@ -154,8 +189,19 @@ int fuse_read(u32 bank, u32 word, u32 *val) int fuse_prog(u32 bank, u32 word, u32 val) { - /* TODO: not implemented yet */ - return -ENOSYS; + if (bank <= RWTM_MAX_BANK) { + if (word >= RWTM_ROW_WORDS) + return -EINVAL; + return rwtm_otp_write(bank, word, val); + } else if (bank == OTP_NB_BANK) { + /* TODO: not implemented yet */ + return -ENOSYS; + } else if (bank == OTP_SB_BANK) { + /* TODO: not implemented yet */ + return -ENOSYS; + } else { + return -EINVAL; + } } int fuse_sense(u32 bank, u32 word, u32 *val) -- cgit v1.1 From 6ac08dc1a83d786d8749525df32c94b94bb36123 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Fri, 8 Apr 2022 16:30:12 +0200 Subject: board: turris: Move Turris Atsha OTP code to separate file MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit OTP code is not Atsha generic but also it is not Omnia specific. It is common for all Turris routers which use Atsha cryptochip for storing OTP. So move this common Turris specific Atsha OTP code from Turris Omnia into separate file. It will be used also by other Turris routers. Signed-off-by: Pali Rohár Reviewed-by: Marek Behún --- board/CZ.NIC/turris_atsha_otp.c | 121 +++++++++++++++++++++++++++++++ board/CZ.NIC/turris_atsha_otp.h | 9 +++ board/CZ.NIC/turris_omnia/Makefile | 2 +- board/CZ.NIC/turris_omnia/turris_omnia.c | 108 +-------------------------- 4 files changed, 135 insertions(+), 105 deletions(-) create mode 100644 board/CZ.NIC/turris_atsha_otp.c create mode 100644 board/CZ.NIC/turris_atsha_otp.h diff --git a/board/CZ.NIC/turris_atsha_otp.c b/board/CZ.NIC/turris_atsha_otp.c new file mode 100644 index 0000000..a4a77c7 --- /dev/null +++ b/board/CZ.NIC/turris_atsha_otp.c @@ -0,0 +1,121 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2017 Marek Behun + * Copyright (C) 2016 Tomas Hlavacek + */ + +#include +#include +#include +#include + +#include "turris_atsha_otp.h" + +#define TURRIS_ATSHA_OTP_VERSION 0 +#define TURRIS_ATSHA_OTP_SERIAL 1 +#define TURRIS_ATSHA_OTP_MAC0 3 +#define TURRIS_ATSHA_OTP_MAC1 4 + +static struct udevice *get_atsha204a_dev(void) +{ + static struct udevice *dev; + + if (dev) + return dev; + + if (uclass_get_device_by_name(UCLASS_MISC, "atsha204a@64", &dev)) { + puts("Cannot find ATSHA204A on I2C bus!\n"); + dev = NULL; + } + + return dev; +} + +static void increment_mac(u8 *mac) +{ + int i; + + for (i = 5; i >= 3; i--) { + mac[i] += 1; + if (mac[i]) + break; + } +} + +static void set_mac_if_invalid(int i, u8 *mac) +{ + u8 oldmac[6]; + + if (is_valid_ethaddr(mac) && + !eth_env_get_enetaddr_by_index("eth", i, oldmac)) + eth_env_set_enetaddr_by_index("eth", i, mac); +} + +int turris_atsha_otp_init_mac_addresses(void) +{ + struct udevice *dev = get_atsha204a_dev(); + u8 mac0[4], mac1[4], mac[6]; + int ret; + + if (!dev) + return -1; + + ret = atsha204a_wakeup(dev); + if (ret) + return ret; + + ret = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false, + TURRIS_ATSHA_OTP_MAC0, mac0); + if (ret) + return ret; + + ret = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false, + TURRIS_ATSHA_OTP_MAC1, mac1); + if (ret) + return ret; + + atsha204a_sleep(dev); + + mac[0] = mac0[1]; + mac[1] = mac0[2]; + mac[2] = mac0[3]; + mac[3] = mac1[1]; + mac[4] = mac1[2]; + mac[5] = mac1[3]; + + set_mac_if_invalid(1, mac); + increment_mac(mac); + set_mac_if_invalid(2, mac); + increment_mac(mac); + set_mac_if_invalid(0, mac); + + return 0; +} + +int turris_atsha_otp_get_serial_number(u32 *version_num, u32 *serial_num) +{ + struct udevice *dev = get_atsha204a_dev(); + int ret; + + if (!dev) + return -1; + + ret = atsha204a_wakeup(dev); + if (ret) + return ret; + + ret = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false, + TURRIS_ATSHA_OTP_VERSION, + (u8 *)version_num); + if (ret) + return ret; + + ret = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false, + TURRIS_ATSHA_OTP_SERIAL, + (u8 *)serial_num); + if (ret) + return ret; + + atsha204a_sleep(dev); + return 0; +} diff --git a/board/CZ.NIC/turris_atsha_otp.h b/board/CZ.NIC/turris_atsha_otp.h new file mode 100644 index 0000000..667d01a --- /dev/null +++ b/board/CZ.NIC/turris_atsha_otp.h @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#ifndef TURRIS_ATSHA_OTP_H +#define TURRIS_ATSHA_OTP_H + +int turris_atsha_otp_init_mac_addresses(void); +int turris_atsha_otp_get_serial_number(u32 *version_num, u32 *serial_num); + +#endif diff --git a/board/CZ.NIC/turris_omnia/Makefile b/board/CZ.NIC/turris_omnia/Makefile index ccdf6c3..b79555a 100644 --- a/board/CZ.NIC/turris_omnia/Makefile +++ b/board/CZ.NIC/turris_omnia/Makefile @@ -2,4 +2,4 @@ # # Copyright (C) 2017 Marek Behun -obj-y := turris_omnia.o +obj-y := turris_omnia.o ../turris_atsha_otp.o diff --git a/board/CZ.NIC/turris_omnia/turris_omnia.c b/board/CZ.NIC/turris_omnia/turris_omnia.c index 33cec65..719e875 100644 --- a/board/CZ.NIC/turris_omnia/turris_omnia.c +++ b/board/CZ.NIC/turris_omnia/turris_omnia.c @@ -14,8 +14,6 @@ #include #include #include -#include -#include #include #include #include @@ -25,10 +23,10 @@ #include #include #include -# include #include "../drivers/ddr/marvell/a38x/ddr3_init.h" #include <../serdes/a38x/high_speed_env_spec.h> +#include "../turris_atsha_otp.h" DECLARE_GLOBAL_DATA_PTR; @@ -71,11 +69,6 @@ enum status_word_bits { MSATA_IND_STSBIT = 0x0020, }; -#define OMNIA_ATSHA204_OTP_VERSION 0 -#define OMNIA_ATSHA204_OTP_SERIAL 1 -#define OMNIA_ATSHA204_OTP_MAC0 3 -#define OMNIA_ATSHA204_OTP_MAC1 4 - /* * Those values and defines are taken from the Marvell U-Boot version * "u-boot-2013.01-2014_T3.0" @@ -594,49 +587,12 @@ int board_late_init(void) return 0; } -static struct udevice *get_atsha204a_dev(void) -{ - static struct udevice *dev; - - if (dev) - return dev; - - if (uclass_get_device_by_name(UCLASS_MISC, "atsha204a@64", &dev)) { - puts("Cannot find ATSHA204A on I2C bus!\n"); - dev = NULL; - } - - return dev; -} - int show_board_info(void) { u32 version_num, serial_num; - int err = 1; - - struct udevice *dev = get_atsha204a_dev(); - - if (dev) { - err = atsha204a_wakeup(dev); - if (err) - goto out; - - err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false, - OMNIA_ATSHA204_OTP_VERSION, - (u8 *)&version_num); - if (err) - goto out; - - err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false, - OMNIA_ATSHA204_OTP_SERIAL, - (u8 *)&serial_num); - if (err) - goto out; - - atsha204a_sleep(dev); - } + int err; -out: + err = turris_atsha_otp_get_serial_number(&version_num, &serial_num); printf("Model: Turris Omnia\n"); printf(" RAM size: %i MiB\n", omnia_get_ram_size_gb() * 1024); if (err) @@ -648,65 +604,9 @@ out: return 0; } -static void increment_mac(u8 *mac) -{ - int i; - - for (i = 5; i >= 3; i--) { - mac[i] += 1; - if (mac[i]) - break; - } -} - -static void set_mac_if_invalid(int i, u8 *mac) -{ - u8 oldmac[6]; - - if (is_valid_ethaddr(mac) && - !eth_env_get_enetaddr_by_index("eth", i, oldmac)) - eth_env_set_enetaddr_by_index("eth", i, mac); -} - int misc_init_r(void) { - int err; - struct udevice *dev = get_atsha204a_dev(); - u8 mac0[4], mac1[4], mac[6]; - - if (!dev) - goto out; - - err = atsha204a_wakeup(dev); - if (err) - goto out; - - err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false, - OMNIA_ATSHA204_OTP_MAC0, mac0); - if (err) - goto out; - - err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false, - OMNIA_ATSHA204_OTP_MAC1, mac1); - if (err) - goto out; - - atsha204a_sleep(dev); - - mac[0] = mac0[1]; - mac[1] = mac0[2]; - mac[2] = mac0[3]; - mac[3] = mac1[1]; - mac[4] = mac1[2]; - mac[5] = mac1[3]; - - set_mac_if_invalid(1, mac); - increment_mac(mac); - set_mac_if_invalid(2, mac); - increment_mac(mac); - set_mac_if_invalid(0, mac); - -out: + turris_atsha_otp_init_mac_addresses(); return 0; } -- cgit v1.1 From ada791db3eb13ad5ac0447c8c8b0343c4d771fb9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Fri, 8 Apr 2022 16:30:13 +0200 Subject: board: turris: Do not cache Atsha device in BSS MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Atsha device is used prior relocation and at this early stage BSS does not have to be ready yet. So do not cache Atsha device in BSS. Fixes support for other Turris routers. Signed-off-by: Pali Rohár Reviewed-by: Marek Behún --- board/CZ.NIC/turris_atsha_otp.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/board/CZ.NIC/turris_atsha_otp.c b/board/CZ.NIC/turris_atsha_otp.c index a4a77c7..840721a 100644 --- a/board/CZ.NIC/turris_atsha_otp.c +++ b/board/CZ.NIC/turris_atsha_otp.c @@ -18,10 +18,8 @@ static struct udevice *get_atsha204a_dev(void) { - static struct udevice *dev; - - if (dev) - return dev; + /* Cannot be static because BSS does not have to be ready at this early stage */ + struct udevice *dev; if (uclass_get_device_by_name(UCLASS_MISC, "atsha204a@64", &dev)) { puts("Cannot find ATSHA204A on I2C bus!\n"); -- cgit v1.1 From 98bbb6e7ab9b263a84c50a581c30089f9126c708 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Fri, 8 Apr 2022 16:30:14 +0200 Subject: board: turris: Allow to specify first eth idx of first MAC address MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Turris Omnia uses first MAC address from OTP for second ethernet interface. Second MAC address for third interface and third MAC address for first interface. Other Turris routers do not have this rotate by one mapping. So add function parameter for specifying id of the first ethernet interface. Signed-off-by: Pali Rohár Reviewed-by: Marek Behún --- board/CZ.NIC/turris_atsha_otp.c | 8 ++++---- board/CZ.NIC/turris_atsha_otp.h | 2 +- board/CZ.NIC/turris_omnia/turris_omnia.c | 2 +- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/board/CZ.NIC/turris_atsha_otp.c b/board/CZ.NIC/turris_atsha_otp.c index 840721a..7a39b7f 100644 --- a/board/CZ.NIC/turris_atsha_otp.c +++ b/board/CZ.NIC/turris_atsha_otp.c @@ -49,7 +49,7 @@ static void set_mac_if_invalid(int i, u8 *mac) eth_env_set_enetaddr_by_index("eth", i, mac); } -int turris_atsha_otp_init_mac_addresses(void) +int turris_atsha_otp_init_mac_addresses(int first_idx) { struct udevice *dev = get_atsha204a_dev(); u8 mac0[4], mac1[4], mac[6]; @@ -81,11 +81,11 @@ int turris_atsha_otp_init_mac_addresses(void) mac[4] = mac1[2]; mac[5] = mac1[3]; - set_mac_if_invalid(1, mac); + set_mac_if_invalid((first_idx + 0) % 3, mac); increment_mac(mac); - set_mac_if_invalid(2, mac); + set_mac_if_invalid((first_idx + 1) % 3, mac); increment_mac(mac); - set_mac_if_invalid(0, mac); + set_mac_if_invalid((first_idx + 2) % 3, mac); return 0; } diff --git a/board/CZ.NIC/turris_atsha_otp.h b/board/CZ.NIC/turris_atsha_otp.h index 667d01a..bd4308f 100644 --- a/board/CZ.NIC/turris_atsha_otp.h +++ b/board/CZ.NIC/turris_atsha_otp.h @@ -3,7 +3,7 @@ #ifndef TURRIS_ATSHA_OTP_H #define TURRIS_ATSHA_OTP_H -int turris_atsha_otp_init_mac_addresses(void); +int turris_atsha_otp_init_mac_addresses(int first_idx); int turris_atsha_otp_get_serial_number(u32 *version_num, u32 *serial_num); #endif diff --git a/board/CZ.NIC/turris_omnia/turris_omnia.c b/board/CZ.NIC/turris_omnia/turris_omnia.c index 719e875..da2fee5 100644 --- a/board/CZ.NIC/turris_omnia/turris_omnia.c +++ b/board/CZ.NIC/turris_omnia/turris_omnia.c @@ -606,7 +606,7 @@ int show_board_info(void) int misc_init_r(void) { - turris_atsha_otp_init_mac_addresses(); + turris_atsha_otp_init_mac_addresses(1); return 0; } -- cgit v1.1 From 08b99b67753a26ce142965151244261cdd73c490 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Fri, 8 Apr 2022 16:30:15 +0200 Subject: board: turris: Rename atsha204a@64 DT node to crypto@64 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit DT node name should be generic, therefore rename atsha204a@64 to crypto@64. Signed-off-by: Pali Rohár Reviewed-by: Marek Behún --- arch/arm/dts/armada-385-turris-omnia-u-boot.dtsi | 2 +- board/CZ.NIC/turris_atsha_otp.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/armada-385-turris-omnia-u-boot.dtsi b/arch/arm/dts/armada-385-turris-omnia-u-boot.dtsi index 008787e..64ebe2c 100644 --- a/arch/arm/dts/armada-385-turris-omnia-u-boot.dtsi +++ b/arch/arm/dts/armada-385-turris-omnia-u-boot.dtsi @@ -29,7 +29,7 @@ u-boot,dm-pre-reloc; /* ATSHA204A at address 0x64 */ - atsha204a@64 { + crypto@64 { u-boot,dm-pre-reloc; compatible = "atmel,atsha204a"; reg = <0x64>; diff --git a/board/CZ.NIC/turris_atsha_otp.c b/board/CZ.NIC/turris_atsha_otp.c index 7a39b7f..8c39f5e 100644 --- a/board/CZ.NIC/turris_atsha_otp.c +++ b/board/CZ.NIC/turris_atsha_otp.c @@ -21,7 +21,7 @@ static struct udevice *get_atsha204a_dev(void) /* Cannot be static because BSS does not have to be ready at this early stage */ struct udevice *dev; - if (uclass_get_device_by_name(UCLASS_MISC, "atsha204a@64", &dev)) { + if (uclass_get_device_by_name(UCLASS_MISC, "crypto@64", &dev)) { puts("Cannot find ATSHA204A on I2C bus!\n"); dev = NULL; } -- cgit v1.1 From 376a7d728ae268dfdd1c7f347d7cee9e54524b35 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Wed, 6 Apr 2022 15:26:35 +0200 Subject: arm: mvebu: turris_omnia: Enable CONFIG_CMD_FUSE MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This allows to read eFuse on Turris Omnia. Signed-off-by: Pali Rohár --- configs/turris_omnia_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/configs/turris_omnia_defconfig b/configs/turris_omnia_defconfig index a5e5298..ad56d38 100644 --- a/configs/turris_omnia_defconfig +++ b/configs/turris_omnia_defconfig @@ -9,6 +9,7 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=2 CONFIG_TARGET_TURRIS_OMNIA=y CONFIG_DDR_RESET_ON_TRAINING_FAILURE=y +CONFIG_MVEBU_EFUSE=y CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0xF0000 CONFIG_ENV_SECT_SIZE=0x10000 @@ -41,6 +42,7 @@ CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y CONFIG_CMD_SHA1SUM=y CONFIG_CMD_LZMADEC=y +CONFIG_CMD_FUSE=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y -- cgit v1.1 From ac47bd230cd3430589c63f81e57b3d30e0abe0db Mon Sep 17 00:00:00 2001 From: Tony Dinh Date: Sun, 17 Apr 2022 16:42:32 -0700 Subject: arm: kirkwood: Sheevaplug : Use Marvell uclass mvgbe and PHY driver for Ethernet The Globalscale Technologies Sheevaplug board has the network chip Marvell 88E1116R. Use uclass mvgbe and the compatible driver M88E1310 driver to bring up Ethernet. - Remove CONFIG_RESET_PHY_R symbol from all board files - Use uclass mvgbe to bring up the network. And remove ad-hoc code. - Enable CONFIG_PHY_MARVELL to properly configure the network. - Miscellaneous changes: Move constants to .c file and remove header file board/Marvell/sheevaplug/sheevaplug.h, use BIT macro, and add/cleanup comments. Signed-off-by: Tony Dinh --- board/Marvell/sheevaplug/sheevaplug.c | 83 ++++++----------------------------- board/Marvell/sheevaplug/sheevaplug.h | 24 ---------- configs/sheevaplug_defconfig | 4 +- include/configs/sheevaplug.h | 19 ++------ 4 files changed, 20 insertions(+), 110 deletions(-) delete mode 100644 board/Marvell/sheevaplug/sheevaplug.h diff --git a/board/Marvell/sheevaplug/sheevaplug.c b/board/Marvell/sheevaplug/sheevaplug.c index 5952d15..26ee39e 100644 --- a/board/Marvell/sheevaplug/sheevaplug.c +++ b/board/Marvell/sheevaplug/sheevaplug.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2021 Tony Dinh + * Copyright (C) 2021-2022 Tony Dinh * (C) Copyright 2009 * Marvell Semiconductor * Written-by: Prafulla Wadaskar @@ -8,17 +8,21 @@ #include #include -#include -#include +#include #include #include #include #include #include -#include "sheevaplug.h" +#include DECLARE_GLOBAL_DATA_PTR; +#define SHEEVAPLUG_OE_LOW (~(0)) +#define SHEEVAPLUG_OE_HIGH (~(0)) +#define SHEEVAPLUG_OE_VAL_LOW BIT(29) /* USB_PWEN low */ +#define SHEEVAPLUG_OE_VAL_HIGH BIT(17) /* LED pin high */ + int board_early_init_f(void) { /* @@ -88,6 +92,11 @@ int board_early_init_f(void) return 0; } +int board_eth_init(struct bd_info *bis) +{ + return cpu_eth_init(bis); +} + int board_init(void) { /* @@ -95,72 +104,8 @@ int board_init(void) */ gd->bd->bi_arch_number = MACH_TYPE_SHEEVAPLUG; - /* adress of boot parameters */ + /* address of boot parameters */ gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; return 0; } - -static int fdt_get_phy_addr(const char *path) -{ - const void *fdt = gd->fdt_blob; - const u32 *reg; - const u32 *val; - int node, phandle, addr; - - /* Find the node by its full path */ - node = fdt_path_offset(fdt, path); - if (node >= 0) { - /* Look up phy-handle */ - val = fdt_getprop(fdt, node, "phy-handle", NULL); - if (val) { - phandle = fdt32_to_cpu(*val); - if (!phandle) - return -1; - /* Follow it to its node */ - node = fdt_node_offset_by_phandle(fdt, phandle); - if (node) { - /* Look up reg */ - reg = fdt_getprop(fdt, node, "reg", NULL); - if (reg) { - addr = fdt32_to_cpu(*reg); - return addr; - } - } - } - } - return -1; -} - -#ifdef CONFIG_RESET_PHY_R -/* Configure and enable MV88E1116 PHY */ -void reset_phy(void) -{ - u16 reg; - int phyaddr; - char *name = "ethernet-controller@72000"; - char *eth0_path = "/ocp@f1000000/ethernet-controller@72000/ethernet0-port@0"; - - if (miiphy_set_current_dev(name)) - return; - - phyaddr = fdt_get_phy_addr(eth0_path); - if (phyaddr < 0) - return; - - /* - * Enable RGMII delay on Tx and Rx for CPU port - * Ref: sec 4.7.2 of chip datasheet - */ - miiphy_write(name, phyaddr, MV88E1116_PGADR_REG, 2); - miiphy_read(name, phyaddr, MV88E1116_MAC_CTRL_REG, ®); - reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL); - miiphy_write(name, phyaddr, MV88E1116_MAC_CTRL_REG, reg); - miiphy_write(name, phyaddr, MV88E1116_PGADR_REG, 0); - - /* reset the phy */ - miiphy_reset(name, phyaddr); - - printf("88E1116 Initialized on %s\n", name); -} -#endif /* CONFIG_RESET_PHY_R */ diff --git a/board/Marvell/sheevaplug/sheevaplug.h b/board/Marvell/sheevaplug/sheevaplug.h deleted file mode 100644 index e026c1b..0000000 --- a/board/Marvell/sheevaplug/sheevaplug.h +++ /dev/null @@ -1,24 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2009 - * Marvell Semiconductor - * Written-by: Prafulla Wadaskar - */ - -#ifndef __SHEEVAPLUG_H -#define __SHEEVAPLUG_H - -#define SHEEVAPLUG_OE_LOW (~(0)) -#define SHEEVAPLUG_OE_HIGH (~(0)) -#define SHEEVAPLUG_OE_VAL_LOW (1 << 29) /* USB_PWEN low */ -#define SHEEVAPLUG_OE_VAL_HIGH (1 << 17) /* LED pin high */ - -/* PHY related */ -#define MV88E1116_LED_FCTRL_REG 10 -#define MV88E1116_CPRSP_CR3_REG 21 -#define MV88E1116_MAC_CTRL_REG 21 -#define MV88E1116_PGADR_REG 22 -#define MV88E1116_RGMII_TXTM_CTRL (1 << 4) -#define MV88E1116_RGMII_RXTM_CTRL (1 << 5) - -#endif /* __SHEEVAPLUG_H */ diff --git a/configs/sheevaplug_defconfig b/configs/sheevaplug_defconfig index 0525bb4..0477cd7 100644 --- a/configs/sheevaplug_defconfig +++ b/configs/sheevaplug_defconfig @@ -21,7 +21,6 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="${x_bootcmd_kernel}; setenv bootargs ${x_bootargs} ${x_bootargs_root}; bootm 0x6400000;" CONFIG_USE_PREBOOT=y # CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_RESET_PHY_R=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_FLASH is not set @@ -29,13 +28,13 @@ CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y CONFIG_CMD_SATA=y CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y CONFIG_CMD_JFFS2=y CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nand0=orion_nand" @@ -54,6 +53,7 @@ CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_MVEBU_MMC=y CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y +CONFIG_PHY_MARVELL=y CONFIG_DM_ETH=y CONFIG_MVGBE=y CONFIG_MII=y diff --git a/include/configs/sheevaplug.h b/include/configs/sheevaplug.h index 0cc58c3..58345e4 100644 --- a/include/configs/sheevaplug.h +++ b/include/configs/sheevaplug.h @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* + * (C) Copyright 2022 Tony Dinh * (C) Copyright 2009-2014 * Gerald Kerma * Marvell Semiconductor @@ -14,17 +15,8 @@ /* * Environment variables configurations */ -/* - * max 4k env size is enough, but in case of nand - * it has to be rounded to sector size - */ - -/* - * Default environment variables - */ - #define CONFIG_EXTRA_ENV_SETTINGS "x_bootargs=console" \ - "=ttyS0,115200 mtdparts="CONFIG_MTDPARTS_DEFAULT \ + "=ttyS0,115200 mtdparts=" CONFIG_MTDPARTS_DEFAULT \ "x_bootcmd_kernel=nand read 0x6400000 0x100000 0x400000\0" \ "x_bootcmd_usb=usb start\0" \ "x_bootargs_root=root=/dev/mtdblock3 rw rootfstype=jffs2\0" @@ -32,16 +24,13 @@ /* * Ethernet Driver configuration */ -#ifdef CONFIG_CMD_NET #define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ #define CONFIG_PHY_BASE_ADR 0 -#endif /* CONFIG_CMD_NET */ /* - * SATA driver configuration + * Support large disk for SATA and USB */ -#ifdef CONFIG_SATA +#define CONFIG_SYS_64BIT_LBA #define CONFIG_LBA48 -#endif /* CONFIG_SATA */ #endif /* _CONFIG_SHEEVAPLUG_H */ -- cgit v1.1