From 8819892bdbcfe8797bb1ebf45806d9b5ebb86674 Mon Sep 17 00:00:00 2001 From: Algapally Santosh Sagar Date: Thu, 21 Sep 2023 16:50:42 +0530 Subject: configs: Add support in Kconfig and convert for armada boards Move the DEFAULT_ENV_IS_RW to Kconfig for easier configuration. Hence, add the CONFIG_DEFAULT_ENV_IS_RW config to the defconfig files to allow enabling them for armada boards. Signed-off-by: Algapally Santosh Sagar Signed-off-by: Venkatesh Yadav Abbarapu Reviewed-by: Simon Glass Link: https://lore.kernel.org/r/20230921112043.3144726-2-venkatesh.abbarapu@amd.com Signed-off-by: Michal Simek --- configs/eDPU_defconfig | 1 + configs/mvebu_db-88f3720_defconfig | 1 + configs/mvebu_espressobin-88f3720_defconfig | 1 + configs/uDPU_defconfig | 1 + drivers/serial/Kconfig | 6 ++++++ include/configs/mvebu_armada-37xx.h | 1 - include/env_default.h | 2 +- include/env_internal.h | 2 +- 8 files changed, 12 insertions(+), 3 deletions(-) diff --git a/configs/eDPU_defconfig b/configs/eDPU_defconfig index f51df78..aef75c7 100644 --- a/configs/eDPU_defconfig +++ b/configs/eDPU_defconfig @@ -20,6 +20,7 @@ CONFIG_DISTRO_DEFAULTS=y CONFIG_USE_PREBOOT=y # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_DEFAULT_ENV_IS_RW=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SYS_PROMPT="eDPU>> " diff --git a/configs/mvebu_db-88f3720_defconfig b/configs/mvebu_db-88f3720_defconfig index 8295670..e6fb801 100644 --- a/configs/mvebu_db-88f3720_defconfig +++ b/configs/mvebu_db-88f3720_defconfig @@ -22,6 +22,7 @@ CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_DEFAULT_ENV_IS_RW=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SYS_MAXARGS=32 diff --git a/configs/mvebu_espressobin-88f3720_defconfig b/configs/mvebu_espressobin-88f3720_defconfig index 6c68c23..8e79fc7 100644 --- a/configs/mvebu_espressobin-88f3720_defconfig +++ b/configs/mvebu_espressobin-88f3720_defconfig @@ -24,6 +24,7 @@ CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_DEFAULT_ENV_IS_RW=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_LATE_INIT=y diff --git a/configs/uDPU_defconfig b/configs/uDPU_defconfig index 988f9ed..6c48b33 100644 --- a/configs/uDPU_defconfig +++ b/configs/uDPU_defconfig @@ -20,6 +20,7 @@ CONFIG_DISTRO_DEFAULTS=y CONFIG_USE_PREBOOT=y # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_DEFAULT_ENV_IS_RW=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SYS_PROMPT="uDPU>> " diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 9f0f84c..8761a64 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -24,6 +24,12 @@ config BAUDRATE in the SPL stage (most drivers) or for choosing a default baudrate in the absence of an environment setting (serial_mxc.c). +config DEFAULT_ENV_IS_RW + bool "Make default environment as writable" + help + Select this to enable to make default environment writable. This + allows modifying the default environment. + config REQUIRE_SERIAL_CONSOLE bool "Require a serial port for console" # Running without a serial console is not supported by the diff --git a/include/configs/mvebu_armada-37xx.h b/include/configs/mvebu_armada-37xx.h index 76e148f..18b55be 100644 --- a/include/configs/mvebu_armada-37xx.h +++ b/include/configs/mvebu_armada-37xx.h @@ -30,7 +30,6 @@ /* * Environment */ -#define DEFAULT_ENV_IS_RW /* required for configuring default fdtfile= */ #ifdef CONFIG_MMC #define BOOT_TARGET_DEVICES_MMC(func, i) func(MMC, mmc, i) diff --git a/include/env_default.h b/include/env_default.h index b16c22d..227cad7 100644 --- a/include/env_default.h +++ b/include/env_default.h @@ -21,7 +21,7 @@ env_t embedded_environment __UBOOT_ENV_SECTION__(environment) = { { #elif defined(DEFAULT_ENV_INSTANCE_STATIC) static char default_environment[] = { -#elif defined(DEFAULT_ENV_IS_RW) +#elif defined(CONFIG_DEFAULT_ENV_IS_RW) char default_environment[] = { #else const char default_environment[] = { diff --git a/include/env_internal.h b/include/env_internal.h index 6a69494..fcb4642 100644 --- a/include/env_internal.h +++ b/include/env_internal.h @@ -89,7 +89,7 @@ typedef struct environment_s { extern env_t embedded_environment; #endif /* ENV_IS_EMBEDDED */ -#ifdef DEFAULT_ENV_IS_RW +#ifdef CONFIG_DEFAULT_ENV_IS_RW extern char default_environment[]; #else extern const char default_environment[]; -- cgit v1.1 From bd9ff681bdd1893d11ab8d4ea79a9f74d0fffdb7 Mon Sep 17 00:00:00 2001 From: Algapally Santosh Sagar Date: Thu, 21 Sep 2023 16:50:43 +0530 Subject: serial: zynqmp: Fetch baudrate from dtb and update The baudrate configured in .config is taken by default by serial. If change of baudrate is required then the .config needs to changed and u-boot recompilation is required or the u-boot environment needs to be updated. To avoid this, support is added to fetch the baudrate directly from the device tree file and update. The serial, prints the log with the configured baudrate in the dtb. The commit c4df0f6f315c ("arm: mvebu: Espressobin: Set default value for $fdtfile env variable") is taken as reference for changing the default environment variable. The default environment stores the default baudrate value, When default baudrate and dtb baudrate are not same glitches are seen on the serial. So, the environment also needs to be updated with the dtb baudrate to avoid the glitches on the serial. Also add test to cover this new function. Signed-off-by: Algapally Santosh Sagar Signed-off-by: Venkatesh Yadav Abbarapu Link: https://lore.kernel.org/r/20230921112043.3144726-3-venkatesh.abbarapu@amd.com Signed-off-by: Michal Simek --- arch/sandbox/dts/test.dts | 1 + doc/README.serial_dt_baud | 41 +++++++++++++++++++++++++++++++++++ drivers/core/ofnode.c | 18 ++++++++++++++++ drivers/serial/Kconfig | 9 ++++++++ drivers/serial/serial-uclass.c | 49 ++++++++++++++++++++++++++++++++++++++++++ include/dm/ofnode.h | 14 ++++++++++-- include/env_default.h | 6 +++++- include/serial.h | 7 ++++++ test/dm/serial.c | 1 + 9 files changed, 143 insertions(+), 3 deletions(-) create mode 100644 doc/README.serial_dt_baud diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts index 2887f6c..c719779 100644 --- a/arch/sandbox/dts/test.dts +++ b/arch/sandbox/dts/test.dts @@ -1572,6 +1572,7 @@ other-node = "/some-bus/c-test@5"; int-values = <0x1937 72993>; u-boot,acpi-ssdt-order = <&acpi_test2 &acpi_test1>; + stdout-path = "serial0:115200n8"; chosen-test { compatible = "denx,u-boot-fdt-test"; reg = <9 1>; diff --git a/doc/README.serial_dt_baud b/doc/README.serial_dt_baud new file mode 100644 index 0000000..f8768d0 --- /dev/null +++ b/doc/README.serial_dt_baud @@ -0,0 +1,41 @@ +Fetch serial baudrate from DT +----------------------------- + +To support fetching of baudrate from DT, the following is done:- + +The baudrate configured in Kconfig symbol CONFIG_BAUDRATE is taken by default by serial. +If change of baudrate is required then the Kconfig symbol CONFIG_BAUDRATE needs to +changed and U-Boot recompilation is required or the U-Boot environment needs to be updated. + +To avoid this, add support to fetch the baudrate directly from the device tree file and +update the environment. + +The default environment stores the default baudrate value. When default baudrate and dtb +baudrate are not same glitches are seen on the serial. +So, the environment also needs to be updated with the dtb baudrate to avoid the glitches on +the serial which is enabled by OF_SERIAL_BAUD. + +The Kconfig SPL_ENV_SUPPORT needs to be enabled to allow patching in SPL. + +The Kconfig DEFAULT_ENV_IS_RW which is enabled by OF_SERIAL_BAUD with making the environment +writable. + +The ofnode_read_baud() function parses and fetches the baudrate value from the DT. This value +is validated and updated to baudrate during serial init. Padding is added at the end of the +default environment and the dt baudrate is updated with the latest value. + +Example:- + +The serial port options are of the form "bbbbpnf", where "bbbb" is the baud rate, "p" is parity ("n", "o", or "e"), +"n" is number of bits, and "f" is flow control ("r" for RTS or omit it). Default is "115200n8". + +chosen { + bootargs = "earlycon console=ttyPS0,115200 clk_ignore_unused root=/dev/ram0 rw init_fatal_sh=1"; + stdout-path = "serial0:115200n8"; + }; + +From the chosen node, stdout-path property is obtained as string. + + stdout-path = "serial0:115200n8"; + +The string is parsed to get the baudrate 115200. This string is converted to integer and updated to the environment. diff --git a/drivers/core/ofnode.c b/drivers/core/ofnode.c index 29a4294..f72ea41 100644 --- a/drivers/core/ofnode.c +++ b/drivers/core/ofnode.c @@ -991,6 +991,24 @@ ofnode ofnode_get_chosen_node(const char *name) return ofnode_path(prop); } +int ofnode_read_baud(void) +{ + const char *str, *p; + u32 baud; + + str = ofnode_read_chosen_string("stdout-path"); + if (!str) + return -EINVAL; + + /* Parse string serial0:115200n8 */ + p = strchr(str, ':'); + if (!p) + return -EINVAL; + + baud = dectoul(p + 1, NULL); + return baud; +} + const void *ofnode_read_aliases_prop(const char *propname, int *sizep) { ofnode node; diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 8761a64..6628a88 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -24,6 +24,15 @@ config BAUDRATE in the SPL stage (most drivers) or for choosing a default baudrate in the absence of an environment setting (serial_mxc.c). +config OF_SERIAL_BAUD + bool "Fetch serial baudrate from device tree" + depends on DM_SERIAL && SPL_ENV_SUPPORT + select DEFAULT_ENV_IS_RW + help + Select this to enable fetching and setting of the baudrate + configured in the DT. Replace the default baudrate with the DT + baudrate and also set it to the environment. + config DEFAULT_ENV_IS_RW bool "Make default environment as writable" help diff --git a/drivers/serial/serial-uclass.c b/drivers/serial/serial-uclass.c index df6a387..e4fa393 100644 --- a/drivers/serial/serial-uclass.c +++ b/drivers/serial/serial-uclass.c @@ -155,12 +155,61 @@ static void serial_find_console_or_panic(void) } #endif /* CONFIG_SERIAL_PRESENT */ +/** + * check_valid_baudrate() - Check whether baudrate is valid or not + * + * @baud: baud rate to check + * Return: 0 if OK, -ve on error + */ +static int check_valid_baudrate(int baud) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(baudrate_table); ++i) { + if (baud == baudrate_table[i]) + return 0; + } + + return -EINVAL; +} + +int fetch_baud_from_dtb(void) +{ + int baud_value, ret; + + baud_value = ofnode_read_baud(); + ret = check_valid_baudrate(baud_value); + if (ret) + return ret; + + return baud_value; +} + /* Called prior to relocation */ int serial_init(void) { #if CONFIG_IS_ENABLED(SERIAL_PRESENT) serial_find_console_or_panic(); gd->flags |= GD_FLG_SERIAL_READY; + + if (IS_ENABLED(CONFIG_OF_SERIAL_BAUD)) { + int ret = 0; + char *ptr = (char*)&default_environment[0]; + + /* + * Fetch the baudrate from the dtb and update the value in the + * default environment. + */ + ret = fetch_baud_from_dtb(); + if (ret != -EINVAL && ret != -EFAULT) { + gd->baudrate = ret; + + while (*ptr != '\0' && *(ptr + 1) != '\0') + ptr++; + ptr += 2; + sprintf(ptr, "baudrate=%d", gd->baudrate); + } + } serial_setbrg(); #endif diff --git a/include/dm/ofnode.h b/include/dm/ofnode.h index 19e97a9..5795115 100644 --- a/include/dm/ofnode.h +++ b/include/dm/ofnode.h @@ -977,12 +977,22 @@ const char *ofnode_read_chosen_string(const char *propname); ofnode ofnode_get_chosen_node(const char *propname); /** - * ofnode_read_aliases_prop() - get the value of a aliases property + * ofnode_read_baud() - get the baudrate from string value of chosen property * - * This looks for a property within the /aliases node and returns its value + * This looks for stdout-path property within the /chosen node and parses its + * value to return baudrate. * * This only works with the control FDT. * + * Return: baudrate value if found, else -ve error code + */ +int ofnode_read_baud(void); + +/** + * ofnode_read_aliases_prop() - get the value of a aliases property + * + * This looks for a property within the /aliases node and returns its value + * * @propname: Property name to look for * @sizep: Returns size of property, or `FDT_ERR_...` error code if function * returns NULL diff --git a/include/env_default.h b/include/env_default.h index 227cad7..2ca4a08 100644 --- a/include/env_default.h +++ b/include/env_default.h @@ -42,7 +42,7 @@ const char default_environment[] = { #if defined(CONFIG_BOOTDELAY) "bootdelay=" __stringify(CONFIG_BOOTDELAY) "\0" #endif -#if defined(CONFIG_BAUDRATE) && (CONFIG_BAUDRATE >= 0) +#if !defined(CONFIG_OF_SERIAL_BAUD) && defined(CONFIG_BAUDRATE) && (CONFIG_BAUDRATE >= 0) "baudrate=" __stringify(CONFIG_BAUDRATE) "\0" #endif #ifdef CONFIG_LOADS_ECHO @@ -119,6 +119,10 @@ const char default_environment[] = { #ifdef CFG_EXTRA_ENV_SETTINGS CFG_EXTRA_ENV_SETTINGS #endif +#ifdef CONFIG_OF_SERIAL_BAUD + /* Padding for baudrate at the end when environment is writable */ + "\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0" +#endif "\0" #else /* CONFIG_USE_DEFAULT_ENV_FILE */ #include "generated/defaultenv_autogenerated.h" diff --git a/include/serial.h b/include/serial.h index 205889d..d129dc3 100644 --- a/include/serial.h +++ b/include/serial.h @@ -339,6 +339,13 @@ int serial_setconfig(struct udevice *dev, uint config); */ int serial_getinfo(struct udevice *dev, struct serial_device_info *info); +/** + * fetch_baud_from_dtb() - Fetch the baudrate value from DT + * + * Return: baudrate if OK, -ve on error + */ +int fetch_baud_from_dtb(void); + void atmel_serial_initialize(void); void mcf_serial_initialize(void); void mpc85xx_serial_initialize(void); diff --git a/test/dm/serial.c b/test/dm/serial.c index 37d17a6..34b783e 100644 --- a/test/dm/serial.c +++ b/test/dm/serial.c @@ -29,6 +29,7 @@ static int dm_test_serial(struct unit_test_state *uts) &dev_serial)); ut_assertok(serial_tstc()); + ut_asserteq(115200, fetch_baud_from_dtb()); /* * test with default config which is the only one supported by * sandbox_serial driver -- cgit v1.1 From 188c803d08c6f1744484de6663f7c5d31ef71cfe Mon Sep 17 00:00:00 2001 From: Venkatesh Yadav Abbarapu Date: Tue, 3 Oct 2023 08:47:13 +0530 Subject: mtd: spi-nor: Add spi flash lock config option Provide an explicit configuration option to disable default "lock" of any flash chip which supports locking. By disabling the lock config will save some amount of memory and also don't expose the lock functionality to the users i.e., via sf protect command. Signed-off-by: Venkatesh Yadav Abbarapu Link: https://lore.kernel.org/r/20231003031715.5343-2-venkatesh.abbarapu@amd.com Signed-off-by: Michal Simek --- cmd/sf.c | 4 +++- drivers/mtd/spi/Kconfig | 7 +++++++ drivers/mtd/spi/spi-nor-core.c | 8 +++++++- 3 files changed, 17 insertions(+), 2 deletions(-) diff --git a/cmd/sf.c b/cmd/sf.c index 30b2bd5..730996c 100644 --- a/cmd/sf.c +++ b/cmd/sf.c @@ -604,7 +604,7 @@ static int do_spi_flash(struct cmd_tbl *cmdtp, int flag, int argc, ret = do_spi_flash_read_write(argc, argv); else if (strcmp(cmd, "erase") == 0) ret = do_spi_flash_erase(argc, argv); - else if (strcmp(cmd, "protect") == 0) + else if (IS_ENABLED(CONFIG_SPI_FLASH_LOCK) && strcmp(cmd, "protect") == 0) ret = do_spi_protect(argc, argv); else if (IS_ENABLED(CONFIG_CMD_SF_TEST) && !strcmp(cmd, "test")) ret = do_spi_flash_test(argc, argv); @@ -629,8 +629,10 @@ U_BOOT_LONGHELP(sf, "sf update addr offset|partition len - erase and write `len' bytes from memory\n" " at `addr' to flash at `offset'\n" " or to start of mtd `partition'\n" +#ifdef CONFIG_SPI_FLASH_LOCK "sf protect lock/unlock sector len - protect/unprotect 'len' bytes starting\n" " at address 'sector'" +#endif #ifdef CONFIG_CMD_SF_TEST "\nsf test offset len - run a very basic destructive test" #endif diff --git a/drivers/mtd/spi/Kconfig b/drivers/mtd/spi/Kconfig index 2b2efc8..732b076 100644 --- a/drivers/mtd/spi/Kconfig +++ b/drivers/mtd/spi/Kconfig @@ -134,6 +134,13 @@ config SPI_FLASH_BAR Bank/Extended address registers are used to access the flash which has size > 16MiB in 3-byte addressing. +config SPI_FLASH_LOCK + bool "Enable the Locking feature" + default y + help + Enable the SPI flash lock support. By default this is set to y. + If you intend not to use the lock support you should say n here. + config SPI_FLASH_UNLOCK_ALL bool "Unlock the entire SPI flash on u-boot startup" default y diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index db20feb..9a1801b 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -1100,6 +1100,7 @@ static int spansion_erase_non_uniform(struct spi_nor *nor, u32 addr, } #endif +#if defined(CONFIG_SPI_FLASH_LOCK) #if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST) /* Write status register and ensure bits in mask match written values */ static int write_sr_and_check(struct spi_nor *nor, u8 status_new, u8 mask) @@ -1387,6 +1388,7 @@ static int stm_is_unlocked(struct spi_nor *nor, loff_t ofs, uint64_t len) return stm_is_unlocked_sr(nor, ofs, len, status); } #endif /* CONFIG_SPI_FLASH_STMICRO */ +#endif static const struct flash_info *spi_nor_read_id(struct spi_nor *nor) { @@ -1462,6 +1464,7 @@ read_err: return ret; } +#if defined(CONFIG_SPI_FLASH_LOCK) #ifdef CONFIG_SPI_FLASH_SST /* * sst26 flash series has its own block protection implementation: @@ -1730,6 +1733,8 @@ sst_write_err: return ret; } #endif +#endif + /* * Write an address range to the nor chip. Data must be written in * FLASH_PAGESIZE chunks. The address range may be any size provided @@ -4104,6 +4109,7 @@ int spi_nor_scan(struct spi_nor *nor) mtd->_read = spi_nor_read; mtd->_write = spi_nor_write; +#if defined(CONFIG_SPI_FLASH_LOCK) #if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST) /* NOR protection support for STmicro/Micron chips and similar */ if (JEDEC_MFR(info) == SNOR_MFR_ST || @@ -4127,7 +4133,7 @@ int spi_nor_scan(struct spi_nor *nor) nor->flash_is_unlocked = sst26_is_unlocked; } #endif - +#endif if (info->flags & USE_FSR) nor->flags |= SNOR_F_USE_FSR; if (info->flags & SPI_NOR_HAS_TB) -- cgit v1.1 From 534892c22c21976af3f17b3519bb9e115925d50e Mon Sep 17 00:00:00 2001 From: Venkatesh Yadav Abbarapu Date: Tue, 3 Oct 2023 08:47:14 +0530 Subject: arm64: versal: Disable the lock option for mini ospi and qspi As mini configs are required only for flashing the images, so disabling the lock config which will save nearly 6KB of memory. Signed-off-by: Venkatesh Yadav Abbarapu Link: https://lore.kernel.org/r/20231003031715.5343-3-venkatesh.abbarapu@amd.com Signed-off-by: Michal Simek --- configs/xilinx_versal_mini_ospi_defconfig | 1 + configs/xilinx_versal_mini_qspi_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/configs/xilinx_versal_mini_ospi_defconfig b/configs/xilinx_versal_mini_ospi_defconfig index 389ca50..539ce2d 100644 --- a/configs/xilinx_versal_mini_ospi_defconfig +++ b/configs/xilinx_versal_mini_ospi_defconfig @@ -57,6 +57,7 @@ CONFIG_SYS_PROMPT="Versal> " CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_SOFT_RESET=y CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y +# CONFIG_SPI_FLASH_LOCK is not set CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MACRONIX=y diff --git a/configs/xilinx_versal_mini_qspi_defconfig b/configs/xilinx_versal_mini_qspi_defconfig index 5724aa3..336aa85 100644 --- a/configs/xilinx_versal_mini_qspi_defconfig +++ b/configs/xilinx_versal_mini_qspi_defconfig @@ -61,6 +61,7 @@ CONFIG_SYS_PROMPT="Versal> " # CONFIG_MMC is not set CONFIG_DM_SPI_FLASH=y # CONFIG_SPI_FLASH_SMART_HWCAPS is not set +# CONFIG_SPI_FLASH_LOCK is not set # CONFIG_SPI_FLASH_UNLOCK_ALL is not set CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_ISSI=y -- cgit v1.1 From dea1c089cfee23e1dfd838e57aba050add2d3193 Mon Sep 17 00:00:00 2001 From: Venkatesh Yadav Abbarapu Date: Tue, 3 Oct 2023 08:47:15 +0530 Subject: arm64: versal_net: Disable the lock option for mini ospi and qspi As mini configs are required only for flashing the images, so disabling the lock config which will save nearly 6KB of memory. Signed-off-by: Venkatesh Yadav Abbarapu Link: https://lore.kernel.org/r/20231003031715.5343-4-venkatesh.abbarapu@amd.com Signed-off-by: Michal Simek --- configs/xilinx_versal_net_mini_ospi_defconfig | 1 + configs/xilinx_versal_net_mini_qspi_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/configs/xilinx_versal_net_mini_ospi_defconfig b/configs/xilinx_versal_net_mini_ospi_defconfig index 0656b23..db3e7c8 100644 --- a/configs/xilinx_versal_net_mini_ospi_defconfig +++ b/configs/xilinx_versal_net_mini_ospi_defconfig @@ -56,6 +56,7 @@ CONFIG_SYS_PROMPT="Versal NET> " CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_SOFT_RESET=y CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y +# CONFIG_SPI_FLASH_LOCK is not set CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MACRONIX=y diff --git a/configs/xilinx_versal_net_mini_qspi_defconfig b/configs/xilinx_versal_net_mini_qspi_defconfig index c0e9ba9..37b3e76 100644 --- a/configs/xilinx_versal_net_mini_qspi_defconfig +++ b/configs/xilinx_versal_net_mini_qspi_defconfig @@ -60,6 +60,7 @@ CONFIG_SYS_PROMPT="Versal NET> " # CONFIG_MMC is not set CONFIG_DM_SPI_FLASH=y # CONFIG_SPI_FLASH_SMART_HWCAPS is not set +# CONFIG_SPI_FLASH_LOCK is not set # CONFIG_SPI_FLASH_UNLOCK_ALL is not set CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MACRONIX=y -- cgit v1.1 From ba9bdfd959f217a96772b83468c065b48f2581f0 Mon Sep 17 00:00:00 2001 From: Venkatesh Yadav Abbarapu Date: Wed, 11 Oct 2023 08:26:47 +0530 Subject: drivers: firmware: Handle error case in the zynqmp_pm_feature Unhandled error coming from xilinx_pm_request() but return value is not read back that's why getting sparse warning as below: warning: variable 'ret' set but not used [-Wunused-but-set-variable]. In case of error return the "ret" value. Signed-off-by: Venkatesh Yadav Abbarapu Link: https://lore.kernel.org/r/20231011025647.17200-1-venkatesh.abbarapu@amd.com Signed-off-by: Michal Simek --- drivers/firmware/firmware-zynqmp.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/firmware/firmware-zynqmp.c b/drivers/firmware/firmware-zynqmp.c index 43fb7fa..8ea15c7 100644 --- a/drivers/firmware/firmware-zynqmp.c +++ b/drivers/firmware/firmware-zynqmp.c @@ -203,6 +203,8 @@ int zynqmp_pm_feature(const u32 api_id) /* Check feature check API version */ ret = xilinx_pm_request(PM_FEATURE_CHECK, api_id, 0, 0, 0, ret_payload); + if (ret) + return ret; /* Return feature check version */ return ret_payload[1] & FIRMWARE_VERSION_MASK; -- cgit v1.1 From 20d1836eeab7a2335892b970575bfb1e9bcac567 Mon Sep 17 00:00:00 2001 From: Venkatesh Yadav Abbarapu Date: Wed, 11 Oct 2023 08:45:15 +0530 Subject: spi: cadence_ospi_versal: Add support for 64-bit address When 64-bit address is passed only lower 32-bit address is getting updated. Program the upper 32-bit address in the DMA destination memory address MSBs register. Signed-off-by: Venkatesh Yadav Abbarapu Link: https://lore.kernel.org/r/20231011031515.4151-1-venkatesh.abbarapu@amd.com Signed-off-by: Michal Simek --- drivers/spi/cadence_ospi_versal.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/spi/cadence_ospi_versal.c b/drivers/spi/cadence_ospi_versal.c index a7685a2..e02a3b3 100644 --- a/drivers/spi/cadence_ospi_versal.c +++ b/drivers/spi/cadence_ospi_versal.c @@ -44,8 +44,10 @@ int cadence_qspi_apb_dma_read(struct cadence_spi_priv *priv, priv->regbase + CQSPI_REG_INDIR_TRIG_ADDR_RANGE); writel(CQSPI_DFLT_DMA_PERIPH_CFG, priv->regbase + CQSPI_REG_DMA_PERIPH_CFG); - writel((unsigned long)rxbuf, priv->regbase + + writel(lower_32_bits((unsigned long)rxbuf), priv->regbase + CQSPI_DMA_DST_ADDR_REG); + writel(upper_32_bits((unsigned long)rxbuf), priv->regbase + + CQSPI_DMA_DST_ADDR_MSB_REG); writel(priv->trigger_address, priv->regbase + CQSPI_DMA_SRC_RD_ADDR_REG); writel(bytes_to_dma, priv->regbase + -- cgit v1.1 From 971a77262473fcdccbf77d616c738ec20d32d7a4 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 12 Oct 2023 10:22:16 +0200 Subject: arm64: zynqmp: Remove fclk driver fclk will never go upstream that's why removing this node from DT. All PL (programmable logic) based IPs should handle clocks self without using this workaround. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/fbb8665b8a58dbe96349abfe5492a509939e165b.1697098930.git.michal.simek@amd.com --- arch/arm/dts/zynqmp-clk-ccf.dtsi | 6 ------ 1 file changed, 6 deletions(-) diff --git a/arch/arm/dts/zynqmp-clk-ccf.dtsi b/arch/arm/dts/zynqmp-clk-ccf.dtsi index 5f1b0b2..dd4569e 100644 --- a/arch/arm/dts/zynqmp-clk-ccf.dtsi +++ b/arch/arm/dts/zynqmp-clk-ccf.dtsi @@ -10,12 +10,6 @@ #include / { - fclk0: fclk0 { - status = "okay"; - compatible = "xlnx,fclk"; - clocks = <&zynqmp_clk PL0_REF>; - }; - pss_ref_clk: pss_ref_clk { bootph-all; compatible = "fixed-clock"; -- cgit v1.1 From f87696afa03db147997bd12efacb7f0ded2ff963 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 12 Oct 2023 14:58:47 +0200 Subject: arm64: zynqmp: Use mdio node by vp-x-a2785-00-revA and vpk120-revA All boards have been converted to use mdio node that's why move ethernet phys under mdio node too. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/6c60f5d29b9d9992bd0130fd263c8ed13cb8166c.1697115523.git.michal.simek@amd.com --- arch/arm/dts/zynqmp-vp-x-a2785-00-revA.dts | 10 +++++++--- arch/arm/dts/zynqmp-vpk120-revA.dts | 10 +++++++--- 2 files changed, 14 insertions(+), 6 deletions(-) diff --git a/arch/arm/dts/zynqmp-vp-x-a2785-00-revA.dts b/arch/arm/dts/zynqmp-vp-x-a2785-00-revA.dts index 2f88aa4..9ab8f5b 100644 --- a/arch/arm/dts/zynqmp-vp-x-a2785-00-revA.dts +++ b/arch/arm/dts/zynqmp-vp-x-a2785-00-revA.dts @@ -119,9 +119,13 @@ phy-mode = "sgmii"; /* DTG generates this properly 1512 */ is-internal-pcspma; /* phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>; */ - /* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */ - phy0: ethernet-phy@0 { /* u131 - M88e1512 */ - reg = <0>; + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + /* reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */ + phy0: ethernet-phy@0 { /* u131 - M88e1512 */ + reg = <0>; + }; }; }; diff --git a/arch/arm/dts/zynqmp-vpk120-revA.dts b/arch/arm/dts/zynqmp-vpk120-revA.dts index 66919f5..ce76e0b 100644 --- a/arch/arm/dts/zynqmp-vpk120-revA.dts +++ b/arch/arm/dts/zynqmp-vpk120-revA.dts @@ -120,9 +120,13 @@ phy-mode = "sgmii"; /* DTG generates this properly 1512 */ is-internal-pcspma; /* phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>; */ - /* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */ - phy0: ethernet-phy@0 { - reg = <0>; + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + /* reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */ + phy0: ethernet-phy@0 { + reg = <0>; + }; }; }; -- cgit v1.1 From ff31d0330ddcb5b719ecc9615bd49c2e6113cc01 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 12 Oct 2023 14:58:48 +0200 Subject: arm64: zynqmp: Remove xlnx,zynqmp-aes node AES can be discovered via firmware interface that's why remove node for it. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/eaf575a6ca92f8c10cefb447c08c1292025deb74.1697115523.git.michal.simek@amd.com --- arch/arm/dts/zynqmp.dtsi | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index f03c201..463ac14 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -220,10 +220,6 @@ compatible = "xlnx,zynqmp-pcap-fpga"; }; - xlnx_aes: zynqmp-aes { - compatible = "xlnx,zynqmp-aes"; - }; - zynqmp_reset: reset-controller { compatible = "xlnx,zynqmp-reset"; #reset-cells = <1>; -- cgit v1.1 From e6b5c01a6c0d9a00632d22849fb1102c0c01fccd Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 12 Oct 2023 14:58:49 +0200 Subject: Revert "arm64: zynqmp: Add power domain description for PL" MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This reverts commit d59fac2f3f247470708a1aed1af96802a05e0e61. This power domain shouldn't be enabled by default. Power domain behavior should be handled on case by case basis. Adding this property to zynqmp.dtsi is breaking some suspend/resume cases that's why remove it from this file. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/7ed2a46383c6918fbbaca2d618459b1ee58f865c.1697115523.git.michal.simek@amd.com --- arch/arm/dts/zynqmp.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 463ac14..366b50a 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -257,7 +257,6 @@ #address-cells = <2>; #size-cells = <2>; ranges; - power-domains = <&zynqmp_firmware PD_PL>; }; remoteproc { -- cgit v1.1 From fa6106f98952f7e0e9475516bf09e87a311edb50 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 12 Oct 2023 14:58:50 +0200 Subject: arm64: zynqmp: Remove address/size-cells from ams node Remove unused address/size-cells which is also done upstream that's why this is pretty much sync patch with upstream. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/0ca8d8fe245ad7cb665f5333202d83f70acfc11f.1697115523.git.michal.simek@amd.com --- arch/arm/dts/zynqmp.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 366b50a..de60233 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -1034,8 +1034,6 @@ compatible = "xlnx,zynqmp-ams-pl"; status = "disabled"; reg = <0x400 0x400>; - #address-cells = <1>; - #size-cells = <0>; }; }; -- cgit v1.1 From 1bccde607e54584c74dc7fd53cfe814ca0343cb0 Mon Sep 17 00:00:00 2001 From: Piyush Mehta Date: Thu, 12 Oct 2023 14:58:51 +0200 Subject: arm64: zynqmp: remove snps, xhci-stream-quirk property for usb To sync up with the upstream bulk-stream feature, removed 'snps,xhci-stream-quirk' DT property for usb. Signed-off-by: Piyush Mehta Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/1f4ecfe3ea6a4d0d8d8de324f5dffd3efc86656a.1697115523.git.michal.simek@amd.com --- arch/arm/dts/zynqmp.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index de60233..2253e77 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -955,7 +955,6 @@ snps,quirk-frame-length-adjustment = <0x20>; clock-names = "ref"; snps,enable_guctl1_ipd_quirk; - snps,xhci-stream-quirk; snps,resume-hs-terminations; /* dma-coherent; */ }; @@ -988,7 +987,6 @@ snps,quirk-frame-length-adjustment = <0x20>; clock-names = "ref"; snps,enable_guctl1_ipd_quirk; - snps,xhci-stream-quirk; snps,resume-hs-terminations; /* dma-coherent; */ }; -- cgit v1.1 From ed1b1dd3bf79afe12b9ae008de50981bda5dbd04 Mon Sep 17 00:00:00 2001 From: Venkatesh Yadav Abbarapu Date: Thu, 12 Oct 2023 15:37:52 +0200 Subject: arm64: zynqmp: Disable the lock option for mini qspi As mini configs are required only for flashing the images, so disabling the lock config which will save nearly 6KB of memory. Signed-off-by: Venkatesh Yadav Abbarapu Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/374d6b3a46d19b7ee171dfe8071676098db93e25.1697117869.git.michal.simek@amd.com --- configs/xilinx_zynqmp_mini_qspi_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/xilinx_zynqmp_mini_qspi_defconfig b/configs/xilinx_zynqmp_mini_qspi_defconfig index a1adfb9..4a74ca7 100644 --- a/configs/xilinx_zynqmp_mini_qspi_defconfig +++ b/configs/xilinx_zynqmp_mini_qspi_defconfig @@ -77,6 +77,7 @@ CONFIG_SPL_DM_SEQ_ALIAS=y # CONFIG_DM_MAILBOX is not set # CONFIG_MMC is not set # CONFIG_SPI_FLASH_SMART_HWCAPS is not set +# CONFIG_SPI_FLASH_LOCK is not set # CONFIG_SPI_FLASH_UNLOCK_ALL is not set CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_ISSI=y -- cgit v1.1 From 03cc435539f447eb777032b034842ed5817f21a6 Mon Sep 17 00:00:00 2001 From: Venkatesh Yadav Abbarapu Date: Thu, 12 Oct 2023 15:39:56 +0200 Subject: ARM: zynq: Disable the config CONFIG_SPI_FLASH_USE_4K_SECTORS Lock size for the flashes will be in terms of sector size, so disable the CONFIG_SPI_FLASH_USE_4K_SECTORS and read it from the flash itself. Signed-off-by: Venkatesh Yadav Abbarapu Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/8e5c2bf3b7e5f366c4e261e8055ea254bda53aa9.1697117993.git.michal.simek@amd.com --- configs/xilinx_zynq_virt_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/xilinx_zynq_virt_defconfig b/configs/xilinx_zynq_virt_defconfig index 817fb41..6145af6 100644 --- a/configs/xilinx_zynq_virt_defconfig +++ b/configs/xilinx_zynq_virt_defconfig @@ -126,6 +126,7 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_SST=y CONFIG_SPI_FLASH_WINBOND=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_PHY_MARVELL=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y -- cgit v1.1 From fdff4b3c489d683ab08d6453ac91af593ab07a2a Mon Sep 17 00:00:00 2001 From: Amit Kumar Mahapatra Date: Thu, 12 Oct 2023 15:58:21 +0200 Subject: arm64: dts: zynqmp: make hw-ecc as the default ecc mode Except for Linux no other component (i.e., u-boot, fsbl or BootRom) of the software stack supports software ecc engine. So, make hw-ecc as the default ecc mode. Signed-off-by: Amit Kumar Mahapatra Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/f47b95616eb40d3a9908ca60df94ec6e873b071c.1697119098.git.michal.simek@amd.com --- arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts index 23a3ff2..160c6c5 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts @@ -141,8 +141,7 @@ reg = <0x0>; #address-cells = <0x2>; #size-cells = <0x1>; - nand-ecc-mode = "soft"; - nand-ecc-algo = "bch"; + nand-ecc-mode = "hw"; nand-rb = <0>; label = "main-storage-0"; nand-ecc-step-size = <1024>; @@ -178,8 +177,7 @@ reg = <0x1>; #address-cells = <0x2>; #size-cells = <0x1>; - nand-ecc-mode = "soft"; - nand-ecc-algo = "bch"; + nand-ecc-mode = "hw"; nand-rb = <0>; label = "main-storage-1"; nand-ecc-step-size = <1024>; -- cgit v1.1 From 3e891448920a8d53205d05e36372d65ae1289734 Mon Sep 17 00:00:00 2001 From: Ibai Erkiaga Date: Fri, 13 Oct 2023 13:37:27 +0100 Subject: zynqmp: migrate gqspi debug to logging The following patch migrates the usage of debug and printf functions to the relevant logging function as per U-Boot DM guidelines. Additionally some of the debugging statements have been rearanged for a more meaningfull debug experience. aarch64-linux-gnu-size reports 229 bytes less when debug is enabled at file level, while is just 5bytes more when disabled. Signed-off-by: Ibai Erkiaga Link: https://lore.kernel.org/r/20231013123739.2757979-1-ibai.erkiaga-elorza@amd.com Signed-off-by: Michal Simek --- drivers/spi/zynqmp_gqspi.c | 82 +++++++++++++++++++--------------------------- 1 file changed, 33 insertions(+), 49 deletions(-) diff --git a/drivers/spi/zynqmp_gqspi.c b/drivers/spi/zynqmp_gqspi.c index ec59ef58..a323994 100644 --- a/drivers/spi/zynqmp_gqspi.c +++ b/drivers/spi/zynqmp_gqspi.c @@ -5,6 +5,8 @@ * Xilinx ZynqMP Generic Quad-SPI(QSPI) controller driver(master mode only) */ +#define LOG_CATEGORY UCLASS_SPI + #include #include #include @@ -192,8 +194,6 @@ static int zynqmp_qspi_of_to_plat(struct udevice *bus) { struct zynqmp_qspi_plat *plat = dev_get_plat(bus); - debug("%s\n", __func__); - plat->regs = (struct zynqmp_qspi_regs *)(dev_read_addr(bus) + GQSPI_REG_OFFSET); plat->dma_regs = (struct zynqmp_qspi_dma_regs *) @@ -250,7 +250,7 @@ static u32 zynqmp_qspi_genfifo_mode(u8 buswidth) case 4: return GQSPI_SPI_MODE_QSPI; default: - debug("Unsupported bus width %u\n", buswidth); + log_warning("Unsupported bus width %u\n", buswidth); return GQSPI_SPI_MODE_SPI; } } @@ -262,6 +262,8 @@ static void zynqmp_qspi_fill_gen_fifo(struct zynqmp_qspi_priv *priv, u32 config_reg, ier; int ret = 0; + log_content("%s, GFIFO_CMD: 0x%X\n", __func__, gqspi_fifo_reg); + writel(gqspi_fifo_reg, ®s->genfifo); config_reg = readl(®s->confr); @@ -278,7 +280,7 @@ static void zynqmp_qspi_fill_gen_fifo(struct zynqmp_qspi_priv *priv, ret = wait_for_bit_le32(®s->isr, GQSPI_IXR_GFEMTY_MASK, 1, GQSPI_TIMEOUT, 1); if (ret) - printf("%s Timeout\n", __func__); + log_warning("%s, Timeout\n", __func__); } @@ -286,6 +288,8 @@ static void zynqmp_qspi_chipselect(struct zynqmp_qspi_priv *priv, int is_on) { u32 gqspi_fifo_reg = 0; + log_debug("%s, assert: %d\r\n", __func__, is_on); + if (is_on) { gqspi_fifo_reg = zynqmp_qspi_bus_select(priv); gqspi_fifo_reg |= GQSPI_SPI_MODE_SPI | @@ -295,8 +299,6 @@ static void zynqmp_qspi_chipselect(struct zynqmp_qspi_priv *priv, int is_on) gqspi_fifo_reg |= GQSPI_IMD_DATA_CS_DEASSERT; } - debug("GFIFO_CMD_CS: 0x%x\n", gqspi_fifo_reg); - zynqmp_qspi_fill_gen_fifo(priv, gqspi_fifo_reg); } @@ -311,8 +313,8 @@ static void zynqmp_qspi_set_tapdelay(struct udevice *bus, u32 baudrateval) clk_rate = plat->frequency; reqhz = (clk_rate / (GQSPI_BAUD_DIV_SHIFT << baudrateval)); - debug("%s, req_hz:%d, clk_rate:%d, baudrateval:%d\n", - __func__, reqhz, clk_rate, baudrateval); + log_debug("%s, clk_rate:%d, baudrateval:%d, bus_clk: %d\n", + __func__, clk_rate, baudrateval, reqhz); if (!(IS_ENABLED(CONFIG_ARCH_VERSAL) || IS_ENABLED(CONFIG_ARCH_VERSAL_NET))) { @@ -362,7 +364,8 @@ static int zynqmp_qspi_set_speed(struct udevice *bus, uint speed) u32 confr; u8 baud_rate_val = 0; - debug("%s\n", __func__); + log_debug("%s, Speed: %d, Max: %d\n", __func__, speed, plat->frequency); + if (speed > plat->frequency) speed = plat->frequency; @@ -383,9 +386,8 @@ static int zynqmp_qspi_set_speed(struct udevice *bus, uint speed) confr &= ~GQSPI_BAUD_DIV_MASK; confr |= (baud_rate_val << 3); writel(confr, ®s->confr); - zynqmp_qspi_set_tapdelay(bus, baud_rate_val); - debug("regs=%p, speed=%d\n", priv->regs, plat->speed_hz); + zynqmp_qspi_set_tapdelay(bus, baud_rate_val); } return 0; @@ -399,8 +401,6 @@ static int zynqmp_qspi_probe(struct udevice *bus) unsigned long clock; int ret; - debug("%s: bus:%p, priv:%p\n", __func__, bus, priv); - priv->regs = plat->regs; priv->dma_regs = plat->dma_regs; priv->io_mode = plat->io_mode; @@ -416,7 +416,6 @@ static int zynqmp_qspi_probe(struct udevice *bus) dev_err(bus, "failed to get rate\n"); return clock; } - debug("%s: CLK %ld\n", __func__, clock); ret = clk_enable(&clk); if (ret) { @@ -429,6 +428,8 @@ static int zynqmp_qspi_probe(struct udevice *bus) /* init the zynq spi hw */ zynqmp_qspi_init_hw(priv); + log_debug("%s, Rerence clock frequency: %ld\n", __func__, clock); + return 0; } @@ -438,7 +439,8 @@ static int zynqmp_qspi_set_mode(struct udevice *bus, uint mode) struct zynqmp_qspi_regs *regs = priv->regs; u32 confr; - debug("%s\n", __func__); + log_debug("%s, 0x%X\n", __func__, mode); + /* Set the SPI Clock phase and polarities */ confr = readl(®s->confr); confr &= ~(GQSPI_CONFIG_CPHA_MASK | GQSPI_CONFIG_CPOL_MASK); @@ -461,16 +463,11 @@ static int zynqmp_qspi_fill_tx_fifo(struct zynqmp_qspi_priv *priv, u32 size) u32 *buf = (u32 *)priv->tx_buf; u32 len = size; - debug("TxFIFO: 0x%x, size: 0x%x\n", readl(®s->isr), - size); - while (size) { ret = wait_for_bit_le32(®s->isr, GQSPI_IXR_TXNFULL_MASK, 1, GQSPI_TIMEOUT, 1); - if (ret) { - printf("%s: Timeout\n", __func__); - return ret; - } + if (ret) + return log_msg_ret("Timeout\n", ret); if (size >= 4) { writel(*buf, ®s->txd0r); @@ -501,10 +498,8 @@ static int zynqmp_qspi_fill_tx_fifo(struct zynqmp_qspi_priv *priv, u32 size) ret = wait_for_bit_le32(®s->isr, GQSPI_IXR_TXFIFOEMPTY_MASK, 1, GQSPI_TIMEOUT, 1); - if (ret) { - printf("%s: Timeout\n", __func__); - return ret; - } + if (ret) + return log_msg_ret("Timeout\n", ret); priv->tx_buf += len; return 0; @@ -516,6 +511,9 @@ static void zynqmp_qspi_genfifo_cmd(struct zynqmp_qspi_priv *priv) u32 gen_fifo_cmd; u8 i, dummy_cycles, addr; + log_debug("%s, opcode: 0x%0X, addr.nbytes: %d, dummy.mbytes: %d\r\n", + __func__, op->cmd.opcode, op->addr.nbytes, op->dummy.nbytes); + /* Send opcode */ gen_fifo_cmd = zynqmp_qspi_bus_select(priv); gen_fifo_cmd |= zynqmp_qspi_genfifo_mode(op->cmd.buswidth); @@ -532,8 +530,6 @@ static void zynqmp_qspi_genfifo_cmd(struct zynqmp_qspi_priv *priv) gen_fifo_cmd |= GQSPI_GFIFO_TX; gen_fifo_cmd |= addr; - debug("GFIFO_CMD_Cmd = 0x%x\n", gen_fifo_cmd); - zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd); } @@ -583,6 +579,8 @@ static int zynqmp_qspi_genfifo_fill_tx(struct zynqmp_qspi_priv *priv) u32 len; int ret = 0; + log_debug("%s, length: %d\r\n", __func__, priv->len); + gen_fifo_cmd = zynqmp_qspi_bus_select(priv); gen_fifo_cmd |= zynqmp_qspi_genfifo_mode(priv->op->data.buswidth); gen_fifo_cmd |= GQSPI_GFIFO_TX | GQSPI_GFIFO_DATA_XFR_MASK; @@ -591,8 +589,6 @@ static int zynqmp_qspi_genfifo_fill_tx(struct zynqmp_qspi_priv *priv) len = zynqmp_qspi_calc_exp(priv, &gen_fifo_cmd); zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd); - debug("GFIFO_CMD_TX:0x%x\n", gen_fifo_cmd); - if (gen_fifo_cmd & GQSPI_GFIFO_EXP_MASK) ret = zynqmp_qspi_fill_tx_fifo(priv, 1 << len); else @@ -608,7 +604,6 @@ static int zynqmp_qspi_start_io(struct zynqmp_qspi_priv *priv, u32 gen_fifo_cmd, u32 *buf) { u32 len; - u32 actuallen = priv->len; u32 config_reg, ier, isr; u32 timeout = GQSPI_TIMEOUT; struct zynqmp_qspi_regs *regs = priv->regs; @@ -623,7 +618,7 @@ static int zynqmp_qspi_start_io(struct zynqmp_qspi_priv *priv, else priv->bytes_to_receive = len; zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd); - debug("GFIFO_CMD_RX:0x%x\n", gen_fifo_cmd); + /* Manual start */ config_reg = readl(®s->confr); config_reg |= GQSPI_STRT_GEN_FIFO; @@ -652,13 +647,8 @@ static int zynqmp_qspi_start_io(struct zynqmp_qspi_priv *priv, } } - debug("buf:0x%lx, rxbuf:0x%lx, *buf:0x%x len: 0x%x\n", - (unsigned long)buf, (unsigned long)priv->rx_buf, - *buf, actuallen); - if (!timeout) { - printf("IO timeout: %d\n", readl(®s->isr)); - return -1; - } + if (!timeout) + return log_msg_retz("Timeout\n", timeout); } return 0; @@ -695,26 +685,18 @@ static int zynqmp_qspi_start_dma(struct zynqmp_qspi_priv *priv, while (priv->len) { zynqmp_qspi_calc_exp(priv, &gen_fifo_cmd); zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd); - - debug("GFIFO_CMD_RX:0x%x\n", gen_fifo_cmd); } ret = wait_for_bit_le32(&dma_regs->dmaisr, GQSPI_DMA_DST_I_STS_DONE, 1, GQSPI_TIMEOUT, 1); - if (ret) { - printf("DMA Timeout:0x%x\n", readl(&dma_regs->dmaisr)); - return -ETIMEDOUT; - } + if (ret) + return log_msg_ret("Timeout:\n", ret); invalidate_dcache_range(addr, addr + size); writel(GQSPI_DMA_DST_I_STS_DONE, &dma_regs->dmaisr); - debug("buf:0x%lx, rxbuf:0x%lx, *buf:0x%x len: 0x%x\n", - (unsigned long)buf, (unsigned long)priv->rx_buf, *buf, - actuallen); - if (buf != priv->rx_buf) memcpy(priv->rx_buf, buf, actuallen); @@ -731,6 +713,8 @@ static int zynqmp_qspi_genfifo_fill_rx(struct zynqmp_qspi_priv *priv) u32 *buf; u32 actuallen = priv->len; + log_debug("%s, length: %d\r\n", __func__, priv->len); + gen_fifo_cmd = zynqmp_qspi_bus_select(priv); gen_fifo_cmd |= zynqmp_qspi_genfifo_mode(priv->op->data.buswidth); gen_fifo_cmd |= GQSPI_GFIFO_RX | GQSPI_GFIFO_DATA_XFR_MASK; -- cgit v1.1 From 820bad0271939d93c2651b29f7ae8adb665a4dfe Mon Sep 17 00:00:00 2001 From: Tejas Bhumkar Date: Fri, 20 Oct 2023 10:36:22 +0530 Subject: arm64: zynqmp: Disable Tri-state for MIO38 Pin MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit gpio38 is used in SOM's kv260 to reset the Ethernet PHY. At present, HW reset is not working properly as Tri-state  is enabled for MIO38, causing inappropriate PHY register reads. Disabled Tri-state for MIO38 to make HW reset work. Tri-state disable : ZynqMP> md 0xFF180208 2 ff180208: 00bfe7a3 00000540 Tri-state enable : ZynqMP> md 0xFF180208 2 ff180208: 00bfe7e3 00000540 Signed-off-by: Tejas Bhumkar Link: https://lore.kernel.org/r/20231020050622.972750-1-tejas.arvind.bhumkar@amd.com Signed-off-by: Michal Simek --- arch/arm/dts/zynqmp-sck-kv-g-revA.dtso | 25 +++++++++++++++++++++++++ arch/arm/dts/zynqmp-sck-kv-g-revB.dtso | 25 +++++++++++++++++++++++++ 2 files changed, 50 insertions(+) diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso b/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso index 22e7d68..c4f1da9 100644 --- a/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso +++ b/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso @@ -190,6 +190,25 @@ &pinctrl0 { status = "okay"; + pinctrl_gpio0_default: gpio0-default { + conf { + groups = "gpio0_38_grp"; + bias-pull-up; + power-source = ; + }; + + mux { + groups = "gpio0_38_grp"; + function = "gpio0"; + }; + + conf-tx { + pins = "MIO38"; + bias-disable; + output-enable; + }; + }; + pinctrl_uart1_default: uart1-default { conf { groups = "uart1_9_grp"; @@ -345,6 +364,12 @@ }; }; +&gpio { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio0_default>; +}; + &uart1 { status = "okay"; pinctrl-names = "default"; diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso b/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso index eadc256..6c5e0e5 100644 --- a/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso +++ b/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso @@ -178,6 +178,25 @@ &pinctrl0 { status = "okay"; + pinctrl_gpio0_default: gpio0-default { + conf { + groups = "gpio0_38_grp"; + bias-pull-up; + power-source = ; + }; + + mux { + groups = "gpio0_38_grp"; + function = "gpio0"; + }; + + conf-tx { + pins = "MIO38"; + bias-disable; + output-enable; + }; + }; + pinctrl_uart1_default: uart1-default { conf { groups = "uart1_9_grp"; @@ -333,6 +352,12 @@ }; }; +&gpio { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio0_default>; +}; + &uart1 { status = "okay"; pinctrl-names = "default"; -- cgit v1.1 From 0d3399dfd8879dc63c91b734c47f80789c4c2b73 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 23 Oct 2023 09:21:53 +0200 Subject: arm: xilinx: Add missing dual parallel flash description Describe flash memories based on the latest DT binding. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/cddf2909d0445eba08b998d42ffc31c1fa3132b9.1698045694.git.michal.simek@amd.com --- arch/arm/dts/zynq-zc706.dts | 5 +++-- arch/arm/dts/zynq-zc770-xm013.dts | 5 +++-- arch/arm/dts/zynqmp-m-a2197-01-revA.dts | 4 +++- arch/arm/dts/zynqmp-m-a2197-02-revA.dts | 4 +++- arch/arm/dts/zynqmp-m-a2197-03-revA.dts | 4 +++- 5 files changed, 15 insertions(+), 7 deletions(-) diff --git a/arch/arm/dts/zynq-zc706.dts b/arch/arm/dts/zynq-zc706.dts index 03eb016..18963a3 100644 --- a/arch/arm/dts/zynq-zc706.dts +++ b/arch/arm/dts/zynq-zc706.dts @@ -309,10 +309,11 @@ &qspi { bootph-all; status = "okay"; - num-cs = <1>; + num-cs = <2>; flash@0 { compatible = "n25q128a11", "jedec,spi-nor"; - reg = <0x0>; + reg = <0>, <1>; + parallel-memories = /bits/ 64 <0x1000000 0x1000000>; /* 16MB */ spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <50000000>; diff --git a/arch/arm/dts/zynq-zc770-xm013.dts b/arch/arm/dts/zynq-zc770-xm013.dts index 21902fb..582aa1f 100644 --- a/arch/arm/dts/zynq-zc770-xm013.dts +++ b/arch/arm/dts/zynq-zc770-xm013.dts @@ -61,10 +61,11 @@ &qspi { status = "okay"; - num-cs = <1>; + num-cs = <2>; flash@0 { compatible = "n25q128a11", "jedec,spi-nor"; - reg = <0x0>; + reg = <0>, <1>; + parallel-memories = /bits/ 64 <0x1000000 0x1000000>; /* 16MB */ spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <50000000>; diff --git a/arch/arm/dts/zynqmp-m-a2197-01-revA.dts b/arch/arm/dts/zynqmp-m-a2197-01-revA.dts index 25ef646..83b8a98 100644 --- a/arch/arm/dts/zynqmp-m-a2197-01-revA.dts +++ b/arch/arm/dts/zynqmp-m-a2197-01-revA.dts @@ -71,11 +71,13 @@ &qspi { status = "okay"; + num-cs = <2>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ + reg = <0>, <1>; + parallel-memories = /bits/ 64 <0x4000000 0x4000000>; /* 64MB */ #address-cells = <1>; #size-cells = <1>; - reg = <0x0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; diff --git a/arch/arm/dts/zynqmp-m-a2197-02-revA.dts b/arch/arm/dts/zynqmp-m-a2197-02-revA.dts index ece9e69..dd37b72 100644 --- a/arch/arm/dts/zynqmp-m-a2197-02-revA.dts +++ b/arch/arm/dts/zynqmp-m-a2197-02-revA.dts @@ -67,11 +67,13 @@ &qspi { status = "okay"; + num-cs = <2>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ + reg = <0>, <1>; + parallel-memories = /bits/ 64 <0x4000000 0x4000000>; /* 64MB */ #address-cells = <1>; #size-cells = <1>; - reg = <0x0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; diff --git a/arch/arm/dts/zynqmp-m-a2197-03-revA.dts b/arch/arm/dts/zynqmp-m-a2197-03-revA.dts index 7372968..811ceba 100644 --- a/arch/arm/dts/zynqmp-m-a2197-03-revA.dts +++ b/arch/arm/dts/zynqmp-m-a2197-03-revA.dts @@ -67,11 +67,13 @@ &qspi { status = "okay"; + num-cs = <2>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ + reg = <0>, <1>; + parallel-memories = /bits/ 64 <0x4000000 0x4000000>; /* 64MB */ #address-cells = <1>; #size-cells = <1>; - reg = <0x0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; -- cgit v1.1 From a156b6ce0f04c29fdf8cba8910f17637e043fd6c Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 26 Oct 2023 08:34:31 +0200 Subject: arm64: zynqmp: Fix Kconfig entry indentation Use tabs instead of space for entry indentation which is standard coding style. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/ff28e719de82258c066f1fedae87f88597f367b5.1698302068.git.michal.simek@amd.com --- arch/arm/mach-zynqmp/Kconfig | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/arch/arm/mach-zynqmp/Kconfig b/arch/arm/mach-zynqmp/Kconfig index 26b80b7..7e7c87d 100644 --- a/arch/arm/mach-zynqmp/Kconfig +++ b/arch/arm/mach-zynqmp/Kconfig @@ -100,30 +100,30 @@ config SPL_ZYNQMP_DRAM_ECC_INIT config SPL_ZYNQMP_DRAM_BANK1_BASE depends on SPL_ZYNQMP_DRAM_ECC_INIT hex "DRAM Bank1 address" - default 0x00000000 - help - Start address of DRAM ECC bank1 + default 0x00000000 + help + Start address of DRAM ECC bank1 config SPL_ZYNQMP_DRAM_BANK1_LEN depends on SPL_ZYNQMP_DRAM_ECC_INIT hex "DRAM Bank1 size" - default 0x80000000 - help - Size in bytes of the DRAM ECC bank1 + default 0x80000000 + help + Size in bytes of the DRAM ECC bank1 config SPL_ZYNQMP_DRAM_BANK2_BASE depends on SPL_ZYNQMP_DRAM_ECC_INIT hex "DRAM Bank2 address" - default 0x800000000 - help - Start address of DRAM ECC bank2 + default 0x800000000 + help + Start address of DRAM ECC bank2 config SPL_ZYNQMP_DRAM_BANK2_LEN depends on SPL_ZYNQMP_DRAM_ECC_INIT hex "DRAM Bank2 size" - default 0x0 - help - Size in bytes of the DRAM ECC bank2. A null size takes no action. + default 0x0 + help + Size in bytes of the DRAM ECC bank2. A null size takes no action. config SYS_MALLOC_F_LEN default 0x600 -- cgit v1.1 From 83cab0b30fcb893a249d6644dd4e7cbe429e6750 Mon Sep 17 00:00:00 2001 From: Venkatesh Yadav Abbarapu Date: Fri, 27 Oct 2023 08:34:46 +0530 Subject: arm64: versal-net: enable CONFIG_MMC_SDHCI_ADMA The Standard Host Controller Interface (SDHCI) specification version 3.00 adds support for Advanced DMA (ADMA) for both 64 and 32 bit widths of DMA. This significantly improves read and write throughput. Signed-off-by: Venkatesh Yadav Abbarapu Link: https://lore.kernel.org/r/20231027030446.4009-1-venkatesh.abbarapu@amd.com Signed-off-by: Michal Simek --- configs/xilinx_versal_net_virt_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/xilinx_versal_net_virt_defconfig b/configs/xilinx_versal_net_virt_defconfig index ccc9431..0553ac6 100644 --- a/configs/xilinx_versal_net_virt_defconfig +++ b/configs/xilinx_versal_net_virt_defconfig @@ -85,6 +85,7 @@ CONFIG_MMC_IO_VOLTAGE=y CONFIG_MMC_UHS_SUPPORT=y CONFIG_MMC_HS400_SUPPORT=y CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ADMA=y CONFIG_MMC_SDHCI_ZYNQ=y CONFIG_ZYNQ_SDHCI_MIN_FREQ=100000 CONFIG_MTD=y -- cgit v1.1 From 1cd59c571cfc7f0c9813e64f81ca1d95380a7e22 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 31 Oct 2023 11:50:54 +0100 Subject: xilinx: versal: Setup 30MHz as default spi frequency Align default SPI configuration with ZynqMP/Versal NET. There is no reason to run on lower frequencies. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/c1d6ebd659f3002649b1200c926f8b9ed3132085.1698749448.git.michal.simek@amd.com --- configs/xilinx_versal_virt_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/xilinx_versal_virt_defconfig b/configs/xilinx_versal_virt_defconfig index b588887..6a2c03c 100644 --- a/configs/xilinx_versal_virt_defconfig +++ b/configs/xilinx_versal_virt_defconfig @@ -6,6 +6,7 @@ CONFIG_ARCH_VERSAL=y CONFIG_TEXT_BASE=0x8000000 CONFIG_SYS_MALLOC_F_LEN=0x100000 CONFIG_NR_DRAM_BANKS=36 +CONFIG_SF_DEFAULT_SPEED=30000000 CONFIG_DEFAULT_DEVICE_TREE="xilinx-versal-virt" CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y -- cgit v1.1 From da10dd10e0128dd32769d333559f44052c3a8245 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 26 Oct 2023 16:04:49 +0200 Subject: ARM: zynq: Add DTSes for mini qspi configurations Mini U-Boot is running out of OCM and it's only purpose is to program non volatile memories. There are different configurations which qspi can be that's why describe them via DT. DT binding is already approved that's why there is no reason not to add it. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/28b3cdd7e91b2b4c3c36d0bf65aa5bac042f248c.1698329087.git.michal.simek@amd.com --- arch/arm/dts/Makefile | 6 ++++++ arch/arm/dts/zynq-cse-qspi-parallel.dts | 22 ++++++++++++++++++++++ arch/arm/dts/zynq-cse-qspi-stacked.dts | 22 ++++++++++++++++++++++ arch/arm/dts/zynq-cse-qspi-x1-single.dts | 16 ++++++++++++++++ arch/arm/dts/zynq-cse-qspi-x1-stacked.dts | 22 ++++++++++++++++++++++ arch/arm/dts/zynq-cse-qspi-x2-single.dts | 16 ++++++++++++++++ arch/arm/dts/zynq-cse-qspi-x2-stacked.dts | 22 ++++++++++++++++++++++ 7 files changed, 126 insertions(+) create mode 100644 arch/arm/dts/zynq-cse-qspi-parallel.dts create mode 100644 arch/arm/dts/zynq-cse-qspi-stacked.dts create mode 100644 arch/arm/dts/zynq-cse-qspi-x1-single.dts create mode 100644 arch/arm/dts/zynq-cse-qspi-x1-stacked.dts create mode 100644 arch/arm/dts/zynq-cse-qspi-x2-single.dts create mode 100644 arch/arm/dts/zynq-cse-qspi-x2-stacked.dts diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 55aceb5..c7e03c5 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -376,6 +376,12 @@ dtb-$(CONFIG_ARCH_ZYNQ) += \ zynq-cse-nand.dtb \ zynq-cse-nor.dtb \ zynq-cse-qspi-single.dtb \ + zynq-cse-qspi-parallel.dtb \ + zynq-cse-qspi-stacked.dtb \ + zynq-cse-qspi-x1-single.dtb \ + zynq-cse-qspi-x1-stacked.dtb \ + zynq-cse-qspi-x2-single.dtb \ + zynq-cse-qspi-x2-stacked.dtb \ zynq-dlc20-rev1.0.dtb \ zynq-microzed.dtb \ zynq-minized.dtb \ diff --git a/arch/arm/dts/zynq-cse-qspi-parallel.dts b/arch/arm/dts/zynq-cse-qspi-parallel.dts new file mode 100644 index 0000000..afa6348 --- /dev/null +++ b/arch/arm/dts/zynq-cse-qspi-parallel.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Xilinx CSE QSPI Quad Parallel DTS + * + * Copyright (C) 2015 - 2017 Xilinx, Inc. + */ + +#include "zynq-cse-qspi.dtsi" + +/ { + model = "Zynq CSE QSPI PARALLEL Board"; +}; + +&qspi { + num-cs = <2>; +}; + +&flash0 { + reg = <0>, <1>; + parallel-memories = /bits/ 64 <0x1000000 0x1000000>; /* 16MB */ + spi-rx-bus-width = <4>; +}; diff --git a/arch/arm/dts/zynq-cse-qspi-stacked.dts b/arch/arm/dts/zynq-cse-qspi-stacked.dts new file mode 100644 index 0000000..47859f7 --- /dev/null +++ b/arch/arm/dts/zynq-cse-qspi-stacked.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Xilinx CSE QSPI Quad Stacked DTS + * + * Copyright (C) 2015 - 2017 Xilinx, Inc. + */ + +#include "zynq-cse-qspi.dtsi" + +/ { + model = "Zynq CSE QSPI STACKED Board"; +}; + +&qspi { + num-cs = <2>; +}; + +&flash0 { + reg = <0>, <1>; + stacked-memories = /bits/ 64 <0x1000000 0x1000000>; /* 16MB */ + spi-rx-bus-width = <4>; +}; diff --git a/arch/arm/dts/zynq-cse-qspi-x1-single.dts b/arch/arm/dts/zynq-cse-qspi-x1-single.dts new file mode 100644 index 0000000..c14fb42 --- /dev/null +++ b/arch/arm/dts/zynq-cse-qspi-x1-single.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Xilinx CSE QSPI x1 Single DTS + * + * Copyright (C) 2015 - 2017 Xilinx, Inc. + */ + +#include "zynq-cse-qspi.dtsi" + +/ { + model = "Zynq CSE QSPI X1 SINGLE Board"; +}; + +&flash0 { + spi-rx-bus-width = <1>; +}; diff --git a/arch/arm/dts/zynq-cse-qspi-x1-stacked.dts b/arch/arm/dts/zynq-cse-qspi-x1-stacked.dts new file mode 100644 index 0000000..0f4d414 --- /dev/null +++ b/arch/arm/dts/zynq-cse-qspi-x1-stacked.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Xilinx CSE QSPI x1 Stacked DTS + * + * Copyright (C) 2015 - 2017 Xilinx, Inc. + */ + +#include "zynq-cse-qspi.dtsi" + +/ { + model = "Zynq CSE QSPI X1 STACKED Board"; +}; + +&qspi { + num-cs = <2>; +}; + +&flash0 { + reg = <0>, <1>; + stacked-memories = /bits/ 64 <0x1000000 0x1000000>; /* 16MB */ + spi-rx-bus-width = <1>; +}; diff --git a/arch/arm/dts/zynq-cse-qspi-x2-single.dts b/arch/arm/dts/zynq-cse-qspi-x2-single.dts new file mode 100644 index 0000000..11be063 --- /dev/null +++ b/arch/arm/dts/zynq-cse-qspi-x2-single.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Xilinx CSE QSPI x2 Single DTS + * + * Copyright (C) 2015 - 2017 Xilinx, Inc. + */ + +#include "zynq-cse-qspi.dtsi" + +/ { + model = "Zynq CSE QSPI X2 SINGLE Board"; +}; + +&flash0 { + spi-rx-bus-width = <2>; +}; diff --git a/arch/arm/dts/zynq-cse-qspi-x2-stacked.dts b/arch/arm/dts/zynq-cse-qspi-x2-stacked.dts new file mode 100644 index 0000000..d1b42e9 --- /dev/null +++ b/arch/arm/dts/zynq-cse-qspi-x2-stacked.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Xilinx CSE QSPI x2 Stacked DTS + * + * Copyright (C) 2015 - 2017 Xilinx, Inc. + */ + +#include "zynq-cse-qspi.dtsi" + +/ { + model = "Zynq CSE QSPI X2 STACKED Board"; +}; + +&qspi { + num-cs = <2>; +}; + +&flash0 { + reg = <0>, <1>; + stacked-memories = /bits/ 64 <0x1000000 0x1000000>; /* 16MB */ + spi-rx-bus-width = <2>; +}; -- cgit v1.1 From a78761805758c9e751c957f423b2de68ffdb4732 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 26 Oct 2023 16:04:50 +0200 Subject: ARM: zynq: Add DTSes for mini qspi configurations Mini U-Boot is running out of OCM and it's only purpose is to program non volatile memories. There are different configurations which qspi can be that's why describe them via DT. DT binding is already approved that's why there is no reason not to add it. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/e7d31a9d9c4a76e171eefc619f31fabd0831a614.1698329087.git.michal.simek@amd.com --- arch/arm/dts/Makefile | 7 +++++++ arch/arm/dts/zynqmp-mini-qspi-parallel.dts | 21 +++++++++++++++++++++ arch/arm/dts/zynqmp-mini-qspi-single.dts | 12 ++++++++++++ arch/arm/dts/zynqmp-mini-qspi-stacked.dts | 21 +++++++++++++++++++++ arch/arm/dts/zynqmp-mini-qspi-x1-single.dts | 17 +++++++++++++++++ arch/arm/dts/zynqmp-mini-qspi-x1-stacked.dts | 23 +++++++++++++++++++++++ arch/arm/dts/zynqmp-mini-qspi-x2-single.dts | 17 +++++++++++++++++ arch/arm/dts/zynqmp-mini-qspi-x2-stacked.dts | 23 +++++++++++++++++++++++ 8 files changed, 141 insertions(+) create mode 100644 arch/arm/dts/zynqmp-mini-qspi-parallel.dts create mode 100644 arch/arm/dts/zynqmp-mini-qspi-single.dts create mode 100644 arch/arm/dts/zynqmp-mini-qspi-stacked.dts create mode 100644 arch/arm/dts/zynqmp-mini-qspi-x1-single.dts create mode 100644 arch/arm/dts/zynqmp-mini-qspi-x1-stacked.dts create mode 100644 arch/arm/dts/zynqmp-mini-qspi-x2-single.dts create mode 100644 arch/arm/dts/zynqmp-mini-qspi-x2-stacked.dts diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index c7e03c5..e7c8637 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -423,6 +423,13 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \ zynqmp-mini-emmc1.dtb \ zynqmp-mini-nand.dtb \ zynqmp-mini-qspi.dtb \ + zynqmp-mini-qspi-parallel.dtb \ + zynqmp-mini-qspi-single.dtb \ + zynqmp-mini-qspi-stacked.dtb \ + zynqmp-mini-qspi-x1-single.dtb \ + zynqmp-mini-qspi-x1-stacked.dtb \ + zynqmp-mini-qspi-x2-single.dtb \ + zynqmp-mini-qspi-x2-stacked.dtb \ zynqmp-sc-revB.dtb \ zynqmp-sc-revC.dtb \ zynqmp-sc-vek280-revA.dtbo \ diff --git a/arch/arm/dts/zynqmp-mini-qspi-parallel.dts b/arch/arm/dts/zynqmp-mini-qspi-parallel.dts new file mode 100644 index 0000000..728e822 --- /dev/null +++ b/arch/arm/dts/zynqmp-mini-qspi-parallel.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Xilinx ZynqMP QSPI Quad Parallel DTS + * + * Copyright (C) 2015 - 2017 Xilinx, Inc. + */ + +#include "zynqmp-mini-qspi.dts" + +/ { + model = "ZynqMP MINI QSPI PARALLEL"; +}; + +&qspi { + num-cs = <2>; +}; + +&flash0 { + reg = <0>, <1>; + parallel-memories = /bits/ 64 <0x10000000 0x10000000>; /* 256MB */ +}; diff --git a/arch/arm/dts/zynqmp-mini-qspi-single.dts b/arch/arm/dts/zynqmp-mini-qspi-single.dts new file mode 100644 index 0000000..0f9306e --- /dev/null +++ b/arch/arm/dts/zynqmp-mini-qspi-single.dts @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Xilinx ZynqMP QSPI single DTS + * + * Copyright (C) 2015 - 2017 Xilinx, Inc. + */ + +#include "zynqmp-mini-qspi.dts" + +/ { + model = "ZynqMP MINI QSPI SINGLE"; +}; diff --git a/arch/arm/dts/zynqmp-mini-qspi-stacked.dts b/arch/arm/dts/zynqmp-mini-qspi-stacked.dts new file mode 100644 index 0000000..9a9541b --- /dev/null +++ b/arch/arm/dts/zynqmp-mini-qspi-stacked.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Xilinx ZynqMP QSPI Quad Stacked DTS + * + * Copyright (C) 2015 - 2017 Xilinx, Inc. + */ + +#include "zynqmp-mini-qspi.dts" + +/ { + model = "ZynqMP MINI QSPI STACKED"; +}; + +&qspi { + num-cs = <2>; +}; + +&flash0 { + reg = <0>, <1>; + stacked-memories = /bits/ 64 <0x10000000 0x10000000>; /* 256MB */ +}; diff --git a/arch/arm/dts/zynqmp-mini-qspi-x1-single.dts b/arch/arm/dts/zynqmp-mini-qspi-x1-single.dts new file mode 100644 index 0000000..5af875c --- /dev/null +++ b/arch/arm/dts/zynqmp-mini-qspi-x1-single.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Xilinx ZynqMP QSPI x1 Single DTS + * + * Copyright (C) 2015 - 2017 Xilinx, Inc. + */ + +#include "zynqmp-mini-qspi.dts" + +/ { + model = "ZynqMP MINI QSPI X1 SINGLE"; +}; + +&flash0 { + spi-tx-bus-width = <1>; + spi-rx-bus-width = <1>; +}; diff --git a/arch/arm/dts/zynqmp-mini-qspi-x1-stacked.dts b/arch/arm/dts/zynqmp-mini-qspi-x1-stacked.dts new file mode 100644 index 0000000..ebf890e --- /dev/null +++ b/arch/arm/dts/zynqmp-mini-qspi-x1-stacked.dts @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Xilinx ZynqMP QSPI x1 Stacked DTS + * + * Copyright (C) 2015 - 2017 Xilinx, Inc. + */ + +#include "zynqmp-mini-qspi.dts" + +/ { + model = "ZynqMP MINI QSPI X1 STACKED"; +}; + +&qspi { + num-cs = <2>; +}; + +&flash0 { + reg = <0>, <1>; + stacked-memories = /bits/ 64 <0x10000000 0x10000000>; /* 256MB */ + spi-tx-bus-width = <1>; + spi-rx-bus-width = <1>; +}; diff --git a/arch/arm/dts/zynqmp-mini-qspi-x2-single.dts b/arch/arm/dts/zynqmp-mini-qspi-x2-single.dts new file mode 100644 index 0000000..a5ab315 --- /dev/null +++ b/arch/arm/dts/zynqmp-mini-qspi-x2-single.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Xilinx CSE QSPI x2 Single DTS + * + * Copyright (C) 2015 - 2017 Xilinx, Inc. + */ + +#include "zynqmp-mini-qspi.dts" + +/ { + model = "ZynqMP MINI QSPI X2 SINGLE"; +}; + +&flash0 { + spi-tx-bus-width = <2>; + spi-rx-bus-width = <2>; +}; diff --git a/arch/arm/dts/zynqmp-mini-qspi-x2-stacked.dts b/arch/arm/dts/zynqmp-mini-qspi-x2-stacked.dts new file mode 100644 index 0000000..e234b76 --- /dev/null +++ b/arch/arm/dts/zynqmp-mini-qspi-x2-stacked.dts @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Xilinx ZynqMP QSPI x2 Stacked DTS + * + * Copyright (C) 2015 - 2017 Xilinx, Inc. + */ + +#include "zynqmp-mini-qspi.dts" + +/ { + model = "ZynqMP MINI QSPI X2 STACKED"; +}; + +&qspi { + num-cs = <2>; +}; + +&flash0 { + reg = <0>, <1>; + stacked-memories = /bits/ 64 <0x10000000 0x10000000>; /* 256MB */ + spi-tx-bus-width = <2>; + spi-rx-bus-width = <2>; +}; -- cgit v1.1 From 0274447bae1e5aa55aa676a6d381036b6c6fc393 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 26 Oct 2023 16:04:51 +0200 Subject: arm64: versal: Add DTSes for mini qspi/ospi configuration Mini U-Boot is running out of OCM and it's only purpose is to program non volatile memories. There are different configurations which ospi/qspi can be that's why describe them via DT. DT binding is already approved that's why there is no reason not to add it. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/9518ab1c4299a45e800b8611172edd78c9243132.1698329087.git.michal.simek@amd.com --- arch/arm/dts/Makefile | 7 +++++++ arch/arm/dts/versal-mini-ospi-stacked.dts | 22 ++++++++++++++++++++++ arch/arm/dts/versal-mini-qspi-parallel.dts | 22 ++++++++++++++++++++++ arch/arm/dts/versal-mini-qspi-stacked.dts | 22 ++++++++++++++++++++++ arch/arm/dts/versal-mini-qspi-x1-single.dts | 17 +++++++++++++++++ arch/arm/dts/versal-mini-qspi-x1-stacked.dts | 23 +++++++++++++++++++++++ arch/arm/dts/versal-mini-qspi-x2-single.dts | 17 +++++++++++++++++ arch/arm/dts/versal-mini-qspi-x2-stacked.dts | 23 +++++++++++++++++++++++ 8 files changed, 153 insertions(+) create mode 100644 arch/arm/dts/versal-mini-ospi-stacked.dts create mode 100644 arch/arm/dts/versal-mini-qspi-parallel.dts create mode 100644 arch/arm/dts/versal-mini-qspi-stacked.dts create mode 100644 arch/arm/dts/versal-mini-qspi-x1-single.dts create mode 100644 arch/arm/dts/versal-mini-qspi-x1-stacked.dts create mode 100644 arch/arm/dts/versal-mini-qspi-x2-single.dts create mode 100644 arch/arm/dts/versal-mini-qspi-x2-stacked.dts diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index e7c8637..6308c5c 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -480,7 +480,14 @@ dtb-$(CONFIG_ARCH_VERSAL) += \ versal-mini-emmc0.dtb \ versal-mini-emmc1.dtb \ versal-mini-ospi-single.dtb \ + versal-mini-ospi-stacked.dtb \ + versal-mini-qspi-parallel.dtb \ versal-mini-qspi-single.dtb \ + versal-mini-qspi-stacked.dtb \ + versal-mini-qspi-x1-single.dtb \ + versal-mini-qspi-x1-stacked.dtb \ + versal-mini-qspi-x2-single.dtb \ + versal-mini-qspi-x2-stacked.dtb \ xilinx-versal-virt.dtb dtb-$(CONFIG_ARCH_VERSAL_NET) += \ versal-net-mini.dtb \ diff --git a/arch/arm/dts/versal-mini-ospi-stacked.dts b/arch/arm/dts/versal-mini-ospi-stacked.dts new file mode 100644 index 0000000..f46125d --- /dev/null +++ b/arch/arm/dts/versal-mini-ospi-stacked.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Xilinx Versal QSPI Quad Stacked DTS + * + * Copyright (C) 2018-2020 Xilinx, Inc. + */ + +#include "versal-mini-ospi.dtsi" + +/ { + model = "Xilinx Versal MINI OSPI STACKED"; +}; + +&ospi { + num-cs = <2>; +}; + +&flash0 { + reg = <0>, <1>; + stacked-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */ + spi-rx-bus-width = <8>; +}; diff --git a/arch/arm/dts/versal-mini-qspi-parallel.dts b/arch/arm/dts/versal-mini-qspi-parallel.dts new file mode 100644 index 0000000..8485cda --- /dev/null +++ b/arch/arm/dts/versal-mini-qspi-parallel.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Xilinx Versal QSPI Quad Parallel DTS + * + * Copyright (C) 2018-2019 Xilinx, Inc. + */ + +#include "versal-mini-qspi.dtsi" + +/ { + model = "Xilinx Versal MINI QSPI PARALLEL"; +}; + +&qspi { + num-cs = <2>; +}; + +&flash0 { + reg = <0>, <1>; + parallel-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */ + spi-rx-bus-width = <4>; +}; diff --git a/arch/arm/dts/versal-mini-qspi-stacked.dts b/arch/arm/dts/versal-mini-qspi-stacked.dts new file mode 100644 index 0000000..54d4277 --- /dev/null +++ b/arch/arm/dts/versal-mini-qspi-stacked.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Xilinx Versal QSPI Quad Stacked DTS + * + * Copyright (C) 2018-2019 Xilinx, Inc. + */ + +#include "versal-mini-qspi.dtsi" + +/ { + model = "Xilinx Versal MINI QSPI STACKED"; +}; + +&qspi { + num-cs = <2>; +}; + +&flash0 { + reg = <0>, <1>; + stacked-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */ + spi-rx-bus-width = <4>; +}; diff --git a/arch/arm/dts/versal-mini-qspi-x1-single.dts b/arch/arm/dts/versal-mini-qspi-x1-single.dts new file mode 100644 index 0000000..4d459a1 --- /dev/null +++ b/arch/arm/dts/versal-mini-qspi-x1-single.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Xilinx Versal QSPI x1 Single DTS + * + * Copyright (C) 2018-2019 Xilinx, Inc. + */ + +#include "versal-mini-qspi.dtsi" + +/ { + model = "Xilinx Versal MINI QSPI X1 SINGLE"; +}; + +&flash0 { + spi-tx-bus-width = <1>; + spi-rx-bus-width = <1>; +}; diff --git a/arch/arm/dts/versal-mini-qspi-x1-stacked.dts b/arch/arm/dts/versal-mini-qspi-x1-stacked.dts new file mode 100644 index 0000000..905dc77 --- /dev/null +++ b/arch/arm/dts/versal-mini-qspi-x1-stacked.dts @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Xilinx Versal QSPI x1 Stacked DTS + * + * Copyright (C) 2018-2019 Xilinx, Inc. + */ + +#include "versal-mini-qspi.dtsi" + +/ { + model = "Xilinx Versal MINI QSPI X1 STACKED"; +}; + +&qspi { + num-cs = <2>; +}; + +&flash0 { + reg = <0>, <1>; + stacked-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */ + spi-tx-bus-width = <1>; + spi-rx-bus-width = <1>; +}; diff --git a/arch/arm/dts/versal-mini-qspi-x2-single.dts b/arch/arm/dts/versal-mini-qspi-x2-single.dts new file mode 100644 index 0000000..d25ad7c --- /dev/null +++ b/arch/arm/dts/versal-mini-qspi-x2-single.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Xilinx Versal QSPI x2 Single DTS + * + * Copyright (C) 2018-2019 Xilinx, Inc. + */ + +#include "versal-mini-qspi.dtsi" + +/ { + model = "Xilinx Versal MINI QSPI X2 SINGLE"; +}; + +&flash0 { + spi-tx-bus-width = <2>; + spi-rx-bus-width = <2>; +}; diff --git a/arch/arm/dts/versal-mini-qspi-x2-stacked.dts b/arch/arm/dts/versal-mini-qspi-x2-stacked.dts new file mode 100644 index 0000000..0c9e740 --- /dev/null +++ b/arch/arm/dts/versal-mini-qspi-x2-stacked.dts @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Xilinx Versal QSPI x2 Stacked DTS + * + * Copyright (C) 2018-2019 Xilinx, Inc. + */ + +#include "versal-mini-qspi.dtsi" + +/ { + model = "Xilinx Versal MINI QSPI X2 STACKED"; +}; + +&qspi { + num-cs = <2>; +}; + +&flash0 { + reg = <0>, <1>; + stacked-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */ + spi-tx-bus-width = <2>; + spi-rx-bus-width = <2>; +}; -- cgit v1.1 From 7faa6b9069dd3973545043e65668859f887397a6 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 26 Oct 2023 16:04:52 +0200 Subject: arm64: versal-net: Add DTSes for mini qspi/ospi configuration Mini U-Boot is running out of OCM and it's only purpose is to program non volatile memories. There are different configurations which ospi/qspi can be that's why describe them via DT. DT binding is already approved that's why there is no reason not to add it. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/a99a8d72201a782fc811715942dea97fb5ab583b.1698329087.git.michal.simek@amd.com --- arch/arm/dts/Makefile | 7 +++++++ arch/arm/dts/versal-net-mini-ospi-stacked.dts | 22 ++++++++++++++++++++++ arch/arm/dts/versal-net-mini-qspi-parallel.dts | 22 ++++++++++++++++++++++ arch/arm/dts/versal-net-mini-qspi-stacked.dts | 22 ++++++++++++++++++++++ arch/arm/dts/versal-net-mini-qspi-x1-single.dts | 17 +++++++++++++++++ arch/arm/dts/versal-net-mini-qspi-x1-stacked.dts | 23 +++++++++++++++++++++++ arch/arm/dts/versal-net-mini-qspi-x2-single.dts | 17 +++++++++++++++++ arch/arm/dts/versal-net-mini-qspi-x2-stacked.dts | 23 +++++++++++++++++++++++ 8 files changed, 153 insertions(+) create mode 100644 arch/arm/dts/versal-net-mini-ospi-stacked.dts create mode 100644 arch/arm/dts/versal-net-mini-qspi-parallel.dts create mode 100644 arch/arm/dts/versal-net-mini-qspi-stacked.dts create mode 100644 arch/arm/dts/versal-net-mini-qspi-x1-single.dts create mode 100644 arch/arm/dts/versal-net-mini-qspi-x1-stacked.dts create mode 100644 arch/arm/dts/versal-net-mini-qspi-x2-single.dts create mode 100644 arch/arm/dts/versal-net-mini-qspi-x2-stacked.dts diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 6308c5c..9e8b208 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -493,7 +493,14 @@ dtb-$(CONFIG_ARCH_VERSAL_NET) += \ versal-net-mini.dtb \ versal-net-mini-emmc.dtb \ versal-net-mini-ospi-single.dtb \ + versal-net-mini-ospi-stacked.dtb \ versal-net-mini-qspi-single.dtb \ + versal-net-mini-qspi-parallel.dtb \ + versal-net-mini-qspi-stacked.dtb \ + versal-net-mini-qspi-x1-single.dtb \ + versal-net-mini-qspi-x1-stacked.dtb \ + versal-net-mini-qspi-x2-single.dtb \ + versal-net-mini-qspi-x2-stacked.dtb \ xilinx-versal-net-virt.dtb dtb-$(CONFIG_ARCH_ZYNQMP_R5) += \ zynqmp-r5.dtb diff --git a/arch/arm/dts/versal-net-mini-ospi-stacked.dts b/arch/arm/dts/versal-net-mini-ospi-stacked.dts new file mode 100644 index 0000000..4bc954a --- /dev/null +++ b/arch/arm/dts/versal-net-mini-ospi-stacked.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Xilinx Versal NET OSPI Quad Stacked DTS + * + * (C) Copyright 2023, Advanced Micro Devices, Inc. + */ + +#include "versal-net-mini-ospi.dtsi" + +/ { + model = "Xilinx Versal NET MINI OSPI STACKED"; +}; + +&ospi { + num-cs = <2>; +}; + +&flash0 { + reg = <0>, <1>; + stacked-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */ + spi-rx-bus-width = <8>; +}; diff --git a/arch/arm/dts/versal-net-mini-qspi-parallel.dts b/arch/arm/dts/versal-net-mini-qspi-parallel.dts new file mode 100644 index 0000000..edc2311 --- /dev/null +++ b/arch/arm/dts/versal-net-mini-qspi-parallel.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Xilinx Versal NET QSPI Quad Parallel DTS + * + * (C) Copyright 2023, Advanced Micro Devices, Inc. + */ + +#include "versal-net-mini-qspi.dtsi" + +/ { + model = "Xilinx Versal NET MINI QSPI PARALLEL"; +}; + +&qspi { + num-cs = <2>; +}; + +&flash0 { + reg = <0>, <1>; + parallel-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */ + spi-rx-bus-width = <4>; +}; diff --git a/arch/arm/dts/versal-net-mini-qspi-stacked.dts b/arch/arm/dts/versal-net-mini-qspi-stacked.dts new file mode 100644 index 0000000..920eed2 --- /dev/null +++ b/arch/arm/dts/versal-net-mini-qspi-stacked.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Xilinx Versal NET QSPI Quad Stacked DTS + * + * (C) Copyright 2023, Advanced Micro Devices, Inc. + */ + +#include "versal-net-mini-qspi.dtsi" + +/ { + model = "Xilinx Versal NET MINI QSPI STACKED"; +}; + +&qspi { + num-cs = <2>; +}; + +&flash0 { + reg = <0>, <1>; + stacked-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */ + spi-rx-bus-width = <4>; +}; diff --git a/arch/arm/dts/versal-net-mini-qspi-x1-single.dts b/arch/arm/dts/versal-net-mini-qspi-x1-single.dts new file mode 100644 index 0000000..856c79c --- /dev/null +++ b/arch/arm/dts/versal-net-mini-qspi-x1-single.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Xilinx Versal NET QSPI x1 Single DTS + * + * (C) Copyright 2023, Advanced Micro Devices, Inc. + */ + +#include "versal-net-mini-qspi.dtsi" + +/ { + model = "Xilinx Versal NET MINI QSPI X1 SINGLE"; +}; + +&flash0 { + spi-tx-bus-width = <1>; + spi-rx-bus-width = <1>; +}; diff --git a/arch/arm/dts/versal-net-mini-qspi-x1-stacked.dts b/arch/arm/dts/versal-net-mini-qspi-x1-stacked.dts new file mode 100644 index 0000000..5f74d98 --- /dev/null +++ b/arch/arm/dts/versal-net-mini-qspi-x1-stacked.dts @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Xilinx Versal NET QSPI x1 Stacked DTS + * + * (C) Copyright 2023, Advanced Micro Devices, Inc. + */ + +#include "versal-net-mini-qspi.dtsi" + +/ { + model = "Xilinx Versal NET MINI QSPI X1 STACKED"; +}; + +&qspi { + num-cs = <2>; +}; + +&flash0 { + reg = <0>, <1>; + stacked-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */ + spi-tx-bus-width = <1>; + spi-rx-bus-width = <1>; +}; diff --git a/arch/arm/dts/versal-net-mini-qspi-x2-single.dts b/arch/arm/dts/versal-net-mini-qspi-x2-single.dts new file mode 100644 index 0000000..6ceaa24 --- /dev/null +++ b/arch/arm/dts/versal-net-mini-qspi-x2-single.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Xilinx Versal NET QSPI x2 Single DTS + * + * (C) Copyright 2023, Advanced Micro Devices, Inc. + */ + +#include "versal-net-mini-qspi.dtsi" + +/ { + model = "Xilinx Versal NET MINI QSPI X2 SINGLE"; +}; + +&flash0 { + spi-tx-bus-width = <2>; + spi-rx-bus-width = <2>; +}; diff --git a/arch/arm/dts/versal-net-mini-qspi-x2-stacked.dts b/arch/arm/dts/versal-net-mini-qspi-x2-stacked.dts new file mode 100644 index 0000000..5f4d0b5 --- /dev/null +++ b/arch/arm/dts/versal-net-mini-qspi-x2-stacked.dts @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Xilinx Versal NET QSPI x2 Stacked DTS + * + * (C) Copyright 2023, Advanced Micro Devices, Inc. + */ + +#include "versal-net-mini-qspi.dtsi" + +/ { + model = "Xilinx Versal NET MINI QSPI X2 STACKED"; +}; + +&qspi { + num-cs = <2>; +}; + +&flash0 { + reg = <0>, <1>; + stacked-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */ + spi-tx-bus-width = <2>; + spi-rx-bus-width = <2>; +}; -- cgit v1.1 From 6e3dbaa0b55e763af189eea83140d759c2d0cb46 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 1 Nov 2023 09:01:03 +0100 Subject: arm64: zynqmp: Comment all smmu entries SMMU is disabled by default and not all masters can be enabled at the same time because of limited number of entries. That's why comment all iommu properties but keep them for reference in DT. In XEN case they should be added back and Xen should have SMMU enabled by default. Also add IDs for DP and DPDMA. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/e868c27c52ded5d8ef25f75ba394b1ab3b31b80a.1698825657.git.michal.simek@amd.com --- arch/arm/dts/zynqmp.dtsi | 59 ++++++++++++++++++++++++------------------------ 1 file changed, 30 insertions(+), 29 deletions(-) diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 2253e77..66d5335 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -339,7 +339,7 @@ clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; - iommus = <&smmu 0x14e8>; + /* iommus = <&smmu 0x14e8>; */ power-domains = <&zynqmp_firmware PD_GDMA>; }; @@ -352,7 +352,7 @@ clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; - iommus = <&smmu 0x14e9>; + /* iommus = <&smmu 0x14e9>; */ power-domains = <&zynqmp_firmware PD_GDMA>; }; @@ -365,7 +365,7 @@ clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; - iommus = <&smmu 0x14ea>; + /* iommus = <&smmu 0x14ea>; */ power-domains = <&zynqmp_firmware PD_GDMA>; }; @@ -378,7 +378,7 @@ clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; - iommus = <&smmu 0x14eb>; + /* iommus = <&smmu 0x14eb>; */ power-domains = <&zynqmp_firmware PD_GDMA>; }; @@ -391,7 +391,7 @@ clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; - iommus = <&smmu 0x14ec>; + /* iommus = <&smmu 0x14ec>; */ power-domains = <&zynqmp_firmware PD_GDMA>; }; @@ -404,7 +404,7 @@ clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; - iommus = <&smmu 0x14ed>; + /* iommus = <&smmu 0x14ed>; */ power-domains = <&zynqmp_firmware PD_GDMA>; }; @@ -417,7 +417,7 @@ clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; - iommus = <&smmu 0x14ee>; + /* iommus = <&smmu 0x14ee>; */ power-domains = <&zynqmp_firmware PD_GDMA>; }; @@ -430,7 +430,7 @@ clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; - iommus = <&smmu 0x14ef>; + /* iommus = <&smmu 0x14ef>; */ power-domains = <&zynqmp_firmware PD_GDMA>; }; @@ -475,7 +475,7 @@ clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; - iommus = <&smmu 0x868>; + /* iommus = <&smmu 0x868>; */ power-domains = <&zynqmp_firmware PD_ADMA>; }; @@ -488,7 +488,7 @@ clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; - iommus = <&smmu 0x869>; + /* iommus = <&smmu 0x869>; */ power-domains = <&zynqmp_firmware PD_ADMA>; }; @@ -501,7 +501,7 @@ clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; - iommus = <&smmu 0x86a>; + /* iommus = <&smmu 0x86a>; */ power-domains = <&zynqmp_firmware PD_ADMA>; }; @@ -514,7 +514,7 @@ clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; - iommus = <&smmu 0x86b>; + /* iommus = <&smmu 0x86b>; */ power-domains = <&zynqmp_firmware PD_ADMA>; }; @@ -527,7 +527,7 @@ clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; - iommus = <&smmu 0x86c>; + /* iommus = <&smmu 0x86c>; */ power-domains = <&zynqmp_firmware PD_ADMA>; }; @@ -540,7 +540,7 @@ clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; - iommus = <&smmu 0x86d>; + /* iommus = <&smmu 0x86d>; */ power-domains = <&zynqmp_firmware PD_ADMA>; }; @@ -553,7 +553,7 @@ clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; - iommus = <&smmu 0x86e>; + /* iommus = <&smmu 0x86e>; */ power-domains = <&zynqmp_firmware PD_ADMA>; }; @@ -566,7 +566,7 @@ clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; - iommus = <&smmu 0x86f>; + /* iommus = <&smmu 0x86f>; */ power-domains = <&zynqmp_firmware PD_ADMA>; }; @@ -586,7 +586,7 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; - iommus = <&smmu 0x872>; + /* iommus = <&smmu 0x872>; */ power-domains = <&zynqmp_firmware PD_NAND>; }; @@ -598,7 +598,7 @@ ; reg = <0x0 0xff0b0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; - iommus = <&smmu 0x874>; + /* iommus = <&smmu 0x874>; */ power-domains = <&zynqmp_firmware PD_ETH_0>; resets = <&zynqmp_reset ZYNQMP_RESET_GEM0>; reset-names = "gem0_rst"; @@ -612,7 +612,7 @@ ; reg = <0x0 0xff0c0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; - iommus = <&smmu 0x875>; + /* iommus = <&smmu 0x875>; */ power-domains = <&zynqmp_firmware PD_ETH_1>; resets = <&zynqmp_reset ZYNQMP_RESET_GEM1>; reset-names = "gem1_rst"; @@ -626,7 +626,7 @@ ; reg = <0x0 0xff0d0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; - iommus = <&smmu 0x876>; + /* iommus = <&smmu 0x876>; */ power-domains = <&zynqmp_firmware PD_ETH_2>; resets = <&zynqmp_reset ZYNQMP_RESET_GEM2>; reset-names = "gem2_rst"; @@ -640,7 +640,7 @@ ; reg = <0x0 0xff0e0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; - iommus = <&smmu 0x877>; + /* iommus = <&smmu 0x877>; */ power-domains = <&zynqmp_firmware PD_ETH_3>; resets = <&zynqmp_reset ZYNQMP_RESET_GEM3>; reset-names = "gem3_rst"; @@ -719,7 +719,7 @@ <0x0 0x0 0x0 0x2 &pcie_intc 0x2>, <0x0 0x0 0x0 0x3 &pcie_intc 0x3>, <0x0 0x0 0x0 0x4 &pcie_intc 0x4>; - iommus = <&smmu 0x4d0>; + /* iommus = <&smmu 0x4d0>; */ power-domains = <&zynqmp_firmware PD_PCIE>; pcie_intc: legacy-interrupt-controller { interrupt-controller; @@ -740,7 +740,7 @@ <0x0 0xc0000000 0x0 0x8000000>; #address-cells = <1>; #size-cells = <0>; - iommus = <&smmu 0x873>; + /* iommus = <&smmu 0x873>; */ power-domains = <&zynqmp_firmware PD_QSPI>; }; @@ -772,8 +772,7 @@ interrupts = ; power-domains = <&zynqmp_firmware PD_SATA>; resets = <&zynqmp_reset ZYNQMP_RESET_SATA>; - iommus = <&smmu 0x4c0>, <&smmu 0x4c1>, - <&smmu 0x4c2>, <&smmu 0x4c3>; + /* iommus = <&smmu 0x4c0>, <&smmu 0x4c1>, <&smmu 0x4c2>, <&smmu 0x4c3>; */ /* dma-coherent; */ }; @@ -785,7 +784,7 @@ interrupts = ; reg = <0x0 0xff160000 0x0 0x1000>; clock-names = "clk_xin", "clk_ahb"; - iommus = <&smmu 0x870>; + /* iommus = <&smmu 0x870>; */ #clock-cells = <1>; clock-output-names = "clk_out_sd0", "clk_in_sd0"; power-domains = <&zynqmp_firmware PD_SD_0>; @@ -800,7 +799,7 @@ interrupts = ; reg = <0x0 0xff170000 0x0 0x1000>; clock-names = "clk_xin", "clk_ahb"; - iommus = <&smmu 0x871>; + /* iommus = <&smmu 0x871>; */ #clock-cells = <1>; clock-output-names = "clk_out_sd1", "clk_in_sd1"; power-domains = <&zynqmp_firmware PD_SD_1>; @@ -951,7 +950,7 @@ interrupts = , , ; - iommus = <&smmu 0x860>; + /* iommus = <&smmu 0x860>; */ snps,quirk-frame-length-adjustment = <0x20>; clock-names = "ref"; snps,enable_guctl1_ipd_quirk; @@ -983,7 +982,7 @@ interrupts = , , ; - iommus = <&smmu 0x861>; + /* iommus = <&smmu 0x861>; */ snps,quirk-frame-length-adjustment = <0x20>; clock-names = "ref"; snps,enable_guctl1_ipd_quirk; @@ -1043,6 +1042,7 @@ interrupt-parent = <&gic>; clock-names = "axi_clk"; power-domains = <&zynqmp_firmware PD_DP>; + /* iommus = <&smmu 0xce4>; */ #dma-cells = <1>; }; @@ -1057,6 +1057,7 @@ reg-names = "dp", "blend", "av_buf", "aud"; interrupts = ; interrupt-parent = <&gic>; + /* iommus = <&smmu 0xce3>; */ clock-names = "dp_apb_clk", "dp_aud_clk", "dp_vtc_pixel_clk_in"; power-domains = <&zynqmp_firmware PD_DP>; -- cgit v1.1 From 7a64be2ba259d184745147ad5163a300475b0b53 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 1 Nov 2023 12:22:13 +0100 Subject: xilinx: Enable SPI_FLASH_MTD by default Provide access to qspi flash layout via mtd command. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/b3c4a3eddb71aab9535b034380d0dbae770828d4.1698837725.git.michal.simek@amd.com --- configs/xilinx_zynq_virt_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/xilinx_zynq_virt_defconfig b/configs/xilinx_zynq_virt_defconfig index 6145af6..c3ee9be 100644 --- a/configs/xilinx_zynq_virt_defconfig +++ b/configs/xilinx_zynq_virt_defconfig @@ -127,6 +127,7 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_SST=y CONFIG_SPI_FLASH_WINBOND=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_SPI_FLASH_MTD=y CONFIG_PHY_MARVELL=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y -- cgit v1.1 From 1332a781e1ae214ee01af49454c1622cc9433517 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 1 Nov 2023 12:22:14 +0100 Subject: ARM: zynq: Add partition description Xilinx is using standard mtd partition layout for quite a long time. It is used for testing purpose on evaluation boards. Also #address/size-cells shouldn't be present without nodes which should use them that's why move them from zynq-7000.dtsi to nand/nor nodes directly. The patch was tested on zc706 and zedboard(with also increasing max frequency and rx bus width). Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/4c3348981bba32d3892194420d78fe8621c47534.1698837725.git.michal.simek@amd.com --- arch/arm/dts/bitmain-antminer-s9.dts | 2 ++ arch/arm/dts/zynq-7000.dtsi | 4 ---- arch/arm/dts/zynq-zc702.dts | 25 +++++++++++++++++++++++++ arch/arm/dts/zynq-zc706.dts | 25 +++++++++++++++++++++++++ arch/arm/dts/zynq-zc770-xm010.dts | 25 +++++++++++++++++++++++++ arch/arm/dts/zynq-zc770-xm011.dts | 19 +++++++++++++++++++ arch/arm/dts/zynq-zc770-xm012.dts | 25 +++++++++++++++++++++++++ arch/arm/dts/zynq-zc770-xm013.dts | 25 +++++++++++++++++++++++++ arch/arm/dts/zynq-zed.dts | 29 ++++++++++++++++++++++++++++- 9 files changed, 174 insertions(+), 5 deletions(-) diff --git a/arch/arm/dts/bitmain-antminer-s9.dts b/arch/arm/dts/bitmain-antminer-s9.dts index 0228b4b..f5ad95a 100644 --- a/arch/arm/dts/bitmain-antminer-s9.dts +++ b/arch/arm/dts/bitmain-antminer-s9.dts @@ -52,6 +52,8 @@ &nfc0 { status = "okay"; + #address-cells = <1>; + #size-cells = <0>; nand@0 { reg = <0>; }; diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi index fb61fe9..f8c786a 100644 --- a/arch/arm/dts/zynq-7000.dtsi +++ b/arch/arm/dts/zynq-7000.dtsi @@ -306,15 +306,11 @@ compatible = "arm,pl353-nand-r2p1"; reg = <0 0 0x1000000>; status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; }; nor0: flash@1,0 { status = "disabled"; compatible = "cfi-flash"; reg = <1 0 0x2000000>; - #address-cells = <1>; - #size-cells = <1>; }; }; diff --git a/arch/arm/dts/zynq-zc702.dts b/arch/arm/dts/zynq-zc702.dts index 8d47f24..0106d7b 100644 --- a/arch/arm/dts/zynq-zc702.dts +++ b/arch/arm/dts/zynq-zc702.dts @@ -406,6 +406,31 @@ spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <50000000>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "qspi-fsbl-uboot"; + reg = <0x0 0x100000>; + }; + partition@100000 { + label = "qspi-linux"; + reg = <0x100000 0x500000>; + }; + partition@600000 { + label = "qspi-device-tree"; + reg = <0x600000 0x20000>; + }; + partition@620000 { + label = "qspi-rootfs"; + reg = <0x620000 0x5e0000>; + }; + partition@c00000 { + label = "qspi-bitstream"; + reg = <0xc00000 0x400000>; + }; + }; }; }; diff --git a/arch/arm/dts/zynq-zc706.dts b/arch/arm/dts/zynq-zc706.dts index 18963a3..ceea982 100644 --- a/arch/arm/dts/zynq-zc706.dts +++ b/arch/arm/dts/zynq-zc706.dts @@ -317,6 +317,31 @@ spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <50000000>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "qspi-fsbl-uboot"; + reg = <0x0 0x100000>; + }; + partition@100000 { + label = "qspi-linux"; + reg = <0x100000 0x500000>; + }; + partition@600000 { + label = "qspi-device-tree"; + reg = <0x600000 0x20000>; + }; + partition@620000 { + label = "qspi-rootfs"; + reg = <0x620000 0x5e0000>; + }; + partition@c00000 { + label = "qspi-bitstream"; + reg = <0xc00000 0x400000>; + }; + }; }; }; diff --git a/arch/arm/dts/zynq-zc770-xm010.dts b/arch/arm/dts/zynq-zc770-xm010.dts index 17680d7..199384b 100644 --- a/arch/arm/dts/zynq-zc770-xm010.dts +++ b/arch/arm/dts/zynq-zc770-xm010.dts @@ -69,6 +69,31 @@ spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <50000000>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "qspi-fsbl-uboot"; + reg = <0x0 0x100000>; + }; + partition@100000 { + label = "qspi-linux"; + reg = <0x100000 0x500000>; + }; + partition@600000 { + label = "qspi-device-tree"; + reg = <0x600000 0x20000>; + }; + partition@620000 { + label = "qspi-rootfs"; + reg = <0x620000 0x5e0000>; + }; + partition@c00000 { + label = "qspi-bitstream"; + reg = <0xc00000 0x400000>; + }; + }; }; }; diff --git a/arch/arm/dts/zynq-zc770-xm011.dts b/arch/arm/dts/zynq-zc770-xm011.dts index d1e9712..f9a086f 100644 --- a/arch/arm/dts/zynq-zc770-xm011.dts +++ b/arch/arm/dts/zynq-zc770-xm011.dts @@ -49,8 +49,27 @@ &nfc0 { status = "okay"; + #address-cells = <1>; + #size-cells = <0>; nand@0 { reg = <0>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "nand-fsbl-uboot"; + reg = <0x0 0x1000000>; + }; + partition@1000000 { + label = "nand-linux"; + reg = <0x1000000 0x2000000>; + }; + partition@3000000 { + label = "nand-rootfs"; + reg = <0x3000000 0x200000>; + }; + }; }; }; diff --git a/arch/arm/dts/zynq-zc770-xm012.dts b/arch/arm/dts/zynq-zc770-xm012.dts index 6e36634..24520e7 100644 --- a/arch/arm/dts/zynq-zc770-xm012.dts +++ b/arch/arm/dts/zynq-zc770-xm012.dts @@ -56,6 +56,31 @@ &nor0 { status = "okay"; bank-width = <1>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "nor-fsbl-uboot"; + reg = <0x0 0x100000>; + }; + partition@100000 { + label = "nor-linux"; + reg = <0x100000 0x500000>; + }; + partition@600000 { + label = "nor-device-tree"; + reg = <0x600000 0x20000>; + }; + partition@620000 { + label = "nor-rootfs"; + reg = <0x620000 0x5e0000>; + }; + partition@c00000 { + label = "nor-bitstream"; + reg = <0xc00000 0x400000>; + }; + }; }; &smcc { diff --git a/arch/arm/dts/zynq-zc770-xm013.dts b/arch/arm/dts/zynq-zc770-xm013.dts index 582aa1f..add7599 100644 --- a/arch/arm/dts/zynq-zc770-xm013.dts +++ b/arch/arm/dts/zynq-zc770-xm013.dts @@ -69,6 +69,31 @@ spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <50000000>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "qspi-fsbl-uboot"; + reg = <0x0 0x100000>; + }; + partition@100000 { + label = "qspi-linux"; + reg = <0x100000 0x500000>; + }; + partition@600000 { + label = "qspi-device-tree"; + reg = <0x600000 0x20000>; + }; + partition@620000 { + label = "qspi-rootfs"; + reg = <0x620000 0x5e0000>; + }; + partition@c00000 { + label = "qspi-bitstream"; + reg = <0xc00000 0x400000>; + }; + }; }; }; diff --git a/arch/arm/dts/zynq-zed.dts b/arch/arm/dts/zynq-zed.dts index 5320b4b..70bc418 100644 --- a/arch/arm/dts/zynq-zed.dts +++ b/arch/arm/dts/zynq-zed.dts @@ -55,8 +55,35 @@ flash@0 { compatible = "spansion,s25fl256s1", "jedec,spi-nor"; reg = <0>; - spi-max-frequency = <30000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + spi-max-frequency = <50000000>; m25p,fast-read; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "qspi-fsbl-uboot"; + reg = <0x0 0x100000>; + }; + partition@100000 { + label = "qspi-linux"; + reg = <0x100000 0x500000>; + }; + partition@600000 { + label = "qspi-device-tree"; + reg = <0x600000 0x20000>; + }; + partition@620000 { + label = "qspi-rootfs"; + reg = <0x620000 0x5e0000>; + }; + partition@c00000 { + label = "qspi-bitstream"; + reg = <0xc00000 0x400000>; + }; + }; }; }; -- cgit v1.1 From 6504242df367bf1934fb6c8f0714f038e127a7e1 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 1 Nov 2023 13:06:15 +0100 Subject: arm64: zynqmp: Add description for nvmem efuse layout Based on discussion with DT folks at link below there is not going to be any name restrictions for child names. That's why add description for current nvmem layout. Link: https://lore.kernel.org/lkml/20231013101450.573-3-praveen.teja.kundanala@amd.com/ Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/af81299cafc2bd13ed30dcd69bdf6efb5fbb7f68.1698840373.git.michal.simek@amd.com --- arch/arm/dts/zynqmp.dtsi | 49 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 66d5335..58a56bc 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -214,6 +214,55 @@ soc_revision: soc-revision@0 { reg = <0x0 0x4>; }; + /* efuse access */ + efuse_dna: efuse-dna@c { + reg = <0xc 0xc>; + }; + efuse_usr0: efuse-usr0@20 { + reg = <0x20 0x4>; + }; + efuse_usr1: efuse-usr1@24 { + reg = <0x24 0x4>; + }; + efuse_usr2: efuse-usr2@28 { + reg = <0x28 0x4>; + }; + efuse_usr3: efuse-usr3@2c { + reg = <0x2c 0x4>; + }; + efuse_usr4: efuse-usr4@30 { + reg = <0x30 0x4>; + }; + efuse_usr5: efuse-usr5@34 { + reg = <0x34 0x4>; + }; + efuse_usr6: efuse-usr6@38 { + reg = <0x38 0x4>; + }; + efuse_usr7: efuse-usr7@3c { + reg = <0x3c 0x4>; + }; + efuse_miscusr: efuse-miscusr@40 { + reg = <0x40 0x4>; + }; + efuse_chash: efuse-chash@50 { + reg = <0x50 0x4>; + }; + efuse_pufmisc: efuse-pufmisc@54 { + reg = <0x54 0x4>; + }; + efuse_sec: efuse-sec@58 { + reg = <0x58 0x4>; + }; + efuse_spkid: efuse-spkid@5c { + reg = <0x5c 0x4>; + }; + efuse_ppk0hash: efuse-ppk0hash@a0 { + reg = <0xa0 0x30>; + }; + efuse_ppk1hash: efuse-ppk1hash@d0 { + reg = <0xd0 0x30>; + }; }; zynqmp_pcap: pcap { -- cgit v1.1 From 37f500d711ec1f6b25189c1f6022ffe5e70a38ab Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 1 Nov 2023 16:05:16 +0100 Subject: dt-bindings: Remove VSC8531 specific RGMII delay definitions Based on Linux upstream discussion value enumeration shouldn't be used. Instead of it delay in pS should be used that's why remove it from the header. Link: https://lore.kernel.org/all/YNsm%2F0dmpBgO8mqr@lunn.ch/ Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/bbd343474856a67252f3b31d22b3b5a80ad04043.1698851109.git.michal.simek@amd.com --- include/dt-bindings/net/mscc-phy-vsc8531.h | 9 --------- 1 file changed, 9 deletions(-) diff --git a/include/dt-bindings/net/mscc-phy-vsc8531.h b/include/dt-bindings/net/mscc-phy-vsc8531.h index 61f5287..c340437 100644 --- a/include/dt-bindings/net/mscc-phy-vsc8531.h +++ b/include/dt-bindings/net/mscc-phy-vsc8531.h @@ -28,13 +28,4 @@ #define VSC8531_FORCE_LED_OFF 14 #define VSC8531_FORCE_LED_ON 15 -#define VSC8531_RGMII_CLK_DELAY_0_2_NS 0 -#define VSC8531_RGMII_CLK_DELAY_0_8_NS 1 -#define VSC8531_RGMII_CLK_DELAY_1_1_NS 2 -#define VSC8531_RGMII_CLK_DELAY_1_7_NS 3 -#define VSC8531_RGMII_CLK_DELAY_2_0_NS 4 -#define VSC8531_RGMII_CLK_DELAY_2_3_NS 5 -#define VSC8531_RGMII_CLK_DELAY_2_6_NS 6 -#define VSC8531_RGMII_CLK_DELAY_3_4_NS 7 - #endif -- cgit v1.1