From 110d321a56c3ea1824104ea6148efe040adf995d Mon Sep 17 00:00:00 2001 From: Benjamin Hahn Date: Wed, 6 Mar 2024 17:18:31 +0100 Subject: board: phytec: common: phytec_som_detection: Add phytec_get_som_type Add a function that gets the som_type from the EEPROM. Add an enum for the som_type. Signed-off-by: Benjamin Hahn --- board/phytec/common/phytec_som_detection.c | 10 ++++++++++ board/phytec/common/phytec_som_detection.h | 8 ++++++++ 2 files changed, 18 insertions(+) diff --git a/board/phytec/common/phytec_som_detection.c b/board/phytec/common/phytec_som_detection.c index c73bf97..f9607b0 100644 --- a/board/phytec/common/phytec_som_detection.c +++ b/board/phytec/common/phytec_som_detection.c @@ -203,6 +203,16 @@ u8 __maybe_unused phytec_get_rev(struct phytec_eeprom_data *data) return api2->pcb_rev; } +u8 __maybe_unused phytec_get_som_type(struct phytec_eeprom_data *data) +{ + if (!data) + data = &eeprom_data; + if (data->api_rev < PHYTEC_API_REV2) + return PHYTEC_EEPROM_INVAL; + + return data->data.data_api2.som_type; +} + #else inline int phytec_eeprom_data_setup(struct phytec_eeprom_data *data, diff --git a/board/phytec/common/phytec_som_detection.h b/board/phytec/common/phytec_som_detection.h index 1100924..7edbfa3 100644 --- a/board/phytec/common/phytec_som_detection.h +++ b/board/phytec/common/phytec_som_detection.h @@ -19,6 +19,13 @@ enum { PHYTEC_API_REV2, }; +enum phytec_som_type_str { + SOM_TYPE_PCM = 0, + SOM_TYPE_PCL, + SOM_TYPE_KSM, + SOM_TYPE_KSP, +}; + static const char * const phytec_som_type_str[] = { "PCM", "PCL", @@ -67,5 +74,6 @@ void __maybe_unused phytec_print_som_info(struct phytec_eeprom_data *data); char * __maybe_unused phytec_get_opt(struct phytec_eeprom_data *data); u8 __maybe_unused phytec_get_rev(struct phytec_eeprom_data *data); +u8 __maybe_unused phytec_get_som_type(struct phytec_eeprom_data *data); #endif /* _PHYTEC_SOM_DETECTION_H */ -- cgit v1.1 From 76832300a9c8b4a61cb7a49e0b9779e931abbc37 Mon Sep 17 00:00:00 2001 From: Benjamin Hahn Date: Wed, 6 Mar 2024 17:18:32 +0100 Subject: board: phycore_imx8mp: Use 2GHz RAM timings for PCL-070 from pcb_rev 1 We need to differ between PCL-070 and PCM-070. PCL-070 supports 2GHz RAM timings from pcb rev 1 or newer. PCM-070 supports 2GHz RAM timings from pcb rev 3 or newer. Signed-off-by: Benjamin Hahn --- board/phytec/phycore_imx8mp/spl.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/board/phytec/phycore_imx8mp/spl.c b/board/phytec/phycore_imx8mp/spl.c index d38f636..df15802 100644 --- a/board/phytec/phycore_imx8mp/spl.c +++ b/board/phytec/phycore_imx8mp/spl.c @@ -46,8 +46,10 @@ void spl_dram_init(void) if (!ret) phytec_print_som_info(NULL); - ret = phytec_get_rev(NULL); - if (ret >= 3 && ret != PHYTEC_EEPROM_INVAL) { + u8 rev = phytec_get_rev(NULL); + u8 somtype = phytec_get_som_type(NULL); + + if (rev != PHYTEC_EEPROM_INVAL && (rev >= 3 || (somtype == SOM_TYPE_PCL && rev >= 1))) { dram_timing.ddrc_cfg[3].val = 0x1323; dram_timing.ddrc_cfg[4].val = 0x1e84800; dram_timing.ddrc_cfg[5].val = 0x7a0118; -- cgit v1.1 From 383d4b130c603d88e57e97091d03d1fd733e1403 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Thu, 7 Mar 2024 05:58:58 -0600 Subject: configs: imx8mp_beacon: Fall back to using TF-A When the board was originally added, it enabled some features which allowed it to bypass Trusted Firmware, but as the feature set of Linux grew and more features became available, the U-Boot config options which bypassed TF-A caused issues, so it needs to return to the standard operating mode of using TF-A or the system no longer boots. Fixes: ab53bd43dbde ("arm64: imx: Add support for imx8mp-beacon-kit") Signed-off-by: Adam Ford Reviewed-by: Fabio Estevam --- configs/imx8mp_beacon_defconfig | 7 ------- 1 file changed, 7 deletions(-) diff --git a/configs/imx8mp_beacon_defconfig b/configs/imx8mp_beacon_defconfig index 29162ac..9d09dd4 100644 --- a/configs/imx8mp_beacon_defconfig +++ b/configs/imx8mp_beacon_defconfig @@ -14,7 +14,6 @@ CONFIG_ENV_OFFSET=0xFFFFDE00 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx8mp-beacon-kit" CONFIG_SPL_TEXT_BASE=0x920000 -CONFIG_SYS_HAS_ARMV8_SECURE_BASE=y CONFIG_TARGET_IMX8MP_BEACON=y CONFIG_SYS_MONITOR_LEN=524288 CONFIG_SPL_MMC=y @@ -23,13 +22,8 @@ CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK=0x960000 CONFIG_SPL=y CONFIG_ARMV8_SPL_EXCEPTION_VECTORS=y -CONFIG_ARMV8_MULTIENTRY=y CONFIG_ARMV8_SET_SMPEN=y # CONFIG_PSCI_RESET is not set -CONFIG_ARMV8_PSCI=y -CONFIG_ARMV8_PSCI_CPUS_PER_CLUSTER=4 -CONFIG_ARMV8_PSCI_RELOCATE=y -CONFIG_ARMV8_SECURE_BASE=0x970000 CONFIG_ARMV8_EA_EL3_FIRST=y CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 CONFIG_SYS_LOAD_ADDR=0x40480000 @@ -85,7 +79,6 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_DEV=2 CONFIG_SYS_MMC_ENV_PART=2 -CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eth1" CONFIG_SPL_DM=y -- cgit v1.1 From 12d3257fa275f1d143f7e3cfc344f3ad04607a66 Mon Sep 17 00:00:00 2001 From: Joao Paulo Goncalves Date: Fri, 8 Mar 2024 11:18:01 -0300 Subject: toradex: tdx-cfg-block: add 0087 i.mx8m mini product variant Add new product id 0087 Verdin iMX8M Mini Quad 2GB IT. Signed-off-by: Joao Paulo Goncalves --- board/toradex/common/tdx-cfg-block.c | 1 + board/toradex/common/tdx-cfg-block.h | 1 + 2 files changed, 2 insertions(+) diff --git a/board/toradex/common/tdx-cfg-block.c b/board/toradex/common/tdx-cfg-block.c index 4a7de54..dcf00d2 100644 --- a/board/toradex/common/tdx-cfg-block.c +++ b/board/toradex/common/tdx-cfg-block.c @@ -157,6 +157,7 @@ const struct toradex_som toradex_modules[] = { [84] = { "Apalis iMX6D 1GB IT", TARGET_IS_ENABLED(APALIS_IMX6) }, [85] = { "Apalis iMX6Q 2GB IT", TARGET_IS_ENABLED(APALIS_IMX6) }, [86] = { "Verdin iMX8M Mini DualLite 2GB IT", TARGET_IS_ENABLED(VERDIN_IMX8MM) }, + [87] = { "Verdin iMX8M Mini Quad 2GB IT", TARGET_IS_ENABLED(VERDIN_IMX8MM) }, }; struct pid4list { diff --git a/board/toradex/common/tdx-cfg-block.h b/board/toradex/common/tdx-cfg-block.h index 021cc21..183ee0f 100644 --- a/board/toradex/common/tdx-cfg-block.h +++ b/board/toradex/common/tdx-cfg-block.h @@ -112,6 +112,7 @@ enum { APALIS_IMX6D_IT_NOWINCE, APALIS_IMX6Q_IT_NOWINCE, /* 85 */ VERDIN_IMX8MMDL_2G_IT, + VERDIN_IMX8MMQ_2G_IT_NO_CAN, }; enum { -- cgit v1.1 From 4484c7b3c38dcb21244a882d0b81d141db1ed162 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Sun, 10 Mar 2024 11:59:01 -0500 Subject: arm: dts: imx8mp-beacon-kit: Resync DTS with Linux 6.8 The device tree has evolved over time, so re-sync. This also partial reverts one change on the PCIe, because U-Boot doesn't have a proper driver. However, since the clock is configured to generate a 100MHz reference clock by default, a proper driver isn't really necessary. Signed-off-by: Adam Ford Acked-by: Peng Fan --- arch/arm/dts/imx8mp-beacon-kit-u-boot.dtsi | 11 ++ arch/arm/dts/imx8mp-beacon-kit.dts | 245 ++++++++++++++++++++++++++++- arch/arm/dts/imx8mp-beacon-som.dtsi | 71 +++++++++ 3 files changed, 321 insertions(+), 6 deletions(-) diff --git a/arch/arm/dts/imx8mp-beacon-kit-u-boot.dtsi b/arch/arm/dts/imx8mp-beacon-kit-u-boot.dtsi index 393fd8e..ed183f8 100644 --- a/arch/arm/dts/imx8mp-beacon-kit-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-beacon-kit-u-boot.dtsi @@ -6,6 +6,13 @@ #include "imx8mp-u-boot.dtsi" / { + /* U-Boot does not yet have a proper PCIe clk driver */ + pcie0_refclk: clock-pcie { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + wdt-reboot { compatible = "wdt-reboot"; wdt = <&wdog1>; @@ -13,6 +20,10 @@ }; }; +&pcie_phy { + clocks = <&pcie0_refclk>; +}; + &{/soc@0/bus@30800000/i2c@30a20000/pmic@25} { bootph-pre-ram; }; diff --git a/arch/arm/dts/imx8mp-beacon-kit.dts b/arch/arm/dts/imx8mp-beacon-kit.dts index cdae45a..a080574 100644 --- a/arch/arm/dts/imx8mp-beacon-kit.dts +++ b/arch/arm/dts/imx8mp-beacon-kit.dts @@ -23,6 +23,12 @@ stdout-path = &uart2; }; + clk_xtal25: clock-xtal25 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + connector { compatible = "usb-c-connector"; label = "USB-C"; @@ -49,6 +55,12 @@ }; }; + dmic_codec: dmic-codec { + compatible = "dmic-codec"; + num-channels = <1>; + #sound-dai-cells = <0>; + }; + gpio-keys { compatible = "gpio-keys"; autorepeat; @@ -82,6 +94,17 @@ }; }; + bridge-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con: endpoint { + remote-endpoint = <&adv7535_out>; + }; + }; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -112,10 +135,13 @@ }; }; - pcie0_refclk: clock-pcie { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <100000000>; + reg_audio: regulator-wm8962 { + compatible = "regulator-fixed"; + regulator-name = "3v3_aud"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca6416_1 11 GPIO_ACTIVE_HIGH>; + enable-active-high; }; reg_usdhc2_vmmc: regulator-usdhc2 { @@ -137,6 +163,68 @@ gpio = <&pca6416_1 0 GPIO_ACTIVE_HIGH>; enable-active-high; }; + + sound-adv7535 { + compatible = "simple-audio-card"; + simple-audio-card,name = "sound-adv7535"; + simple-audio-card,format = "i2s"; + + simple-audio-card,cpu { + sound-dai = <&sai5>; + system-clock-direction-out; + }; + + simple-audio-card,codec { + sound-dai = <&adv_bridge>; + }; + }; + + sound-dmic { + compatible = "simple-audio-card"; + simple-audio-card,name = "sound-pdm"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&dailink_master>; + simple-audio-card,frame-master = <&dailink_master>; + + dailink_master: simple-audio-card,cpu { + sound-dai = <&micfil>; + }; + + simple-audio-card,codec { + sound-dai = <&dmic_codec>; + }; + }; + + sound-wm8962 { + compatible = "simple-audio-card"; + simple-audio-card,name = "wm8962"; + simple-audio-card,format = "i2s"; + simple-audio-card,widgets = "Headphone", "Headphones", + "Microphone", "Headset Mic", + "Speaker", "Speaker"; + simple-audio-card,routing = "Headphones", "HPOUTL", + "Headphones", "HPOUTR", + "Speaker", "SPKOUTL", + "Speaker", "SPKOUTR", + "Headset Mic", "MICBIAS", + "IN3R", "Headset Mic"; + + simple-audio-card,cpu { + sound-dai = <&sai3>; + }; + + simple-audio-card,codec { + sound-dai = <&wm8962>; + clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO1>; + frame-master; + bitclock-master; + }; + }; +}; + +&audio_blk_ctrl { + assigned-clocks = <&clk IMX8MP_AUDIO_PLL1>, <&clk IMX8MP_AUDIO_PLL2>; + assigned-clock-rates = <393216000>, <135475200>; }; &ecspi2 { @@ -146,7 +234,7 @@ status = "okay"; tpm: tpm@0 { - compatible = "infineon,slb9670"; + compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; reg = <0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_tpm>; @@ -211,6 +299,42 @@ interrupt-controller; #interrupt-cells = <2>; }; + + adv_bridge: hdmi@3d { + compatible = "adi,adv7535"; + reg = <0x3d>, <0x3c>, <0x3e>, <0x3f>; + reg-names = "main", "cec", "edid", "packet"; + adi,dsi-lanes = <4>; + #sound-dai-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + adv7535_in: endpoint { + remote-endpoint = <&dsi_out>; + }; + }; + + port@1 { + reg = <1>; + + adv7535_out: endpoint { + remote-endpoint = <&hdmi_con>; + }; + }; + }; + }; + + pcieclk: clock-generator@68 { + compatible = "renesas,9fgv0241"; + reg = <0x68>; + clocks = <&clk_xtal25>; + #clock-cells = <1>; + }; }; &i2c3 { @@ -239,6 +363,34 @@ clock-frequency = <384000>; status = "okay"; + wm8962: audio-codec@1a { + compatible = "wlf,wm8962"; + reg = <0x1a>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wm8962>; + clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO1>; + assigned-clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO1>; + assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL2_OUT>; + assigned-clock-rates = <22576000>; + DCVDD-supply = <®_audio>; + DBVDD-supply = <®_audio>; + AVDD-supply = <®_audio>; + CPVDD-supply = <®_audio>; + MICVDD-supply = <®_audio>; + PLLVDD-supply = <®_audio>; + SPKVDD1-supply = <®_audio>; + SPKVDD2-supply = <®_audio>; + gpio-cfg = < + 0x0000 /* 0:Default */ + 0x0000 /* 1:Default */ + 0x0000 /* 2:FN_DMICCLK */ + 0x0000 /* 3:Default */ + 0x0000 /* 4:FN_DMICCDAT */ + 0x0000 /* 5:Default */ + >; + #sound-dai-cells = <0>; + }; + pca6416: gpio@20 { compatible = "nxp,pcal6416"; reg = <0x20>; @@ -301,6 +453,34 @@ }; }; +&lcdif1 { + status = "okay"; +}; + +&micfil { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pdm>; + assigned-clocks = <&clk IMX8MP_CLK_PDM>; + assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; + assigned-clock-rates = <49152000>; + status = "okay"; +}; + +&mipi_dsi { + samsung,esc-clock-frequency = <10000000>; + status = "okay"; + + ports { + port@1 { + reg = <1>; + + dsi_out: endpoint { + remote-endpoint = <&adv7535_in>; + }; + }; + }; +}; + &pcie { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pcie>; @@ -309,12 +489,34 @@ }; &pcie_phy { + fsl,clkreq-unsupported; fsl,refclk-pad-mode = ; - clocks = <&pcie0_refclk>; + clocks = <&pcieclk 1>; clock-names = "ref"; status = "okay"; }; +&sai3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3>; + assigned-clocks = <&clk IMX8MP_CLK_SAI3>, + <&clk IMX8MP_AUDIO_PLL2> ; + assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL2_OUT>; + assigned-clock-rates = <12288000>, <361267200>; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + +&sai5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai5>; + assigned-clocks = <&clk IMX8MP_CLK_SAI5>; + assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; + assigned-clock-rates = <12288000>; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + &snvs_pwrkey { status = "okay"; }; @@ -471,12 +673,37 @@ >; }; + pinctrl_pdm: pdmgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_RXC__AUDIOMIX_PDM_CLK 0xd6 + MX8MP_IOMUXC_SAI5_RXD0__AUDIOMIX_PDM_BIT_STREAM00 0xd6 + >; + }; + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { fsl,pins = < MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40 >; }; + pinctrl_sai3: sai3grp { + fsl,pins = < + MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0xd6 + MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0xd6 + MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0xd6 + MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0xd6 + MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK 0xd6 + >; + }; + + pinctrl_sai5: sai5grp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_SAI5_TX_DATA00 0xd6 + MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_SAI5_TX_BCLK 0xd6 + MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI5_TX_SYNC 0xd6 + >; + }; + pinctrl_tpm: tpmgrp { fsl,pins = < MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00 0x19 /* Reset */ @@ -547,4 +774,10 @@ MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 >; }; + + pinctrl_wm8962: wm8962grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO14__CCM_CLKO1 0x59 + >; + }; }; diff --git a/arch/arm/dts/imx8mp-beacon-som.dtsi b/arch/arm/dts/imx8mp-beacon-som.dtsi index e5da908..8be251b 100644 --- a/arch/arm/dts/imx8mp-beacon-som.dtsi +++ b/arch/arm/dts/imx8mp-beacon-som.dtsi @@ -50,6 +50,8 @@ phy-mode = "rgmii-id"; phy-handle = <ðphy0>; snps,force_thresh_dma_mode; + snps,mtl-rx-config = <&mtl_rx_setup>; + snps,mtl-tx-config = <&mtl_tx_setup>; status = "okay"; mdio { @@ -66,6 +68,71 @@ interrupts = <10 IRQ_TYPE_LEVEL_LOW>; }; }; + + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <5>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,priority = <0x1>; + snps,map-to-dma-channel = <0>; + }; + + queue1 { + snps,dcb-algorithm; + snps,priority = <0x2>; + snps,map-to-dma-channel = <1>; + }; + + queue2 { + snps,dcb-algorithm; + snps,priority = <0x4>; + snps,map-to-dma-channel = <2>; + }; + + queue3 { + snps,dcb-algorithm; + snps,priority = <0x8>; + snps,map-to-dma-channel = <3>; + }; + + queue4 { + snps,dcb-algorithm; + snps,priority = <0xf0>; + snps,map-to-dma-channel = <4>; + }; + }; + + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <5>; + snps,tx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,priority = <0x1>; + }; + + queue1 { + snps,dcb-algorithm; + snps,priority = <0x2>; + }; + + queue2 { + snps,dcb-algorithm; + snps,priority = <0x4>; + }; + + queue3 { + snps,dcb-algorithm; + snps,priority = <0x8>; + }; + + queue4 { + snps,dcb-algorithm; + snps,priority = <0xf0>; + }; + }; }; &flexspi { @@ -206,6 +273,10 @@ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; uart-has-rtscts; status = "okay"; + + bluetooth { + compatible = "nxp,88w8997-bt"; + }; }; &usdhc1 { -- cgit v1.1