From d171c70716d49f0e14eb357ab645c8e72b791ca1 Mon Sep 17 00:00:00 2001 From: York Sun Date: Mon, 5 Nov 2018 18:01:06 +0000 Subject: move data structure out of cpu.h Move static definitions to cpu.c file, as it doesn't allow the cpu.h file to be included in multiple c files. Signed-off-by: York Sun --- arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 297 ++++++++++++++++++++++++ arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 300 ------------------------- 2 files changed, 297 insertions(+), 300 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index be00bd5..e01b029 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -33,6 +33,303 @@ DECLARE_GLOBAL_DATA_PTR; +static struct cpu_type cpu_type_list[] = { + CPU_TYPE_ENTRY(LS2080A, LS2080A, 8), + CPU_TYPE_ENTRY(LS2085A, LS2085A, 8), + CPU_TYPE_ENTRY(LS2045A, LS2045A, 4), + CPU_TYPE_ENTRY(LS2088A, LS2088A, 8), + CPU_TYPE_ENTRY(LS2084A, LS2084A, 8), + CPU_TYPE_ENTRY(LS2048A, LS2048A, 4), + CPU_TYPE_ENTRY(LS2044A, LS2044A, 4), + CPU_TYPE_ENTRY(LS2081A, LS2081A, 8), + CPU_TYPE_ENTRY(LS2041A, LS2041A, 4), + CPU_TYPE_ENTRY(LS1043A, LS1043A, 4), + CPU_TYPE_ENTRY(LS1023A, LS1023A, 2), + CPU_TYPE_ENTRY(LS1046A, LS1046A, 4), + CPU_TYPE_ENTRY(LS1026A, LS1026A, 2), + CPU_TYPE_ENTRY(LS2040A, LS2040A, 4), + CPU_TYPE_ENTRY(LS1012A, LS1012A, 1), + CPU_TYPE_ENTRY(LS1088A, LS1088A, 8), + CPU_TYPE_ENTRY(LS1084A, LS1084A, 8), + CPU_TYPE_ENTRY(LS1048A, LS1048A, 4), + CPU_TYPE_ENTRY(LS1044A, LS1044A, 4), +}; + +#define EARLY_PGTABLE_SIZE 0x5000 +static struct mm_region early_map[] = { +#ifdef CONFIG_FSL_LSCH3 + { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE, + CONFIG_SYS_FSL_CCSR_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, + { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, + SYS_FSL_OCRAM_SPACE_SIZE, + PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE + }, + { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1, + CONFIG_SYS_FSL_QSPI_SIZE1, + PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE}, +#ifdef CONFIG_FSL_IFC + /* For IFC Region #1, only the first 4MB is cache-enabled */ + { CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_BASE1, + CONFIG_SYS_FSL_IFC_SIZE1_1, + PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE + }, + { CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1, + CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1, + CONFIG_SYS_FSL_IFC_SIZE1 - CONFIG_SYS_FSL_IFC_SIZE1_1, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE + }, + { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1, + CONFIG_SYS_FSL_IFC_SIZE1, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE + }, +#endif + { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, + CONFIG_SYS_FSL_DRAM_SIZE1, +#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) + PTE_BLOCK_MEMTYPE(MT_NORMAL) | +#else /* Start with nGnRnE and PXN and UXN to prevent speculative access */ + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN | +#endif + PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS + }, +#ifdef CONFIG_FSL_IFC + /* Map IFC region #2 up to CONFIG_SYS_FLASH_BASE for NAND boot */ + { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2, + CONFIG_SYS_FLASH_BASE - CONFIG_SYS_FSL_IFC_BASE2, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE + }, +#endif + { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, + CONFIG_SYS_FSL_DCSR_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, + { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, + CONFIG_SYS_FSL_DRAM_SIZE2, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN | + PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS + }, +#elif defined(CONFIG_FSL_LSCH2) + { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE, + CONFIG_SYS_FSL_CCSR_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, + { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, + SYS_FSL_OCRAM_SPACE_SIZE, + PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE + }, + { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, + CONFIG_SYS_FSL_DCSR_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, + { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE, + CONFIG_SYS_FSL_QSPI_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE + }, +#ifdef CONFIG_FSL_IFC + { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE, + CONFIG_SYS_FSL_IFC_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE + }, +#endif + { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, + CONFIG_SYS_FSL_DRAM_SIZE1, +#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) + PTE_BLOCK_MEMTYPE(MT_NORMAL) | +#else /* Start with nGnRnE and PXN and UXN to prevent speculative access */ + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN | +#endif + PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS + }, + { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, + CONFIG_SYS_FSL_DRAM_SIZE2, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN | + PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS + }, +#endif + {}, /* list terminator */ +}; + +static struct mm_region final_map[] = { +#ifdef CONFIG_FSL_LSCH3 + { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE, + CONFIG_SYS_FSL_CCSR_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, + { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, + SYS_FSL_OCRAM_SPACE_SIZE, + PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE + }, + { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, + CONFIG_SYS_FSL_DRAM_SIZE1, + PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS + }, + { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1, + CONFIG_SYS_FSL_QSPI_SIZE1, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, + { CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2, + CONFIG_SYS_FSL_QSPI_SIZE2, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, +#ifdef CONFIG_FSL_IFC + { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2, + CONFIG_SYS_FSL_IFC_SIZE2, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, +#endif + { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, + CONFIG_SYS_FSL_DCSR_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, + { CONFIG_SYS_FSL_MC_BASE, CONFIG_SYS_FSL_MC_BASE, + CONFIG_SYS_FSL_MC_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, + { CONFIG_SYS_FSL_NI_BASE, CONFIG_SYS_FSL_NI_BASE, + CONFIG_SYS_FSL_NI_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, + /* For QBMAN portal, only the first 64MB is cache-enabled */ + { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE, + CONFIG_SYS_FSL_QBMAN_SIZE_1, + PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN | PTE_BLOCK_NS + }, + { CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1, + CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1, + CONFIG_SYS_FSL_QBMAN_SIZE - CONFIG_SYS_FSL_QBMAN_SIZE_1, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, + { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR, + CONFIG_SYS_PCIE1_PHYS_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, + { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR, + CONFIG_SYS_PCIE2_PHYS_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, + { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR, + CONFIG_SYS_PCIE3_PHYS_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, +#ifdef CONFIG_ARCH_LS2080A + { CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR, + CONFIG_SYS_PCIE4_PHYS_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, +#endif + { CONFIG_SYS_FSL_WRIOP1_BASE, CONFIG_SYS_FSL_WRIOP1_BASE, + CONFIG_SYS_FSL_WRIOP1_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, + { CONFIG_SYS_FSL_AIOP1_BASE, CONFIG_SYS_FSL_AIOP1_BASE, + CONFIG_SYS_FSL_AIOP1_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, + { CONFIG_SYS_FSL_PEBUF_BASE, CONFIG_SYS_FSL_PEBUF_BASE, + CONFIG_SYS_FSL_PEBUF_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, + { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, + CONFIG_SYS_FSL_DRAM_SIZE2, + PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS + }, +#elif defined(CONFIG_FSL_LSCH2) + { CONFIG_SYS_FSL_BOOTROM_BASE, CONFIG_SYS_FSL_BOOTROM_BASE, + CONFIG_SYS_FSL_BOOTROM_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, + { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE, + CONFIG_SYS_FSL_CCSR_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, + { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, + SYS_FSL_OCRAM_SPACE_SIZE, + PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE + }, + { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, + CONFIG_SYS_FSL_DCSR_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, + { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE, + CONFIG_SYS_FSL_QSPI_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, +#ifdef CONFIG_FSL_IFC + { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE, + CONFIG_SYS_FSL_IFC_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE + }, +#endif + { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, + CONFIG_SYS_FSL_DRAM_SIZE1, + PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS + }, + { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE, + CONFIG_SYS_FSL_QBMAN_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, + { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, + CONFIG_SYS_FSL_DRAM_SIZE2, + PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS + }, + { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR, + CONFIG_SYS_PCIE1_PHYS_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, + { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR, + CONFIG_SYS_PCIE2_PHYS_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, + { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR, + CONFIG_SYS_PCIE3_PHYS_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, + { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3, + CONFIG_SYS_FSL_DRAM_SIZE3, + PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS + }, +#endif +#ifdef CONFIG_SYS_MEM_RESERVE_SECURE + {}, /* space holder for secure mem */ +#endif + {}, +}; + struct mm_region *mem_map = early_map; void cpu_name(char *name) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h index 48d0ab1..3926aa3 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h @@ -7,30 +7,6 @@ #ifndef _FSL_LAYERSCAPE_CPU_H #define _FSL_LAYERSCAPE_CPU_H -static struct cpu_type cpu_type_list[] = { - CPU_TYPE_ENTRY(LS2080A, LS2080A, 8), - CPU_TYPE_ENTRY(LS2085A, LS2085A, 8), - CPU_TYPE_ENTRY(LS2045A, LS2045A, 4), - CPU_TYPE_ENTRY(LS2088A, LS2088A, 8), - CPU_TYPE_ENTRY(LS2084A, LS2084A, 8), - CPU_TYPE_ENTRY(LS2048A, LS2048A, 4), - CPU_TYPE_ENTRY(LS2044A, LS2044A, 4), - CPU_TYPE_ENTRY(LS2081A, LS2081A, 8), - CPU_TYPE_ENTRY(LS2041A, LS2041A, 4), - CPU_TYPE_ENTRY(LS1043A, LS1043A, 4), - CPU_TYPE_ENTRY(LS1023A, LS1023A, 2), - CPU_TYPE_ENTRY(LS1046A, LS1046A, 4), - CPU_TYPE_ENTRY(LS1026A, LS1026A, 2), - CPU_TYPE_ENTRY(LS2040A, LS2040A, 4), - CPU_TYPE_ENTRY(LS1012A, LS1012A, 1), - CPU_TYPE_ENTRY(LS1088A, LS1088A, 8), - CPU_TYPE_ENTRY(LS1084A, LS1084A, 8), - CPU_TYPE_ENTRY(LS1048A, LS1048A, 4), - CPU_TYPE_ENTRY(LS1044A, LS1044A, 4), -}; - -#ifndef CONFIG_SYS_DCACHE_OFF - #ifdef CONFIG_FSL_LSCH3 #define CONFIG_SYS_FSL_CCSR_BASE 0x00000000 #define CONFIG_SYS_FSL_CCSR_SIZE 0x10000000 @@ -90,282 +66,6 @@ static struct cpu_type cpu_type_list[] = { #define CONFIG_SYS_FSL_DRAM_SIZE3 0x7800000000 /* 480GB */ #endif -#define EARLY_PGTABLE_SIZE 0x5000 -static struct mm_region early_map[] = { -#ifdef CONFIG_FSL_LSCH3 - { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE, - CONFIG_SYS_FSL_CCSR_SIZE, - PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, - { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, - SYS_FSL_OCRAM_SPACE_SIZE, - PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE - }, - { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1, - CONFIG_SYS_FSL_QSPI_SIZE1, - PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE}, -#ifdef CONFIG_FSL_IFC - /* For IFC Region #1, only the first 4MB is cache-enabled */ - { CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_BASE1, - CONFIG_SYS_FSL_IFC_SIZE1_1, - PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE - }, - { CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1, - CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1, - CONFIG_SYS_FSL_IFC_SIZE1 - CONFIG_SYS_FSL_IFC_SIZE1_1, - PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE - }, - { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1, - CONFIG_SYS_FSL_IFC_SIZE1, - PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE - }, -#endif - { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, - CONFIG_SYS_FSL_DRAM_SIZE1, -#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) - PTE_BLOCK_MEMTYPE(MT_NORMAL) | -#else /* Start with nGnRnE and PXN and UXN to prevent speculative access */ - PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN | -#endif - PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS - }, -#ifdef CONFIG_FSL_IFC - /* Map IFC region #2 up to CONFIG_SYS_FLASH_BASE for NAND boot */ - { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2, - CONFIG_SYS_FLASH_BASE - CONFIG_SYS_FSL_IFC_BASE2, - PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE - }, -#endif - { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, - CONFIG_SYS_FSL_DCSR_SIZE, - PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, - { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, - CONFIG_SYS_FSL_DRAM_SIZE2, - PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN | - PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS - }, -#elif defined(CONFIG_FSL_LSCH2) - { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE, - CONFIG_SYS_FSL_CCSR_SIZE, - PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, - { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, - SYS_FSL_OCRAM_SPACE_SIZE, - PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE - }, - { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, - CONFIG_SYS_FSL_DCSR_SIZE, - PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, - { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE, - CONFIG_SYS_FSL_QSPI_SIZE, - PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE - }, -#ifdef CONFIG_FSL_IFC - { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE, - CONFIG_SYS_FSL_IFC_SIZE, - PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE - }, -#endif - { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, - CONFIG_SYS_FSL_DRAM_SIZE1, -#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) - PTE_BLOCK_MEMTYPE(MT_NORMAL) | -#else /* Start with nGnRnE and PXN and UXN to prevent speculative access */ - PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN | -#endif - PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS - }, - { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, - CONFIG_SYS_FSL_DRAM_SIZE2, - PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN | - PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS - }, -#endif - {}, /* list terminator */ -}; - -static struct mm_region final_map[] = { -#ifdef CONFIG_FSL_LSCH3 - { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE, - CONFIG_SYS_FSL_CCSR_SIZE, - PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, - { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, - SYS_FSL_OCRAM_SPACE_SIZE, - PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE - }, - { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, - CONFIG_SYS_FSL_DRAM_SIZE1, - PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS - }, - { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1, - CONFIG_SYS_FSL_QSPI_SIZE1, - PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, - { CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2, - CONFIG_SYS_FSL_QSPI_SIZE2, - PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, -#ifdef CONFIG_FSL_IFC - { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2, - CONFIG_SYS_FSL_IFC_SIZE2, - PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, -#endif - { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, - CONFIG_SYS_FSL_DCSR_SIZE, - PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, - { CONFIG_SYS_FSL_MC_BASE, CONFIG_SYS_FSL_MC_BASE, - CONFIG_SYS_FSL_MC_SIZE, - PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, - { CONFIG_SYS_FSL_NI_BASE, CONFIG_SYS_FSL_NI_BASE, - CONFIG_SYS_FSL_NI_SIZE, - PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, - /* For QBMAN portal, only the first 64MB is cache-enabled */ - { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE, - CONFIG_SYS_FSL_QBMAN_SIZE_1, - PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN | PTE_BLOCK_NS - }, - { CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1, - CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1, - CONFIG_SYS_FSL_QBMAN_SIZE - CONFIG_SYS_FSL_QBMAN_SIZE_1, - PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, - { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR, - CONFIG_SYS_PCIE1_PHYS_SIZE, - PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, - { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR, - CONFIG_SYS_PCIE2_PHYS_SIZE, - PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, - { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR, - CONFIG_SYS_PCIE3_PHYS_SIZE, - PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, -#ifdef CONFIG_ARCH_LS2080A - { CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR, - CONFIG_SYS_PCIE4_PHYS_SIZE, - PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, -#endif - { CONFIG_SYS_FSL_WRIOP1_BASE, CONFIG_SYS_FSL_WRIOP1_BASE, - CONFIG_SYS_FSL_WRIOP1_SIZE, - PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, - { CONFIG_SYS_FSL_AIOP1_BASE, CONFIG_SYS_FSL_AIOP1_BASE, - CONFIG_SYS_FSL_AIOP1_SIZE, - PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, - { CONFIG_SYS_FSL_PEBUF_BASE, CONFIG_SYS_FSL_PEBUF_BASE, - CONFIG_SYS_FSL_PEBUF_SIZE, - PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, - { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, - CONFIG_SYS_FSL_DRAM_SIZE2, - PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS - }, -#elif defined(CONFIG_FSL_LSCH2) - { CONFIG_SYS_FSL_BOOTROM_BASE, CONFIG_SYS_FSL_BOOTROM_BASE, - CONFIG_SYS_FSL_BOOTROM_SIZE, - PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, - { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE, - CONFIG_SYS_FSL_CCSR_SIZE, - PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, - { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, - SYS_FSL_OCRAM_SPACE_SIZE, - PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE - }, - { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, - CONFIG_SYS_FSL_DCSR_SIZE, - PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, - { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE, - CONFIG_SYS_FSL_QSPI_SIZE, - PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, -#ifdef CONFIG_FSL_IFC - { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE, - CONFIG_SYS_FSL_IFC_SIZE, - PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE - }, -#endif - { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, - CONFIG_SYS_FSL_DRAM_SIZE1, - PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS - }, - { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE, - CONFIG_SYS_FSL_QBMAN_SIZE, - PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, - { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, - CONFIG_SYS_FSL_DRAM_SIZE2, - PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS - }, - { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR, - CONFIG_SYS_PCIE1_PHYS_SIZE, - PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, - { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR, - CONFIG_SYS_PCIE2_PHYS_SIZE, - PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, - { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR, - CONFIG_SYS_PCIE3_PHYS_SIZE, - PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, - { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3, - CONFIG_SYS_FSL_DRAM_SIZE3, - PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS - }, -#endif -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE - {}, /* space holder for secure mem */ -#endif - {}, -}; -#endif /* !CONFIG_SYS_DCACHE_OFF */ - int fsl_qoriq_core_to_cluster(unsigned int core); u32 cpu_mask(void); -- cgit v1.1 From b6cba297affba968a8d8465655c71cb3ec8a9bde Mon Sep 17 00:00:00 2001 From: Rajesh Bhagat Date: Mon, 5 Nov 2018 18:01:10 +0000 Subject: env: allow flash and nand env driver to compile together Define env_ptr as static in flash and nand env driver to allow these to compile together. Signed-off-by: Rajesh Bhagat Reviewed-by: York Sun --- env/flash.c | 12 ++++++------ env/nand.c | 6 ++---- include/environment.h | 1 - 3 files changed, 8 insertions(+), 11 deletions(-) diff --git a/env/flash.c b/env/flash.c index 32236c7..dca6567 100644 --- a/env/flash.c +++ b/env/flash.c @@ -44,16 +44,16 @@ DECLARE_GLOBAL_DATA_PTR; #define INITENV #endif +#if defined(CONFIG_ENV_ADDR_REDUND) && defined(CMD_SAVEENV) || \ + !defined(CONFIG_ENV_ADDR_REDUND) && defined(INITENV) #ifdef ENV_IS_EMBEDDED -env_t *env_ptr = &environment; - -static __maybe_unused env_t *flash_addr = (env_t *)CONFIG_ENV_ADDR; - +static env_t *env_ptr = &environment; #else /* ! ENV_IS_EMBEDDED */ -env_t *env_ptr = (env_t *)CONFIG_ENV_ADDR; -static __maybe_unused env_t *flash_addr = (env_t *)CONFIG_ENV_ADDR; +static env_t *env_ptr = (env_t *)CONFIG_ENV_ADDR; #endif /* ENV_IS_EMBEDDED */ +#endif +static __maybe_unused env_t *flash_addr = (env_t *)CONFIG_ENV_ADDR; /* CONFIG_ENV_ADDR is supposed to be on sector boundary */ static ulong __maybe_unused end_addr = diff --git a/env/nand.c b/env/nand.c index 3698e68..29eda66 100644 --- a/env/nand.c +++ b/env/nand.c @@ -40,11 +40,9 @@ #endif #if defined(ENV_IS_EMBEDDED) -env_t *env_ptr = &environment; +static env_t *env_ptr = &environment; #elif defined(CONFIG_NAND_ENV_DST) -env_t *env_ptr = (env_t *)CONFIG_NAND_ENV_DST; -#else /* ! ENV_IS_EMBEDDED */ -env_t *env_ptr; +static env_t *env_ptr = (env_t *)CONFIG_NAND_ENV_DST; #endif /* ENV_IS_EMBEDDED */ DECLARE_GLOBAL_DATA_PTR; diff --git a/include/environment.h b/include/environment.h index 5e90f15..7da1291 100644 --- a/include/environment.h +++ b/include/environment.h @@ -157,7 +157,6 @@ extern env_t environment; #endif /* ENV_IS_EMBEDDED */ extern const unsigned char default_environment[]; -extern env_t *env_ptr; #if defined(CONFIG_NEEDS_MANUAL_RELOC) extern void env_reloc(void); -- cgit v1.1 From 119c01c2a571bb901dd0170b85924f74e362b75c Mon Sep 17 00:00:00 2001 From: Rajesh Bhagat Date: Mon, 5 Nov 2018 18:01:15 +0000 Subject: env: sf: define API to override sf environment address Defines env_sf_get_env_addr API to override sf environment address, required to support multiple environment. Signed-off-by: Rajesh Bhagat Reviewed-by: York Sun --- env/sf.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/env/sf.c b/env/sf.c index 2e3c600..23cbad5 100644 --- a/env/sf.c +++ b/env/sf.c @@ -298,10 +298,17 @@ out: } #endif +#ifdef CONFIG_ENV_ADDR +__weak void *env_sf_get_env_addr(void) +{ + return (void *)CONFIG_ENV_ADDR; +} +#endif + #if defined(INITENV) && defined(CONFIG_ENV_ADDR) static int env_sf_init(void) { - env_t *env_ptr = (env_t *)(CONFIG_ENV_ADDR); + env_t *env_ptr = (env_t *)env_sf_get_env_addr(); if (crc32(0, env_ptr->data, ENV_SIZE) == env_ptr->crc) { gd->env_addr = (ulong)&(env_ptr->data); -- cgit v1.1 From 088d52cfa8ec515316e20a6168dc2dd163c799b9 Mon Sep 17 00:00:00 2001 From: Rajesh Bhagat Date: Mon, 5 Nov 2018 18:01:19 +0000 Subject: driver/ifc: replace __ilog2 with LOG2 macro Replaces __ilog2 function call with LOG2 macro, required to use macros in global variables. Also, corrects the value passed in LOG2 for some PowerPC platforms. Minimum value that can be configured is is 64K for IFC IP. Signed-off-by: Pankit Garg Signed-off-by: Rajesh Bhagat [YS: fix white space around operator] Reviewed-by: York Sun --- include/configs/B4860QDS.h | 2 +- include/configs/T102xQDS.h | 2 +- include/configs/T1040QDS.h | 2 +- include/configs/T208xQDS.h | 2 +- include/configs/T4240QDS.h | 2 +- include/configs/T4240RDB.h | 2 +- include/fsl_ifc.h | 10 +++++----- 7 files changed, 11 insertions(+), 11 deletions(-) diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h index f758ea7..252e127 100644 --- a/include/configs/B4860QDS.h +++ b/include/configs/B4860QDS.h @@ -276,7 +276,7 @@ unsigned long get_board_ddr_clk(void); | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_GPCM \ | CSPR_V) -#define CONFIG_SYS_AMASK3 IFC_AMASK(4 * 1024) +#define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024) #define CONFIG_SYS_CSOR3 0x0 /* QIXIS Timing parameters for IFC CS3 */ #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ diff --git a/include/configs/T102xQDS.h b/include/configs/T102xQDS.h index 42bfd07..f3b0fe0 100644 --- a/include/configs/T102xQDS.h +++ b/include/configs/T102xQDS.h @@ -290,7 +290,7 @@ unsigned long get_board_ddr_clk(void); | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_GPCM \ | CSPR_V) -#define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) +#define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024) #define CONFIG_SYS_CSOR3 0x0 /* QIXIS Timing parameters for IFC CS3 */ #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h index 7d90797..2d5c96f 100644 --- a/include/configs/T1040QDS.h +++ b/include/configs/T1040QDS.h @@ -215,7 +215,7 @@ unsigned long get_board_ddr_clk(void); | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_GPCM \ | CSPR_V) -#define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) +#define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024) #define CONFIG_SYS_CSOR3 0x0 /* QIXIS Timing parameters for IFC CS3 */ #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 833a060..1dcf277 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -266,7 +266,7 @@ unsigned long get_board_ddr_clk(void); | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_GPCM \ | CSPR_V) -#define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) +#define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024) #define CONFIG_SYS_CSOR3 0x0 /* QIXIS Timing parameters for IFC CS3 */ #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ diff --git a/include/configs/T4240QDS.h b/include/configs/T4240QDS.h index 34b3b05..0693901 100644 --- a/include/configs/T4240QDS.h +++ b/include/configs/T4240QDS.h @@ -191,7 +191,7 @@ unsigned long get_board_ddr_clk(void); | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_GPCM \ | CSPR_V) -#define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) +#define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024) #define CONFIG_SYS_CSOR3 0x0 /* QIXIS Timing parameters for IFC CS3 */ #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index f5eed09..42252c7 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -460,7 +460,7 @@ unsigned long get_board_ddr_clk(void); | CSPR_MSEL_GPCM \ | CSPR_V) -#define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) +#define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024) #define CONFIG_SYS_CSOR3 0x0 /* CPLD Timing parameters for IFC CS3 */ diff --git a/include/fsl_ifc.h b/include/fsl_ifc.h index 8120ca0..17697c7 100644 --- a/include/fsl_ifc.h +++ b/include/fsl_ifc.h @@ -70,7 +70,7 @@ #define IFC_AMASK_MASK 0xFFFF0000 #define IFC_AMASK_SHIFT 16 #define IFC_AMASK(n) (IFC_AMASK_MASK << \ - (__ilog2(n) - IFC_AMASK_SHIFT)) + (LOG2(n) - IFC_AMASK_SHIFT)) /* * Chip Select Option Register IFC_NAND Machine @@ -111,7 +111,7 @@ /* Pages Per Block */ #define CSOR_NAND_PB_MASK 0x00000700 #define CSOR_NAND_PB_SHIFT 8 -#define CSOR_NAND_PB(n) ((__ilog2(n) - 5) << CSOR_NAND_PB_SHIFT) +#define CSOR_NAND_PB(n) ((LOG2(n) - 5) << CSOR_NAND_PB_SHIFT) /* Time for Read Enable High to Output High Impedance */ #define CSOR_NAND_TRHZ_MASK 0x0000001C #define CSOR_NAND_TRHZ_SHIFT 2 @@ -164,7 +164,7 @@ /* GPCM Timeout Count */ #define CSOR_GPCM_GPTO_MASK 0x0F000000 #define CSOR_GPCM_GPTO_SHIFT 24 -#define CSOR_GPCM_GPTO(n) ((__ilog2(n) - 8) << CSOR_GPCM_GPTO_SHIFT) +#define CSOR_GPCM_GPTO(n) ((LOG2(n) - 8) << CSOR_GPCM_GPTO_SHIFT) /* GPCM External Access Termination mode for read access */ #define CSOR_GPCM_RGETA_EXT 0x00080000 /* GPCM External Access Termination mode for write access */ @@ -644,7 +644,7 @@ enum ifc_nand_fir_opcodes { */ #define IFC_NAND_NCR_FTOCNT_MASK 0x1E000000 #define IFC_NAND_NCR_FTOCNT_SHIFT 25 -#define IFC_NAND_NCR_FTOCNT(n) ((_ilog2(n) - 8) << IFC_NAND_NCR_FTOCNT_SHIFT) +#define IFC_NAND_NCR_FTOCNT(n) ((LOG2(n) - 8) << IFC_NAND_NCR_FTOCNT_SHIFT) /* * NAND_AUTOBOOT_TRGR @@ -727,7 +727,7 @@ enum ifc_nand_fir_opcodes { /* Sequence Timeout Count */ #define IFC_NORCR_STOCNT_MASK 0x000F0000 #define IFC_NORCR_STOCNT_SHIFT 16 -#define IFC_NORCR_STOCNT(n) ((__ilog2(n) - 8) << IFC_NORCR_STOCNT_SHIFT) +#define IFC_NORCR_STOCNT(n) ((LOG2(n) - 8) << IFC_NORCR_STOCNT_SHIFT) /* * GPCM Machine specific registers -- cgit v1.1 From bb50569dc4c3ac71af075d5e994d0a37579efc51 Mon Sep 17 00:00:00 2001 From: York Sun Date: Mon, 5 Nov 2018 18:01:23 +0000 Subject: armv8: layerscape: Enable routing SError exception In case SError happens at EL2, if SCR_EL3[EA] is not routing it to EL3, and SCR_EL3[RW] is set to aarch64, setting HCR_EL2[AMO] routes the exception to EL2. Otherwise this exception is not taken. Signed-off-by: York Sun --- arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S index ef3987e..11b5fb2 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S +++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S @@ -71,6 +71,15 @@ ENDPROC(smp_kick_all_cpus) ENTRY(lowlevel_init) mov x29, lr /* Save LR */ + /* unmask SError and abort */ + msr daifclr, #4 + + /* Set HCR_EL2[AMO] so SError @EL2 is taken */ + mrs x0, hcr_el2 + orr x0, x0, #0x20 /* AMO */ + msr hcr_el2, x0 + isb + switch_el x1, 1f, 100f, 100f /* skip if not in EL3 */ 1: -- cgit v1.1 From e3506480466084a09d9882d546c3c3c677b13962 Mon Sep 17 00:00:00 2001 From: Pankit Garg Date: Mon, 5 Nov 2018 18:01:28 +0000 Subject: armv8: fsl-layerscape: change tlb base from OCRAM to DDR in EL < 3 Change tlb base address from OCRAM to DDR when exception level is less than 3. Signed-off-by: Ruchika Gupta Signed-off-by: Pankit Garg Reviewed-by: York Sun --- arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index e01b029..336909c 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -371,7 +371,10 @@ static inline void early_mmu_setup(void) unsigned int el = current_el(); /* global data is already setup, no allocation yet */ - gd->arch.tlb_addr = CONFIG_SYS_FSL_OCRAM_BASE; + if (el == 3) + gd->arch.tlb_addr = CONFIG_SYS_FSL_OCRAM_BASE; + else + gd->arch.tlb_addr = CONFIG_SYS_DDR_SDRAM_BASE; gd->arch.tlb_fillptr = gd->arch.tlb_addr; gd->arch.tlb_size = EARLY_PGTABLE_SIZE; -- cgit v1.1 From 9bd5fe7027d9e64b82d11a5769ac56a54bbd8e82 Mon Sep 17 00:00:00 2001 From: Pankit Garg Date: Mon, 5 Nov 2018 18:01:33 +0000 Subject: drivers: ifc: dynamic chipselect mapping support IFC driver changes to implement the chipselect mappings at run time. Defines init_early_memctl_regs and init_final_memctl_regs with chipselect dynamic mapping for nor and nand boot. Signed-off-by: Pankit Garg Signed-off-by: Rajesh Bhagat [YS: fix checkpatch issues] Reviewed-by: York Sun --- drivers/misc/fsl_ifc.c | 488 +++++++++++++++++++++++++++++++++++-------------- include/fsl_ifc.h | 17 ++ 2 files changed, 369 insertions(+), 136 deletions(-) diff --git a/drivers/misc/fsl_ifc.c b/drivers/misc/fsl_ifc.c index 7d66c3c..0c3394f 100644 --- a/drivers/misc/fsl_ifc.c +++ b/drivers/misc/fsl_ifc.c @@ -7,185 +7,401 @@ #include #include -void print_ifc_regs(void) -{ - int i, j; - - printf("IFC Controller Registers\n"); - for (i = 0; i < CONFIG_SYS_FSL_IFC_BANK_COUNT; i++) { - printf("CSPR%d:0x%08X\tAMASK%d:0x%08X\tCSOR%d:0x%08X\n", - i, get_ifc_cspr(i), i, get_ifc_amask(i), - i, get_ifc_csor(i)); - for (j = 0; j < 4; j++) - printf("IFC_FTIM%d:0x%08X\n", j, get_ifc_ftim(i, j)); - } -} - -void init_early_memctl_regs(void) -{ +struct ifc_regs ifc_cfg_default_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { + { + "cs0", #if defined(CONFIG_SYS_CSPR0) && defined(CONFIG_SYS_CSOR0) - set_ifc_ftim(IFC_CS0, IFC_FTIM0, CONFIG_SYS_CS0_FTIM0); - set_ifc_ftim(IFC_CS0, IFC_FTIM1, CONFIG_SYS_CS0_FTIM1); - set_ifc_ftim(IFC_CS0, IFC_FTIM2, CONFIG_SYS_CS0_FTIM2); - set_ifc_ftim(IFC_CS0, IFC_FTIM3, CONFIG_SYS_CS0_FTIM3); - -#ifndef CONFIG_A003399_NOR_WORKAROUND + CONFIG_SYS_CSPR0, #ifdef CONFIG_SYS_CSPR0_EXT - set_ifc_cspr_ext(IFC_CS0, CONFIG_SYS_CSPR0_EXT); -#endif + CONFIG_SYS_CSPR0_EXT, +#else + 0, +#endif +#ifdef CONFIG_SYS_AMASK0 + CONFIG_SYS_AMASK0, +#else + 0, +#endif + CONFIG_SYS_CSOR0, + { + CONFIG_SYS_CS0_FTIM0, + CONFIG_SYS_CS0_FTIM1, + CONFIG_SYS_CS0_FTIM2, + CONFIG_SYS_CS0_FTIM3, + }, #ifdef CONFIG_SYS_CSOR0_EXT - set_ifc_csor_ext(IFC_CS0, CONFIG_SYS_CSOR0_EXT); + CONFIG_SYS_CSOR0_EXT, +#else + 0, +#endif +#ifdef CONFIG_SYS_CSPR0_FINAL + CONFIG_SYS_CSPR0_FINAL, +#else + 0, #endif - set_ifc_cspr(IFC_CS0, CONFIG_SYS_CSPR0); - set_ifc_amask(IFC_CS0, CONFIG_SYS_AMASK0); - set_ifc_csor(IFC_CS0, CONFIG_SYS_CSOR0); +#ifdef CONFIG_SYS_AMASK0_FINAL + CONFIG_SYS_AMASK0_FINAL, +#else + 0, #endif #endif + }, +#if CONFIG_SYS_FSL_IFC_BANK_COUNT >= 2 + { + "cs1", +#if defined(CONFIG_SYS_CSPR1) && defined(CONFIG_SYS_CSOR1) + CONFIG_SYS_CSPR1, #ifdef CONFIG_SYS_CSPR1_EXT - set_ifc_cspr_ext(IFC_CS1, CONFIG_SYS_CSPR1_EXT); -#endif + CONFIG_SYS_CSPR1_EXT, +#else + 0, +#endif +#ifdef CONFIG_SYS_AMASK1 + CONFIG_SYS_AMASK1, +#else + 0, +#endif + CONFIG_SYS_CSOR1, + { + CONFIG_SYS_CS1_FTIM0, + CONFIG_SYS_CS1_FTIM1, + CONFIG_SYS_CS1_FTIM2, + CONFIG_SYS_CS1_FTIM3, + }, #ifdef CONFIG_SYS_CSOR1_EXT - set_ifc_csor_ext(IFC_CS1, CONFIG_SYS_CSOR1_EXT); + CONFIG_SYS_CSOR1_EXT, +#else + 0, #endif -#if defined(CONFIG_SYS_CSPR1) && defined(CONFIG_SYS_CSOR1) - set_ifc_ftim(IFC_CS1, IFC_FTIM0, CONFIG_SYS_CS1_FTIM0); - set_ifc_ftim(IFC_CS1, IFC_FTIM1, CONFIG_SYS_CS1_FTIM1); - set_ifc_ftim(IFC_CS1, IFC_FTIM2, CONFIG_SYS_CS1_FTIM2); - set_ifc_ftim(IFC_CS1, IFC_FTIM3, CONFIG_SYS_CS1_FTIM3); - - set_ifc_csor(IFC_CS1, CONFIG_SYS_CSOR1); - set_ifc_amask(IFC_CS1, CONFIG_SYS_AMASK1); - set_ifc_cspr(IFC_CS1, CONFIG_SYS_CSPR1); +#ifdef CONFIG_SYS_CSPR1_FINAL + CONFIG_SYS_CSPR1_FINAL, +#else + 0, +#endif +#ifdef CONFIG_SYS_AMASK1_FINAL + CONFIG_SYS_AMASK1_FINAL, +#else + 0, +#endif +#endif + }, #endif +#if CONFIG_SYS_FSL_IFC_BANK_COUNT >= 3 + { + "cs2", +#if defined(CONFIG_SYS_CSPR2) && defined(CONFIG_SYS_CSOR2) + CONFIG_SYS_CSPR2, #ifdef CONFIG_SYS_CSPR2_EXT - set_ifc_cspr_ext(IFC_CS2, CONFIG_SYS_CSPR2_EXT); -#endif + CONFIG_SYS_CSPR2_EXT, +#else + 0, +#endif +#ifdef CONFIG_SYS_AMASK2 + CONFIG_SYS_AMASK2, +#else + 0, +#endif + CONFIG_SYS_CSOR2, + { + CONFIG_SYS_CS2_FTIM0, + CONFIG_SYS_CS2_FTIM1, + CONFIG_SYS_CS2_FTIM2, + CONFIG_SYS_CS2_FTIM3, + }, #ifdef CONFIG_SYS_CSOR2_EXT - set_ifc_csor_ext(IFC_CS2, CONFIG_SYS_CSOR2_EXT); + CONFIG_SYS_CSOR2_EXT, +#else + 0, +#endif +#ifdef CONFIG_SYS_CSPR2_FINAL + CONFIG_SYS_CSPR2_FINAL, +#else + 0, +#endif +#ifdef CONFIG_SYS_AMASK2_FINAL + CONFIG_SYS_AMASK2_FINAL, +#else + 0, #endif -#if defined(CONFIG_SYS_CSPR2) && defined(CONFIG_SYS_CSOR2) - set_ifc_ftim(IFC_CS2, IFC_FTIM0, CONFIG_SYS_CS2_FTIM0); - set_ifc_ftim(IFC_CS2, IFC_FTIM1, CONFIG_SYS_CS2_FTIM1); - set_ifc_ftim(IFC_CS2, IFC_FTIM2, CONFIG_SYS_CS2_FTIM2); - set_ifc_ftim(IFC_CS2, IFC_FTIM3, CONFIG_SYS_CS2_FTIM3); - - set_ifc_csor(IFC_CS2, CONFIG_SYS_CSOR2); - set_ifc_amask(IFC_CS2, CONFIG_SYS_AMASK2); - set_ifc_cspr(IFC_CS2, CONFIG_SYS_CSPR2); +#endif + }, #endif +#if CONFIG_SYS_FSL_IFC_BANK_COUNT >= 4 + { + "cs3", +#if defined(CONFIG_SYS_CSPR3) && defined(CONFIG_SYS_CSOR3) + CONFIG_SYS_CSPR3, #ifdef CONFIG_SYS_CSPR3_EXT - set_ifc_cspr_ext(IFC_CS3, CONFIG_SYS_CSPR3_EXT); -#endif + CONFIG_SYS_CSPR3_EXT, +#else + 0, +#endif +#ifdef CONFIG_SYS_AMASK3 + CONFIG_SYS_AMASK3, +#else + 0, +#endif + CONFIG_SYS_CSOR3, + { + CONFIG_SYS_CS3_FTIM0, + CONFIG_SYS_CS3_FTIM1, + CONFIG_SYS_CS3_FTIM2, + CONFIG_SYS_CS3_FTIM3, + }, #ifdef CONFIG_SYS_CSOR3_EXT - set_ifc_csor_ext(IFC_CS3, CONFIG_SYS_CSOR3_EXT); + CONFIG_SYS_CSOR3_EXT, +#else + 0, +#endif +#ifdef CONFIG_SYS_CSPR3_FINAL + CONFIG_SYS_CSPR3_FINAL, +#else + 0, +#endif +#ifdef CONFIG_SYS_AMASK3_FINAL + CONFIG_SYS_AMASK3_FINAL, +#else + 0, #endif -#if defined(CONFIG_SYS_CSPR3) && defined(CONFIG_SYS_CSOR3) - set_ifc_ftim(IFC_CS3, IFC_FTIM0, CONFIG_SYS_CS3_FTIM0); - set_ifc_ftim(IFC_CS3, IFC_FTIM1, CONFIG_SYS_CS3_FTIM1); - set_ifc_ftim(IFC_CS3, IFC_FTIM2, CONFIG_SYS_CS3_FTIM2); - set_ifc_ftim(IFC_CS3, IFC_FTIM3, CONFIG_SYS_CS3_FTIM3); - - set_ifc_cspr(IFC_CS3, CONFIG_SYS_CSPR3); - set_ifc_amask(IFC_CS3, CONFIG_SYS_AMASK3); - set_ifc_csor(IFC_CS3, CONFIG_SYS_CSOR3); +#endif + }, #endif +#if CONFIG_SYS_FSL_IFC_BANK_COUNT >= 5 + { + "cs4", +#if defined(CONFIG_SYS_CSPR4) && defined(CONFIG_SYS_CSOR4) + CONFIG_SYS_CSPR4, #ifdef CONFIG_SYS_CSPR4_EXT - set_ifc_cspr_ext(IFC_CS4, CONFIG_SYS_CSPR4_EXT); -#endif + CONFIG_SYS_CSPR4_EXT, +#else + 0, +#endif +#ifdef CONFIG_SYS_AMASK4 + CONFIG_SYS_AMASK4, +#else + 0, +#endif + CONFIG_SYS_CSOR4, + { + CONFIG_SYS_CS4_FTIM0, + CONFIG_SYS_CS4_FTIM1, + CONFIG_SYS_CS4_FTIM2, + CONFIG_SYS_CS4_FTIM3, + }, #ifdef CONFIG_SYS_CSOR4_EXT - set_ifc_csor_ext(IFC_CS4, CONFIG_SYS_CSOR4_EXT); + CONFIG_SYS_CSOR4_EXT, +#else + 0, #endif -#if defined(CONFIG_SYS_CSPR4) && defined(CONFIG_SYS_CSOR4) - set_ifc_ftim(IFC_CS4, IFC_FTIM0, CONFIG_SYS_CS4_FTIM0); - set_ifc_ftim(IFC_CS4, IFC_FTIM1, CONFIG_SYS_CS4_FTIM1); - set_ifc_ftim(IFC_CS4, IFC_FTIM2, CONFIG_SYS_CS4_FTIM2); - set_ifc_ftim(IFC_CS4, IFC_FTIM3, CONFIG_SYS_CS4_FTIM3); - - set_ifc_cspr(IFC_CS4, CONFIG_SYS_CSPR4); - set_ifc_amask(IFC_CS4, CONFIG_SYS_AMASK4); - set_ifc_csor(IFC_CS4, CONFIG_SYS_CSOR4); +#ifdef CONFIG_SYS_CSPR4_FINAL + CONFIG_SYS_CSPR4_FINAL, +#else + 0, +#endif +#ifdef CONFIG_SYS_AMASK4_FINAL + CONFIG_SYS_AMASK4_FINAL, +#else + 0, +#endif +#endif + }, #endif +#if CONFIG_SYS_FSL_IFC_BANK_COUNT >= 6 + { + "cs5", +#if defined(CONFIG_SYS_CSPR5) && defined(CONFIG_SYS_CSOR5) + CONFIG_SYS_CSPR5, #ifdef CONFIG_SYS_CSPR5_EXT - set_ifc_cspr_ext(IFC_CS5, CONFIG_SYS_CSPR5_EXT); -#endif + CONFIG_SYS_CSPR5_EXT, +#else + 0, +#endif +#ifdef CONFIG_SYS_AMASK5 + CONFIG_SYS_AMASK5, +#else + 0, +#endif + CONFIG_SYS_CSOR5, + { + CONFIG_SYS_CS5_FTIM0, + CONFIG_SYS_CS5_FTIM1, + CONFIG_SYS_CS5_FTIM2, + CONFIG_SYS_CS5_FTIM3, + }, #ifdef CONFIG_SYS_CSOR5_EXT - set_ifc_csor_ext(IFC_CS5, CONFIG_SYS_CSOR5_EXT); + CONFIG_SYS_CSOR5_EXT, +#else + 0, #endif -#if defined(CONFIG_SYS_CSPR5) && defined(CONFIG_SYS_CSOR5) - set_ifc_ftim(IFC_CS5, IFC_FTIM0, CONFIG_SYS_CS5_FTIM0); - set_ifc_ftim(IFC_CS5, IFC_FTIM1, CONFIG_SYS_CS5_FTIM1); - set_ifc_ftim(IFC_CS5, IFC_FTIM2, CONFIG_SYS_CS5_FTIM2); - set_ifc_ftim(IFC_CS5, IFC_FTIM3, CONFIG_SYS_CS5_FTIM3); - - set_ifc_cspr(IFC_CS5, CONFIG_SYS_CSPR5); - set_ifc_amask(IFC_CS5, CONFIG_SYS_AMASK5); - set_ifc_csor(IFC_CS5, CONFIG_SYS_CSOR5); +#ifdef CONFIG_SYS_CSPR5_FINAL + CONFIG_SYS_CSPR5_FINAL, +#else + 0, +#endif +#ifdef CONFIG_SYS_AMASK5_FINAL + CONFIG_SYS_AMASK5_FINAL, +#else + 0, +#endif +#endif + }, #endif +#if CONFIG_SYS_FSL_IFC_BANK_COUNT >= 7 + { + "cs6", +#if defined(CONFIG_SYS_CSPR6) && defined(CONFIG_SYS_CSOR6) + CONFIG_SYS_CSPR6, #ifdef CONFIG_SYS_CSPR6_EXT - set_ifc_cspr_ext(IFC_CS6, CONFIG_SYS_CSPR6_EXT); -#endif + CONFIG_SYS_CSPR6_EXT, +#else + 0, +#endif +#ifdef CONFIG_SYS_AMASK6 + CONFIG_SYS_AMASK6, +#else + 0, +#endif + CONFIG_SYS_CSOR6, + { + CONFIG_SYS_CS6_FTIM0, + CONFIG_SYS_CS6_FTIM1, + CONFIG_SYS_CS6_FTIM2, + CONFIG_SYS_CS6_FTIM3, + }, #ifdef CONFIG_SYS_CSOR6_EXT - set_ifc_csor_ext(IFC_CS6, CONFIG_SYS_CSOR6_EXT); + CONFIG_SYS_CSOR6_EXT, +#else + 0, #endif -#if defined(CONFIG_SYS_CSPR6) && defined(CONFIG_SYS_CSOR6) - set_ifc_ftim(IFC_CS6, IFC_FTIM0, CONFIG_SYS_CS6_FTIM0); - set_ifc_ftim(IFC_CS6, IFC_FTIM1, CONFIG_SYS_CS6_FTIM1); - set_ifc_ftim(IFC_CS6, IFC_FTIM2, CONFIG_SYS_CS6_FTIM2); - set_ifc_ftim(IFC_CS6, IFC_FTIM3, CONFIG_SYS_CS6_FTIM3); - - set_ifc_cspr(IFC_CS6, CONFIG_SYS_CSPR6); - set_ifc_amask(IFC_CS6, CONFIG_SYS_AMASK6); - set_ifc_csor(IFC_CS6, CONFIG_SYS_CSOR6); +#ifdef CONFIG_SYS_CSPR6_FINAL + CONFIG_SYS_CSPR6_FINAL, +#else + 0, +#endif +#ifdef CONFIG_SYS_AMASK6_FINAL + CONFIG_SYS_AMASK6_FINAL, +#else + 0, +#endif +#endif + }, #endif +#if CONFIG_SYS_FSL_IFC_BANK_COUNT >= 8 + { + "cs7", +#if defined(CONFIG_SYS_CSPR7) && defined(CONFIG_SYS_CSOR7) + CONFIG_SYS_CSPR7, #ifdef CONFIG_SYS_CSPR7_EXT - set_ifc_cspr_ext(IFC_CS7, CONFIG_SYS_CSPR7_EXT); + CONFIG_SYS_CSPR7_EXT, +#else + 0, #endif -#ifdef CONFIG_SYS_CSOR7_EXT - set_ifc_csor_ext(IFC_CS7, CONFIG_SYS_CSOR7_EXT); +#ifdef CONFIG_SYS_AMASK7 + CONFIG_SYS_AMASK7, +#else + 0, #endif -#if defined(CONFIG_SYS_CSPR7) && defined(CONFIG_SYS_CSOR7) - set_ifc_ftim(IFC_CS7, IFC_FTIM0, CONFIG_SYS_CS7_FTIM0); - set_ifc_ftim(IFC_CS7, IFC_FTIM1, CONFIG_SYS_CS7_FTIM1); - set_ifc_ftim(IFC_CS7, IFC_FTIM2, CONFIG_SYS_CS7_FTIM2); - set_ifc_ftim(IFC_CS7, IFC_FTIM3, CONFIG_SYS_CS7_FTIM3); + CONFIG_SYS_CSOR7, +#ifdef CONFIG_SYS_CSOR7_EXT + CONFIG_SYS_CSOR7_EXT, +#else + 0, +#endif + { + CONFIG_SYS_CS7_FTIM0, + CONFIG_SYS_CS7_FTIM1, + CONFIG_SYS_CS7_FTIM2, + CONFIG_SYS_CS7_FTIM3, + }, +#ifdef CONFIG_SYS_CSPR7_FINAL + CONFIG_SYS_CSPR7_FINAL, +#else + 0, +#endif +#ifdef CONFIG_SYS_AMASK7_FINAL + CONFIG_SYS_AMASK7_FINAL, +#else + 0, +#endif +#endif + }, +#endif +}; - set_ifc_cspr(IFC_CS7, CONFIG_SYS_CSPR7); - set_ifc_amask(IFC_CS7, CONFIG_SYS_AMASK7); - set_ifc_csor(IFC_CS7, CONFIG_SYS_CSOR7); -#endif +__weak void ifc_cfg_boot_info(struct ifc_regs_info *regs_info) +{ + regs_info->regs = ifc_cfg_default_boot; + regs_info->cs_size = CONFIG_SYS_FSL_IFC_BANK_COUNT; +} + +void print_ifc_regs(void) +{ + int i, j; + + printf("IFC Controller Registers\n"); + for (i = 0; i < CONFIG_SYS_FSL_IFC_BANK_COUNT; i++) { + printf("CSPR%d:0x%08X\tAMASK%d:0x%08X\tCSOR%d:0x%08X\n", + i, get_ifc_cspr(i), i, get_ifc_amask(i), + i, get_ifc_csor(i)); + for (j = 0; j < 4; j++) + printf("IFC_FTIM%d:0x%08X\n", j, get_ifc_ftim(i, j)); + } +} + +void init_early_memctl_regs(void) +{ + int i, j; + struct ifc_regs *regs; + struct ifc_regs_info regs_info = {0}; + + ifc_cfg_boot_info(®s_info); + regs = regs_info.regs; + + for (i = 0 ; i < regs_info.cs_size; i++) { + if (regs[i].pr && (regs[i].pr & CSPR_V)) { + /* skip setting cspr/csor_ext in below condition */ + if (!(CONFIG_IS_ENABLED(A003399_NOR_WORKAROUND) && + i == 0 && + ((regs[0].pr & CSPR_MSEL) == CSPR_MSEL_NOR))) { + if (regs[i].pr_ext) + set_ifc_cspr_ext(i, regs[i].pr_ext); + if (regs[i].or_ext) + set_ifc_csor_ext(i, regs[i].or_ext); + } + + for (j = 0; j < ARRAY_SIZE(regs->ftim); j++) + set_ifc_ftim(i, j, regs[i].ftim[j]); + + set_ifc_csor(i, regs[i].or); + set_ifc_amask(i, regs[i].amask); + set_ifc_cspr(i, regs[i].pr); + } + } } void init_final_memctl_regs(void) { -#ifdef CONFIG_SYS_CSPR0_FINAL - set_ifc_cspr(IFC_CS0, CONFIG_SYS_CSPR0_FINAL); -#endif -#ifdef CONFIG_SYS_AMASK0_FINAL - set_ifc_amask(IFC_CS0, CONFIG_SYS_AMASK0); -#endif -#ifdef CONFIG_SYS_CSPR1_FINAL - set_ifc_cspr(IFC_CS1, CONFIG_SYS_CSPR1_FINAL); -#endif -#ifdef CONFIG_SYS_AMASK1_FINAL - set_ifc_amask(IFC_CS1, CONFIG_SYS_AMASK1_FINAL); -#endif -#ifdef CONFIG_SYS_CSPR2_FINAL - set_ifc_cspr(IFC_CS2, CONFIG_SYS_CSPR2_FINAL); -#endif -#ifdef CONFIG_SYS_AMASK2_FINAL - set_ifc_amask(IFC_CS2, CONFIG_SYS_AMASK2); -#endif -#ifdef CONFIG_SYS_CSPR3_FINAL - set_ifc_cspr(IFC_CS3, CONFIG_SYS_CSPR3_FINAL); -#endif -#ifdef CONFIG_SYS_AMASK3_FINAL - set_ifc_amask(IFC_CS3, CONFIG_SYS_AMASK3); -#endif + int i; + struct ifc_regs *regs; + struct ifc_regs_info regs_info; + + ifc_cfg_boot_info(®s_info); + regs = regs_info.regs; + + for (i = 0 ; i < regs_info.cs_size && i < ARRAY_SIZE(regs->ftim); i++) { + if (!(regs[i].pr_final & CSPR_V)) + continue; + if (regs[i].pr_final) + set_ifc_cspr(i, regs[i].pr_final); + if (regs[i].amask_final) + set_ifc_amask(i, (i == 1) ? regs[i].amask_final : + regs[i].amask); + } } diff --git a/include/fsl_ifc.h b/include/fsl_ifc.h index 17697c7..3edcc39 100644 --- a/include/fsl_ifc.h +++ b/include/fsl_ifc.h @@ -1031,6 +1031,23 @@ struct fsl_ifc { struct fsl_ifc_runtime *rregs; }; +struct ifc_regs { + const char *name; + u32 pr; + u32 pr_ext; + u32 amask; + u32 or; + u32 ftim[4]; + u32 or_ext; + u32 pr_final; + u32 amask_final; +}; + +struct ifc_regs_info { + struct ifc_regs *regs; + u32 cs_size; +}; + #ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A002769 #undef CSPR_MSEL_NOR #define CSPR_MSEL_NOR CSPR_MSEL_GPCM -- cgit v1.1 From 535d76a1215064866b1eb7f0aa61796fc32d31c1 Mon Sep 17 00:00:00 2001 From: Rajesh Bhagat Date: Mon, 5 Nov 2018 18:01:37 +0000 Subject: armv8: layerscape: Add TFABOOT support Adds TFABOOT support config option and add generic code to enable execution from DDR. Signed-off-by: York Sun Signed-off-by: Rajesh Bhagat --- arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 7 +++++++ arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 9 ++++++--- 2 files changed, 13 insertions(+), 3 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index f2111fa..9092757 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -514,3 +514,10 @@ config HAS_FSL_XHCI_USB help For some SoC(such as LS1043A and LS1046A), USB and QE-HDLC multiplex use pins, select it when the pins are assigned to USB. + +config TFABOOT + bool "Support for booting from TFA" + default n + help + Enabling this will make a U-Boot binary that is capable of being + booted via TFA. diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index 336909c..901ecb9 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -88,7 +88,8 @@ static struct mm_region early_map[] = { #endif { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_SIZE1, -#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_TFABOOT) || \ + (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)) PTE_BLOCK_MEMTYPE(MT_NORMAL) | #else /* Start with nGnRnE and PXN and UXN to prevent speculative access */ PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN | @@ -139,7 +140,8 @@ static struct mm_region early_map[] = { #endif { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_SIZE1, -#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_TFABOOT) || \ + (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)) PTE_BLOCK_MEMTYPE(MT_NORMAL) | #else /* Start with nGnRnE and PXN and UXN to prevent speculative access */ PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN | @@ -1236,7 +1238,8 @@ void update_early_mmu_table(void) __weak int dram_init(void) { fsl_initdram(); -#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) +#if (!defined(CONFIG_SPL) && !defined(CONFIG_TFABOOT)) || \ + defined(CONFIG_SPL_BUILD) /* This will break-before-make MMU for DDR */ update_early_mmu_table(); #endif -- cgit v1.1 From 4c417384620025a7b64e2bd256e7641529b3ddf8 Mon Sep 17 00:00:00 2001 From: Rajesh Bhagat Date: Mon, 5 Nov 2018 18:01:42 +0000 Subject: armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg Signed-off-by: Rajesh Bhagat [YS: fix multiple checkpatch issues] Reviewed-by: York Sun --- arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 189 +++++++++++++++++++++ .../include/asm/arch-fsl-layerscape/immap_lsch2.h | 20 +++ .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 49 ++++++ arch/arm/include/asm/arch-fsl-layerscape/soc.h | 17 ++ 4 files changed, 275 insertions(+) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index 901ecb9..0b6f1e1 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -31,6 +31,10 @@ #include #include +#ifdef CONFIG_TFABOOT +#include +#endif + DECLARE_GLOBAL_DATA_PTR; static struct cpu_type cpu_type_list[] = { @@ -581,7 +585,192 @@ void enable_caches(void) icache_enable(); dcache_enable(); } +#endif /* CONFIG_SYS_DCACHE_OFF */ + +#ifdef CONFIG_TFABOOT +enum boot_src __get_boot_src(u32 porsr1) +{ + enum boot_src src = BOOT_SOURCE_RESERVED; + u32 rcw_src = (porsr1 & RCW_SRC_MASK) >> RCW_SRC_BIT; +#if !defined(CONFIG_FSL_LSCH3_2) + u32 val; +#endif + debug("%s: rcw_src 0x%x\n", __func__, rcw_src); + +#if defined(CONFIG_FSL_LSCH3) +#if defined(CONFIG_FSL_LSCH3_2) + switch (rcw_src) { + case RCW_SRC_SDHC1_VAL: + src = BOOT_SOURCE_SD_MMC; + break; + case RCW_SRC_SDHC2_VAL: + src = BOOT_SOURCE_SD_MMC2; + break; + case RCW_SRC_I2C1_VAL: + src = BOOT_SOURCE_I2C1_EXTENDED; + break; + case RCW_SRC_FLEXSPI_NAND2K_VAL: + src = BOOT_SOURCE_XSPI_NAND; + break; + case RCW_SRC_FLEXSPI_NAND4K_VAL: + src = BOOT_SOURCE_XSPI_NAND; + break; + case RCW_SRC_RESERVED_1_VAL: + src = BOOT_SOURCE_RESERVED; + break; + case RCW_SRC_FLEXSPI_NOR_24B: + src = BOOT_SOURCE_XSPI_NOR; + break; + default: + src = BOOT_SOURCE_RESERVED; + } +#else + val = rcw_src & RCW_SRC_TYPE_MASK; + if (val == RCW_SRC_NOR_VAL) { + val = rcw_src & NOR_TYPE_MASK; + + switch (val) { + case NOR_16B_VAL: + case NOR_32B_VAL: + src = BOOT_SOURCE_IFC_NOR; + break; + default: + src = BOOT_SOURCE_RESERVED; + } + } else { + /* RCW SRC Serial Flash */ + val = rcw_src & RCW_SRC_SERIAL_MASK; + switch (val) { + case RCW_SRC_QSPI_VAL: + /* RCW SRC Serial NOR (QSPI) */ + src = BOOT_SOURCE_QSPI_NOR; + break; + case RCW_SRC_SD_CARD_VAL: + /* RCW SRC SD Card */ + src = BOOT_SOURCE_SD_MMC; + break; + case RCW_SRC_EMMC_VAL: + /* RCW SRC EMMC */ + src = BOOT_SOURCE_SD_MMC2; + break; + case RCW_SRC_I2C1_VAL: + /* RCW SRC I2C1 Extended */ + src = BOOT_SOURCE_I2C1_EXTENDED; + break; + default: + src = BOOT_SOURCE_RESERVED; + } + } +#endif +#elif defined(CONFIG_FSL_LSCH2) + /* RCW SRC NAND */ + val = rcw_src & RCW_SRC_NAND_MASK; + if (val == RCW_SRC_NAND_VAL) { + val = rcw_src & NAND_RESERVED_MASK; + if (val != NAND_RESERVED_1 && val != NAND_RESERVED_2) + src = BOOT_SOURCE_IFC_NAND; + + } else { + /* RCW SRC NOR */ + val = rcw_src & RCW_SRC_NOR_MASK; + if (val == NOR_8B_VAL || val == NOR_16B_VAL) { + src = BOOT_SOURCE_IFC_NOR; + } else { + switch (rcw_src) { + case QSPI_VAL1: + case QSPI_VAL2: + src = BOOT_SOURCE_QSPI_NOR; + break; + case SD_VAL: + src = BOOT_SOURCE_SD_MMC; + break; + default: + src = BOOT_SOURCE_RESERVED; + } + } + } #endif + debug("%s: src 0x%x\n", __func__, src); + return src; +} + +enum boot_src get_boot_src(void) +{ + u32 porsr1; + +#if defined(CONFIG_FSL_LSCH3) + u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE; + + porsr1 = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4); +#elif defined(CONFIG_FSL_LSCH2) + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + + porsr1 = in_be32(&gur->porsr1); +#endif + debug("%s: porsr1 0x%x\n", __func__, porsr1); + + return __get_boot_src(porsr1); +} + +#ifdef CONFIG_ENV_IS_IN_MMC +int mmc_get_env_dev(void) +{ + enum boot_src src = get_boot_src(); + int dev = CONFIG_SYS_MMC_ENV_DEV; + + switch (src) { + case BOOT_SOURCE_SD_MMC: + dev = 0; + break; + case BOOT_SOURCE_SD_MMC2: + dev = 1; + break; + default: + break; + } + + return dev; +} +#endif + +enum env_location env_get_location(enum env_operation op, int prio) +{ + enum boot_src src = get_boot_src(); + enum env_location env_loc = ENVL_NOWHERE; + + if (prio) + return ENVL_UNKNOWN; + + switch (src) { + case BOOT_SOURCE_IFC_NOR: + env_loc = ENVL_FLASH; + break; + case BOOT_SOURCE_QSPI_NOR: + /* FALLTHROUGH */ + case BOOT_SOURCE_XSPI_NOR: + env_loc = ENVL_SPI_FLASH; + break; + case BOOT_SOURCE_IFC_NAND: + /* FALLTHROUGH */ + case BOOT_SOURCE_QSPI_NAND: + /* FALLTHROUGH */ + case BOOT_SOURCE_XSPI_NAND: + env_loc = ENVL_NAND; + break; + case BOOT_SOURCE_SD_MMC: + /* FALLTHROUGH */ + case BOOT_SOURCE_SD_MMC2: + env_loc = ENVL_MMC; + break; + case BOOT_SOURCE_I2C1_EXTENDED: + /* FALLTHROUGH */ + default: + break; + } + + return env_loc; +} +#endif /* CONFIG_TFABOOT */ u32 initiator_type(u32 cluster, int init_id) { diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index 8c10526..4d0f16f 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -677,6 +677,26 @@ struct ccsr_gpio { #define SCR0_CLIENTPD_MASK 0x00000001 #define SCR0_USFCFG_MASK 0x00000400 +#ifdef CONFIG_TFABOOT +#define RCW_SRC_MASK (0xFF800000) +#define RCW_SRC_BIT 23 + +/* RCW SRC NAND */ +#define RCW_SRC_NAND_MASK (0x100) +#define RCW_SRC_NAND_VAL (0x100) +#define NAND_RESERVED_MASK (0xFC) +#define NAND_RESERVED_1 (0x0) +#define NAND_RESERVED_2 (0x80) + +/* RCW SRC NOR */ +#define RCW_SRC_NOR_MASK (0x1F0) +#define NOR_8B_VAL (0x10) +#define NOR_16B_VAL (0x20) +#define SD_VAL (0x40) +#define QSPI_VAL1 (0x44) +#define QSPI_VAL2 (0x45) +#endif + uint get_svr(void); #endif /* __ARCH_FSL_LSCH2_IMMAP_H__*/ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index b0cec74..8ddff55 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -82,6 +82,55 @@ #define CONFIG_SYS_FSL_JR0_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET) +#ifdef CONFIG_TFABOOT +#ifdef CONFIG_FSL_LSCH3_2 +/* RCW_SRC field in Power-On Reset Control Register 1 */ +#define RCW_SRC_MASK 0x07800000 +#define RCW_SRC_BIT 23 + +/* CFG_RCW_SRC[3:0] */ +#define RCW_SRC_TYPE_MASK 0x8 +#define RCW_SRC_ADDR_OFFSET_8MB 0x800000 + +/* RCW SRC HARDCODED */ +#define RCW_SRC_HARDCODED_VAL 0x0 /* 0x00 - 0x07 */ + +#define RCW_SRC_SDHC1_VAL 0x8 /* 0x8 */ +#define RCW_SRC_SDHC2_VAL 0x9 /* 0x9 */ +#define RCW_SRC_I2C1_VAL 0xa /* 0xa */ +#define RCW_SRC_RESERVED_UART_VAL 0xb /* 0xb */ +#define RCW_SRC_FLEXSPI_NAND2K_VAL 0xc /* 0xc */ +#define RCW_SRC_FLEXSPI_NAND4K_VAL 0xd /* 0xd */ +#define RCW_SRC_RESERVED_1_VAL 0xe /* 0xe */ +#define RCW_SRC_FLEXSPI_NOR_24B 0xf /* 0xf */ +#else +#define RCW_SRC_MASK (0xFF800000) +#define RCW_SRC_BIT 23 +/* CFG_RCW_SRC[6:0] */ +#define RCW_SRC_TYPE_MASK (0x70) + +/* RCW SRC HARDCODED */ +#define RCW_SRC_HARDCODED_VAL (0x10) /* 0x10 - 0x1f */ +/* Hardcoded will also have CFG_RCW_SRC[7] as 1. 0x90 - 0x9f */ + +/* RCW SRC NOR */ +#define RCW_SRC_NOR_VAL (0x20) +#define NOR_TYPE_MASK (0x10) +#define NOR_16B_VAL (0x0) /* 0x20 - 0x2f */ +#define NOR_32B_VAL (0x10) /* 0x30 - 0x3f */ + +/* RCW SRC Serial Flash + * 1. SERIAL NOR (QSPI) + * 2. OTHERS (SD/MMC, SPI, I2C1 + */ +#define RCW_SRC_SERIAL_MASK (0x7F) +#define RCW_SRC_QSPI_VAL (0x62) /* 0x62 */ +#define RCW_SRC_SD_CARD_VAL (0x40) /* 0x40 */ +#define RCW_SRC_EMMC_VAL (0x41) /* 0x41 */ +#define RCW_SRC_I2C1_VAL (0x49) /* 0x49 */ +#endif +#endif + /* Security Monitor */ #define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0x00e90000) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h index 61b6e4b..d327c7b 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h @@ -53,6 +53,23 @@ struct cpu_type { #define CPU_TYPE_ENTRY(n, v, nc) \ { .name = #n, .soc_ver = SVR_##v, .num_cores = (nc)} + +#ifdef CONFIG_TFABOOT +enum boot_src { + BOOT_SOURCE_RESERVED = 0, + BOOT_SOURCE_IFC_NOR, + BOOT_SOURCE_IFC_NAND, + BOOT_SOURCE_QSPI_NOR, + BOOT_SOURCE_QSPI_NAND, + BOOT_SOURCE_XSPI_NOR, + BOOT_SOURCE_XSPI_NAND, + BOOT_SOURCE_SD_MMC, + BOOT_SOURCE_SD_MMC2, + BOOT_SOURCE_I2C1_EXTENDED, +}; + +enum boot_src get_boot_src(void); +#endif #endif #define SVR_WO_E 0xFFFFFE #define SVR_LS1012A 0x870400 -- cgit v1.1 From b6c97f4d94144cab494d0844268cca05e04af3d0 Mon Sep 17 00:00:00 2001 From: Rajesh Bhagat Date: Mon, 5 Nov 2018 18:01:48 +0000 Subject: armv8: layerscape: remove EL3 specific erratas for TFABOOT Removes EL3 specific erratas for TFABOOT, And now taken care in TFA. ARM_ERRATA_855873, SYS_FSL_ERRATUM_A008850, SYS_FSL_ERRATUM_A008511, SYS_FSL_ERRATUM_A008336, SYS_FSL_ERRATUM_A009663, SYS_FSL_ERRATUM_A009803, SYS_FSL_ERRATUM_A009942, SYS_FSL_ERRATUM_A010165 Signed-off-by: Rajesh Bhagat Reviewed-by: York Sun --- arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 9092757..1872c66 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -1,7 +1,7 @@ config ARCH_LS1012A bool select ARMV8_SET_SMPEN - select ARM_ERRATA_855873 + select ARM_ERRATA_855873 if !TFABOOT select FSL_LSCH2 select SYS_FSL_SRDS_1 select SYS_HAS_SERDES @@ -22,22 +22,22 @@ config ARCH_LS1012A config ARCH_LS1043A bool select ARMV8_SET_SMPEN - select ARM_ERRATA_855873 + select ARM_ERRATA_855873 if !TFABOOT select FSL_LSCH2 select SYS_FSL_SRDS_1 select SYS_HAS_SERDES select SYS_FSL_DDR select SYS_FSL_DDR_BE select SYS_FSL_DDR_VER_50 - select SYS_FSL_ERRATUM_A008850 + select SYS_FSL_ERRATUM_A008850 if !TFABOOT select SYS_FSL_ERRATUM_A008997 select SYS_FSL_ERRATUM_A009007 select SYS_FSL_ERRATUM_A009008 - select SYS_FSL_ERRATUM_A009660 - select SYS_FSL_ERRATUM_A009663 + select SYS_FSL_ERRATUM_A009660 if !TFABOOT + select SYS_FSL_ERRATUM_A009663 if !TFABOOT select SYS_FSL_ERRATUM_A009798 select SYS_FSL_ERRATUM_A009929 - select SYS_FSL_ERRATUM_A009942 + select SYS_FSL_ERRATUM_A009942 if !TFABOOT select SYS_FSL_ERRATUM_A010315 select SYS_FSL_ERRATUM_A010539 select SYS_FSL_HAS_DDR3 @@ -62,17 +62,17 @@ config ARCH_LS1046A select SYS_FSL_DDR select SYS_FSL_DDR_BE select SYS_FSL_DDR_VER_50 - select SYS_FSL_ERRATUM_A008336 - select SYS_FSL_ERRATUM_A008511 - select SYS_FSL_ERRATUM_A008850 + select SYS_FSL_ERRATUM_A008336 if !TFABOOT + select SYS_FSL_ERRATUM_A008511 if !TFABOOT + select SYS_FSL_ERRATUM_A008850 if !TFABOOT select SYS_FSL_ERRATUM_A008997 select SYS_FSL_ERRATUM_A009007 select SYS_FSL_ERRATUM_A009008 select SYS_FSL_ERRATUM_A009798 select SYS_FSL_ERRATUM_A009801 - select SYS_FSL_ERRATUM_A009803 - select SYS_FSL_ERRATUM_A009942 - select SYS_FSL_ERRATUM_A010165 + select SYS_FSL_ERRATUM_A009803 if !TFABOOT + select SYS_FSL_ERRATUM_A009942 if !TFABOOT + select SYS_FSL_ERRATUM_A010165 if !TFABOOT select SYS_FSL_ERRATUM_A010539 select SYS_FSL_HAS_DDR4 select SYS_FSL_SRDS_2 -- cgit v1.1 From 2141d250f510fb33d6b42ff35bfa8f3fbbc343d0 Mon Sep 17 00:00:00 2001 From: Pankit Garg Date: Mon, 5 Nov 2018 18:01:52 +0000 Subject: armv8: fsl-layerscape: bootcmd identification for TFABOOT Adds bootcmd identificaton on basis on boot source, valid in TFABOOT configuration. Signed-off-by: Rajesh Bhagat Signed-off-by: Pankit Garg [YS: remove unnecessary braces] Reviewed-by: York Sun --- arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 14 ++++++ arch/arm/cpu/armv8/fsl-layerscape/soc.c | 77 +++++++++++++++++++++++++++++++++ 2 files changed, 91 insertions(+) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index 0b6f1e1..e25515e 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -33,6 +33,9 @@ #ifdef CONFIG_TFABOOT #include +#ifdef CONFIG_CHAIN_OF_TRUST +#include +#endif #endif DECLARE_GLOBAL_DATA_PTR; @@ -741,6 +744,14 @@ enum env_location env_get_location(enum env_operation op, int prio) if (prio) return ENVL_UNKNOWN; +#ifdef CONFIG_CHAIN_OF_TRUST + /* Check Boot Mode + * If Boot Mode is Secure, return ENVL_NOWHERE + */ + if (fsl_check_boot_mode_secure() == 1) + goto done; +#endif + switch (src) { case BOOT_SOURCE_IFC_NOR: env_loc = ENVL_FLASH; @@ -768,6 +779,9 @@ enum env_location env_get_location(enum env_operation op, int prio) break; } +#ifdef CONFIG_CHAIN_OF_TRUST +done: +#endif return env_loc; } #endif /* CONFIG_TFABOOT */ diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 54fb074..c0a8e301 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -24,6 +24,10 @@ #include #endif #include +#ifdef CONFIG_TFABOOT +#include +DECLARE_GLOBAL_DATA_PTR; +#endif bool soc_has_dp_ddr(void) { @@ -679,12 +683,85 @@ int qspi_ahb_init(void) } #endif +#ifdef CONFIG_TFABOOT +#define MAX_BOOTCMD_SIZE 256 + +int fsl_setenv_bootcmd(void) +{ + int ret; + enum boot_src src = get_boot_src(); + char bootcmd_str[MAX_BOOTCMD_SIZE]; + + switch (src) { +#ifdef IFC_NOR_BOOTCOMMAND + case BOOT_SOURCE_IFC_NOR: + sprintf(bootcmd_str, IFC_NOR_BOOTCOMMAND); + break; +#endif +#ifdef QSPI_NOR_BOOTCOMMAND + case BOOT_SOURCE_QSPI_NOR: + sprintf(bootcmd_str, QSPI_NOR_BOOTCOMMAND); + break; +#endif +#ifdef XSPI_NOR_BOOTCOMMAND + case BOOT_SOURCE_XSPI_NOR: + sprintf(bootcmd_str, XSPI_NOR_BOOTCOMMAND); + break; +#endif +#ifdef IFC_NAND_BOOTCOMMAND + case BOOT_SOURCE_IFC_NAND: + sprintf(bootcmd_str, IFC_NAND_BOOTCOMMAND); + break; +#endif +#ifdef QSPI_NAND_BOOTCOMMAND + case BOOT_SOURCE_QSPI_NAND: + sprintf(bootcmd_str, QSPI_NAND_BOOTCOMMAND); + break; +#endif +#ifdef XSPI_NAND_BOOTCOMMAND + case BOOT_SOURCE_XSPI_NAND: + sprintf(bootcmd_str, XSPI_NAND_BOOTCOMMAND); + break; +#endif +#ifdef SD_BOOTCOMMAND + case BOOT_SOURCE_SD_MMC: + sprintf(bootcmd_str, SD_BOOTCOMMAND); + break; +#endif +#ifdef SD2_BOOTCOMMAND + case BOOT_SOURCE_SD_MMC2: + sprintf(bootcmd_str, SD2_BOOTCOMMAND); + break; +#endif + default: +#ifdef QSPI_NOR_BOOTCOMMAND + sprintf(bootcmd_str, QSPI_NOR_BOOTCOMMAND); +#endif + break; + } + + ret = env_set("bootcmd", bootcmd_str); + if (ret) { + printf("Failed to set bootcmd: ret = %d\n", ret); + return ret; + } + return 0; +} +#endif + #ifdef CONFIG_BOARD_LATE_INIT int board_late_init(void) { #ifdef CONFIG_CHAIN_OF_TRUST fsl_setenv_chain_of_trust(); #endif +#ifdef CONFIG_TFABOOT + /* + * check if gd->env_addr is default_environment; then setenv bootcmd + */ + if (gd->env_addr + gd->reloc_off == (ulong)&default_environment[0]) + fsl_setenv_bootcmd(); +#endif #ifdef CONFIG_QSPI_AHB_INIT qspi_ahb_init(); #endif -- cgit v1.1 From 681d489e6281b9d4a1896ad7b8c926bb2286ed7a Mon Sep 17 00:00:00 2001 From: Rajesh Bhagat Date: Mon, 5 Nov 2018 18:01:58 +0000 Subject: armv8: layerscape: add SMC calls for DDR size and bank info Adds SMC calls for getting DDR size and bank info for TFABOOT. Signed-off-by: Rajesh Bhagat Signed-off-by: Pankit Garg Reviewed-by: York Sun --- arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 84 ++++++++++++++++++++++++++ arch/arm/include/asm/arch-fsl-layerscape/soc.h | 4 ++ 2 files changed, 88 insertions(+) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index e25515e..ca632eb 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -1229,12 +1229,96 @@ phys_size_t get_effective_memsize(void) return ea_size; } +#ifdef CONFIG_TFABOOT +phys_size_t tfa_get_dram_size(void) +{ + struct pt_regs regs; + phys_size_t dram_size = 0; + + regs.regs[0] = SMC_DRAM_BANK_INFO; + regs.regs[1] = -1; + + smc_call(®s); + if (regs.regs[0]) + return 0; + + dram_size = regs.regs[1]; + return dram_size; +} + +static int tfa_dram_init_banksize(void) +{ + int i = 0, ret = 0; + struct pt_regs regs; + phys_size_t dram_size = tfa_get_dram_size(); + + debug("dram_size %llx\n", dram_size); + + if (!dram_size) + return -EINVAL; + + do { + regs.regs[0] = SMC_DRAM_BANK_INFO; + regs.regs[1] = i; + + smc_call(®s); + if (regs.regs[0]) { + ret = -EINVAL; + break; + } + + debug("bank[%d]: start %lx, size %lx\n", i, regs.regs[1], + regs.regs[2]); + gd->bd->bi_dram[i].start = regs.regs[1]; + gd->bd->bi_dram[i].size = regs.regs[2]; + + dram_size -= gd->bd->bi_dram[i].size; + + i++; + } while (dram_size); + + if (i > 0) + ret = 0; + +#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) + /* Assign memory for MC */ +#ifdef CONFIG_SYS_DDR_BLOCK3_BASE + if (gd->bd->bi_dram[2].size >= + board_reserve_ram_top(gd->bd->bi_dram[2].size)) { + gd->arch.resv_ram = gd->bd->bi_dram[2].start + + gd->bd->bi_dram[2].size - + board_reserve_ram_top(gd->bd->bi_dram[2].size); + } else +#endif + { + if (gd->bd->bi_dram[1].size >= + board_reserve_ram_top(gd->bd->bi_dram[1].size)) { + gd->arch.resv_ram = gd->bd->bi_dram[1].start + + gd->bd->bi_dram[1].size - + board_reserve_ram_top(gd->bd->bi_dram[1].size); + } else if (gd->bd->bi_dram[0].size > + board_reserve_ram_top(gd->bd->bi_dram[0].size)) { + gd->arch.resv_ram = gd->bd->bi_dram[0].start + + gd->bd->bi_dram[0].size - + board_reserve_ram_top(gd->bd->bi_dram[0].size); + } + } +#endif /* CONFIG_FSL_MC_ENET */ + + return ret; +} +#endif + int dram_init_banksize(void) { #ifdef CONFIG_SYS_DP_DDR_BASE_PHY phys_size_t dp_ddr_size; #endif +#ifdef CONFIG_TFABOOT + if (!tfa_dram_init_banksize()) + return 0; +#endif /* * gd->ram_size has the total size of DDR memory, less reserved secure * memory. The DDR extends from low region to high region(s) presuming diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h index d327c7b..ef228b6 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h @@ -55,6 +55,10 @@ struct cpu_type { { .name = #n, .soc_ver = SVR_##v, .num_cores = (nc)} #ifdef CONFIG_TFABOOT +#define SMC_DRAM_BANK_INFO (0xC200FF12) + +phys_size_t tfa_get_dram_size(void); + enum boot_src { BOOT_SOURCE_RESERVED = 0, BOOT_SOURCE_IFC_NOR, -- cgit v1.1 From 5a73ec6169d1db85eacc4ad2fc74dad92a846c9e Mon Sep 17 00:00:00 2001 From: Rajesh Bhagat Date: Mon, 5 Nov 2018 18:02:05 +0000 Subject: armv8: layerscape: skip OCRAM init for TFABOOT OCRAM initialization is performed by TFA, Hence skipped from u-boot. Signed-off-by: Ruchika Gupta Reviewed-by: York Sun --- arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S index 11b5fb2..cbc9112 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S +++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S @@ -304,7 +304,8 @@ ENTRY(lowlevel_init) 100: #endif -#if defined(CONFIG_FSL_LSCH2) && !defined(CONFIG_SPL_BUILD) +#if !defined(CONFIG_TFABOOT) && \ + (defined(CONFIG_FSL_LSCH2) && !defined(CONFIG_SPL_BUILD)) bl fsl_ocram_init #endif -- cgit v1.1 From 56db948b85aa7c03c79b2c796500de4523924a9d Mon Sep 17 00:00:00 2001 From: York Sun Date: Mon, 5 Nov 2018 18:02:09 +0000 Subject: armv8: fsl-layerscape: Update parsing boot source Workaround of erratum A010539 clears the RCW source field in PORSR1 register, causing failure of detecting boot source using this method. Use SMC call if U-Boot runs at EL2. If SMC is not implemented or running at EL3, continue to read PORSR1 and presume QSPI as boot source if erratum workaround A010539 is enabled and RCW source is cleared. Signed-off-by: York Sun --- arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 26 ++++++++++++++++++++++---- arch/arm/include/asm/arch-fsl-layerscape/soc.h | 1 + 2 files changed, 23 insertions(+), 4 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index ca632eb..36189f7 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -693,23 +693,41 @@ enum boot_src __get_boot_src(u32 porsr1) } } #endif + + if (CONFIG_IS_ENABLED(SYS_FSL_ERRATUM_A010539) && !rcw_src) + src = BOOT_SOURCE_QSPI_NOR; + debug("%s: src 0x%x\n", __func__, src); return src; } enum boot_src get_boot_src(void) { - u32 porsr1; + struct pt_regs regs; + u32 porsr1 = 0; #if defined(CONFIG_FSL_LSCH3) u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE; - - porsr1 = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4); #elif defined(CONFIG_FSL_LSCH2) struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); +#endif + + if (current_el() == 2) { + regs.regs[0] = SIP_SVC_RCW; - porsr1 = in_be32(&gur->porsr1); + smc_call(®s); + if (!regs.regs[0]) + porsr1 = regs.regs[1]; + } + + if (current_el() == 3 || !porsr1) { +#ifdef CONFIG_FSL_LSCH3 + porsr1 = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4); +#elif defined(CONFIG_FSL_LSCH2) + porsr1 = in_be32(&gur->porsr1); #endif + } + debug("%s: porsr1 0x%x\n", __func__, porsr1); return __get_boot_src(porsr1); diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h index ef228b6..daa1c70 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h @@ -56,6 +56,7 @@ struct cpu_type { #ifdef CONFIG_TFABOOT #define SMC_DRAM_BANK_INFO (0xC200FF12) +#define SIP_SVC_RCW 0xC200FF18 phys_size_t tfa_get_dram_size(void); -- cgit v1.1 From 339fb297d45fdb98d45c2ea944b40b3e3a63d150 Mon Sep 17 00:00:00 2001 From: Rajesh Bhagat Date: Mon, 5 Nov 2018 18:02:13 +0000 Subject: armv8: sec_firmware: change el2_to_aarch32 SMC ID Changes the el2_to_aarch32 SMC ID from 0xc000ff04 to 0xc200ff17, it is applicable to both TFA and non-TFA boot. Signed-off-by: Rajesh Bhagat Reviewed-by: York Sun --- arch/arm/cpu/armv8/sec_firmware_asm.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv8/sec_firmware_asm.S b/arch/arm/cpu/armv8/sec_firmware_asm.S index 1c0f963..af1b2da 100644 --- a/arch/arm/cpu/armv8/sec_firmware_asm.S +++ b/arch/arm/cpu/armv8/sec_firmware_asm.S @@ -68,7 +68,7 @@ ENTRY(armv8_el2_to_aarch32) mov x3, x2 mov x2, x1 mov x1, x4 - ldr x0, =0xc000ff04 + ldr x0, =0xc200ff17 smc #0 ret ENDPROC(armv8_el2_to_aarch32) -- cgit v1.1 From 2e17cb8a42404201298c53fe752327f59db6ff8e Mon Sep 17 00:00:00 2001 From: Pankit Garg Date: Mon, 5 Nov 2018 18:02:19 +0000 Subject: armv8: sec_firmware: return job ring status as true in TFABOOT Returns job ring status as true in TFABOOT, as one job ring is always reserved. Signed-off-by: Ruchika Gupta Signed-off-by: Pankit Garg Reviewed-by: York Sun --- arch/arm/cpu/armv8/sec_firmware.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/cpu/armv8/sec_firmware.c b/arch/arm/cpu/armv8/sec_firmware.c index a13c92e..8dc0ac9 100644 --- a/arch/arm/cpu/armv8/sec_firmware.c +++ b/arch/arm/cpu/armv8/sec_firmware.c @@ -348,6 +348,10 @@ unsigned int sec_firmware_support_psci_version(void) */ bool sec_firmware_support_hwrng(void) { +#ifdef CONFIG_TFABOOT + /* return true as TFA has one job ring reserved */ + return true; +#endif if (sec_firmware_addr & SEC_FIRMWARE_RUNNING) { return true; } -- cgit v1.1 From 382c53f94631027782ead8147847906b1dcc5d11 Mon Sep 17 00:00:00 2001 From: Rajesh Bhagat Date: Mon, 5 Nov 2018 18:02:23 +0000 Subject: net: fm: add TFABOOT support Adds TFABOOT support and allows to pick FMAN firmware on basis of boot source. Signed-off-by: Pankit Garg Signed-off-by: Rajesh Bhagat [YS: fix checkpatch issues] Reviewed-by: York Sun --- drivers/net/fm/fm.c | 103 ++++++++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 100 insertions(+), 3 deletions(-) diff --git a/drivers/net/fm/fm.c b/drivers/net/fm/fm.c index c5cf188..e19d777 100644 --- a/drivers/net/fm/fm.c +++ b/drivers/net/fm/fm.c @@ -11,12 +11,14 @@ #include "fm.h" #include /* For struct qe_firmware */ -#ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND #include -#elif defined(CONFIG_SYS_QE_FW_IN_SPIFLASH) #include -#elif defined(CONFIG_SYS_QE_FMAN_FW_IN_MMC) #include +#include + +#ifdef CONFIG_ARM64 +#include +#include #endif struct fm_muram muram[CONFIG_SYS_NUM_FMAN]; @@ -347,6 +349,100 @@ static void fm_init_qmi(struct fm_qmi_common *qmi) } /* Init common part of FM, index is fm num# like fm as above */ +#ifdef CONFIG_TFABOOT +int fm_init_common(int index, struct ccsr_fman *reg) +{ + int rc; + void *addr = NULL; + enum boot_src src = get_boot_src(); + + if (src == BOOT_SOURCE_IFC_NOR) { + addr = (void *)(CONFIG_SYS_FMAN_FW_ADDR + + CONFIG_SYS_FSL_IFC_BASE); + } else if (src == BOOT_SOURCE_IFC_NAND) { + size_t fw_length = CONFIG_SYS_QE_FMAN_FW_LENGTH; + + addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH); + + rc = nand_read(get_nand_dev_by_index(0), + (loff_t)CONFIG_SYS_FMAN_FW_ADDR, + &fw_length, (u_char *)addr); + if (rc == -EUCLEAN) { + printf("NAND read of FMAN firmware at offset 0x%x failed %d\n", + CONFIG_SYS_FMAN_FW_ADDR, rc); + } + } else if (src == BOOT_SOURCE_QSPI_NOR) { + struct spi_flash *ucode_flash; + + addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH); + int ret = 0; + +#ifdef CONFIG_DM_SPI_FLASH + struct udevice *new; + + /* speed and mode will be read from DT */ + ret = spi_flash_probe_bus_cs(CONFIG_ENV_SPI_BUS, + CONFIG_ENV_SPI_CS, 0, 0, &new); + + ucode_flash = dev_get_uclass_priv(new); +#else + ucode_flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, + CONFIG_ENV_SPI_CS, + CONFIG_ENV_SPI_MAX_HZ, + CONFIG_ENV_SPI_MODE); +#endif + if (!ucode_flash) { + printf("SF: probe for ucode failed\n"); + } else { + ret = spi_flash_read(ucode_flash, + CONFIG_SYS_FMAN_FW_ADDR + + CONFIG_SYS_FSL_QSPI_BASE, + CONFIG_SYS_QE_FMAN_FW_LENGTH, + addr); + if (ret) + printf("SF: read for ucode failed\n"); + spi_flash_free(ucode_flash); + } + } else if (src == BOOT_SOURCE_SD_MMC) { + int dev = CONFIG_SYS_MMC_ENV_DEV; + + addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH); + u32 cnt = CONFIG_SYS_QE_FMAN_FW_LENGTH / 512; + u32 blk = CONFIG_SYS_FMAN_FW_ADDR / 512; + struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV); + + if (!mmc) { + printf("\nMMC cannot find device for ucode\n"); + } else { + printf("\nMMC read: dev # %u, block # %u, count %u ...\n", + dev, blk, cnt); + mmc_init(mmc); + (void)blk_dread(mmc_get_blk_desc(mmc), blk, cnt, + addr); + } + } else { + addr = NULL; + } + + /* Upload the Fman microcode if it's present */ + rc = fman_upload_firmware(index, ®->fm_imem, addr); + if (rc) + return rc; + env_set_addr("fman_ucode", addr); + + fm_init_muram(index, ®->muram); + fm_init_qmi(®->fm_qmi_common); + fm_init_fpm(®->fm_fpm); + + /* clear DMA status */ + setbits_be32(®->fm_dma.fmdmsr, FMDMSR_CLEAR_ALL); + + /* set DMA mode */ + setbits_be32(®->fm_dma.fmdmmr, FMDMMR_SBER); + + return fm_init_bmi(index, ®->fm_bmi_common); +} +#else int fm_init_common(int index, struct ccsr_fman *reg) { int rc; @@ -429,3 +525,4 @@ int fm_init_common(int index, struct ccsr_fman *reg) return fm_init_bmi(index, ®->fm_bmi_common); } +#endif -- cgit v1.1 From c5e6637f6889c0f7a45ad5ecd8f90a5268e5e067 Mon Sep 17 00:00:00 2001 From: Rajesh Bhagat Date: Mon, 5 Nov 2018 18:02:28 +0000 Subject: drivers: qe: add TFABOOT support Adds TFABOOT support and allows to pick QE firmware on basis of boot source. Signed-off-by: Pankit Garg Signed-off-by: Rajesh Bhagat [YS: remove line continuation in quoted string] Reviewed-by: York Sun --- drivers/qe/qe.c | 82 ++++++++++++++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 79 insertions(+), 3 deletions(-) diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c index 7010bbc..70d02d3 100644 --- a/drivers/qe/qe.c +++ b/drivers/qe/qe.c @@ -13,12 +13,15 @@ #include #include #include +#include +#include + #ifdef CONFIG_ARCH_LS1021A #include #endif - -#ifdef CONFIG_SYS_QE_FMAN_FW_IN_MMC -#include +#ifdef CONFIG_ARM64 +#include +#include #endif #define MPC85xx_DEVDISR_QE_DISABLE 0x1 @@ -170,6 +173,33 @@ void qe_put_snum(u8 snum) } } +#ifdef CONFIG_TFABOOT +void qe_init(uint qe_base) +{ + enum boot_src src = get_boot_src(); + + /* Init the QE IMMR base */ + qe_immr = (qe_map_t *)qe_base; + + if (src == BOOT_SOURCE_IFC_NOR) { + /* + * Upload microcode to IRAM for those SOCs + * which do not have ROM in QE. + */ + qe_upload_firmware((const void *)(CONFIG_SYS_QE_FW_ADDR + + CONFIG_SYS_FSL_IFC_BASE)); + + /* enable the microcode in IRAM */ + out_be32(&qe_immr->iram.iready, QE_IRAM_READY); + } + + gd->arch.mp_alloc_base = QE_DATAONLY_BASE; + gd->arch.mp_alloc_top = gd->arch.mp_alloc_base + QE_DATAONLY_SIZE; + + qe_sdma_init(); + qe_snums_init(); +} +#else void qe_init(uint qe_base) { /* Init the QE IMMR base */ @@ -192,8 +222,53 @@ void qe_init(uint qe_base) qe_snums_init(); } #endif +#endif #ifdef CONFIG_U_QE +#ifdef CONFIG_TFABOOT +void u_qe_init(void) +{ + enum boot_src src = get_boot_src(); + + qe_immr = (qe_map_t *)(CONFIG_SYS_IMMR + QE_IMMR_OFFSET); + + void *addr = (void *)CONFIG_SYS_QE_FW_ADDR; + + if (src == BOOT_SOURCE_IFC_NOR) + addr = (void *)(CONFIG_SYS_QE_FW_ADDR + CONFIG_SYS_FSL_IFC_BASE); + + if (src == BOOT_SOURCE_QSPI_NOR) + addr = (void *)(CONFIG_SYS_QE_FW_ADDR + CONFIG_SYS_FSL_QSPI_BASE); + + if (src == BOOT_SOURCE_SD_MMC) { + int dev = CONFIG_SYS_MMC_ENV_DEV; + u32 cnt = CONFIG_SYS_QE_FMAN_FW_LENGTH / 512; + u32 blk = CONFIG_SYS_QE_FW_ADDR / 512; + + if (mmc_initialize(gd->bd)) { + printf("%s: mmc_initialize() failed\n", __func__); + return; + } + addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH); + struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV); + + if (!mmc) { + free(addr); + printf("\nMMC cannot find device for ucode\n"); + } else { + printf("\nMMC read: dev # %u, block # %u, count %u ...\n", + dev, blk, cnt); + mmc_init(mmc); + (void)blk_dread(mmc_get_blk_desc(mmc), blk, cnt, + addr); + } + } + if (!u_qe_upload_firmware(addr)) + out_be32(&qe_immr->iram.iready, QE_IRAM_READY); + if (src == BOOT_SOURCE_SD_MMC) + free(addr); +} +#else void u_qe_init(void) { qe_immr = (qe_map_t *)(CONFIG_SYS_IMMR + QE_IMMR_OFFSET); @@ -229,6 +304,7 @@ void u_qe_init(void) #endif } #endif +#endif #ifdef CONFIG_U_QE void u_qe_resume(void) -- cgit v1.1 From ade32bb47375bdfaf52e151d904e2da5b4eb4344 Mon Sep 17 00:00:00 2001 From: Pankit Garg Date: Mon, 5 Nov 2018 18:02:31 +0000 Subject: armv8: fsl-layerscape: add support of MC framework for TFA Add support of MC framework for TFA Make MC framework independent of boot source. Signed-off-by: Rajesh Bhagat Signed-off-by: Pankit Garg Reviewed-by: York Sun --- arch/arm/cpu/armv8/fsl-layerscape/soc.c | 53 ++++++++++++++++++++++++++++++++- 1 file changed, 52 insertions(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index c0a8e301..0092a22 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -747,6 +747,54 @@ int fsl_setenv_bootcmd(void) } return 0; } + +int fsl_setenv_mcinitcmd(void) +{ + int ret = 0; + enum boot_src src = get_boot_src(); + + switch (src) { +#ifdef IFC_MC_INIT_CMD + case BOOT_SOURCE_IFC_NAND: + case BOOT_SOURCE_IFC_NOR: + ret = env_set("mcinitcmd", IFC_MC_INIT_CMD); + break; +#endif +#ifdef QSPI_MC_INIT_CMD + case BOOT_SOURCE_QSPI_NAND: + case BOOT_SOURCE_QSPI_NOR: + ret = env_set("mcinitcmd", QSPI_MC_INIT_CMD); + break; +#endif +#ifdef XSPI_MC_INIT_CMD + case BOOT_SOURCE_XSPI_NAND: + case BOOT_SOURCE_XSPI_NOR: + ret = env_set("mcinitcmd", XSPI_MC_INIT_CMD); + break; +#endif +#ifdef SD_MC_INIT_CMD + case BOOT_SOURCE_SD_MMC: + ret = env_set("mcinitcmd", SD_MC_INIT_CMD); + break; +#endif +#ifdef SD2_MC_INIT_CMD + case BOOT_SOURCE_SD_MMC2: + ret = env_set("mcinitcmd", SD2_MC_INIT_CMD); + break; +#endif + default: +#ifdef QSPI_MC_INIT_CMD + ret = env_set("mcinitcmd", QSPI_MC_INIT_CMD); +#endif + break; + } + + if (ret) { + printf("Failed to set mcinitcmd: ret = %d\n", ret); + return ret; + } + return 0; +} #endif #ifdef CONFIG_BOARD_LATE_INIT @@ -758,9 +806,12 @@ int board_late_init(void) #ifdef CONFIG_TFABOOT /* * check if gd->env_addr is default_environment; then setenv bootcmd + * and mcinitcmd. */ - if (gd->env_addr + gd->reloc_off == (ulong)&default_environment[0]) + if (gd->env_addr + gd->reloc_off == (ulong)&default_environment[0]) { fsl_setenv_bootcmd(); + fsl_setenv_mcinitcmd(); + } #endif #ifdef CONFIG_QSPI_AHB_INIT qspi_ahb_init(); -- cgit v1.1 From 8e156bb17638b2ce88cafc89be7a553c91d2448c Mon Sep 17 00:00:00 2001 From: Rajesh Bhagat Date: Mon, 5 Nov 2018 18:02:36 +0000 Subject: armv8: ls1046ardb: Add TFABOOT support TFABOOT support includes: - ls1046ardb_tfa_defconfig to be loaded by trusted firmware - environment address and size changes for TFABOOT - FMAN address changes for TFABOOT - define BOOTCOMMAND for TFABOOT Signed-off-by: York Sun Signed-off-by: Pankit Garg Signed-off-by: Vinitha V Pillai Signed-off-by: Rajesh Bhagat --- board/freescale/ls1046ardb/MAINTAINERS | 2 + board/freescale/ls1046ardb/ddr.c | 12 ++++++ configs/ls1046ardb_tfa_SECURE_BOOT_defconfig | 53 ++++++++++++++++++++++++++ configs/ls1046ardb_tfa_defconfig | 56 ++++++++++++++++++++++++++++ include/configs/ls1046a_common.h | 12 ++++++ include/configs/ls1046ardb.h | 15 ++++++++ 6 files changed, 150 insertions(+) create mode 100644 configs/ls1046ardb_tfa_SECURE_BOOT_defconfig create mode 100644 configs/ls1046ardb_tfa_defconfig diff --git a/board/freescale/ls1046ardb/MAINTAINERS b/board/freescale/ls1046ardb/MAINTAINERS index aac649a..b7d9564 100644 --- a/board/freescale/ls1046ardb/MAINTAINERS +++ b/board/freescale/ls1046ardb/MAINTAINERS @@ -1,5 +1,6 @@ LS1046A BOARD M: Mingkai Hu +M: Rajesh Bhagat S: Maintained F: board/freescale/ls1046ardb/ F: board/freescale/ls1046ardb/ls1046ardb.c @@ -8,6 +9,7 @@ F: configs/ls1046ardb_qspi_defconfig F: configs/ls1046ardb_qspi_spl_defconfig F: configs/ls1046ardb_sdcard_defconfig F: configs/ls1046ardb_emmc_defconfig +F: configs/ls1046ardb_tfa_defconfig LS1046A_SECURE_BOOT BOARD M: Ruchika Gupta diff --git a/board/freescale/ls1046ardb/ddr.c b/board/freescale/ls1046ardb/ddr.c index 82b1b1d..321222d 100644 --- a/board/freescale/ls1046ardb/ddr.c +++ b/board/freescale/ls1046ardb/ddr.c @@ -97,6 +97,17 @@ found: popts->cpo_sample = 0x61; } +#ifdef CONFIG_TFABOOT +int fsl_initdram(void) +{ + gd->ram_size = tfa_get_dram_size(); + + if (!gd->ram_size) + gd->ram_size = fsl_ddr_sdram_size(); + + return 0; +} +#else int fsl_initdram(void) { phys_size_t dram_size; @@ -117,3 +128,4 @@ int fsl_initdram(void) return 0; } +#endif diff --git a/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig new file mode 100644 index 0000000..bdd8748 --- /dev/null +++ b/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig @@ -0,0 +1,53 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS1046ARDB=y +CONFIG_SYS_TEXT_BASE=0x82000000 +CONFIG_SECURE_BOOT=y +CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y +CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y +CONFIG_QSPI_AHB_INIT=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_TFABOOT=y +CONFIG_BOOTDELAY=10 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.quadspi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)" +CONFIG_MISC_INIT_R=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_NAND=y +CONFIG_CMD_PCI=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_CACHE=y +CONFIG_MP=y +CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.quadspi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)" +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb" +CONFIG_DM=y +CONFIG_FSL_CAAM=y +CONFIG_FSL_ESDHC=y +CONFIG_SPI_FLASH=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_PHYLIB=y +CONFIG_PHY_AQUANTIA=y +CONFIG_E1000=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE=y +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_USB=y +CONFIG_FSL_QSPI=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_STORAGE=y +CONFIG_RSA=y +CONFIG_BLK=y +CONFIG_DM_MMC=y diff --git a/configs/ls1046ardb_tfa_defconfig b/configs/ls1046ardb_tfa_defconfig new file mode 100644 index 0000000..d6595eb --- /dev/null +++ b/configs/ls1046ardb_tfa_defconfig @@ -0,0 +1,56 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS1046ARDB=y +CONFIG_SYS_TEXT_BASE=0x82000000 +CONFIG_QSPI_AHB_INIT=y +CONFIG_TFABOOT=y +CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y +CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTDELAY=10 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.quadspi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)" +CONFIG_MISC_INIT_R=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_NAND=y +CONFIG_CMD_PCI=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_CACHE=y +CONFIG_MP=y +CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.quadspi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)" +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb" +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_DM=y +CONFIG_FSL_CAAM=y +CONFIG_FSL_ESDHC=y +CONFIG_SPI_FLASH=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_PHYLIB=y +CONFIG_PHY_AQUANTIA=y +CONFIG_E1000=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE=y +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_FSL_QSPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_STORAGE=y +CONFIG_BLK=y +CONFIG_DM_MMC=y +CONFIG_DM_SCSI=y +CONFIG_SATA_CEVA=y +CONFIG_SCSI_AHCI=y +CONFIG_SCSI=y +CONFIG_AHCI=y diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h index cdb73f6..6e36c93 100644 --- a/include/configs/ls1046a_common.h +++ b/include/configs/ls1046a_common.h @@ -33,7 +33,11 @@ #include /* Link Definitions */ +#ifdef CONFIG_TFABOOT +#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE +#else #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) +#endif #define CONFIG_SKIP_LOWLEVEL_INIT @@ -165,6 +169,13 @@ #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 #endif +#ifdef CONFIG_TFABOOT +#define CONFIG_SYS_FMAN_FW_ADDR 0x900000 +#define CONFIG_ENV_SPI_BUS 0 +#define CONFIG_ENV_SPI_CS 0 +#define CONFIG_ENV_SPI_MAX_HZ 1000000 +#define CONFIG_ENV_SPI_MODE 0x03 +#else #ifdef CONFIG_SD_BOOT /* * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is @@ -187,6 +198,7 @@ #define CONFIG_SYS_QE_FMAN_FW_IN_NOR #define CONFIG_SYS_FMAN_FW_ADDR 0x60900000 #endif +#endif #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) #endif diff --git a/include/configs/ls1046ardb.h b/include/configs/ls1046ardb.h index dcb5854..77b50db 100644 --- a/include/configs/ls1046ardb.h +++ b/include/configs/ls1046ardb.h @@ -160,6 +160,13 @@ #define CONFIG_ENV_OVERWRITE #endif +#ifdef CONFIG_TFABOOT +#define CONFIG_SYS_MMC_ENV_DEV 0 + +#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ +#define CONFIG_ENV_OFFSET 0x500000 /* 5MB */ +#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256KB */ +#else #if defined(CONFIG_SD_BOOT) #define CONFIG_SYS_MMC_ENV_DEV 0 #define CONFIG_ENV_OFFSET (3 * 1024 * 1024) @@ -169,6 +176,7 @@ #define CONFIG_ENV_OFFSET 0x300000 /* 3MB */ #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256KB */ #endif +#endif #define AQR105_IRQ_MASK 0x80000000 /* FMan */ @@ -206,6 +214,12 @@ #ifndef SPL_NO_MISC #undef CONFIG_BOOTCOMMAND +#ifdef CONFIG_TFABOOT +#define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \ + "env exists secureboot && esbc_halt;;" +#define SD_BOOTCOMMAND "run distro_bootcmd;run sd_bootcmd; " \ + "env exists secureboot && esbc_halt;" +#else #if defined(CONFIG_QSPI_BOOT) #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \ "env exists secureboot && esbc_halt;;" @@ -214,6 +228,7 @@ "env exists secureboot && esbc_halt;" #endif #endif +#endif #include -- cgit v1.1 From 50e2d41f6c9b252ec00b3ed33264d091db7ed479 Mon Sep 17 00:00:00 2001 From: Rajesh Bhagat Date: Mon, 5 Nov 2018 18:02:40 +0000 Subject: armv8: ls1046aqds: Add TFABOOT support TFABOOT support includes: - ls1046aqds_tfa_defconfig to be loaded by trusted firmware - environment address and size changes for TFABOOT - FMAN address changes for TFABOOT - define BOOTCOMMAND for TFABOOT Signed-off-by: Pankit Garg Signed-off-by: Vinitha V Pillai Signed-off-by: Rajesh Bhagat Reviewed-by: York Sun --- board/freescale/ls1046aqds/MAINTAINERS | 2 + board/freescale/ls1046aqds/ddr.c | 11 ++ board/freescale/ls1046aqds/ls1046aqds.c | 148 ++++++++++++++++++++++++++- configs/ls1046aqds_tfa_SECURE_BOOT_defconfig | 65 ++++++++++++ configs/ls1046aqds_tfa_defconfig | 65 ++++++++++++ include/configs/ls1046aqds.h | 59 ++++++++++- 6 files changed, 347 insertions(+), 3 deletions(-) create mode 100644 configs/ls1046aqds_tfa_SECURE_BOOT_defconfig create mode 100644 configs/ls1046aqds_tfa_defconfig diff --git a/board/freescale/ls1046aqds/MAINTAINERS b/board/freescale/ls1046aqds/MAINTAINERS index 76190c6..22c3926 100644 --- a/board/freescale/ls1046aqds/MAINTAINERS +++ b/board/freescale/ls1046aqds/MAINTAINERS @@ -1,5 +1,6 @@ LS1046AQDS BOARD M: Mingkai Hu +M: Rajesh Bhagat S: Maintained F: board/freescale/ls1046aqds/ F: include/configs/ls1046aqds.h @@ -9,6 +10,7 @@ F: configs/ls1046aqds_sdcard_ifc_defconfig F: configs/ls1046aqds_sdcard_qspi_defconfig F: configs/ls1046aqds_qspi_defconfig F: configs/ls1046aqds_lpuart_defconfig +F: configs/ls1046aqds_tfa_defconfig M: Sumit Garg S: Maintained diff --git a/board/freescale/ls1046aqds/ddr.c b/board/freescale/ls1046aqds/ddr.c index 08f7610..45b1f37 100644 --- a/board/freescale/ls1046aqds/ddr.c +++ b/board/freescale/ls1046aqds/ddr.c @@ -92,6 +92,16 @@ found: popts->cpo_sample = 0x70; } +#ifdef CONFIG_TFABOOT +int fsl_initdram(void) +{ + gd->ram_size = tfa_get_dram_size(); + if (!gd->ram_size) + gd->ram_size = fsl_ddr_sdram_size(); + + return 0; +} +#else int fsl_initdram(void) { phys_size_t dram_size; @@ -116,3 +126,4 @@ int fsl_initdram(void) return 0; } +#endif diff --git a/board/freescale/ls1046aqds/ls1046aqds.c b/board/freescale/ls1046aqds/ls1046aqds.c index 0da8238..b71c174 100644 --- a/board/freescale/ls1046aqds/ls1046aqds.c +++ b/board/freescale/ls1046aqds/ls1046aqds.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -32,12 +33,140 @@ DECLARE_GLOBAL_DATA_PTR; +#ifdef CONFIG_TFABOOT +struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { + { + "nor0", + CONFIG_SYS_NOR0_CSPR, + CONFIG_SYS_NOR0_CSPR_EXT, + CONFIG_SYS_NOR_AMASK, + CONFIG_SYS_NOR_CSOR, + { + CONFIG_SYS_NOR_FTIM0, + CONFIG_SYS_NOR_FTIM1, + CONFIG_SYS_NOR_FTIM2, + CONFIG_SYS_NOR_FTIM3 + }, + + }, + { + "nor1", + CONFIG_SYS_NOR1_CSPR, + CONFIG_SYS_NOR1_CSPR_EXT, + CONFIG_SYS_NOR_AMASK, + CONFIG_SYS_NOR_CSOR, + { + CONFIG_SYS_NOR_FTIM0, + CONFIG_SYS_NOR_FTIM1, + CONFIG_SYS_NOR_FTIM2, + CONFIG_SYS_NOR_FTIM3 + }, + }, + { + "nand", + CONFIG_SYS_NAND_CSPR, + CONFIG_SYS_NAND_CSPR_EXT, + CONFIG_SYS_NAND_AMASK, + CONFIG_SYS_NAND_CSOR, + { + CONFIG_SYS_NAND_FTIM0, + CONFIG_SYS_NAND_FTIM1, + CONFIG_SYS_NAND_FTIM2, + CONFIG_SYS_NAND_FTIM3 + }, + }, + { + "fpga", + CONFIG_SYS_FPGA_CSPR, + CONFIG_SYS_FPGA_CSPR_EXT, + CONFIG_SYS_FPGA_AMASK, + CONFIG_SYS_FPGA_CSOR, + { + CONFIG_SYS_FPGA_FTIM0, + CONFIG_SYS_FPGA_FTIM1, + CONFIG_SYS_FPGA_FTIM2, + CONFIG_SYS_FPGA_FTIM3 + }, + } +}; + +struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { + { + "nand", + CONFIG_SYS_NAND_CSPR, + CONFIG_SYS_NAND_CSPR_EXT, + CONFIG_SYS_NAND_AMASK, + CONFIG_SYS_NAND_CSOR, + { + CONFIG_SYS_NAND_FTIM0, + CONFIG_SYS_NAND_FTIM1, + CONFIG_SYS_NAND_FTIM2, + CONFIG_SYS_NAND_FTIM3 + }, + }, + { + "nor0", + CONFIG_SYS_NOR0_CSPR, + CONFIG_SYS_NOR0_CSPR_EXT, + CONFIG_SYS_NOR_AMASK, + CONFIG_SYS_NOR_CSOR, + { + CONFIG_SYS_NOR_FTIM0, + CONFIG_SYS_NOR_FTIM1, + CONFIG_SYS_NOR_FTIM2, + CONFIG_SYS_NOR_FTIM3 + }, + }, + { + "nor1", + CONFIG_SYS_NOR1_CSPR, + CONFIG_SYS_NOR1_CSPR_EXT, + CONFIG_SYS_NOR_AMASK, + CONFIG_SYS_NOR_CSOR, + { + CONFIG_SYS_NOR_FTIM0, + CONFIG_SYS_NOR_FTIM1, + CONFIG_SYS_NOR_FTIM2, + CONFIG_SYS_NOR_FTIM3 + }, + }, + { + "fpga", + CONFIG_SYS_FPGA_CSPR, + CONFIG_SYS_FPGA_CSPR_EXT, + CONFIG_SYS_FPGA_AMASK, + CONFIG_SYS_FPGA_CSOR, + { + CONFIG_SYS_FPGA_FTIM0, + CONFIG_SYS_FPGA_FTIM1, + CONFIG_SYS_FPGA_FTIM2, + CONFIG_SYS_FPGA_FTIM3 + }, + } +}; + +void ifc_cfg_boot_info(struct ifc_regs_info *regs_info) +{ + enum boot_src src = get_boot_src(); + + if (src == BOOT_SOURCE_IFC_NAND) + regs_info->regs = ifc_cfg_nand_boot; + else + regs_info->regs = ifc_cfg_nor_boot; + regs_info->cs_size = CONFIG_SYS_FSL_IFC_BANK_COUNT; +} + +#endif + enum { MUX_TYPE_GPIO, }; int checkboard(void) { +#ifdef CONFIG_TFABOOT + enum boot_src src = get_boot_src(); +#endif char buf[64]; #ifndef CONFIG_SD_BOOT u8 sw; @@ -45,6 +174,12 @@ int checkboard(void) puts("Board: LS1046AQDS, boot from "); +#ifdef CONFIG_TFABOOT + if (src == BOOT_SOURCE_SD_MMC) + puts("SD\n"); + else { +#endif + #ifdef CONFIG_SD_BOOT puts("SD\n"); #else @@ -63,6 +198,9 @@ int checkboard(void) printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); #endif +#ifdef CONFIG_TFABOOT + } +#endif printf("Sys ID: 0x%02x, Sys Ver: 0x%02x\n", QIXIS_READ(id), QIXIS_READ(arch)); @@ -153,7 +291,8 @@ int dram_init(void) */ select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); fsl_initdram(); -#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) +#if (!defined(CONFIG_SPL) && !defined(CONFIG_TFABOOT)) || \ + defined(CONFIG_SPL_BUILD) /* This will break-before-make MMU for DDR */ update_early_mmu_table(); #endif @@ -342,3 +481,10 @@ u16 flash_read16(void *addr) return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00); } + +#ifdef CONFIG_TFABOOT +void *env_sf_get_env_addr(void) +{ + return (void *)(CONFIG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET); +} +#endif diff --git a/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig new file mode 100644 index 0000000..e554d2d --- /dev/null +++ b/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig @@ -0,0 +1,65 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS1046AQDS=y +CONFIG_SYS_TEXT_BASE=0x82000000 +CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y +CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y +CONFIG_SECURE_BOOT=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_TFABOOT=y +CONFIG_BOOTDELAY=10 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:4m(nand_uboot),36m(nand_kernel),472m(nand_free);spi0.0:2m(uboot),14m(free)" +# CONFIG_USE_BOOTCOMMAND is not set +CONFIG_MISC_INIT_R=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_IMLS=y +CONFIG_CMD_GREPENV=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_NAND=y +CONFIG_CMD_PCI=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_CACHE=y +CONFIG_MP=y +CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:4m(nand_uboot),36m(nand_kernel),472m(nand_free);spi0.0:2m(uboot),14m(free)" +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart" +CONFIG_ENV_IS_NOWHERE=y +CONFIG_DM=y +CONFIG_FSL_CAAM=y +CONFIG_DM_MMC=y +CONFIG_FSL_ESDHC=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_CFI_DRIVER=y +CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y +CONFIG_SYS_FLASH_CFI=y +CONFIG_SPI_FLASH=y +CONFIG_PHYLIB=y +CONFIG_E1000=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE=y +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_FSL_DSPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_STORAGE=y +CONFIG_RSA=y +CONFIG_DM_SCSI=y +CONFIG_SATA_CEVA=y +CONFIG_SCSI_AHCI=y +CONFIG_SCSI=y +CONFIG_AHCI=y diff --git a/configs/ls1046aqds_tfa_defconfig b/configs/ls1046aqds_tfa_defconfig new file mode 100644 index 0000000..44c5ca5 --- /dev/null +++ b/configs/ls1046aqds_tfa_defconfig @@ -0,0 +1,65 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS1046AQDS=y +CONFIG_SYS_TEXT_BASE=0x82000000 +CONFIG_TFABOOT=y +CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y +CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTDELAY=10 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:4m(nand_uboot),36m(nand_kernel),472m(nand_free);spi0.0:2m(uboot),14m(free)" +# CONFIG_USE_BOOTCOMMAND is not set +CONFIG_MISC_INIT_R=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_IMLS=y +CONFIG_CMD_GREPENV=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_NAND=y +CONFIG_CMD_PCI=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_CACHE=y +CONFIG_MP=y +CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:4m(nand_uboot),36m(nand_kernel),472m(nand_free);spi0.0:2m(uboot),14m(free)" +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart" +CONFIG_ENV_IS_IN_FLASH=y +CONFIG_ENV_IS_IN_NAND=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_DM=y +CONFIG_FSL_CAAM=y +CONFIG_DM_MMC=y +CONFIG_FSL_ESDHC=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_CFI_DRIVER=y +CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y +CONFIG_SYS_FLASH_CFI=y +CONFIG_SPI_FLASH=y +CONFIG_PHYLIB=y +CONFIG_E1000=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE=y +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_FSL_DSPI=y +CONFIG_FSL_QSPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_STORAGE=y +CONFIG_DM_SCSI=y +CONFIG_SATA_CEVA=y +CONFIG_SCSI_AHCI=y +CONFIG_SCSI=y +CONFIG_AHCI=y diff --git a/include/configs/ls1046aqds.h b/include/configs/ls1046aqds.h index 9ae0953..886fe72 100644 --- a/include/configs/ls1046aqds.h +++ b/include/configs/ls1046aqds.h @@ -50,7 +50,8 @@ unsigned long get_board_ddr_clk(void); #endif /* QSPI */ -#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) +#if defined(CONFIG_TFABOOT) || \ + defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) #ifdef CONFIG_FSL_QSPI #define CONFIG_SPI_FLASH_SPANSION #define FSL_QSPI_FLASH_SIZE (1 << 24) @@ -227,7 +228,8 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) #endif -#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) +#if defined(CONFIG_TFABOOT) || \ + defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) #define CONFIG_QIXIS_I2C_ACCESS #define CONFIG_SYS_I2C_EARLY_INIT #endif @@ -282,6 +284,40 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_FPGA_FTIM3 0x0 #endif +#ifdef CONFIG_TFABOOT +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT +#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR +#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK +#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR +#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 +#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 +#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 +#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 +#else #ifdef CONFIG_NAND_BOOT #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR @@ -349,6 +385,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 #endif +#endif /* * I2C bus multiplexer @@ -399,6 +436,14 @@ unsigned long get_board_ddr_clk(void); */ #define CONFIG_ENV_OVERWRITE +#ifdef CONFIG_TFABOOT +#define CONFIG_SYS_MMC_ENV_DEV 0 + +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_OFFSET 0x500000 /* 5MB */ +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x500000) +#define CONFIG_ENV_SECT_SIZE 0x20000 +#else #ifdef CONFIG_NAND_BOOT #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_ENV_OFFSET (12 * CONFIG_SYS_NAND_BLOCK_SIZE) @@ -415,10 +460,19 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_ENV_SECT_SIZE 0x20000 #define CONFIG_ENV_SIZE 0x20000 #endif +#endif #define CONFIG_CMDLINE_TAG #undef CONFIG_BOOTCOMMAND +#ifdef CONFIG_TFABOOT +#define QSPI_NOR_BOOTCOMMAND "sf probe && sf read $kernel_load " \ + "e0000 f00000 && bootm $kernel_load" +#define IFC_NOR_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \ + "$kernel_size && bootm $kernel_load" +#define SD_BOOTCOMMAND "mmc info; mmc read $kernel_load" \ + "$kernel_addr_sd $kernel_size_sd && bootm $kernel_load" +#else #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) #define CONFIG_BOOTCOMMAND "sf probe && sf read $kernel_load " \ "e0000 f00000 && bootm $kernel_load" @@ -426,6 +480,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \ "$kernel_size && bootm $kernel_load" #endif +#endif #include -- cgit v1.1 From f71b5f1101f6445af9b0dc53d533f84c9e7a8a04 Mon Sep 17 00:00:00 2001 From: Rajesh Bhagat Date: Mon, 5 Nov 2018 18:02:44 +0000 Subject: armv8: ls1043ardb: Add TFABOOT support TFABOOT support includes: - ls1043ardb_tfa_defconfig to be loaded by trusted firmware - environment address and size changes for TFABOOT - FMAN and QE address changes for TFABOOT - define BOOTCOMMAND for TFABOOT Signed-off-by: Pankit Garg Signed-off-by: Vinitha V Pillai Signed-off-by: Rajesh Bhagat Reviewed-by: York Sun --- board/freescale/ls1043ardb/MAINTAINERS | 2 + board/freescale/ls1043ardb/ddr.c | 14 ++++ board/freescale/ls1043ardb/ls1043ardb.c | 110 +++++++++++++++++++++++++++ configs/ls1043ardb_tfa_SECURE_BOOT_defconfig | 55 ++++++++++++++ configs/ls1043ardb_tfa_defconfig | 52 +++++++++++++ include/configs/ls1043a_common.h | 27 ++++++- include/configs/ls1043ardb.h | 29 +++++++ 7 files changed, 288 insertions(+), 1 deletion(-) create mode 100644 configs/ls1043ardb_tfa_SECURE_BOOT_defconfig create mode 100644 configs/ls1043ardb_tfa_defconfig diff --git a/board/freescale/ls1043ardb/MAINTAINERS b/board/freescale/ls1043ardb/MAINTAINERS index 88fe42e..3f64a6f 100644 --- a/board/freescale/ls1043ardb/MAINTAINERS +++ b/board/freescale/ls1043ardb/MAINTAINERS @@ -1,5 +1,6 @@ LS1043A BOARD M: Mingkai Hu +M: Rajesh Bhagat S: Maintained F: board/freescale/ls1043ardb/ F: board/freescale/ls1043ardb/ls1043ardb.c @@ -7,6 +8,7 @@ F: include/configs/ls1043ardb.h F: configs/ls1043ardb_defconfig F: configs/ls1043ardb_nand_defconfig F: configs/ls1043ardb_sdcard_defconfig +F: configs/ls1043ardb_tfa_defconfig LS1043A_SECURE_BOOT BOARD M: Ruchika Gupta diff --git a/board/freescale/ls1043ardb/ddr.c b/board/freescale/ls1043ardb/ddr.c index 7bc0f56..784e482 100644 --- a/board/freescale/ls1043ardb/ddr.c +++ b/board/freescale/ls1043ardb/ddr.c @@ -205,6 +205,19 @@ phys_size_t fixed_sdram(void) } #endif +#ifdef CONFIG_TFABOOT +int fsl_initdram(void) +{ + gd->ram_size = tfa_get_dram_size(); + if (!gd->ram_size) +#ifdef CONFIG_SYS_DDR_RAW_TIMING + gd->ram_size = fsl_ddr_sdram_size(); +#else + gd->ram_size = 0x80000000; +#endif + return 0; +} +#else int fsl_initdram(void) { phys_size_t dram_size; @@ -236,3 +249,4 @@ int fsl_initdram(void) return 0; } +#endif diff --git a/board/freescale/ls1043ardb/ls1043ardb.c b/board/freescale/ls1043ardb/ls1043ardb.c index f31f0ec..fbd9a26 100644 --- a/board/freescale/ls1043ardb/ls1043ardb.c +++ b/board/freescale/ls1043ardb/ls1043ardb.c @@ -27,6 +27,104 @@ DECLARE_GLOBAL_DATA_PTR; +#ifdef CONFIG_TFABOOT +struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { + { + "nor", + CONFIG_SYS_NOR_CSPR, + CONFIG_SYS_NOR_CSPR_EXT, + CONFIG_SYS_NOR_AMASK, + CONFIG_SYS_NOR_CSOR, + { + CONFIG_SYS_NOR_FTIM0, + CONFIG_SYS_NOR_FTIM1, + CONFIG_SYS_NOR_FTIM2, + CONFIG_SYS_NOR_FTIM3 + }, + + }, + { + "nand", + CONFIG_SYS_NAND_CSPR, + CONFIG_SYS_NAND_CSPR_EXT, + CONFIG_SYS_NAND_AMASK, + CONFIG_SYS_NAND_CSOR, + { + CONFIG_SYS_NAND_FTIM0, + CONFIG_SYS_NAND_FTIM1, + CONFIG_SYS_NAND_FTIM2, + CONFIG_SYS_NAND_FTIM3 + }, + }, + { + "cpld", + CONFIG_SYS_CPLD_CSPR, + CONFIG_SYS_CPLD_CSPR_EXT, + CONFIG_SYS_CPLD_AMASK, + CONFIG_SYS_CPLD_CSOR, + { + CONFIG_SYS_CPLD_FTIM0, + CONFIG_SYS_CPLD_FTIM1, + CONFIG_SYS_CPLD_FTIM2, + CONFIG_SYS_CPLD_FTIM3 + }, + } +}; + +struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { + { + "nand", + CONFIG_SYS_NAND_CSPR, + CONFIG_SYS_NAND_CSPR_EXT, + CONFIG_SYS_NAND_AMASK, + CONFIG_SYS_NAND_CSOR, + { + CONFIG_SYS_NAND_FTIM0, + CONFIG_SYS_NAND_FTIM1, + CONFIG_SYS_NAND_FTIM2, + CONFIG_SYS_NAND_FTIM3 + }, + }, + { + "nor", + CONFIG_SYS_NOR_CSPR, + CONFIG_SYS_NOR_CSPR_EXT, + CONFIG_SYS_NOR_AMASK, + CONFIG_SYS_NOR_CSOR, + { + CONFIG_SYS_NOR_FTIM0, + CONFIG_SYS_NOR_FTIM1, + CONFIG_SYS_NOR_FTIM2, + CONFIG_SYS_NOR_FTIM3 + }, + }, + { + "cpld", + CONFIG_SYS_CPLD_CSPR, + CONFIG_SYS_CPLD_CSPR_EXT, + CONFIG_SYS_CPLD_AMASK, + CONFIG_SYS_CPLD_CSOR, + { + CONFIG_SYS_CPLD_FTIM0, + CONFIG_SYS_CPLD_FTIM1, + CONFIG_SYS_CPLD_FTIM2, + CONFIG_SYS_CPLD_FTIM3 + }, + } +}; + +void ifc_cfg_boot_info(struct ifc_regs_info *regs_info) +{ + enum boot_src src = get_boot_src(); + + if (src == BOOT_SOURCE_IFC_NAND) + regs_info->regs = ifc_cfg_nand_boot; + else + regs_info->regs = ifc_cfg_nor_boot; + regs_info->cs_size = CONFIG_SYS_FSL_IFC_BANK_COUNT; +} + +#endif int board_early_init_f(void) { fsl_lsch2_early_init_f(); @@ -38,6 +136,9 @@ int board_early_init_f(void) int checkboard(void) { +#ifdef CONFIG_TFABOOT + enum boot_src src = get_boot_src(); +#endif static const char *freq[2] = {"100.00MHZ", "156.25MHZ"}; #ifndef CONFIG_SD_BOOT u8 cfg_rcw_src1, cfg_rcw_src2; @@ -47,6 +148,12 @@ int checkboard(void) printf("Board: LS1043ARDB, boot from "); +#ifdef CONFIG_TFABOOT + if (src == BOOT_SOURCE_SD_MMC) + puts("SD\n"); + else { +#endif + #ifdef CONFIG_SD_BOOT puts("SD\n"); #else @@ -64,6 +171,9 @@ int checkboard(void) printf("Invalid setting of SW4\n"); #endif +#ifdef CONFIG_TFABOOT + } +#endif printf("CPLD: V%x.%x\nPCBA: V%x.0\n", CPLD_READ(cpld_ver), CPLD_READ(cpld_ver_sub), CPLD_READ(pcba_ver)); diff --git a/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig new file mode 100644 index 0000000..0ad9db7 --- /dev/null +++ b/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig @@ -0,0 +1,55 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS1043ARDB=y +CONFIG_SYS_TEXT_BASE=0x82000000 +CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y +CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y +CONFIG_SECURE_BOOT=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTDELAY=10 +CONFIG_TFABOOT=y +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)" +CONFIG_MISC_INIT_R=y +CONFIG_CMD_IMLS=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_NAND=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_CACHE=y +CONFIG_MP=y +CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)" +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb" +CONFIG_DM=y +CONFIG_DM_MMC=y +CONFIG_FSL_ESDHC=y +CONFIG_FSL_CAAM=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_CFI_DRIVER=y +CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y +CONFIG_SYS_FLASH_CFI=y +CONFIG_SPI_FLASH=y +CONFIG_PHYLIB=y +CONFIG_PHY_GIGE=y +CONFIG_E1000=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE=y +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_STORAGE=y +CONFIG_RSA=y +CONFIG_SPL_RSA=y +CONFIG_RSA_SOFTWARE_EXP=y diff --git a/configs/ls1043ardb_tfa_defconfig b/configs/ls1043ardb_tfa_defconfig new file mode 100644 index 0000000..662a966 --- /dev/null +++ b/configs/ls1043ardb_tfa_defconfig @@ -0,0 +1,52 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS1043ARDB=y +CONFIG_SYS_TEXT_BASE=0x82000000 +CONFIG_TFABOOT=y +CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y +CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTDELAY=10 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)" +CONFIG_MISC_INIT_R=y +CONFIG_CMD_IMLS=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_NAND=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_CACHE=y +CONFIG_MP=y +CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)" +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb" +CONFIG_ENV_IS_IN_FLASH=y +CONFIG_ENV_IS_IN_NAND=y +CONFIG_DM=y +CONFIG_FSL_CAAM=y +CONFIG_DM_MMC=y +CONFIG_FSL_ESDHC=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_CFI_DRIVER=y +CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y +CONFIG_SYS_FLASH_CFI=y +CONFIG_SPI_FLASH=y +CONFIG_PHYLIB=y +CONFIG_PHY_AQUANTIA=y +CONFIG_E1000=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE=y +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_STORAGE=y diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index 4279d53..27350df 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -33,7 +33,11 @@ #include /* Link Definitions */ +#ifdef CONFIG_TFABOOT +#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE +#else #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) +#endif #define CONFIG_SKIP_LOWLEVEL_INIT @@ -119,7 +123,8 @@ /* IFC */ #ifndef SPL_NO_IFC -#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) +#if defined(CONFIG_TFABOOT) || \ + (!defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)) #define CONFIG_FSL_IFC /* * CONFIG_SYS_FLASH_BASE has the final address (core view) @@ -182,6 +187,16 @@ #ifdef CONFIG_SYS_DPAA_FMAN #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 +#ifdef CONFIG_TFABOOT +#define CONFIG_SYS_FMAN_FW_ADDR 0x900000 +#define CONFIG_SYS_QE_FW_ADDR 0x940000 + +#define CONFIG_ENV_SPI_BUS 0 +#define CONFIG_ENV_SPI_CS 0 +#define CONFIG_ENV_SPI_MAX_HZ 1000000 +#define CONFIG_ENV_SPI_MODE 0x03 + +#else #ifdef CONFIG_NAND_BOOT /* Store Fman ucode at offeset 0x900000(72 blocks). */ #define CONFIG_SYS_QE_FMAN_FW_IN_NAND @@ -208,6 +223,7 @@ #define CONFIG_SYS_FMAN_FW_ADDR 0x60900000 #define CONFIG_SYS_QE_FW_ADDR 0x60940000 #endif +#endif #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) #endif @@ -300,6 +316,14 @@ #undef CONFIG_BOOTCOMMAND +#ifdef CONFIG_TFABOOT +#define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \ + "env exists secureboot && esbc_halt;" +#define SD_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; " \ + "env exists secureboot && esbc_halt;" +#define IFC_NOR_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; " \ + "env exists secureboot && esbc_halt;" +#else #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \ "env exists secureboot && esbc_halt;" @@ -311,6 +335,7 @@ "env exists secureboot && esbc_halt;" #endif #endif +#endif /* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h index 54e6eef..a0d3987 100644 --- a/include/configs/ls1043ardb.h +++ b/include/configs/ls1043ardb.h @@ -162,6 +162,25 @@ #define CONFIG_SYS_CPLD_FTIM3 0x0 /* IFC Timing Params */ +#ifdef CONFIG_TFABOOT +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 + +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 +#else #ifdef CONFIG_NAND_BOOT #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR @@ -199,6 +218,7 @@ #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 #endif +#endif #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_CPLD_CSPR_EXT #define CONFIG_SYS_CSPR2 CONFIG_SYS_CPLD_CSPR @@ -227,6 +247,14 @@ #define CONFIG_ENV_OVERWRITE #endif +#ifdef CONFIG_TFABOOT +#define CONFIG_SYS_MMC_ENV_DEV 0 + +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_OFFSET 0x500000 +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x500000) +#define CONFIG_ENV_SECT_SIZE 0x20000 +#else #if defined(CONFIG_NAND_BOOT) #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_ENV_OFFSET (24 * CONFIG_SYS_NAND_BLOCK_SIZE) @@ -239,6 +267,7 @@ #define CONFIG_ENV_SECT_SIZE 0x20000 #define CONFIG_ENV_SIZE 0x20000 #endif +#endif /* FMan */ #ifndef SPL_NO_FMAN -- cgit v1.1 From 8aa6b17a4d2fe4f75414da8493cf8c0fa59ccf3a Mon Sep 17 00:00:00 2001 From: Rajesh Bhagat Date: Mon, 5 Nov 2018 18:02:48 +0000 Subject: armv8: ls1043aqds: Add TFABOOT support TFABOOT support includes: - ls1043aqds_tfa_defconfig to be loaded by trusted firmware - environment address and size changes for TFABOOT - define BOOTCOMMAND for TFABOOT Signed-off-by: Pankit Garg Signed-off-by: Vinitha V Pillai Signed-off-by: Rajesh Bhagat Reviewed-by: York Sun --- board/freescale/ls1043aqds/MAINTAINERS | 2 + board/freescale/ls1043aqds/ddr.c | 11 ++ board/freescale/ls1043aqds/ls1043aqds.c | 147 ++++++++++++++++++++++++++- configs/ls1043aqds_tfa_SECURE_BOOT_defconfig | 61 +++++++++++ configs/ls1043aqds_tfa_defconfig | 59 +++++++++++ include/configs/ls1043aqds.h | 50 ++++++++- 6 files changed, 327 insertions(+), 3 deletions(-) create mode 100644 configs/ls1043aqds_tfa_SECURE_BOOT_defconfig create mode 100644 configs/ls1043aqds_tfa_defconfig diff --git a/board/freescale/ls1043aqds/MAINTAINERS b/board/freescale/ls1043aqds/MAINTAINERS index 3c8e8c2..d10eb56 100644 --- a/board/freescale/ls1043aqds/MAINTAINERS +++ b/board/freescale/ls1043aqds/MAINTAINERS @@ -1,5 +1,6 @@ LS1043AQDS BOARD M: Mingkai Hu +M: Rajesh Bhagat S: Maintained F: board/freescale/ls1043aqds/ F: include/configs/ls1043aqds.h @@ -10,3 +11,4 @@ F: configs/ls1043aqds_sdcard_ifc_defconfig F: configs/ls1043aqds_sdcard_qspi_defconfig F: configs/ls1043aqds_qspi_defconfig F: configs/ls1043aqds_lpuart_defconfig +F: configs/ls1043aqds_tfa_defconfig diff --git a/board/freescale/ls1043aqds/ddr.c b/board/freescale/ls1043aqds/ddr.c index efc441a..d29a3ad 100644 --- a/board/freescale/ls1043aqds/ddr.c +++ b/board/freescale/ls1043aqds/ddr.c @@ -108,6 +108,16 @@ found: #endif } +#ifdef CONFIG_TFABOOT +int fsl_initdram(void) +{ + gd->ram_size = tfa_get_dram_size(); + if (!gd->ram_size) + gd->ram_size = fsl_ddr_sdram_size(); + + return 0; +} +#else int fsl_initdram(void) { phys_size_t dram_size; @@ -131,3 +141,4 @@ int fsl_initdram(void) return 0; } +#endif diff --git a/board/freescale/ls1043aqds/ls1043aqds.c b/board/freescale/ls1043aqds/ls1043aqds.c index 44cc509..45f006d 100644 --- a/board/freescale/ls1043aqds/ls1043aqds.c +++ b/board/freescale/ls1043aqds/ls1043aqds.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -46,8 +47,135 @@ enum { #define CFG_UART_MUX_SHIFT 1 #define CFG_LPUART_EN 0x1 +#ifdef CONFIG_TFABOOT +struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { + { + "nor0", + CONFIG_SYS_NOR0_CSPR, + CONFIG_SYS_NOR0_CSPR_EXT, + CONFIG_SYS_NOR_AMASK, + CONFIG_SYS_NOR_CSOR, + { + CONFIG_SYS_NOR_FTIM0, + CONFIG_SYS_NOR_FTIM1, + CONFIG_SYS_NOR_FTIM2, + CONFIG_SYS_NOR_FTIM3 + }, + + }, + { + "nor1", + CONFIG_SYS_NOR1_CSPR, + CONFIG_SYS_NOR1_CSPR_EXT, + CONFIG_SYS_NOR_AMASK, + CONFIG_SYS_NOR_CSOR, + { + CONFIG_SYS_NOR_FTIM0, + CONFIG_SYS_NOR_FTIM1, + CONFIG_SYS_NOR_FTIM2, + CONFIG_SYS_NOR_FTIM3 + }, + }, + { + "nand", + CONFIG_SYS_NAND_CSPR, + CONFIG_SYS_NAND_CSPR_EXT, + CONFIG_SYS_NAND_AMASK, + CONFIG_SYS_NAND_CSOR, + { + CONFIG_SYS_NAND_FTIM0, + CONFIG_SYS_NAND_FTIM1, + CONFIG_SYS_NAND_FTIM2, + CONFIG_SYS_NAND_FTIM3 + }, + }, + { + "fpga", + CONFIG_SYS_FPGA_CSPR, + CONFIG_SYS_FPGA_CSPR_EXT, + CONFIG_SYS_FPGA_AMASK, + CONFIG_SYS_FPGA_CSOR, + { + CONFIG_SYS_FPGA_FTIM0, + CONFIG_SYS_FPGA_FTIM1, + CONFIG_SYS_FPGA_FTIM2, + CONFIG_SYS_FPGA_FTIM3 + }, + } +}; + +struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { + { + "nand", + CONFIG_SYS_NAND_CSPR, + CONFIG_SYS_NAND_CSPR_EXT, + CONFIG_SYS_NAND_AMASK, + CONFIG_SYS_NAND_CSOR, + { + CONFIG_SYS_NAND_FTIM0, + CONFIG_SYS_NAND_FTIM1, + CONFIG_SYS_NAND_FTIM2, + CONFIG_SYS_NAND_FTIM3 + }, + }, + { + "nor0", + CONFIG_SYS_NOR0_CSPR, + CONFIG_SYS_NOR0_CSPR_EXT, + CONFIG_SYS_NOR_AMASK, + CONFIG_SYS_NOR_CSOR, + { + CONFIG_SYS_NOR_FTIM0, + CONFIG_SYS_NOR_FTIM1, + CONFIG_SYS_NOR_FTIM2, + CONFIG_SYS_NOR_FTIM3 + }, + }, + { + "nor1", + CONFIG_SYS_NOR1_CSPR, + CONFIG_SYS_NOR1_CSPR_EXT, + CONFIG_SYS_NOR_AMASK, + CONFIG_SYS_NOR_CSOR, + { + CONFIG_SYS_NOR_FTIM0, + CONFIG_SYS_NOR_FTIM1, + CONFIG_SYS_NOR_FTIM2, + CONFIG_SYS_NOR_FTIM3 + }, + }, + { + "fpga", + CONFIG_SYS_FPGA_CSPR, + CONFIG_SYS_FPGA_CSPR_EXT, + CONFIG_SYS_FPGA_AMASK, + CONFIG_SYS_FPGA_CSOR, + { + CONFIG_SYS_FPGA_FTIM0, + CONFIG_SYS_FPGA_FTIM1, + CONFIG_SYS_FPGA_FTIM2, + CONFIG_SYS_FPGA_FTIM3 + }, + } +}; + +void ifc_cfg_boot_info(struct ifc_regs_info *regs_info) +{ + enum boot_src src = get_boot_src(); + + if (src == BOOT_SOURCE_IFC_NAND) + regs_info->regs = ifc_cfg_nand_boot; + else + regs_info->regs = ifc_cfg_nor_boot; + regs_info->cs_size = CONFIG_SYS_FSL_IFC_BANK_COUNT; +} +#endif + int checkboard(void) { +#ifdef CONFIG_TFABOOT + enum boot_src src = get_boot_src(); +#endif char buf[64]; #ifndef CONFIG_SD_BOOT u8 sw; @@ -55,6 +183,12 @@ int checkboard(void) puts("Board: LS1043AQDS, boot from "); +#ifdef CONFIG_TFABOOT + if (src == BOOT_SOURCE_SD_MMC) + puts("SD\n"); + else { +#endif + #ifdef CONFIG_SD_BOOT puts("SD\n"); #else @@ -73,6 +207,9 @@ int checkboard(void) printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); #endif +#ifdef CONFIG_TFABOOT + } +#endif printf("Sys ID: 0x%02x, Sys Ver: 0x%02x\n", QIXIS_READ(id), QIXIS_READ(arch)); @@ -156,7 +293,8 @@ int dram_init(void) */ select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); fsl_initdram(); -#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) +#if (!defined(CONFIG_SPL) && !defined(CONFIG_TFABOOT)) || \ + defined(CONFIG_SPL_BUILD) /* This will break-before-make MMU for DDR */ update_early_mmu_table(); #endif @@ -386,3 +524,10 @@ u16 flash_read16(void *addr) return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00); } + +#ifdef CONFIG_TFABOOT +void *env_sf_get_env_addr(void) +{ + return (void *)(CONFIG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET); +} +#endif diff --git a/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig new file mode 100644 index 0000000..c375e1b --- /dev/null +++ b/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig @@ -0,0 +1,61 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS1043AQDS=y +CONFIG_SYS_TEXT_BASE=0x82000000 +CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y +CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y +CONFIG_SECURE_BOOT=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTDELAY=10 +CONFIG_TFABOOT=y +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)" +# CONFIG_USE_BOOTCOMMAND is not set +CONFIG_MISC_INIT_R=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_IMLS=y +CONFIG_CMD_GREPENV=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_NAND=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_CACHE=y +CONFIG_MP=y +CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)" +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart" +CONFIG_ENV_IS_NOWHERE=y +CONFIG_DM=y +CONFIG_SATA_CEVA=y +CONFIG_FSL_CAAM=y +CONFIG_DM_MMC=y +CONFIG_FSL_ESDHC=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_CFI_DRIVER=y +CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y +CONFIG_SYS_FLASH_CFI=y +CONFIG_SPI_FLASH=y +CONFIG_PHYLIB=y +CONFIG_E1000=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE=y +CONFIG_DM_SCSI=y +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_STORAGE=y +CONFIG_RSA=y +CONFIG_SPL_RSA=y +CONFIG_RSA_SOFTWARE_EXP=y diff --git a/configs/ls1043aqds_tfa_defconfig b/configs/ls1043aqds_tfa_defconfig new file mode 100644 index 0000000..6fa0418 --- /dev/null +++ b/configs/ls1043aqds_tfa_defconfig @@ -0,0 +1,59 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS1043AQDS=y +CONFIG_SYS_TEXT_BASE=0x82000000 +CONFIG_TFABOOT=y +CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y +CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTDELAY=10 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)" +# CONFIG_USE_BOOTCOMMAND is not set +CONFIG_MISC_INIT_R=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_IMLS=y +CONFIG_CMD_GREPENV=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_NAND=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_CACHE=y +CONFIG_MP=y +CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)" +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart" +CONFIG_ENV_IS_IN_FLASH=y +CONFIG_ENV_IS_IN_NAND=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_DM=y +CONFIG_SATA_CEVA=y +CONFIG_FSL_CAAM=y +CONFIG_DM_MMC=y +CONFIG_FSL_ESDHC=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_CFI_DRIVER=y +CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y +CONFIG_SYS_FLASH_CFI=y +CONFIG_SPI_FLASH=y +CONFIG_PHYLIB=y +CONFIG_E1000=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE=y +CONFIG_DM_SCSI=y +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_STORAGE=y diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h index 68f202f..ed07d9f 100644 --- a/include/configs/ls1043aqds.h +++ b/include/configs/ls1043aqds.h @@ -196,7 +196,8 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_NAND_U_BOOT_SIZE (640 << 10) #endif -#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) +#if defined(CONFIG_TFABOOT) || \ + defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) #define CONFIG_QIXIS_I2C_ACCESS #define CONFIG_SYS_I2C_EARLY_INIT #endif @@ -251,6 +252,40 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_FPGA_FTIM3 0x0 #endif +#ifdef CONFIG_TFABOOT +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT +#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR +#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK +#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR +#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 +#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 +#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 +#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 +#else #ifdef CONFIG_NAND_BOOT #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR @@ -318,6 +353,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 #endif +#endif /* * I2C bus multiplexer @@ -349,7 +385,8 @@ unsigned long get_board_ddr_clk(void); #define VDD_MV_MAX 1212 /* QSPI device */ -#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) +#if defined(CONFIG_TFABOOT) || \ + (defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)) #define CONFIG_FSL_QSPI #ifdef CONFIG_FSL_QSPI #define CONFIG_SPI_FLASH_SPANSION @@ -381,6 +418,14 @@ unsigned long get_board_ddr_clk(void); */ #define CONFIG_ENV_OVERWRITE +#ifdef CONFIG_TFABOOT +#define CONFIG_SYS_MMC_ENV_DEV 0 + +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_OFFSET 0x500000 /* 5MB */ +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x500000) +#define CONFIG_ENV_SECT_SIZE 0x20000 +#else #ifdef CONFIG_NAND_BOOT #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_ENV_OFFSET (24 * CONFIG_SYS_NAND_BLOCK_SIZE) @@ -397,6 +442,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_ENV_SECT_SIZE 0x20000 #define CONFIG_ENV_SIZE 0x20000 #endif +#endif #define CONFIG_CMDLINE_TAG -- cgit v1.1 From 1f6180dff9b5c1b6df87f54b0fb0d458798d557e Mon Sep 17 00:00:00 2001 From: Rajesh Bhagat Date: Mon, 5 Nov 2018 18:02:53 +0000 Subject: armv8: ls1012ardb: Add TFABOOT support TFABOOT support includes: - ls1012ardb_tfa_defconfig to be loaded by trusted firmware - environment address and size changes for TFABOOT - define BOOTCOMMAND for TFABOOT - enable PFE validation for secure boot Signed-off-by: Rajesh Bhagat Signed-off-by: Vinitha V Pillai Signed-off-by: Pankit Garg Reviewed-by: York Sun --- board/freescale/ls1012ardb/Kconfig | 4 ++ board/freescale/ls1012ardb/MAINTAINERS | 2 + board/freescale/ls1012ardb/ls1012ardb.c | 16 +++++++- configs/ls1012ardb_tfa_SECURE_BOOT_defconfig | 59 ++++++++++++++++++++++++++++ configs/ls1012ardb_tfa_defconfig | 57 +++++++++++++++++++++++++++ include/configs/ls1012a_common.h | 16 +++++++- include/configs/ls1012ardb.h | 6 +++ 7 files changed, 158 insertions(+), 2 deletions(-) create mode 100644 configs/ls1012ardb_tfa_SECURE_BOOT_defconfig create mode 100644 configs/ls1012ardb_tfa_defconfig diff --git a/board/freescale/ls1012ardb/Kconfig b/board/freescale/ls1012ardb/Kconfig index 4cd66bd..51efd0f 100644 --- a/board/freescale/ls1012ardb/Kconfig +++ b/board/freescale/ls1012ardb/Kconfig @@ -33,6 +33,10 @@ config SYS_LS_PFE_FW_ADDR hex "Flash address of PFE firmware" default 0x40a00000 +config SYS_LS_PFE_ESBC_ADDR + hex "PFE Firmware HDR Addr" + default 0x40700000 + config DDR_PFE_PHYS_BASEADDR hex "PFE DDR physical base address" default 0x03800000 diff --git a/board/freescale/ls1012ardb/MAINTAINERS b/board/freescale/ls1012ardb/MAINTAINERS index a0a0d8d..bb2a183 100644 --- a/board/freescale/ls1012ardb/MAINTAINERS +++ b/board/freescale/ls1012ardb/MAINTAINERS @@ -1,9 +1,11 @@ LS1012ARDB BOARD M: Prabhakar Kushwaha +M: Rajesh Bhagat S: Maintained F: board/freescale/ls1012ardb/ F: include/configs/ls1012ardb.h F: configs/ls1012ardb_qspi_defconfig +F: configs/ls1012ardb_tfa_defconfig M: Sumit Garg S: Maintained diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c index 888f850..f648a90 100644 --- a/board/freescale/ls1012ardb/ls1012ardb.c +++ b/board/freescale/ls1012ardb/ls1012ardb.c @@ -87,8 +87,19 @@ int checkboard(void) return 0; } +#ifdef CONFIG_TFABOOT int dram_init(void) { + gd->ram_size = tfa_get_dram_size(); + if (!gd->ram_size) + gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + + return 0; +} +#else +int dram_init(void) +{ +#ifndef CONFIG_TFABOOT static const struct fsl_mmdc_info mparam = { 0x05180000, /* mdctl */ 0x00030035, /* mdpdc */ @@ -106,6 +117,7 @@ int dram_init(void) }; mmdc_init(&mparam); +#endif gd->ram_size = CONFIG_SYS_SDRAM_SIZE; #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) @@ -115,6 +127,7 @@ int dram_init(void) return 0; } +#endif int board_early_init_f(void) @@ -132,7 +145,8 @@ int board_init(void) * Set CCI-400 control override register to enable barrier * transaction */ - out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); + if (current_el() == 3) + out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); #ifdef CONFIG_SYS_FSL_ERRATUM_A010315 erratum_a010315(); diff --git a/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig new file mode 100644 index 0000000..1cb811f --- /dev/null +++ b/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig @@ -0,0 +1,59 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS1012ARDB=y +CONFIG_SYS_TEXT_BASE=0x82000000 +CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y +CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y +CONFIG_SECURE_BOOT=y +CONFIG_QSPI_AHB_INIT=y +CONFIG_AHCI=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_NR_DRAM_BANKS=2 +# CONFIG_SYS_MALLOC_F is not set +CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_TFABOOT=y +CONFIG_BOOTDELAY=10 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 quiet lpj=250000" +# CONFIG_USE_BOOTCOMMAND is not set +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_CMD_GREPENV=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_CACHE=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-rdb" +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_DM=y +CONFIG_SATA_CEVA=y +CONFIG_DM_MMC=y +CONFIG_FSL_ESDHC=y +CONFIG_DM_SPI_FLASH=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_SPI_FLASH=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_E1000=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE=y +CONFIG_DM_SCSI=y +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_FSL_DSPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_STORAGE=y +CONFIG_RSA=y +CONFIG_RSA_SOFTWARE_EXP=y diff --git a/configs/ls1012ardb_tfa_defconfig b/configs/ls1012ardb_tfa_defconfig new file mode 100644 index 0000000..557bf6c --- /dev/null +++ b/configs/ls1012ardb_tfa_defconfig @@ -0,0 +1,57 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS1012ARDB=y +CONFIG_SYS_TEXT_BASE=0x82000000 +CONFIG_QSPI_AHB_INIT=y +CONFIG_TFABOOT=y +CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y +CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y +CONFIG_AHCI=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_NR_DRAM_BANKS=2 +# CONFIG_SYS_MALLOC_F is not set +CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_BOOTDELAY=10 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 quiet lpj=250000" +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_CMD_GREPENV=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_CACHE=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-rdb" +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_DM=y +CONFIG_SATA_CEVA=y +CONFIG_DM_MMC=y +CONFIG_FSL_ESDHC=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_FSL_PFE=y +CONFIG_DM_ETH=y +CONFIG_E1000=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE=y +CONFIG_DM_SCSI=y +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_FSL_DSPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_STORAGE=y diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h index 787adbc..324dba2 100644 --- a/include/configs/ls1012a_common.h +++ b/include/configs/ls1012a_common.h @@ -16,7 +16,11 @@ #define CONFIG_SKIP_LOWLEVEL_INIT +#ifdef CONFIG_TFABOOT +#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE +#else #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) +#endif #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 @@ -34,7 +38,7 @@ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024) /*SPI device */ -#ifdef CONFIG_QSPI_BOOT +#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_TFABOOT) #define CONFIG_SYS_QE_FW_IN_SPIFLASH #define CONFIG_SYS_FMAN_FW_ADDR 0x400d0000 #define CONFIG_ENV_SPI_BUS 0 @@ -58,7 +62,11 @@ #define CONFIG_ENV_OVERWRITE #define CONFIG_ENV_SIZE 0x40000 /* 256KB */ +#ifdef CONFIG_TFABOOT +#define CONFIG_ENV_OFFSET 0x500000 /* 5MB */ +#else #define CONFIG_ENV_OFFSET 0x300000 /* 3MB */ +#endif #define CONFIG_ENV_SECT_SIZE 0x40000 #endif @@ -106,9 +114,15 @@ "kernel_size=0x2800000\0" \ #undef CONFIG_BOOTCOMMAND +#ifdef CONFIG_TFABOOT +#define QSPI_NOR_BOOTCOMMAND "pfe stop; sf probe 0:0; sf read $kernel_load "\ + "$kernel_start $kernel_size && "\ + "bootm $kernel_load" +#else #define CONFIG_BOOTCOMMAND "pfe stop; sf probe 0:0; sf read $kernel_load "\ "$kernel_start $kernel_size && "\ "bootm $kernel_load" +#endif /* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h index 17554ea..f149a60 100644 --- a/include/configs/ls1012ardb.h +++ b/include/configs/ls1012ardb.h @@ -112,8 +112,14 @@ "bootm $load_addr#$board\0" #undef CONFIG_BOOTCOMMAND +#ifdef CONFIG_TFABOOT +#undef QSPI_NOR_BOOTCOMMAND +#define QSPI_NOR_BOOTCOMMAND "pfe stop; run distro_bootcmd; run qspi_bootcmd; "\ + "env exists secureboot && esbc_halt;" +#else #define CONFIG_BOOTCOMMAND "pfe stop; run distro_bootcmd; run qspi_bootcmd; "\ "env exists secureboot && esbc_halt;" +#endif #include -- cgit v1.1 From e5141cbe965e947ee42aa77aea569327fb80810d Mon Sep 17 00:00:00 2001 From: Rajesh Bhagat Date: Mon, 5 Nov 2018 18:02:59 +0000 Subject: armv8: ls1012aqds: fix secure boot compilation Includes environment.h file in ls1012aqds.c Also, enables pfe validation Signed-off-by: Vinitha V Pillai Reviewed-by: York Sun --- board/freescale/ls1012aqds/Kconfig | 10 ++++++++++ board/freescale/ls1012aqds/ls1012aqds.c | 6 ++++++ include/configs/ls1012aqds.h | 1 + 3 files changed, 17 insertions(+) diff --git a/board/freescale/ls1012aqds/Kconfig b/board/freescale/ls1012aqds/Kconfig index b702fb2..8844557 100644 --- a/board/freescale/ls1012aqds/Kconfig +++ b/board/freescale/ls1012aqds/Kconfig @@ -16,6 +16,12 @@ config SYS_LS_PPA_FW_ADDR hex "PPA Firmware Addr" default 0x40400000 +if CHAIN_OF_TRUST +config SYS_LS_PPA_ESBC_ADDR + hex "PPA Firmware HDR Addr" + default 0x40680000 +endif + if FSL_PFE config BOARD_SPECIFIC_OPTIONS # dummy @@ -33,6 +39,10 @@ config SYS_LS_PFE_FW_ADDR hex "Flash address of PFE firmware" default 0x40a00000 +config SYS_LS_PFE_ESBC_ADDR + hex "PFE Firmware HDR Addr" + default 0x40700000 + config DDR_PFE_PHYS_BASEADDR hex "PFE DDR physical base address" default 0x03800000 diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c index 7102237..3a1c235 100644 --- a/board/freescale/ls1012aqds/ls1012aqds.c +++ b/board/freescale/ls1012aqds/ls1012aqds.c @@ -18,12 +18,14 @@ #include #include #include +#include #include #include #include #include #include #include +#include #include "../common/qixis.h" #include "ls1012aqds_qixis.h" #include "ls1012aqds_pfe.h" @@ -121,6 +123,10 @@ int board_init(void) gd->env_addr = (ulong)&default_environment[0]; #endif +#ifdef CONFIG_FSL_CAAM + sec_init(); +#endif + #ifdef CONFIG_FSL_LS_PPA ppa_init(); #endif diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h index c5bdea6..c76bfdc 100644 --- a/include/configs/ls1012aqds.h +++ b/include/configs/ls1012aqds.h @@ -117,4 +117,5 @@ #define CONFIG_SYS_MEMTEST_START 0x80000000 #define CONFIG_SYS_MEMTEST_END 0x9fffffff +#include #endif /* __LS1012AQDS_H__ */ -- cgit v1.1 From 10c8aa16d4f6b395d72fb0b0d06ed405e1985d81 Mon Sep 17 00:00:00 2001 From: Rajesh Bhagat Date: Mon, 5 Nov 2018 18:03:04 +0000 Subject: armv8: ls1012aqds: Add TFABOOT support TFABOOT support includes: - ls1012aqds_tfa_defconfig to be loaded by trusted firmware - environment address and size changes for TFABOOT - define BOOTCOMMAND for TFABOOT Signed-off-by: Rajesh Bhagat Signed-off-by: Vinitha V Pillai Signed-off-by: Pankit Garg Reviewed-by: York Sun --- board/freescale/ls1012aqds/MAINTAINERS | 2 + board/freescale/ls1012aqds/ls1012aqds.c | 17 ++++++-- configs/ls1012aqds_tfa_SECURE_BOOT_defconfig | 65 ++++++++++++++++++++++++++++ configs/ls1012aqds_tfa_defconfig | 63 +++++++++++++++++++++++++++ 4 files changed, 144 insertions(+), 3 deletions(-) create mode 100644 configs/ls1012aqds_tfa_SECURE_BOOT_defconfig create mode 100644 configs/ls1012aqds_tfa_defconfig diff --git a/board/freescale/ls1012aqds/MAINTAINERS b/board/freescale/ls1012aqds/MAINTAINERS index 27c4aff..2dcc22a 100644 --- a/board/freescale/ls1012aqds/MAINTAINERS +++ b/board/freescale/ls1012aqds/MAINTAINERS @@ -1,6 +1,8 @@ LS1012AQDS BOARD M: Prabhakar Kushwaha +M: Rajesh Bhagat S: Maintained F: board/freescale/ls1012aqds/ F: include/configs/ls1012aqds.h F: configs/ls1012aqds_qspi_defconfig +F: configs/ls1012aqds_tfa_defconfig diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c index 3a1c235..a862fe6 100644 --- a/board/freescale/ls1012aqds/ls1012aqds.c +++ b/board/freescale/ls1012aqds/ls1012aqds.c @@ -57,6 +57,16 @@ int checkboard(void) return 0; } +#ifdef CONFIG_TFABOOT +int dram_init(void) +{ + gd->ram_size = tfa_get_dram_size(); + if (!gd->ram_size) + gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + + return 0; +} +#else int dram_init(void) { static const struct fsl_mmdc_info mparam = { @@ -76,7 +86,6 @@ int dram_init(void) }; mmdc_init(&mparam); - gd->ram_size = CONFIG_SYS_SDRAM_SIZE; #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) /* This will break-before-make MMU for DDR */ @@ -85,6 +94,7 @@ int dram_init(void) return 0; } +#endif int board_early_init_f(void) { @@ -112,8 +122,9 @@ int board_init(void) /* Set CCI-400 control override register to enable barrier * transaction */ - out_le32(&cci->ctrl_ord, - CCI400_CTRLORD_EN_BARRIER); + if (current_el() == 3) + out_le32(&cci->ctrl_ord, + CCI400_CTRLORD_EN_BARRIER); #ifdef CONFIG_SYS_FSL_ERRATUM_A010315 erratum_a010315(); diff --git a/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig new file mode 100644 index 0000000..b4423cb --- /dev/null +++ b/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig @@ -0,0 +1,65 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS1012AQDS=y +CONFIG_SECURE_BOOT=y +CONFIG_SYS_TEXT_BASE=0x82000000 +CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y +CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y +CONFIG_QSPI_AHB_INIT=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_NR_DRAM_BANKS=2 +# CONFIG_SYS_MALLOC_F is not set +CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_TFABOOT=y +CONFIG_BOOTDELAY=10 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 quiet lpj=250000" +# CONFIG_USE_BOOTCOMMAND is not set +CONFIG_MISC_INIT_R=y +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_CMD_GREPENV=y +CONFIG_CMD_EEPROM=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_CACHE=y +CONFIG_CMD_DATE=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-qds" +CONFIG_ENV_IS_NOWHERE=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_DM=y +CONFIG_SCSI_AHCI=y +CONFIG_SATA_CEVA=y +CONFIG_DM_MMC=y +CONFIG_FSL_ESDHC=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_FSL_PFE=y +CONFIG_DM_ETH=y +CONFIG_E1000=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE=y +CONFIG_SCSI=y +CONFIG_DM_SCSI=y +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_FSL_DSPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_STORAGE=y +CONFIG_RSA=y +CONFIG_RSA_SOFTWARE_EXP=y diff --git a/configs/ls1012aqds_tfa_defconfig b/configs/ls1012aqds_tfa_defconfig new file mode 100644 index 0000000..78a4479 --- /dev/null +++ b/configs/ls1012aqds_tfa_defconfig @@ -0,0 +1,63 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS1012AQDS=y +CONFIG_SYS_TEXT_BASE=0x82000000 +CONFIG_QSPI_AHB_INIT=y +CONFIG_TFABOOT=y +CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y +CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y +CONFIG_AHCI=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_NR_DRAM_BANKS=2 +# CONFIG_SYS_MALLOC_F is not set +CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_BOOTDELAY=10 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 quiet lpj=250000" +# CONFIG_USE_BOOTCOMMAND is not set +CONFIG_MISC_INIT_R=y +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_CMD_GREPENV=y +CONFIG_CMD_EEPROM=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_CACHE=y +CONFIG_CMD_DATE=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-qds" +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_DM=y +CONFIG_SCSI_AHCI=y +CONFIG_SATA_CEVA=y +CONFIG_DM_MMC=y +CONFIG_FSL_ESDHC=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_FSL_PFE=y +CONFIG_DM_ETH=y +CONFIG_E1000=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE=y +CONFIG_SCSI=y +CONFIG_DM_SCSI=y +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_FSL_DSPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_STORAGE=y -- cgit v1.1 From 7f91b6584446856f8b4b4d8bb28ac77f9f011e6c Mon Sep 17 00:00:00 2001 From: Rajesh Bhagat Date: Mon, 5 Nov 2018 18:03:08 +0000 Subject: armv8: ls1012afrx: Add TFABOOT support TFABOOT support includes: - ls1012a2g5rdb/ls1012afrdm/ls1012afrwy_tfa_defconfig to be loaded by trusted firmware - define BOOTCOMMAND for TFABOOT Signed-off-by: Pankit Garg Signed-off-by: Rajesh Bhagat [YS: remove unnecessary braces] Reviewed-by: York Sun --- board/freescale/ls1012afrdm/MAINTAINERS | 3 ++ board/freescale/ls1012afrdm/ls1012afrdm.c | 28 +++++++++++++- configs/ls1012a2g5rdb_tfa_defconfig | 50 +++++++++++++++++++++++++ configs/ls1012afrdm_tfa_defconfig | 50 +++++++++++++++++++++++++ configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig | 53 +++++++++++++++++++++++++++ configs/ls1012afrwy_tfa_defconfig | 51 ++++++++++++++++++++++++++ include/configs/ls1012a2g5rdb.h | 6 +++ include/configs/ls1012afrdm.h | 5 +++ include/configs/ls1012afrwy.h | 6 +++ 9 files changed, 251 insertions(+), 1 deletion(-) create mode 100644 configs/ls1012a2g5rdb_tfa_defconfig create mode 100644 configs/ls1012afrdm_tfa_defconfig create mode 100644 configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig create mode 100644 configs/ls1012afrwy_tfa_defconfig diff --git a/board/freescale/ls1012afrdm/MAINTAINERS b/board/freescale/ls1012afrdm/MAINTAINERS index f3fcdb8..5ef4ae8 100644 --- a/board/freescale/ls1012afrdm/MAINTAINERS +++ b/board/freescale/ls1012afrdm/MAINTAINERS @@ -1,9 +1,12 @@ LS1012AFRDM BOARD M: Prabhakar Kushwaha +M: Rajesh Bhagat S: Maintained F: board/freescale/ls1012afrdm/ F: include/configs/ls1012afrdm.h F: configs/ls1012afrdm_qspi_defconfig +F: configs/ls1012afrdm_tfa_defconfig +F: configs/ls1012afrwy_tfa_defconfig LS1012AFRWY BOARD M: Bhaskar Upadhaya diff --git a/board/freescale/ls1012afrdm/ls1012afrdm.c b/board/freescale/ls1012afrdm/ls1012afrdm.c index 5db1027..b4c611e 100644 --- a/board/freescale/ls1012afrdm/ls1012afrdm.c +++ b/board/freescale/ls1012afrdm/ls1012afrdm.c @@ -80,6 +80,30 @@ int esdhc_status_fixup(void *blob, const char *compat) } #endif +#ifdef CONFIG_TFABOOT +int dram_init(void) +{ +#ifdef CONFIG_TARGET_LS1012AFRWY + int board_rev; +#endif + + gd->ram_size = tfa_get_dram_size(); + + if (!gd->ram_size) { +#ifdef CONFIG_TARGET_LS1012AFRWY + board_rev = get_board_version(); + + if (board_rev & BOARD_REV_C) + gd->ram_size = SYS_SDRAM_SIZE_1024; + else + gd->ram_size = SYS_SDRAM_SIZE_512; +#else + gd->ram_size = CONFIG_SYS_SDRAM_SIZE; +#endif + } + return 0; +} +#else int dram_init(void) { #ifdef CONFIG_TARGET_LS1012AFRWY @@ -122,6 +146,7 @@ int dram_init(void) return 0; } +#endif int board_early_init_f(void) { @@ -139,7 +164,8 @@ int board_init(void) * Set CCI-400 control override register to enable barrier * transaction */ - out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); + if (current_el() == 3) + out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); #ifdef CONFIG_ENV_IS_NOWHERE gd->env_addr = (ulong)&default_environment[0]; diff --git a/configs/ls1012a2g5rdb_tfa_defconfig b/configs/ls1012a2g5rdb_tfa_defconfig new file mode 100644 index 0000000..3987eb4 --- /dev/null +++ b/configs/ls1012a2g5rdb_tfa_defconfig @@ -0,0 +1,50 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS1012A2G5RDB=y +CONFIG_SYS_TEXT_BASE=0x82000000 +CONFIG_QSPI_AHB_INIT=y +CONFIG_TFABOOT=y +CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y +CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y +CONFIG_AHCI=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_NR_DRAM_BANKS=2 +# CONFIG_SYS_MALLOC_F is not set +CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_BOOTDELAY=10 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 quiet lpj=250000" +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_CMD_GREPENV=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_CACHE=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-2g5rdb" +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_DM=y +CONFIG_SATA_CEVA=y +CONFIG_DM_MMC=y +CONFIG_FSL_ESDHC=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_FSL_PFE=y +CONFIG_DM_ETH=y +CONFIG_DM_SCSI=y +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_STORAGE=y diff --git a/configs/ls1012afrdm_tfa_defconfig b/configs/ls1012afrdm_tfa_defconfig new file mode 100644 index 0000000..703f9cb --- /dev/null +++ b/configs/ls1012afrdm_tfa_defconfig @@ -0,0 +1,50 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS1012AFRDM=y +CONFIG_SYS_TEXT_BASE=0x82000000 +CONFIG_QSPI_AHB_INIT=y +CONFIG_TFABOOT=y +CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y +CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_NR_DRAM_BANKS=2 +# CONFIG_SYS_MALLOC_F is not set +CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_BOOTDELAY=10 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 quiet lpj=250000" +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_CMD_GREPENV=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_CACHE=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-frdm" +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_DM=y +# CONFIG_MMC is not set +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_FSL_PFE=y +CONFIG_DM_ETH=y +CONFIG_E1000=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE=y +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_STORAGE=y diff --git a/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig b/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig new file mode 100644 index 0000000..0c6f474 --- /dev/null +++ b/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig @@ -0,0 +1,53 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS1012AFRWY=y +CONFIG_SYS_TEXT_BASE=0x82000000 +CONFIG_TFABOOT=y +CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y +CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y +CONFIG_SECURE_BOOT=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_NR_DRAM_BANKS=2 +# CONFIG_SYS_MALLOC_F is not set +CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_BOOTDELAY=10 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 quiet lpj=250000" +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_CMD_GREPENV=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_CACHE=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-frwy" +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_DM=y +# CONFIG_BLK is not set +CONFIG_DM_MMC=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_FSL_PFE=y +CONFIG_DM_ETH=y +CONFIG_E1000=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE=y +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_STORAGE=y +CONFIG_RSA=y +CONFIG_RSA_SOFTWARE_EXP=y diff --git a/configs/ls1012afrwy_tfa_defconfig b/configs/ls1012afrwy_tfa_defconfig new file mode 100644 index 0000000..2d6002c --- /dev/null +++ b/configs/ls1012afrwy_tfa_defconfig @@ -0,0 +1,51 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS1012AFRWY=y +CONFIG_SYS_TEXT_BASE=0x82000000 +CONFIG_TFABOOT=y +CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y +CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_NR_DRAM_BANKS=2 +# CONFIG_SYS_MALLOC_F is not set +CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_BOOTDELAY=10 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 quiet lpj=250000" +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_CMD_GREPENV=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_CACHE=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-frwy" +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_DM=y +# CONFIG_BLK is not set +CONFIG_DM_MMC=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_FSL_PFE=y +CONFIG_DM_ETH=y +CONFIG_E1000=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE=y +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_STORAGE=y diff --git a/include/configs/ls1012a2g5rdb.h b/include/configs/ls1012a2g5rdb.h index 71e4a8b..cb32938 100644 --- a/include/configs/ls1012a2g5rdb.h +++ b/include/configs/ls1012a2g5rdb.h @@ -93,10 +93,16 @@ "bootm $load_addr#$board\0" #undef CONFIG_BOOTCOMMAND +#ifdef CONFIG_TFABOOT +#undef QSPI_NOR_BOOTCOMMAND +#define QSPI_NOR_BOOTCOMMAND "pfe stop;run distro_bootcmd; run qspi_bootcmd; " \ + "env exists secureboot && esbc_halt;" +#else #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) #define CONFIG_BOOTCOMMAND "pfe stop;run distro_bootcmd; run qspi_bootcmd; " \ "env exists secureboot && esbc_halt;" #endif +#endif #define DEFAULT_PFE_MDIO_NAME "PFE_MDIO" #define DEFAULT_PFE_MDIO1_NAME "PFE_MDIO1" diff --git a/include/configs/ls1012afrdm.h b/include/configs/ls1012afrdm.h index 7affabf..8c7d4e5 100644 --- a/include/configs/ls1012afrdm.h +++ b/include/configs/ls1012afrdm.h @@ -65,7 +65,12 @@ "$kernel_addr $kernel_size && bootm $load_addr#$board\0" #undef CONFIG_BOOTCOMMAND +#ifdef CONFIG_TFABOOT +#undef QSPI_NOR_BOOTCOMMAND +#define QSPI_NOR_BOOTCOMMAND "pfe stop;run distro_bootcmd;run qspi_bootcmd" +#else #define CONFIG_BOOTCOMMAND "pfe stop;run distro_bootcmd;run qspi_bootcmd" +#endif #define CONFIG_CMD_MEMINFO #define CONFIG_SYS_MEMTEST_START 0x80000000 diff --git a/include/configs/ls1012afrwy.h b/include/configs/ls1012afrwy.h index e450002..ebb1df4 100644 --- a/include/configs/ls1012afrwy.h +++ b/include/configs/ls1012afrwy.h @@ -119,8 +119,14 @@ "bootm $load_addr#$board\0" #undef CONFIG_BOOTCOMMAND +#ifdef CONFIG_TFABOOT +#undef QSPI_NOR_BOOTCOMMAND +#define QSPI_NOR_BOOTCOMMAND "pfe stop; run distro_bootcmd; run sd_bootcmd; "\ + "env exists secureboot && esbc_halt;" +#else #define CONFIG_BOOTCOMMAND "pfe stop; run distro_bootcmd; run sd_bootcmd; "\ "env exists secureboot && esbc_halt;" +#endif #define CONFIG_CMD_MEMINFO #define CONFIG_CMD_MEMTEST #define CONFIG_SYS_MEMTEST_START 0x80000000 -- cgit v1.1 From 5fcae59741d95f946b45e0c48dfaeb16f3b617ae Mon Sep 17 00:00:00 2001 From: Peng Ma Date: Thu, 11 Oct 2018 10:34:19 +0000 Subject: scsi: ceva: add ls1046a soc support Add ahci compatible support for ls1046a soc. Signed-off-by: Peng Ma Reviewed-by: York Sun --- drivers/ata/sata_ceva.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/ata/sata_ceva.c b/drivers/ata/sata_ceva.c index 65896d1..a2d21d9 100644 --- a/drivers/ata/sata_ceva.c +++ b/drivers/ata/sata_ceva.c @@ -99,6 +99,7 @@ enum ceva_soc { CEVA_LS1012A, CEVA_LS1021A, CEVA_LS1043A, + CEVA_LS1046A, }; struct ceva_sata_priv { @@ -138,6 +139,7 @@ static int ceva_init_sata(struct ceva_sata_priv *priv) case CEVA_LS1012A: case CEVA_LS1043A: + case CEVA_LS1046A: writel(ECC_DIS_ADDR_CH2, ECC_DIS_VAL_CH2); writel(CEVA_PHY1_CFG, base + AHCI_VEND_PPCFG); writel(CEVA_TRANS_CFG, base + AHCI_VEND_PTC); @@ -170,6 +172,7 @@ static const struct udevice_id sata_ceva_ids[] = { { .compatible = "fsl,ls1012a-ahci", .data = CEVA_LS1012A }, { .compatible = "fsl,ls1021a-ahci", .data = CEVA_LS1021A }, { .compatible = "fsl,ls1043a-ahci", .data = CEVA_LS1043A }, + { .compatible = "fsl,ls1046a-ahci", .data = CEVA_LS1046A }, { } }; -- cgit v1.1 From 539e0cb6dc48216e802157f224a2ea138c2ac8eb Mon Sep 17 00:00:00 2001 From: Peng Ma Date: Thu, 11 Oct 2018 10:34:20 +0000 Subject: armv8: dts: fsl-ls1046a: add sata node support One ls1046a, there is one SATA 3.0 advanced host controller interface which is a high-performance SATA solution that delivers comprehensive and fully-compliant generation 3 (1.5 Gb/s - 6.0 Gb/s) serial ATA capabilities, in accordance with the serial ATA revision 3.0 of Serial ATA International Organization. Add sata node to support this feature. Signed-off-by: Peng Ma Reviewed-by: York Sun --- arch/arm/dts/fsl-ls1046a-qds.dtsi | 4 ++++ arch/arm/dts/fsl-ls1046a-rdb.dts | 4 ++++ arch/arm/dts/fsl-ls1046a.dtsi | 8 ++++++++ 3 files changed, 16 insertions(+) diff --git a/arch/arm/dts/fsl-ls1046a-qds.dtsi b/arch/arm/dts/fsl-ls1046a-qds.dtsi index ba36853..ada8a85 100644 --- a/arch/arm/dts/fsl-ls1046a-qds.dtsi +++ b/arch/arm/dts/fsl-ls1046a-qds.dtsi @@ -76,3 +76,7 @@ &lpuart0 { status = "okay"; }; + +&sata { + status = "okay"; +}; diff --git a/arch/arm/dts/fsl-ls1046a-rdb.dts b/arch/arm/dts/fsl-ls1046a-rdb.dts index 136de245..ba30fd2 100644 --- a/arch/arm/dts/fsl-ls1046a-rdb.dts +++ b/arch/arm/dts/fsl-ls1046a-rdb.dts @@ -39,3 +39,7 @@ reg = <1>; }; }; + +&sata { + status = "okay"; +}; diff --git a/arch/arm/dts/fsl-ls1046a.dtsi b/arch/arm/dts/fsl-ls1046a.dtsi index 7687d12..5ac10e0 100644 --- a/arch/arm/dts/fsl-ls1046a.dtsi +++ b/arch/arm/dts/fsl-ls1046a.dtsi @@ -291,5 +291,13 @@ ranges = <0x81000000 0x0 0x00000000 0x50 0x00020000 0x0 0x00010000 /* downstream I/O */ 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ }; + + sata: sata@3200000 { + compatible = "fsl,ls1046a-ahci"; + reg = <0x0 0x3200000 0x0 0x10000>; + interrupts = <0 69 4>; + clocks = <&clockgen 4 1>; + status = "disabled"; + }; }; }; -- cgit v1.1 From a492f7ff891aaeae3b0438f0a47f8d19e15f24b2 Mon Sep 17 00:00:00 2001 From: Peng Ma Date: Thu, 11 Oct 2018 10:34:21 +0000 Subject: arm64: ls1046ardb: enable DM support for sata Enable related configs to support sata DM feature. Signed-off-by: Peng Ma [YS: moveconfig.py -s -d] Reviewed-by: York Sun --- configs/ls1046ardb_qspi_defconfig | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/configs/ls1046ardb_qspi_defconfig b/configs/ls1046ardb_qspi_defconfig index e780acc..fa4a08f 100644 --- a/configs/ls1046ardb_qspi_defconfig +++ b/configs/ls1046ardb_qspi_defconfig @@ -3,6 +3,7 @@ CONFIG_TARGET_LS1046ARDB=y CONFIG_SYS_TEXT_BASE=0x40100000 CONFIG_FSL_LS_PPA=y CONFIG_QSPI_AHB_INIT=y +CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y CONFIG_NR_DRAM_BANKS=2 CONFIG_FIT_VERBOSE=y @@ -26,6 +27,7 @@ CONFIG_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_DM=y +CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y @@ -38,6 +40,7 @@ CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE=y +CONFIG_DM_SCSI=y CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y @@ -46,4 +49,3 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_STORAGE=y -- cgit v1.1 From 39105100120f489b2a414c93ed79033aa48d2734 Mon Sep 17 00:00:00 2001 From: Peng Ma Date: Thu, 11 Oct 2018 10:34:22 +0000 Subject: arm64: ls1046aqds: enable DM support for sata Enable related configs to support sata DM feature. Signed-off-by: Peng Ma [YS: moveconfig.py -s -d] Reviewed-by: York Sun --- configs/ls1046aqds_defconfig | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/configs/ls1046aqds_defconfig b/configs/ls1046aqds_defconfig index 47a8dcd..f7a35df 100644 --- a/configs/ls1046aqds_defconfig +++ b/configs/ls1046aqds_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_TARGET_LS1046AQDS=y CONFIG_SYS_TEXT_BASE=0x60100000 CONFIG_FSL_LS_PPA=y +CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y CONFIG_NR_DRAM_BANKS=2 CONFIG_FIT_VERBOSE=y @@ -30,6 +31,7 @@ CONFIG_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart" CONFIG_ENV_IS_IN_FLASH=y CONFIG_DM=y +CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y @@ -44,6 +46,7 @@ CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE=y +CONFIG_DM_SCSI=y CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y @@ -52,4 +55,3 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_STORAGE=y -- cgit v1.1 From aaaffe9050b34c2a70ac9031b7157bf2ef7c7007 Mon Sep 17 00:00:00 2001 From: Peng Ma Date: Mon, 22 Oct 2018 10:39:49 +0800 Subject: scsi: ceva: add ls1088a soc support Add ahci compatible support for ls1088a soc. Signed-off-by: Peng Ma Reviewed-by: Simon Glass Reviewed-by: York Sun --- drivers/ata/sata_ceva.c | 22 ++++++++++++++++++---- 1 file changed, 18 insertions(+), 4 deletions(-) diff --git a/drivers/ata/sata_ceva.c b/drivers/ata/sata_ceva.c index a2d21d9..fa86797 100644 --- a/drivers/ata/sata_ceva.c +++ b/drivers/ata/sata_ceva.c @@ -82,15 +82,19 @@ #define CEVA_AXICC_CFG 0x3fffffff /* for ls1021a */ -#define LS1021_AHCI_VEND_AXICC 0xC0 +#define LS1021_AHCI_VEND_AXICC 0xC0 #define LS1021_CEVA_PHY2_CFG 0x28183414 #define LS1021_CEVA_PHY3_CFG 0x0e080e06 #define LS1021_CEVA_PHY4_CFG 0x064a080b #define LS1021_CEVA_PHY5_CFG 0x2aa86470 +/* for ls1088a */ +#define LS1088_ECC_DIS_ADDR_CH2 0x100520 +#define LS1088_ECC_DIS_VAL_CH2 0x40000000 + /* ecc addr-val pair */ -#define ECC_DIS_ADDR_CH2 0x80000000 -#define ECC_DIS_VAL_CH2 0x20140520 +#define ECC_DIS_ADDR_CH2 0x20140520 +#define ECC_DIS_VAL_CH2 0x80000000 #define SATA_ECC_REG_ADDR 0x20220520 #define SATA_ECC_DISABLE 0x00020000 @@ -100,6 +104,7 @@ enum ceva_soc { CEVA_LS1021A, CEVA_LS1043A, CEVA_LS1046A, + CEVA_LS1088A, }; struct ceva_sata_priv { @@ -140,7 +145,15 @@ static int ceva_init_sata(struct ceva_sata_priv *priv) case CEVA_LS1012A: case CEVA_LS1043A: case CEVA_LS1046A: - writel(ECC_DIS_ADDR_CH2, ECC_DIS_VAL_CH2); + writel(ECC_DIS_VAL_CH2, ECC_DIS_ADDR_CH2); + writel(CEVA_PHY1_CFG, base + AHCI_VEND_PPCFG); + writel(CEVA_TRANS_CFG, base + AHCI_VEND_PTC); + if (priv->flag & FLAG_COHERENT) + writel(CEVA_AXICC_CFG, base + AHCI_VEND_AXICC); + break; + + case CEVA_LS1088A: + writel(LS1088_ECC_DIS_VAL_CH2, LS1088_ECC_DIS_ADDR_CH2); writel(CEVA_PHY1_CFG, base + AHCI_VEND_PPCFG); writel(CEVA_TRANS_CFG, base + AHCI_VEND_PTC); if (priv->flag & FLAG_COHERENT) @@ -173,6 +186,7 @@ static const struct udevice_id sata_ceva_ids[] = { { .compatible = "fsl,ls1021a-ahci", .data = CEVA_LS1021A }, { .compatible = "fsl,ls1043a-ahci", .data = CEVA_LS1043A }, { .compatible = "fsl,ls1046a-ahci", .data = CEVA_LS1046A }, + { .compatible = "fsl,ls1088a-ahci", .data = CEVA_LS1088A }, { } }; -- cgit v1.1 From 3e586ee30772cd4505b6cfa62bf1e6384d810b67 Mon Sep 17 00:00:00 2001 From: Peng Ma Date: Mon, 22 Oct 2018 10:39:50 +0800 Subject: armv8: dts: fsl-ls1088a: add sata node support One ls1088a, there is one SATA 3.0 advanced host controller interface which is a high-performance SATA solution that delivers comprehensive and fully-compliant generation 3 (1.5 Gb/s - 6.0 Gb/s) serial ATA capabilities, in accordance with the serial ATA revision 3.0 of Serial ATA International Organization. Add sata node to support this feature. Signed-off-by: Peng Ma Reviewed-by: Simon Glass Reviewed-by: York Sun --- arch/arm/dts/fsl-ls1088a-qds.dts | 4 ++++ arch/arm/dts/fsl-ls1088a-rdb.dts | 4 ++++ arch/arm/dts/fsl-ls1088a.dtsi | 8 ++++++++ 3 files changed, 16 insertions(+) diff --git a/arch/arm/dts/fsl-ls1088a-qds.dts b/arch/arm/dts/fsl-ls1088a-qds.dts index 36116f7..4ea451c 100644 --- a/arch/arm/dts/fsl-ls1088a-qds.dts +++ b/arch/arm/dts/fsl-ls1088a-qds.dts @@ -104,3 +104,7 @@ reg = <1>; }; }; + +&sata { + status = "okay"; +}; diff --git a/arch/arm/dts/fsl-ls1088a-rdb.dts b/arch/arm/dts/fsl-ls1088a-rdb.dts index 0be3f8d..f30bbb7 100644 --- a/arch/arm/dts/fsl-ls1088a-rdb.dts +++ b/arch/arm/dts/fsl-ls1088a-rdb.dts @@ -37,3 +37,7 @@ reg = <1>; }; }; + +&sata { + status = "okay"; +}; diff --git a/arch/arm/dts/fsl-ls1088a.dtsi b/arch/arm/dts/fsl-ls1088a.dtsi index 72d755a..9455e03 100644 --- a/arch/arm/dts/fsl-ls1088a.dtsi +++ b/arch/arm/dts/fsl-ls1088a.dtsi @@ -150,4 +150,12 @@ ranges = <0x81000000 0x0 0x00000000 0x30 0x00020000 0x0 0x00010000 /* downstream I/O */ 0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ }; + + sata: sata@3200000 { + compatible = "fsl,ls1088a-ahci"; + reg = <0x0 0x3200000 0x0 0x10000>; + interrupts = <0 133 4>; + status = "disabled"; + }; + }; -- cgit v1.1 From b9c716ea66ed5701fc1246d6edeb77ddab78a1da Mon Sep 17 00:00:00 2001 From: Peng Ma Date: Mon, 22 Oct 2018 10:39:51 +0800 Subject: arm64: ls1088a: enable DM support for sata Enable related configs to support sata DM feature. Signed-off-by: Peng Ma Reviewed-by: Simon Glass [YS: moveconfig.py -s -d] Reviewed-by: York Sun --- configs/ls1088aqds_defconfig | 3 +++ configs/ls1088ardb_qspi_defconfig | 4 +++- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/configs/ls1088aqds_defconfig b/configs/ls1088aqds_defconfig index 177c568..dbc0bdf 100644 --- a/configs/ls1088aqds_defconfig +++ b/configs/ls1088aqds_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_TARGET_LS1088AQDS=y CONFIG_SYS_TEXT_BASE=0x30100000 CONFIG_FSL_LS_PPA=y +CONFIG_AHCI=y CONFIG_NR_DRAM_BANKS=2 # CONFIG_SYS_MALLOC_F is not set CONFIG_FIT_VERBOSE=y @@ -28,6 +29,7 @@ CONFIG_ENV_IS_IN_FLASH=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SCSI_AHCI=y +CONFIG_SATA_CEVA=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_MTD_NOR_FLASH=y @@ -41,6 +43,7 @@ CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE=y +CONFIG_DM_SCSI=y CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/ls1088ardb_qspi_defconfig b/configs/ls1088ardb_qspi_defconfig index 089faa4..f13ae0a 100644 --- a/configs/ls1088ardb_qspi_defconfig +++ b/configs/ls1088ardb_qspi_defconfig @@ -3,6 +3,7 @@ CONFIG_TARGET_LS1088ARDB=y CONFIG_SYS_TEXT_BASE=0x20100000 CONFIG_FSL_LS_PPA=y CONFIG_QSPI_AHB_INIT=y +CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y CONFIG_NR_DRAM_BANKS=2 # CONFIG_SYS_MALLOC_F is not set @@ -30,6 +31,7 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SCSI_AHCI=y +CONFIG_SATA_CEVA=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_DM_SPI_FLASH=y @@ -42,6 +44,7 @@ CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE=y +CONFIG_DM_SCSI=y CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y @@ -51,6 +54,5 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y -CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y -- cgit v1.1 From 1039d1ac63d540398c5ebb681864dd6e04f86e7b Mon Sep 17 00:00:00 2001 From: Peng Ma Date: Mon, 22 Oct 2018 10:43:20 +0800 Subject: scsi: ceva: add ls2080a soc support Add ahci compatible support for ls2080a soc. Signed-off-by: Peng Ma Acked-by: Michal Simek [YS: add fallthrough comment] Reviewed-by: York Sun --- drivers/ata/sata_ceva.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/ata/sata_ceva.c b/drivers/ata/sata_ceva.c index fa86797..8887be9 100644 --- a/drivers/ata/sata_ceva.c +++ b/drivers/ata/sata_ceva.c @@ -105,6 +105,7 @@ enum ceva_soc { CEVA_LS1043A, CEVA_LS1046A, CEVA_LS1088A, + CEVA_LS2080A, }; struct ceva_sata_priv { @@ -146,6 +147,8 @@ static int ceva_init_sata(struct ceva_sata_priv *priv) case CEVA_LS1043A: case CEVA_LS1046A: writel(ECC_DIS_VAL_CH2, ECC_DIS_ADDR_CH2); + /* fallthrough */ + case CEVA_LS2080A: writel(CEVA_PHY1_CFG, base + AHCI_VEND_PPCFG); writel(CEVA_TRANS_CFG, base + AHCI_VEND_PTC); if (priv->flag & FLAG_COHERENT) @@ -187,6 +190,7 @@ static const struct udevice_id sata_ceva_ids[] = { { .compatible = "fsl,ls1043a-ahci", .data = CEVA_LS1043A }, { .compatible = "fsl,ls1046a-ahci", .data = CEVA_LS1046A }, { .compatible = "fsl,ls1088a-ahci", .data = CEVA_LS1088A }, + { .compatible = "fsl,ls2080a-ahci", .data = CEVA_LS2080A }, { } }; -- cgit v1.1 From 8ec42856f182726cf90867c43d0a1993928775bc Mon Sep 17 00:00:00 2001 From: Peng Ma Date: Mon, 22 Oct 2018 10:43:21 +0800 Subject: armv8: dts: fsl-ls2080a: add sata node support One ls2080a, there is one SATA 3.0 advanced host controller interface which is a high-performance SATA solution that delivers comprehensive and fully-compliant generation 3 (1.5 Gb/s - 6.0 Gb/s) serial ATA capabilities, in accordance with the serial ATA revision 3.0 of Serial ATA International Organization. Add sata node to support this feature. Signed-off-by: Peng Ma Reviewed-by: Simon Glass Reviewed-by: York Sun --- arch/arm/dts/fsl-ls2080a-qds.dts | 4 ++++ arch/arm/dts/fsl-ls2080a-rdb.dts | 4 ++++ arch/arm/dts/fsl-ls2080a.dtsi | 8 ++++++++ 3 files changed, 16 insertions(+) diff --git a/arch/arm/dts/fsl-ls2080a-qds.dts b/arch/arm/dts/fsl-ls2080a-qds.dts index fbd6c78..39fbc1b 100644 --- a/arch/arm/dts/fsl-ls2080a-qds.dts +++ b/arch/arm/dts/fsl-ls2080a-qds.dts @@ -64,3 +64,7 @@ reg = <0>; }; }; + +&sata { + status = "okay"; +}; diff --git a/arch/arm/dts/fsl-ls2080a-rdb.dts b/arch/arm/dts/fsl-ls2080a-rdb.dts index 541bcd3..e7567cf 100644 --- a/arch/arm/dts/fsl-ls2080a-rdb.dts +++ b/arch/arm/dts/fsl-ls2080a-rdb.dts @@ -32,3 +32,7 @@ reg = <0>; }; }; + +&sata { + status = "okay"; +}; diff --git a/arch/arm/dts/fsl-ls2080a.dtsi b/arch/arm/dts/fsl-ls2080a.dtsi index 2d537ae..5c0769b 100644 --- a/arch/arm/dts/fsl-ls2080a.dtsi +++ b/arch/arm/dts/fsl-ls2080a.dtsi @@ -156,4 +156,12 @@ ranges = <0x81000000 0x0 0x00000000 0x16 0x00020000 0x0 0x00010000 /* downstream I/O */ 0x82000000 0x0 0x40000000 0x16 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ }; + + sata: sata@3200000 { + compatible = "fsl,ls2080a-ahci"; + reg = <0x0 0x3200000 0x0 0x10000>; + interrupts = <0 133 0x4>; /* Level high type */ + status = "disabled"; + }; + }; -- cgit v1.1 From 71037f62ff3355e268627dc142594f8b974703f6 Mon Sep 17 00:00:00 2001 From: Peng Ma Date: Mon, 22 Oct 2018 10:43:22 +0800 Subject: arm64: ls2080a: enable DM support for sata Enable related configs to support sata DM feature. Signed-off-by: Peng Ma Reviewed-by: Simon Glass [YS: moveconfig -s -d] Reviewed-by: York Sun --- configs/ls2080aqds_defconfig | 4 +++- configs/ls2080ardb_defconfig | 4 +++- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/configs/ls2080aqds_defconfig b/configs/ls2080aqds_defconfig index f4a361a..51cf327 100644 --- a/configs/ls2080aqds_defconfig +++ b/configs/ls2080aqds_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_TARGET_LS2080AQDS=y CONFIG_SYS_TEXT_BASE=0x30100000 CONFIG_FSL_LS_PPA=y +CONFIG_AHCI=y CONFIG_NR_DRAM_BANKS=3 # CONFIG_SYS_MALLOC_F is not set CONFIG_FIT_VERBOSE=y @@ -31,6 +32,7 @@ CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds" CONFIG_ENV_IS_IN_FLASH=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y +CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y @@ -47,6 +49,7 @@ CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE=y +CONFIG_DM_SCSI=y CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y @@ -55,5 +58,4 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_STORAGE=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/ls2080ardb_defconfig b/configs/ls2080ardb_defconfig index 1c13bba..a1ddc1a 100644 --- a/configs/ls2080ardb_defconfig +++ b/configs/ls2080ardb_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_TARGET_LS2080ARDB=y CONFIG_SYS_TEXT_BASE=0x30100000 CONFIG_FSL_LS_PPA=y +CONFIG_AHCI=y CONFIG_NR_DRAM_BANKS=3 # CONFIG_SYS_MALLOC_F is not set CONFIG_FIT_VERBOSE=y @@ -31,6 +32,7 @@ CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-rdb" CONFIG_ENV_IS_IN_FLASH=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y +CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y @@ -47,6 +49,7 @@ CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE=y +CONFIG_DM_SCSI=y CONFIG_CONS_INDEX=2 CONFIG_SYS_NS16550=y CONFIG_SPI=y @@ -56,5 +59,4 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_STORAGE=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y -- cgit v1.1 From f668c52033548ad1d6430ebd29cdda713819415f Mon Sep 17 00:00:00 2001 From: Alison Wang Date: Tue, 16 Oct 2018 16:19:22 +0800 Subject: arm: ls1021a: Add timer_init() in board_init_f for SPL I2C is used to access DDR SPD in the DDR initialization for SPL. In i2c_write process, get_timer() will be called. In board_init_f for SPL, timer_init() is not called before. The system counter is not enabled and the counter frequency is not set to 12.5MHz in SPL. The parameters for do_div() are zero too. It could not be found until CONFIG_USE_PRIVATE_LIBGCC is enabled in default. When CONFIG_USE_PRIVATE_LIBGCC is enabled, U-Boot will use its own set of libgcc functions. As the parameters for do_div() are zero, __div0 will be called. Then the processor will stay in an endless loop after calling hang(). This patch will add timer_init() in board_init_f for SPL and fix a series of issues it caused. Signed-off-by: Alison Wang Reviewed-by: York Sun --- board/freescale/ls1021aqds/ls1021aqds.c | 1 + board/freescale/ls1021atwr/ls1021atwr.c | 1 + 2 files changed, 2 insertions(+) diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c index c828dac..c08be1e 100644 --- a/board/freescale/ls1021aqds/ls1021aqds.c +++ b/board/freescale/ls1021aqds/ls1021aqds.c @@ -244,6 +244,7 @@ void board_init_f(ulong dummy) if (major == SOC_MAJOR_VER_1_0) out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER); + timer_init(); dram_init(); /* Allow OCRAM access permission as R/W */ diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c index dcd6d93..beb82ce 100644 --- a/board/freescale/ls1021atwr/ls1021atwr.c +++ b/board/freescale/ls1021atwr/ls1021atwr.c @@ -467,6 +467,7 @@ void board_init_f(ulong dummy) preloader_console_init(); + timer_init(); dram_init(); /* Allow OCRAM access permission as R/W */ -- cgit v1.1 From 5b595df338ed1a8ef9ead46c811ba00b29f1185e Mon Sep 17 00:00:00 2001 From: Pramod Kumar Date: Fri, 12 Oct 2018 14:04:27 +0000 Subject: armv8: ls1088ardb_pb: Add support for board detection ls1088ardb-pb and ls1088ardb both boards are ls1088a based soc, board type detection is dynamic at boot time Signed-off-by: Pramod Kumar Reviewed-by: York Sun --- board/freescale/ls1088a/ls1088a.c | 27 +++++++++++++++++++++++++-- include/configs/ls1088a_common.h | 3 ++- 2 files changed, 27 insertions(+), 3 deletions(-) diff --git a/board/freescale/ls1088a/ls1088a.c b/board/freescale/ls1088a/ls1088a.c index 517a8ce..1e2ad98 100644 --- a/board/freescale/ls1088a/ls1088a.c +++ b/board/freescale/ls1088a/ls1088a.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2017 NXP + * Copyright 2017-2018 NXP */ #include #include @@ -67,6 +67,24 @@ int init_func_vid(void) } #endif +int is_pb_board(void) +{ + u8 board_id; + + board_id = QIXIS_READ(id); + if (board_id == LS1088ARDB_PB_BOARD) + return 1; + else + return 0; +} + +int fixup_ls1088ardb_pb_banner(void *fdt) +{ + fdt_setprop_string(fdt, 0, "model", "LS1088ARDB-PB Board"); + + return 0; +} + #if !defined(CONFIG_SPL_BUILD) int checkboard(void) { @@ -79,7 +97,10 @@ int checkboard(void) #ifdef CONFIG_TARGET_LS1088AQDS printf("Board: LS1088A-QDS, "); #else - printf("Board: LS1088A-RDB, "); + if (is_pb_board()) + printf("Board: LS1088ARDB-PB, "); + else + printf("Board: LS1088A-RDB, "); #endif sw = QIXIS_READ(arch); @@ -585,6 +606,8 @@ int ft_board_setup(void *blob, bd_t *bd) if (err) return err; #endif + if (is_pb_board()) + fixup_ls1088ardb_pb_banner(blob); return 0; } diff --git a/include/configs/ls1088a_common.h b/include/configs/ls1088a_common.h index 822fd76..743d0cf 100644 --- a/include/configs/ls1088a_common.h +++ b/include/configs/ls1088a_common.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright 2017 NXP + * Copyright 2017-2018 NXP */ #ifndef __LS1088_COMMON_H @@ -27,6 +27,7 @@ #include #include +#define LS1088ARDB_PB_BOARD 0x4A /* Link Definitions */ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) -- cgit v1.1 From 4c9d4a75f12f9ae7a1164f62cee532ef7a48e5f5 Mon Sep 17 00:00:00 2001 From: Ashish Kumar Date: Fri, 12 Oct 2018 14:45:59 +0530 Subject: ls1088a: Move CONFIG_FSL_QSPI to defconfig Signed-off-by: Rajat Srivastava Signed-off-by: Ashish Kumar Reviewed-by: York Sun --- configs/ls1088aqds_qspi_SECURE_BOOT_defconfig | 1 + configs/ls1088aqds_qspi_defconfig | 1 + configs/ls1088aqds_sdcard_qspi_defconfig | 1 + configs/ls1088ardb_qspi_SECURE_BOOT_defconfig | 1 + configs/ls1088ardb_qspi_defconfig | 1 + configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig | 1 + configs/ls1088ardb_sdcard_qspi_defconfig | 1 + include/configs/ls1088aqds.h | 1 - include/configs/ls1088ardb.h | 1 - 9 files changed, 7 insertions(+), 2 deletions(-) diff --git a/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig b/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig index b184d23..28850db 100644 --- a/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig @@ -45,6 +45,7 @@ CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y +CONFIG_FSL_QSPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/ls1088aqds_qspi_defconfig b/configs/ls1088aqds_qspi_defconfig index c63426d..997bafd 100644 --- a/configs/ls1088aqds_qspi_defconfig +++ b/configs/ls1088aqds_qspi_defconfig @@ -45,6 +45,7 @@ CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y +CONFIG_FSL_QSPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/ls1088aqds_sdcard_qspi_defconfig b/configs/ls1088aqds_sdcard_qspi_defconfig index f83c17b..02f6613 100644 --- a/configs/ls1088aqds_sdcard_qspi_defconfig +++ b/configs/ls1088aqds_sdcard_qspi_defconfig @@ -55,6 +55,7 @@ CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y +CONFIG_FSL_QSPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig index ff72ec5..63ac174 100644 --- a/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig @@ -46,6 +46,7 @@ CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y +CONFIG_FSL_QSPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/ls1088ardb_qspi_defconfig b/configs/ls1088ardb_qspi_defconfig index f13ae0a..5503a71 100644 --- a/configs/ls1088ardb_qspi_defconfig +++ b/configs/ls1088ardb_qspi_defconfig @@ -49,6 +49,7 @@ CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y +CONFIG_FSL_QSPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig b/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig index f7ec11f..d839e43 100644 --- a/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig @@ -58,6 +58,7 @@ CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y +CONFIG_FSL_QSPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/ls1088ardb_sdcard_qspi_defconfig b/configs/ls1088ardb_sdcard_qspi_defconfig index b56e11e..53fa087 100644 --- a/configs/ls1088ardb_sdcard_qspi_defconfig +++ b/configs/ls1088ardb_sdcard_qspi_defconfig @@ -56,6 +56,7 @@ CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y +CONFIG_FSL_QSPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/include/configs/ls1088aqds.h b/include/configs/ls1088aqds.h index f4e350d..829c539 100644 --- a/include/configs/ls1088aqds.h +++ b/include/configs/ls1088aqds.h @@ -324,7 +324,6 @@ unsigned long get_board_ddr_clk(void); /* QSPI device */ #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) -#define CONFIG_FSL_QSPI #define FSL_QSPI_FLASH_SIZE (1 << 26) #define FSL_QSPI_FLASH_NUM 2 diff --git a/include/configs/ls1088ardb.h b/include/configs/ls1088ardb.h index 14731c5..5269bcd 100644 --- a/include/configs/ls1088ardb.h +++ b/include/configs/ls1088ardb.h @@ -275,7 +275,6 @@ #ifndef SPL_NO_QSPI /* QSPI device */ #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) -#define CONFIG_FSL_QSPI #define FSL_QSPI_FLASH_SIZE (1 << 26) #define FSL_QSPI_FLASH_NUM 2 #endif -- cgit v1.1 From df182a42a45a1db76a4e0a3346947e31f70dc26a Mon Sep 17 00:00:00 2001 From: Priyanka Jain Date: Thu, 11 Oct 2018 05:11:23 +0000 Subject: board/freescale/vid: Add correction for ltc3882 read error. Voltage regulator LTC3882 device has 0.5% voltage read error. So for NXP SoC devices this generally equates to 2mV Update set_voltage_to_LTC for below: 1.Add coorection of upto 2mV in voltage comparison to take care of voltage read error of voltage regulator 2.Add loop max count kept as 100 to avoid infinte loop. Signed-off-by: Priyanka Jain Reviewed-by: York Sun --- board/freescale/common/vid.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/board/freescale/common/vid.c b/board/freescale/common/vid.c index eb5cf88..db158cb 100644 --- a/board/freescale/common/vid.c +++ b/board/freescale/common/vid.c @@ -318,6 +318,7 @@ static int set_voltage_to_IR(int i2caddress, int vdd) static int set_voltage_to_LTC(int i2caddress, int vdd) { int ret, vdd_last, vdd_target = vdd; + int count = 100, temp = 0; /* Scale up to the LTC resolution is 1/4096V */ vdd = (vdd * 4096) / 1000; @@ -343,7 +344,9 @@ static int set_voltage_to_LTC(int i2caddress, int vdd) printf("VID: Couldn't read sensor abort VID adjust\n"); return -1; } - } while (vdd_last != vdd_target); + count--; + temp = vdd_last - vdd_target; + } while ((abs(temp) > 2) && (count > 0)); return vdd_last; } -- cgit v1.1 From 6252faa0da0954b548f05d23c65734cd8c905382 Mon Sep 17 00:00:00 2001 From: Priyanka Jain Date: Thu, 27 Sep 2018 10:32:05 +0530 Subject: armv8: lsch3: Add support of serdes3 module Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain Reviewed-by: York Sun --- arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 3 + .../cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c | 71 ++++++++++++++++++++++ .../include/asm/arch-fsl-layerscape/fsl_serdes.h | 2 + 3 files changed, 76 insertions(+) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 1872c66..2d1946c 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -348,6 +348,9 @@ config SYS_FSL_SRDS_1 config SYS_FSL_SRDS_2 bool +config SYS_NXP_SRDS_3 + bool + config SYS_HAS_SERDES bool diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c index 2bef841..bb50e3d 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* + * Copyright 2016-2018 NXP * Copyright 2014-2015 Freescale Semiconductor, Inc. */ @@ -16,6 +17,9 @@ static u8 serdes1_prtcl_map[SERDES_PRCTL_COUNT]; #ifdef CONFIG_SYS_FSL_SRDS_2 static u8 serdes2_prtcl_map[SERDES_PRCTL_COUNT]; #endif +#ifdef CONFIG_SYS_NXP_SRDS_3 +static u8 serdes3_prtcl_map[SERDES_PRCTL_COUNT]; +#endif #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) int xfi_dpmac[XFI8 + 1]; @@ -57,6 +61,12 @@ int is_serdes_configured(enum srds_prtcl device) ret |= serdes2_prtcl_map[device]; #endif +#ifdef CONFIG_SYS_NXP_SRDS_3 + if (!serdes3_prtcl_map[NONE]) + fsl_serdes_init(); + + ret |= serdes3_prtcl_map[device]; +#endif return !!ret; } @@ -82,6 +92,13 @@ int serdes_get_first_lane(u32 sd, enum srds_prtcl device) cfg >>= FSL_CHASSIS3_SRDS2_PRTCL_SHIFT; break; #endif +#ifdef CONFIG_SYS_NXP_SRDS_3 + case NXP_SRDS_3: + cfg = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS3_REGSR - 1]); + cfg &= FSL_CHASSIS3_SRDS3_PRTCL_MASK; + cfg >>= FSL_CHASSIS3_SRDS3_PRTCL_SHIFT; + break; +#endif default: printf("invalid SerDes%d\n", sd); break; @@ -201,6 +218,12 @@ struct serdes_prctl_info srds_prctl_info[] = { .shift = FSL_CHASSIS3_SRDS2_PRTCL_SHIFT }, #endif +#ifdef CONFIG_SYS_NXP_SRDS_3 + {.id = 3, + .mask = FSL_CHASSIS3_SRDS3_PRTCL_MASK, + .shift = FSL_CHASSIS3_SRDS3_PRTCL_SHIFT + }, +#endif {} /* NULL ENTRY */ }; @@ -341,6 +364,11 @@ int setup_serdes_volt(u32 svdd) (void *)(CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + 0x10000); u32 cfg_rcwsrds2 = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS2_REGSR - 1]); #endif +#ifdef CONFIG_SYS_NXP_SRDS_3 + struct ccsr_serdes __iomem *serdes3_base = + (void *)(CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + 0x20000); + u32 cfg_rcwsrds3 = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS3_REGSR - 1]); +#endif u32 cfg_tmp; int svdd_cur, svdd_tar; int ret = 1; @@ -370,6 +398,9 @@ int setup_serdes_volt(u32 svdd) #ifdef CONFIG_SYS_FSL_SRDS_2 do_enabled_lanes_reset(2, cfg_rcwsrds2, serdes2_base, false); #endif +#ifdef CONFIG_SYS_NXP_SRDS_3 + do_enabled_lanes_reset(3, cfg_rcwsrds3, serdes3_base, false); +#endif /* Put the all enabled PLL in reset */ #ifdef CONFIG_SYS_FSL_SRDS_1 @@ -383,6 +414,12 @@ int setup_serdes_volt(u32 svdd) do_pll_reset(cfg_tmp, serdes2_base); #endif +#ifdef CONFIG_SYS_NXP_SRDS_3 + cfg_tmp = cfg_rcwsrds3 & 0x30; + cfg_tmp >>= 4; + do_pll_reset(cfg_tmp, serdes3_base); +#endif + /* Put the Rx/Tx calibration into reset */ #ifdef CONFIG_SYS_FSL_SRDS_1 do_rx_tx_cal_reset(serdes1_base); @@ -392,6 +429,10 @@ int setup_serdes_volt(u32 svdd) do_rx_tx_cal_reset(serdes2_base); #endif +#ifdef CONFIG_SYS_NXP_SRDS_3 + do_rx_tx_cal_reset(serdes3_base); +#endif + ret = set_serdes_volt(svdd); if (ret < 0) { printf("could not change SVDD\n"); @@ -408,6 +449,11 @@ int setup_serdes_volt(u32 svdd) cfg_tmp >>= 2; do_serdes_enable(cfg_tmp, serdes2_base); #endif +#ifdef CONFIG_SYS_NXP_SRDS_3 + cfg_tmp = cfg_rcwsrds3 & 0x30; + cfg_tmp >>= 4; + do_serdes_enable(cfg_tmp, serdes3_base); +#endif /* Wait for at at least 625us, ensure the PLLs being reset are locked */ udelay(800); @@ -422,6 +468,13 @@ int setup_serdes_volt(u32 svdd) cfg_tmp >>= 2; do_pll_lock(cfg_tmp, serdes2_base); #endif + +#ifdef CONFIG_SYS_NXP_SRDS_3 + cfg_tmp = cfg_rcwsrds3 & 0x30; + cfg_tmp >>= 4; + do_pll_lock(cfg_tmp, serdes3_base); +#endif + /* Take the all enabled lanes out of reset */ #ifdef CONFIG_SYS_FSL_SRDS_1 do_enabled_lanes_reset(1, cfg_rcwsrds1, serdes1_base, true); @@ -430,6 +483,10 @@ int setup_serdes_volt(u32 svdd) do_enabled_lanes_reset(2, cfg_rcwsrds2, serdes2_base, true); #endif +#ifdef CONFIG_SYS_NXP_SRDS_3 + do_enabled_lanes_reset(3, cfg_rcwsrds3, serdes3_base, true); +#endif + /* For each PLL being reset, and achieved PLL lock set RST_DONE */ #ifdef CONFIG_SYS_FSL_SRDS_1 cfg_tmp = cfg_rcwsrds1 & 0x3; @@ -441,6 +498,12 @@ int setup_serdes_volt(u32 svdd) do_pll_reset_done(cfg_tmp, serdes2_base); #endif +#ifdef CONFIG_SYS_NXP_SRDS_3 + cfg_tmp = cfg_rcwsrds3 & 0x30; + cfg_tmp >>= 4; + do_pll_reset_done(cfg_tmp, serdes3_base); +#endif + return ret; } @@ -472,4 +535,12 @@ void fsl_serdes_init(void) FSL_CHASSIS3_SRDS2_PRTCL_SHIFT, serdes2_prtcl_map); #endif +#ifdef CONFIG_SYS_NXP_SRDS_3 + serdes_init(NXP_SRDS_3, + CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + NXP_SRDS_3 * 0x10000, + FSL_CHASSIS3_SRDS3_REGSR, + FSL_CHASSIS3_SRDS3_PRTCL_MASK, + FSL_CHASSIS3_SRDS3_PRTCL_SHIFT, + serdes3_prtcl_map); +#endif } diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h index 6981076..c041a31 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* + * Copyright 2018 NXP * Copyright 2015 Freescale Semiconductor, Inc. */ @@ -57,6 +58,7 @@ enum srds_prtcl { enum srds { FSL_SRDS_1 = 0, FSL_SRDS_2 = 1, + NXP_SRDS_3 = 2, }; #elif defined(CONFIG_FSL_LSCH2) enum srds_prtcl { -- cgit v1.1 From db1e3df7ce71369a6b48382550df661f41dd5826 Mon Sep 17 00:00:00 2001 From: Priyanka Jain Date: Thu, 11 Oct 2018 05:22:34 +0000 Subject: board/freescale/vid: Add vdd table for NXP LX2160A SoC Signed-off-by: Priyanka Jain Reviewed-by: York Sun --- board/freescale/common/vid.c | 37 +++++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/board/freescale/common/vid.c b/board/freescale/common/vid.c index db158cb..0ca389c 100644 --- a/board/freescale/common/vid.c +++ b/board/freescale/common/vid.c @@ -382,6 +382,42 @@ int adjust_vdd(ulong vdd_override) int ret, i2caddress; unsigned long vdd_string_override; char *vdd_string; +#ifdef CONFIG_ARCH_LX2160A + static const u16 vdd[32] = { + 8250, + 7875, + 7750, + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 8000, + 8125, + 8250, + 0, /* reserved */ + 8500, + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + }; +#else #ifdef CONFIG_ARCH_LS1088A static const uint16_t vdd[32] = { 10250, @@ -454,6 +490,7 @@ int adjust_vdd(ulong vdd_override) 0, /* reserved */ }; #endif +#endif struct vdd_drive { u8 vid; unsigned voltage; -- cgit v1.1 From d6fdec211f7913c97917ba262fa257fdcb6b000e Mon Sep 17 00:00:00 2001 From: Priyanka Jain Date: Mon, 29 Oct 2018 09:11:29 +0000 Subject: armv8:fsl-layerscape: Add support for Chassis 3.2 NXP layerscape architecture Chassis 3.2 builds upon chassis3 architecture with changes like DDR Memory map change, removal of IFC and support of upto 8 I2C controller. Patch add README.lsch3_2 and the above changes under macro CONFIG_NXP_LSCH3_2. Signed-off-by: Sriram Dash Signed-off-by: Priyanka Jain Reviewed-by: York Sun --- arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 3 +++ arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 18 +++++++++++++-- .../cpu/armv8/fsl-layerscape/doc/README.lsch3_2 | 27 ++++++++++++++++++++++ arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 13 ++++++++++- .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 12 ++++++++-- 5 files changed, 68 insertions(+), 5 deletions(-) create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3_2 diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 2d1946c..650ac94 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -180,6 +180,9 @@ config FSL_LSCH2 config FSL_LSCH3 bool +config NXP_LSCH3_2 + bool + config FSL_MC_ENET bool "Management Complex network" depends on ARCH_LS2080A || ARCH_LS1088A diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index 36189f7..5c62bcc 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -120,6 +120,13 @@ static struct mm_region early_map[] = { PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN | PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS }, +#ifdef CONFIG_SYS_FSL_DRAM_BASE3 + { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3, + CONFIG_SYS_FSL_DRAM_SIZE3, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN | + PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS + }, +#endif #elif defined(CONFIG_FSL_LSCH2) { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_SIZE, @@ -266,6 +273,13 @@ static struct mm_region final_map[] = { PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS }, +#ifdef CONFIG_SYS_FSL_DRAM_BASE3 + { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3, + CONFIG_SYS_FSL_DRAM_SIZE3, + PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS + }, +#endif #elif defined(CONFIG_FSL_LSCH2) { CONFIG_SYS_FSL_BOOTROM_BASE, CONFIG_SYS_FSL_BOOTROM_BASE, CONFIG_SYS_FSL_BOOTROM_SIZE, @@ -595,13 +609,13 @@ enum boot_src __get_boot_src(u32 porsr1) { enum boot_src src = BOOT_SOURCE_RESERVED; u32 rcw_src = (porsr1 & RCW_SRC_MASK) >> RCW_SRC_BIT; -#if !defined(CONFIG_FSL_LSCH3_2) +#if !defined(CONFIG_NXP_LSCH3_2) u32 val; #endif debug("%s: rcw_src 0x%x\n", __func__, rcw_src); #if defined(CONFIG_FSL_LSCH3) -#if defined(CONFIG_FSL_LSCH3_2) +#if defined(CONFIG_NXP_LSCH3_2) switch (rcw_src) { case RCW_SRC_SDHC1_VAL: src = BOOT_SOURCE_SD_MMC; diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3_2 b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3_2 new file mode 100644 index 0000000..6d4bd0b --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3_2 @@ -0,0 +1,27 @@ +# +# Copyright 2018 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +# + +NXP LayerScape with Chassis Generation 3.2 + +This architecture supports NXP ARMv8 SoCs with Chassis generation 3.2 +for example LX2160A. + +This architecture is enhancement over Chassis Generation 3 with +few differences mentioned below + +1)DDR Layout +============ +Entire DDR region splits into three regions. + - Region 1 is at address 0x8000_0000 to 0xffff_ffff. + - Region 2 is at address 0x20_8000_0000 to 0x3f_ffff_ffff, + - Region 3 is at address 0x60_0000_0000 to the top of memory, + for example 140GB, 0x63_7fff_ffff. + +All DDR memory is marked as cache-enabled. + +2)IFC is removed + +3)Number of I2C controllers increased to 8 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h index 3926aa3..eaa9ed2 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright 2017 NXP + * Copyright 2017-2018 NXP * Copyright 2014-2015, Freescale Semiconductor */ @@ -12,15 +12,19 @@ #define CONFIG_SYS_FSL_CCSR_SIZE 0x10000000 #define CONFIG_SYS_FSL_QSPI_BASE1 0x20000000 #define CONFIG_SYS_FSL_QSPI_SIZE1 0x10000000 +#ifndef CONFIG_NXP_LSCH3_2 #define CONFIG_SYS_FSL_IFC_BASE1 0x30000000 #define CONFIG_SYS_FSL_IFC_SIZE1 0x10000000 #define CONFIG_SYS_FSL_IFC_SIZE1_1 0x400000 +#endif #define CONFIG_SYS_FSL_DRAM_BASE1 0x80000000 #define CONFIG_SYS_FSL_DRAM_SIZE1 0x80000000 #define CONFIG_SYS_FSL_QSPI_BASE2 0x400000000 #define CONFIG_SYS_FSL_QSPI_SIZE2 0x100000000 +#ifndef CONFIG_NXP_LSCH3_2 #define CONFIG_SYS_FSL_IFC_BASE2 0x500000000 #define CONFIG_SYS_FSL_IFC_SIZE2 0x100000000 +#endif #define CONFIG_SYS_FSL_DCSR_BASE 0x700000000 #define CONFIG_SYS_FSL_DCSR_SIZE 0x40000000 #define CONFIG_SYS_FSL_MC_BASE 0x80c000000 @@ -40,8 +44,15 @@ #define CONFIG_SYS_FSL_AIOP1_SIZE 0x100000000 #define CONFIG_SYS_FSL_PEBUF_BASE 0x4c00000000 #define CONFIG_SYS_FSL_PEBUF_SIZE 0x400000000 +#ifdef CONFIG_NXP_LSCH3_2 +#define CONFIG_SYS_FSL_DRAM_BASE2 0x2080000000 +#define CONFIG_SYS_FSL_DRAM_SIZE2 0x1F80000000 +#define CONFIG_SYS_FSL_DRAM_BASE3 0x6000000000 +#define CONFIG_SYS_FSL_DRAM_SIZE3 0x2000000000 +#else #define CONFIG_SYS_FSL_DRAM_BASE2 0x8080000000 #define CONFIG_SYS_FSL_DRAM_SIZE2 0x7F80000000 +#endif #elif defined(CONFIG_FSL_LSCH2) #define CONFIG_SYS_FSL_BOOTROM_BASE 0x0 #define CONFIG_SYS_FSL_BOOTROM_SIZE 0x1000000 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index 8ddff55..ba37b89 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -2,7 +2,7 @@ /* * LayerScape Internal Memory Map * - * Copyright (C) 2017 NXP Semiconductors + * Copyright 2017-2018 NXP * Copyright 2014 Freescale Semiconductor, Inc. */ @@ -21,7 +21,9 @@ #define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR (CONFIG_SYS_IMMR + 0x00370000) #define SYS_FSL_QSPI_ADDR (CONFIG_SYS_IMMR + 0x010c0000) #define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x01140000) +#ifndef CONFIG_NXP_LSCH3_2 #define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x01240000) +#endif #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011C0500) #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011C0600) #define SYS_FSL_LS2080A_LS2085A_TIMER_ADDR 0x023d0000 @@ -45,6 +47,12 @@ #define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01010000) #define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x01020000) #define I2C4_BASE_ADDR (CONFIG_SYS_IMMR + 0x01030000) +#ifdef CONFIG_NXP_LSCH3_2 +#define I2C5_BASE_ADDR (CONFIG_SYS_IMMR + 0x01040000) +#define I2C6_BASE_ADDR (CONFIG_SYS_IMMR + 0x01050000) +#define I2C7_BASE_ADDR (CONFIG_SYS_IMMR + 0x01060000) +#define I2C8_BASE_ADDR (CONFIG_SYS_IMMR + 0x01070000) +#endif #define GPIO4_BASE_ADDR (CONFIG_SYS_IMMR + 0x01330000) #define GPIO4_GPDIR_ADDR (GPIO4_BASE_ADDR + 0x0) #define GPIO4_GPDAT_ADDR (GPIO4_BASE_ADDR + 0x8) @@ -83,7 +91,7 @@ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET) #ifdef CONFIG_TFABOOT -#ifdef CONFIG_FSL_LSCH3_2 +#ifdef CONFIG_NXP_LSCH3_2 /* RCW_SRC field in Power-On Reset Control Register 1 */ #define RCW_SRC_MASK 0x07800000 #define RCW_SRC_BIT 23 -- cgit v1.1 From 4909b89ec763f0c7030fa8474f9b6c5df866b01f Mon Sep 17 00:00:00 2001 From: Priyanka Jain Date: Mon, 29 Oct 2018 09:17:09 +0000 Subject: armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei Signed-off-by: Hou Zhiqiang Signed-off-by: Meenakshi Aggarwal Signed-off-by: Vabhav Sharma Signed-off-by: Sriram Dash Signed-off-by: Priyanka Jain Reviewed-by: York Sun --- arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 52 +++++++- arch/arm/cpu/armv8/fsl-layerscape/Makefile | 6 +- arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 15 ++- arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc | 57 +++++++++ .../cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c | 36 ++++++ arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 2 +- arch/arm/cpu/armv8/fsl-layerscape/lx2160a_serdes.c | 132 +++++++++++++++++++++ arch/arm/dts/fsl-lx2160a.dtsi | 118 ++++++++++++++++++ arch/arm/include/asm/arch-fsl-layerscape/config.h | 56 +++++++++ .../include/asm/arch-fsl-layerscape/fsl_serdes.h | 28 +++++ .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 26 ++++ arch/arm/include/asm/arch-fsl-layerscape/soc.h | 6 + .../asm/arch-fsl-layerscape/stream_id_lsch3.h | 9 +- drivers/ddr/fsl/Kconfig | 1 + drivers/net/ldpaa_eth/Makefile | 3 +- drivers/net/ldpaa_eth/lx2160a.c | 107 +++++++++++++++++ 16 files changed, 644 insertions(+), 10 deletions(-) create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/lx2160a_serdes.c create mode 100644 arch/arm/dts/fsl-lx2160a.dtsi create mode 100644 drivers/net/ldpaa_eth/lx2160a.c diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 650ac94..2b086da 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -170,6 +170,42 @@ config ARCH_LS2080A imply DISTRO_DEFAULTS imply PANIC_HANG +config ARCH_LX2160A + bool + select ARMV8_SET_SMPEN + select FSL_LSCH3 + select NXP_LSCH3_2 + select SYS_HAS_SERDES + select SYS_FSL_SRDS_1 + select SYS_FSL_SRDS_2 + select SYS_NXP_SRDS_3 + select SYS_FSL_DDR + select SYS_FSL_DDR_LE + select SYS_FSL_DDR_VER_50 + select SYS_FSL_EC1 + select SYS_FSL_EC2 + select SYS_FSL_HAS_RGMII + select SYS_FSL_HAS_SEC + select SYS_FSL_HAS_CCN508 + select SYS_FSL_HAS_DDR4 + select SYS_FSL_SEC_COMPAT_5 + select SYS_FSL_SEC_LE + select ARCH_EARLY_INIT_R + select BOARD_EARLY_INIT_F + select SYS_I2C_MXC + select SYS_I2C_MXC_I2C1 + select SYS_I2C_MXC_I2C2 + select SYS_I2C_MXC_I2C3 + select SYS_I2C_MXC_I2C4 + select SYS_I2C_MXC_I2C5 + select SYS_I2C_MXC_I2C6 + select SYS_I2C_MXC_I2C7 + select SYS_I2C_MXC_I2C8 + imply DISTRO_DEFAULTS + imply PANIC_HANG + imply SCSI + imply SCSI_AHCI + config FSL_LSCH2 bool select SYS_FSL_HAS_CCI400 @@ -185,7 +221,7 @@ config NXP_LSCH3_2 config FSL_MC_ENET bool "Management Complex network" - depends on ARCH_LS2080A || ARCH_LS1088A + depends on ARCH_LS2080A || ARCH_LS1088A || ARCH_LX2160A default y select RESV_RAM help @@ -202,6 +238,7 @@ config FSL_PCIE_COMPAT default "fsl,ls1046a-pcie" if ARCH_LS1046A default "fsl,ls2080a-pcie" if ARCH_LS2080A default "fsl,ls1088a-pcie" if ARCH_LS1088A + default "fsl,lx2160a-pcie" if ARCH_LX2160A help This compatible is used to find pci controller node in Kernel DT to complete fixup. @@ -300,6 +337,7 @@ config MAX_CPUS default 4 if ARCH_LS1046A default 16 if ARCH_LS2080A default 8 if ARCH_LS1088A + default 16 if ARCH_LX2160A default 1 help Set this number to the maximum number of possible CPUs in the SoC. @@ -342,6 +380,9 @@ config SYS_FSL_HAS_CCI400 config SYS_FSL_HAS_CCN504 bool +config SYS_FSL_HAS_CCN508 + bool + config SYS_FSL_HAS_DP_DDR bool @@ -404,6 +445,7 @@ config SYS_FSL_DSPI_CLK_DIV config SYS_FSL_DUART_CLK_DIV int "DUART clock divider" default 1 if ARCH_LS1043A + default 4 if ARCH_LX2160A default 2 help This is the divider that is used to derive DUART clock from Platform @@ -464,13 +506,15 @@ config RESV_RAM config SYS_FSL_EC1 bool help - Ethernet controller 1, this is connected to MAC3. + Ethernet controller 1, this is connected to + MAC17 for LX2160A or to MAC3 for other SoCs Provides DPAA2 capabilities config SYS_FSL_EC2 bool help - Ethernet controller 2, this is connected to MAC4. + Ethernet controller 2, this is connected to + MAC18 for LX2160A or to MAC4 for other SoCs Provides DPAA2 capabilities config SYS_FSL_ERRATUM_A008336 @@ -506,7 +550,7 @@ config SYS_FSL_HAS_RGMII config SYS_MC_RSV_MEM_ALIGN hex "Management Complex reserved memory alignment" depends on RESV_RAM - default 0x20000000 if ARCH_LS2080A || ARCH_LS1088A + default 0x20000000 if ARCH_LS2080A || ARCH_LS1088A || ARCH_LX2160A help Reserved memory needs to be aligned for MC to use. Default value is 512MB. diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile index 91fdbad..e9bc987 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile +++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile @@ -1,5 +1,5 @@ # SPDX-License-Identifier: GPL-2.0+ -# +# Copyright 2016-2018 NXP # Copyright 2014-2015, Freescale Semiconductor obj-y += cpu.o @@ -22,6 +22,10 @@ obj-$(CONFIG_SYS_HAS_SERDES) += fsl_lsch2_serdes.o endif endif +ifneq ($(CONFIG_ARCH_LX2160A),) +obj-$(CONFIG_SYS_HAS_SERDES) += lx2160a_serdes.o +endif + ifneq ($(CONFIG_ARCH_LS2080A),) obj-$(CONFIG_SYS_HAS_SERDES) += ls2080a_serdes.o endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index 5c62bcc..1fc025b 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -60,6 +60,9 @@ static struct cpu_type cpu_type_list[] = { CPU_TYPE_ENTRY(LS1084A, LS1084A, 8), CPU_TYPE_ENTRY(LS1048A, LS1048A, 4), CPU_TYPE_ENTRY(LS1044A, LS1044A, 4), + CPU_TYPE_ENTRY(LX2160A, LX2160A, 16), + CPU_TYPE_ENTRY(LX2120A, LX2120A, 12), + CPU_TYPE_ENTRY(LX2080A, LX2080A, 8), }; #define EARLY_PGTABLE_SIZE 0x5000 @@ -246,7 +249,7 @@ static struct mm_region final_map[] = { PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, -#ifdef CONFIG_ARCH_LS2080A +#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A) { CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_SIZE, PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | @@ -366,6 +369,10 @@ void cpu_name(char *name) for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++) if ((cpu_type_list[i].soc_ver & SVR_WO_E) == ver) { strcpy(name, cpu_type_list[i].name); +#ifdef CONFIG_ARCH_LX2160A + if (IS_C_PROCESSOR(svr)) + strcat(name, "C"); +#endif if (IS_E_PROCESSOR(svr)) strcat(name, "E"); @@ -1164,10 +1171,16 @@ void __efi_runtime reset_cpu(ulong addr) { u32 val; +#ifdef CONFIG_ARCH_LX2160A + val = in_le32(rstcr); + val |= 0x01; + out_le32(rstcr, val); +#else /* Raise RESET_REQ_B */ val = scfg_in32(rstcr); val |= 0x02; scfg_out32(rstcr, val); +#endif } #ifdef CONFIG_EFI_LOADER diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc index 276ab90..a0e2621 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc +++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc @@ -7,6 +7,7 @@ SoC overview 5. LS1046A 6. LS2088A 7. LS2081A + 8. LX2160A LS1043A --------- @@ -271,3 +272,59 @@ Refer to LS2084A(LS2088A) section above for details. It has one more similar SoC personality 1)LS2041A, few difference w.r.t. LS2081A: a) Four 64-bit ARM v8 Cortex-A72 CPUs + +LX2160A +-------- +The QorIQ LX2160A processor is built in the 16FFC process on +the Layerscape architecture combining sixteen ARM A72 processor +cores with advanced, high-performance datapath acceleration and +network, peripheral interfaces required for networking, wireless +infrastructure, storage, and general-purpose embedded applications. + +LX2160A is compliant with the Layerscape Chassis Generation 3.2. + +The LX2160A SoC includes the following function and features: + Sixteen 32-bit / 64-bit ARM v8 A72 CPUs + Cache Coherent Interconnect Fabric (CCN508 aka “Eliot”) + Two 64-bit 3.2GT/s DDR4 SDRAM memory controllers with ECC. + Data path acceleration architecture (DPAA2) + 24 Serdes lanes at up to 25 GHz + Ethernet interfaces + Single WRIOP tile supporting 130Gbps using 18 MACs + Support for 10G-SXGMII (aka USXGMII). + Support for SGMII (and 1000Base-KX) + Support for XFI (and 10GBase-KR) + Support for CAUI4 (100G); CAUI2 (50G) and 25G-AUI(25G). + Support for XLAUI (and 40GBase-KR4) for 40G. + Support for two RGMII parallel interfaces. + Energy efficient Ethernet support (802.3az) + IEEE 1588 support. + High-speed peripheral interfaces + Two PCIe Gen 4.0 8-lane controllers supporting SR-IOV, + Four PCIe Gen 4.0 4-lane controllers. + Four serial ATA (SATA 3.0) controllers. + Two USB 3.0 controllers with integrated PHY + Two Enhanced secure digital host controllers + Two Controller Area Network (CAN) modules + Flexible Serial peripheral interface (FlexSPI) controller. + Three Serial peripheral interface (SPI) controllers. + Eight I2C Controllers. + Four PL011 UARTs supporting two 4-pin UART ports or four 2-pin UART ports. + General Purpose IO (GPIO) + Support for hardware virtualization and partitioning (ARM MMU-500) + Support for GIC (ARM GIC-500) + QorIQ platform Trust Architecture 3.0 + One Secure WatchDog timer and one Non-Secure Watchdog timer. + ARM Generic Timer + Two Flextimers + Debug supporting run control, data acquisition, high-speed trace, + performance/event monitoring + Thermal Monitor Unit (TMU) with +/- 2C accuracy + Support for Voltage ID (VID) for yield improvement + +LX2160A SoC has 2 more similar SoC personalities +1)LX2120A, few difference w.r.t. LX2160A: + a) Twelve 64-bit ARM v8 Cortex-A72 CPUs + +2)LX2080A, few difference w.r.t. LX2160A: + a) Eight 64-bit ARM v8 Cortex-A72 CPUs diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c index bb50e3d..ab1be3f 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c @@ -22,9 +22,18 @@ static u8 serdes3_prtcl_map[SERDES_PRCTL_COUNT]; #endif #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) +#ifdef CONFIG_ARCH_LX2160A +int xfi_dpmac[XFI14 + 1]; +int sgmii_dpmac[SGMII18 + 1]; +int a25gaui_dpmac[_25GE10 + 1]; +int xlaui_dpmac[_40GE2 + 1]; +int caui2_dpmac[_50GE2 + 1]; +int caui4_dpmac[_100GE2 + 1]; +#else int xfi_dpmac[XFI8 + 1]; int sgmii_dpmac[SGMII16 + 1]; #endif +#endif __weak void wriop_init_dpmac_qsgmii(int sd, int lane_prtcl) { @@ -146,6 +155,32 @@ void serdes_init(u32 sd, u32 sd_addr, u32 rcwsr, u32 sd_prctl_mask, else { serdes_prtcl_map[lane_prtcl] = 1; #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) +#ifdef CONFIG_ARCH_LX2160A + if (lane_prtcl >= XFI1 && lane_prtcl <= XFI14) + wriop_init_dpmac(sd, xfi_dpmac[lane_prtcl], + (int)lane_prtcl); + + if (lane_prtcl >= SGMII1 && lane_prtcl <= SGMII18) + wriop_init_dpmac(sd, sgmii_dpmac[lane_prtcl], + (int)lane_prtcl); + + if (lane_prtcl >= _25GE1 && lane_prtcl <= _25GE10) + wriop_init_dpmac(sd, a25gaui_dpmac[lane_prtcl], + (int)lane_prtcl); + + if (lane_prtcl >= _40GE1 && lane_prtcl <= _40GE2) + wriop_init_dpmac(sd, xlaui_dpmac[lane_prtcl], + (int)lane_prtcl); + + if (lane_prtcl >= _50GE1 && lane_prtcl <= _50GE2) + wriop_init_dpmac(sd, caui2_dpmac[lane_prtcl], + (int)lane_prtcl); + + if (lane_prtcl >= _100GE1 && lane_prtcl <= _100GE2) + wriop_init_dpmac(sd, caui4_dpmac[lane_prtcl], + (int)lane_prtcl); + +#else switch (lane_prtcl) { case QSGMII_A: case QSGMII_B: @@ -167,6 +202,7 @@ void serdes_init(u32 sd, u32 sd_addr, u32 rcwsr, u32 sd_prctl_mask, break; } #endif +#endif } } diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S index cbc9112..6721a57 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S +++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S @@ -354,7 +354,7 @@ get_svr: ret #endif -#ifdef CONFIG_SYS_FSL_HAS_CCN504 +#if defined(CONFIG_SYS_FSL_HAS_CCN504) || defined(CONFIG_SYS_FSL_HAS_CCN508) hnf_pstate_poll: /* x0 has the desired status, return 0 for success, 1 for timeout * clobber x1, x2, x3, x4, x6, x7 diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lx2160a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/lx2160a_serdes.c new file mode 100644 index 0000000..a04a370 --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-layerscape/lx2160a_serdes.c @@ -0,0 +1,132 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ + +#include +#include + +struct serdes_config { + u8 protocol; + u8 lanes[SRDS_MAX_LANES]; +}; + +static struct serdes_config serdes1_cfg_tbl[] = { + /* SerDes 1 */ + {0x01, {PCIE2, PCIE2, PCIE2, PCIE2, PCIE1, PCIE1, PCIE1, PCIE1 } }, + {0x02, {PCIE2, PCIE2, PCIE2, PCIE2, SGMII6, SGMII5, SGMII4, SGMII3 } }, + {0x03, {PCIE2, PCIE2, PCIE2, PCIE2, XFI6, XFI5, XFI4, + XFI3 } }, + {0x04, {SGMII10, SGMII9, SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, + SGMII3 } }, + {0x05, {XFI10, XFI9, XFI8, XFI7, PCIE1, PCIE1, PCIE1, + PCIE1 } }, + {0x06, {SGMII10, SGMII9, SGMII8, SGMII7, SGMII6, SGMII5, XFI4, + XFI3 } }, + {0x07, {SGMII10, SGMII9, SGMII8, SGMII7, XFI6, XFI5, XFI4, + XFI3 } }, + {0x08, {XFI10, XFI9, XFI8, XFI7, XFI6, XFI5, XFI4, XFI3 } }, + {0x09, {SGMII10, SGMII9, SGMII8, PCIE2, SGMII6, SGMII5, SGMII4, + PCIE1 } }, + {0x0A, {XFI10, XFI9, XFI8, PCIE2, XFI6, XFI5, XFI4, PCIE1 } }, + {0x0B, {SGMII10, SGMII9, PCIE2, PCIE2, SGMII6, SGMII5, PCIE1, PCIE1 } }, + {0x0C, {SGMII10, SGMII9, PCIE2, PCIE2, PCIE1, PCIE1, PCIE1, PCIE1 } }, + {0x0D, {_100GE2, _100GE2, _100GE2, _100GE2, _100GE1, _100GE1, _100GE1, + _100GE1 } }, + {0x0E, {PCIE2, PCIE2, PCIE2, PCIE2, _100GE1, _100GE1, _100GE1, + _100GE1 } }, + {0x0F, {PCIE2, PCIE2, PCIE2, PCIE2, _50GE2, _50GE2, _50GE1, _50GE1 } }, + {0x10, {PCIE2, PCIE2, PCIE2, PCIE2, _25GE6, _25GE5, _50GE1, _50GE1 } }, + {0x11, {PCIE2, PCIE2, PCIE2, PCIE2, _25GE6, _25GE5, _25GE4, _25GE3 } }, + {0x12, {XFI10, XFI9, XFI8, XFI7, _25GE6, _25GE5, XFI4, + XFI3 } }, + {0x13, {_40GE2, _40GE2, _40GE2, _40GE2, _25GE6, _25GE5, XFI4, XFI3 } }, + {0x14, {_40GE2, _40GE2, _40GE2, _40GE2, _40GE1, _40GE1, _40GE1, + _40GE1 } }, + {0x15, {_25GE10, _25GE9, PCIE2, PCIE2, _25GE6, _25GE5, _25GE4, + _25GE3 } }, + {0x16, {XFI10, XFI9, PCIE2, PCIE2, XFI6, XFI5, XFI4, XFI3 } }, + {} +}; + +static struct serdes_config serdes2_cfg_tbl[] = { + /* SerDes 2 */ + {0x01, {PCIE3, PCIE3, SATA1, SATA2, PCIE4, PCIE4, PCIE4, PCIE4 } }, + {0x02, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3 } }, + {0x03, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4 } }, + {0x04, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SATA1, SATA2 } }, + {0x05, {PCIE3, PCIE3, PCIE3, PCIE3, SATA3, SATA4, SATA1, SATA2 } }, + {0x06, {PCIE3, PCIE3, PCIE3, PCIE3, SGMII15, SGMII16, XFI13, + XFI14 } }, + {0x07, {PCIE3, SGMII12, SGMII17, SGMII18, PCIE4, SGMII16, XFI13, + XFI14 } }, + {0x08, {NONE, NONE, SATA1, SATA2, SATA3, SATA4, XFI13, XFI14 } }, + {0x09, {SGMII11, SGMII12, SGMII17, SGMII18, SGMII15, SGMII16, SGMII13, + SGMII14} }, + {0x0A, {SGMII11, SGMII12, SGMII17, SGMII18, PCIE4, PCIE4, PCIE4, + PCIE4 } }, + {0x0B, {PCIE3, SGMII12, SGMII17, SGMII18, PCIE4, SGMII16, SGMII13, + SGMII14 } }, + {0x0C, {SGMII11, SGMII12, SGMII17, SGMII18, PCIE4, PCIE4, SATA1, + SATA2 } }, + {0x0D, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SGMII13, SGMII14 } }, + {0x0E, {PCIE3, PCIE3, SGMII17, SGMII18, PCIE4, PCIE4, SGMII13, + SGMII14 } }, + {} +}; + +static struct serdes_config serdes3_cfg_tbl[] = { + /* SerDes 3 */ + {0x02, {PCIE5, PCIE5, PCIE5, PCIE5, PCIE5, PCIE5, PCIE5, PCIE5 } }, + {0x03, {PCIE5, PCIE5, PCIE5, PCIE5, PCIE6, PCIE6, PCIE6, PCIE6 } }, + {} +}; + +static struct serdes_config *serdes_cfg_tbl[] = { + serdes1_cfg_tbl, + serdes2_cfg_tbl, + serdes3_cfg_tbl, +}; + +enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane) +{ + struct serdes_config *ptr; + + if (serdes >= ARRAY_SIZE(serdes_cfg_tbl)) + return 0; + + ptr = serdes_cfg_tbl[serdes]; + while (ptr->protocol) { + if (ptr->protocol == cfg) + return ptr->lanes[lane]; + ptr++; + } + + return 0; +} + +int is_serdes_prtcl_valid(int serdes, u32 prtcl) +{ + int i; + struct serdes_config *ptr; + + if (serdes >= ARRAY_SIZE(serdes_cfg_tbl)) + return 0; + + ptr = serdes_cfg_tbl[serdes]; + while (ptr->protocol) { + if (ptr->protocol == prtcl) + break; + ptr++; + } + + if (!ptr->protocol) + return 0; + + for (i = 0; i < SRDS_MAX_LANES; i++) { + if (ptr->lanes[i] != NONE) + return 1; + } + + return 0; +} diff --git a/arch/arm/dts/fsl-lx2160a.dtsi b/arch/arm/dts/fsl-lx2160a.dtsi new file mode 100644 index 0000000..b407dc6 --- /dev/null +++ b/arch/arm/dts/fsl-lx2160a.dtsi @@ -0,0 +1,118 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP lx2160a SOC common device tree source + * + * Copyright 2018 NXP + * + */ + +/ { + compatible = "fsl,lx2160a"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + memory@80000000 { + device_type = "memory"; + reg = <0x00000000 0x80000000 0 0x80000000>; + /* DRAM space - 1, size : 2 GB DRAM */ + }; + + sysclk: sysclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "sysclk"; + }; + + clockgen: clocking@1300000 { + compatible = "fsl,ls2080a-clockgen"; + reg = <0 0x1300000 0 0xa0000>; + #clock-cells = <2>; + clocks = <&sysclk>; + }; + + gic: interrupt-controller@6000000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */ + <0x0 0x06200000 0 0x100000>; /* GICR */ + #interrupt-cells = <3>; + interrupt-controller; + interrupts = <1 9 0x4>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */ + <1 14 0x8>, /* Physical NS PPI, active-low */ + <1 11 0x8>, /* Virtual PPI, active-low */ + <1 10 0x8>; /* Hypervisor PPI, active-low */ + }; + + uart0: serial@21c0000 { + compatible = "arm,pl011"; + reg = <0x0 0x21c0000 0x0 0x1000>; + clocks = <&clockgen 4 0>; + }; + + uart1: serial@21d0000 { + compatible = "arm,pl011"; + reg = <0x0 0x21d0000 0x0 0x1000>; + clocks = <&clockgen 4 0>; + }; + + uart2: serial@21e0000 { + compatible = "arm,pl011"; + reg = <0x0 0x21e0000 0x0 0x1000>; + clocks = <&clockgen 4 0>; + status = "disabled"; + }; + + uart3: serial@21f0000 { + compatible = "arm,pl011"; + reg = <0x0 0x21f0000 0x0 0x1000>; + clocks = <&clockgen 4 0>; + status = "disabled"; + }; + + dspi0: dspi@2100000 { + compatible = "fsl,vf610-dspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2100000 0x0 0x10000>; + interrupts = <0 26 0x4>; /* Level high type */ + num-cs = <6>; + }; + + dspi1: dspi@2110000 { + compatible = "fsl,vf610-dspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2110000 0x0 0x10000>; + interrupts = <0 240 0x4>; /* Level high type */ + num-cs = <6>; + }; + + dspi2: dspi@2120000 { + compatible = "fsl,vf610-dspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2120000 0x0 0x10000>; + interrupts = <0 241 0x4>; /* Level high type */ + num-cs = <6>; + }; + + usb0: usb3@3100000 { + compatible = "fsl,layerscape-dwc3"; + reg = <0x0 0x3100000 0x0 0x10000>; + interrupts = <0 80 0x4>; /* Level high type */ + dr_mode = "host"; + }; + + usb1: usb3@3110000 { + compatible = "fsl,layerscape-dwc3"; + reg = <0x0 0x3110000 0x0 0x10000>; + interrupts = <0 81 0x4>; /* Level high type */ + dr_mode = "host"; + }; +}; diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index bd4ca88..d4f80a2 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* + * Copyright 2016-2018 NXP * Copyright 2015, Freescale Semiconductor */ @@ -176,6 +177,61 @@ #define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */ #define CONFIG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */ +/* LX2160A Soc Support */ +#elif defined(CONFIG_ARCH_LX2160A) +#define TZPC_BASE 0x02200000 +#define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804) +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_EARLY_INIT +#define SRDS_MAX_LANES 8 +#ifndef L1_CACHE_BYTES +#define L1_CACHE_SHIFT 6 +#define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT) +#endif +#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2 +#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1, 4, 4, 4, 4 } +#define CONFIG_SYS_FSL_NUM_CC_PLLS 4 + +#define CONFIG_SYS_PAGE_SIZE 0x10000 + +#define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */ +#define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */ +#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00040000 /* Real size 256K */ + +/* DDR */ +#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) +#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE + +#define CONFIG_SYS_FSL_CCSR_GUR_LE +#define CONFIG_SYS_FSL_CCSR_SCFG_LE +#define CONFIG_SYS_FSL_ESDHC_LE +#define CONFIG_SYS_FSL_PEX_LUT_LE + +#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN + +/* Generic Interrupt Controller Definitions */ +#define GICD_BASE 0x06000000 +#define GICR_BASE 0x06200000 + +/* SMMU Definitions */ +#define SMMU_BASE 0x05000000 /* GR0 Base */ + +/* SFP */ +#define CONFIG_SYS_FSL_SFP_VER_3_4 +#define CONFIG_SYS_FSL_SFP_LE +#define CONFIG_SYS_FSL_SRK_LE + +/* Security Monitor */ +#define CONFIG_SYS_FSL_SEC_MON_LE + +/* Secure Boot */ +#define CONFIG_ESBC_HDR_LS + +/* DCFG - GUR */ +#define CONFIG_SYS_FSL_CCSR_GUR_LE + +#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 + #elif defined(CONFIG_FSL_LSCH2) #define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */ #define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h index c041a31..68354ff 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h @@ -20,8 +20,12 @@ enum srds_prtcl { PCIE2, PCIE3, PCIE4, + PCIE5, + PCIE6, SATA1, SATA2, + SATA3, + SATA4, XAUI1, XAUI2, XFI1, @@ -32,6 +36,12 @@ enum srds_prtcl { XFI6, XFI7, XFI8, + XFI9, + XFI10, + XFI11, + XFI12, + XFI13, + XFI14, SGMII1, SGMII2, SGMII3, @@ -48,10 +58,28 @@ enum srds_prtcl { SGMII14, SGMII15, SGMII16, + SGMII17, + SGMII18, QSGMII_A, QSGMII_B, QSGMII_C, QSGMII_D, + _25GE1, + _25GE2, + _25GE3, + _25GE4, + _25GE5, + _25GE6, + _25GE7, + _25GE8, + _25GE9, + _25GE10, + _40GE1, + _40GE2, + _50GE1, + _50GE2, + _100GE1, + _100GE2, SERDES_PRCTL_COUNT }; diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index ba37b89..0535224 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -15,7 +15,11 @@ #define CONFIG_SYS_FSL_DDR3_ADDR 0x08210000 #define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00E00000) #define CONFIG_SYS_FSL_PMU_ADDR (CONFIG_SYS_IMMR + 0x00E30000) +#ifdef CONFIG_ARCH_LX2160A +#define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00e88180) +#else #define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00E60000) +#endif #define CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR (CONFIG_SYS_IMMR + 0x00300000) #define CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR (CONFIG_SYS_IMMR + 0x00310000) #define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR (CONFIG_SYS_IMMR + 0x00370000) @@ -324,6 +328,28 @@ struct ccsr_gur { #define FSL_CHASSIS3_SRDS2_PRTCL_SHIFT FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT #define FSL_CHASSIS3_SRDS1_REGSR 29 #define FSL_CHASSIS3_SRDS2_REGSR 29 +#elif defined(CONFIG_ARCH_LX2160A) +#define FSL_CHASSIS3_EC1_REGSR 27 +#define FSL_CHASSIS3_EC2_REGSR 27 +#define FSL_CHASSIS3_EC1_REGSR_PRTCL_MASK 0x00000003 +#define FSL_CHASSIS3_EC1_REGSR_PRTCL_SHIFT 0 +#define FSL_CHASSIS3_EC2_REGSR_PRTCL_MASK 0x00000007 +#define FSL_CHASSIS3_EC2_REGSR_PRTCL_SHIFT 2 +#define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK 0x001F0000 +#define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT 16 +#define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK 0x03E00000 +#define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT 21 +#define FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_MASK 0x7C000000 +#define FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_SHIFT 26 +#define FSL_CHASSIS3_SRDS1_PRTCL_MASK FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK +#define FSL_CHASSIS3_SRDS1_PRTCL_SHIFT FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT +#define FSL_CHASSIS3_SRDS2_PRTCL_MASK FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK +#define FSL_CHASSIS3_SRDS2_PRTCL_SHIFT FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT +#define FSL_CHASSIS3_SRDS3_PRTCL_MASK FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_MASK +#define FSL_CHASSIS3_SRDS3_PRTCL_SHIFT FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_SHIFT +#define FSL_CHASSIS3_SRDS1_REGSR 29 +#define FSL_CHASSIS3_SRDS2_REGSR 29 +#define FSL_CHASSIS3_SRDS3_REGSR 29 #elif defined(CONFIG_ARCH_LS1088A) #define FSL_CHASSIS3_EC1_REGSR 26 #define FSL_CHASSIS3_EC2_REGSR 26 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h index daa1c70..f5bef6d 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h @@ -96,12 +96,18 @@ enum boot_src get_boot_src(void); #define SVR_LS2044A 0x870930 #define SVR_LS2081A 0x870918 #define SVR_LS2041A 0x870914 +#define SVR_LX2160A 0x873601 +#define SVR_LX2120A 0x873621 +#define SVR_LX2080A 0x873603 #define SVR_MAJ(svr) (((svr) >> 4) & 0xf) #define SVR_MIN(svr) (((svr) >> 0) & 0xf) #define SVR_REV(svr) (((svr) >> 0) & 0xff) #define SVR_SOC_VER(svr) (((svr) >> 8) & SVR_WO_E) #define IS_E_PROCESSOR(svr) (!((svr >> 8) & 0x1)) +#ifdef CONFIG_ARCH_LX2160A +#define IS_C_PROCESSOR(svr) (!((svr >> 12) & 0x1)) +#endif #define IS_SVR_REV(svr, maj, min) \ ((SVR_MAJ(svr) == (maj)) && (SVR_MIN(svr) == (min))) #define SVR_DEV(svr) ((svr) >> 8) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h index 8d002da..e017d8b 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* + * Copyright 2015-2018 NXP * Copyright 2014 Freescale Semiconductor, Inc. * */ @@ -69,11 +70,11 @@ #define FSL_SDMMC_STREAM_ID 3 #define FSL_SATA1_STREAM_ID 4 -#if defined(CONFIG_ARCH_LS2080A) +#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A) #define FSL_SATA2_STREAM_ID 5 #endif -#if defined(CONFIG_ARCH_LS2080A) +#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A) #define FSL_DMA_STREAM_ID 6 #elif defined(CONFIG_ARCH_LS1088A) #define FSL_DMA_STREAM_ID 5 @@ -82,6 +83,10 @@ /* PCI - programmed in PEXn_LUT */ #define FSL_PEX_STREAM_ID_START 7 +#ifdef CONFIG_ARCH_LX2160A +#define FSL_PEX_STREAM_ID_NUM (0x100) +#endif + #if defined(CONFIG_ARCH_LS2080A) #define FSL_PEX_STREAM_ID_END 22 #elif defined(CONFIG_ARCH_LS1088A) diff --git a/drivers/ddr/fsl/Kconfig b/drivers/ddr/fsl/Kconfig index a3d2bd5..c5bd8a8 100644 --- a/drivers/ddr/fsl/Kconfig +++ b/drivers/ddr/fsl/Kconfig @@ -34,6 +34,7 @@ config SYS_NUM_DDR_CTLRS ARCH_P4080 || \ ARCH_P5020 || \ ARCH_P5040 || \ + ARCH_LX2160A || \ ARCH_T4160 default 1 diff --git a/drivers/net/ldpaa_eth/Makefile b/drivers/net/ldpaa_eth/Makefile index 477ee4f..1d85b2c 100644 --- a/drivers/net/ldpaa_eth/Makefile +++ b/drivers/net/ldpaa_eth/Makefile @@ -1,8 +1,9 @@ # SPDX-License-Identifier: GPL-2.0+ -# +# Copyright 2015-2018 NXP # Copyright 2014 Freescale Semiconductor, Inc. obj-y += ldpaa_wriop.o obj-y += ldpaa_eth.o obj-$(CONFIG_ARCH_LS2080A) += ls2080a.o obj-$(CONFIG_ARCH_LS1088A) += ls1088a.o +obj-$(CONFIG_ARCH_LX2160A) += lx2160a.o diff --git a/drivers/net/ldpaa_eth/lx2160a.c b/drivers/net/ldpaa_eth/lx2160a.c new file mode 100644 index 0000000..7dd46c0 --- /dev/null +++ b/drivers/net/ldpaa_eth/lx2160a.c @@ -0,0 +1,107 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ +#include +#include +#include +#include +#include +#include + +u32 dpmac_to_devdisr[] = { + [WRIOP1_DPMAC1] = FSL_CHASSIS3_DEVDISR2_DPMAC1, + [WRIOP1_DPMAC2] = FSL_CHASSIS3_DEVDISR2_DPMAC2, + [WRIOP1_DPMAC3] = FSL_CHASSIS3_DEVDISR2_DPMAC3, + [WRIOP1_DPMAC4] = FSL_CHASSIS3_DEVDISR2_DPMAC4, + [WRIOP1_DPMAC5] = FSL_CHASSIS3_DEVDISR2_DPMAC5, + [WRIOP1_DPMAC6] = FSL_CHASSIS3_DEVDISR2_DPMAC6, + [WRIOP1_DPMAC7] = FSL_CHASSIS3_DEVDISR2_DPMAC7, + [WRIOP1_DPMAC8] = FSL_CHASSIS3_DEVDISR2_DPMAC8, + [WRIOP1_DPMAC9] = FSL_CHASSIS3_DEVDISR2_DPMAC9, + [WRIOP1_DPMAC10] = FSL_CHASSIS3_DEVDISR2_DPMAC10, + [WRIOP1_DPMAC11] = FSL_CHASSIS3_DEVDISR2_DPMAC11, + [WRIOP1_DPMAC12] = FSL_CHASSIS3_DEVDISR2_DPMAC12, + [WRIOP1_DPMAC13] = FSL_CHASSIS3_DEVDISR2_DPMAC13, + [WRIOP1_DPMAC14] = FSL_CHASSIS3_DEVDISR2_DPMAC14, + [WRIOP1_DPMAC15] = FSL_CHASSIS3_DEVDISR2_DPMAC15, + [WRIOP1_DPMAC16] = FSL_CHASSIS3_DEVDISR2_DPMAC16, + [WRIOP1_DPMAC17] = FSL_CHASSIS3_DEVDISR2_DPMAC17, + [WRIOP1_DPMAC18] = FSL_CHASSIS3_DEVDISR2_DPMAC18, +}; + +static int is_device_disabled(int dpmac_id) +{ + struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; + u32 devdisr2 = in_le32(&gur->devdisr2); + + return dpmac_to_devdisr[dpmac_id] & devdisr2; +} + +void wriop_dpmac_disable(int dpmac_id) +{ + struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; + + setbits_le32(&gur->devdisr2, dpmac_to_devdisr[dpmac_id]); +} + +void wriop_dpmac_enable(int dpmac_id) +{ + struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; + + clrbits_le32(&gur->devdisr2, dpmac_to_devdisr[dpmac_id]); +} + +phy_interface_t wriop_dpmac_enet_if(int dpmac_id, int lane_prtcl) +{ + enum srds_prtcl; + + if (is_device_disabled(dpmac_id + 1)) + return PHY_INTERFACE_MODE_NONE; + + if (lane_prtcl >= SGMII1 && lane_prtcl <= SGMII18) + return PHY_INTERFACE_MODE_SGMII; + + if (lane_prtcl >= XFI1 && lane_prtcl <= XFI14) + return PHY_INTERFACE_MODE_XGMII; + + if (lane_prtcl >= _25GE1 && lane_prtcl <= _25GE10) + return PHY_INTERFACE_MODE_25G_AUI; + + if (lane_prtcl >= _40GE1 && lane_prtcl <= _40GE2) + return PHY_INTERFACE_MODE_XLAUI; + + if (lane_prtcl >= _50GE1 && lane_prtcl <= _50GE2) + return PHY_INTERFACE_MODE_CAUI2; + + if (lane_prtcl >= _100GE1 && lane_prtcl <= _100GE2) + return PHY_INTERFACE_MODE_CAUI4; + + return PHY_INTERFACE_MODE_NONE; +} + +#ifdef CONFIG_SYS_FSL_HAS_RGMII +void fsl_rgmii_init(void) +{ + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + u32 ec; + +#ifdef CONFIG_SYS_FSL_EC1 + ec = gur_in32(&gur->rcwsr[FSL_CHASSIS3_EC1_REGSR - 1]) + & FSL_CHASSIS3_EC1_REGSR_PRTCL_MASK; + ec >>= FSL_CHASSIS3_EC1_REGSR_PRTCL_SHIFT; + + if (!ec) + wriop_init_dpmac_enet_if(17, PHY_INTERFACE_MODE_RGMII_ID); +#endif + +#ifdef CONFIG_SYS_FSL_EC2 + ec = gur_in32(&gur->rcwsr[FSL_CHASSIS3_EC2_REGSR - 1]) + & FSL_CHASSIS3_EC2_REGSR_PRTCL_MASK; + ec >>= FSL_CHASSIS3_EC2_REGSR_PRTCL_SHIFT; + + if (!ec) + wriop_init_dpmac_enet_if(18, PHY_INTERFACE_MODE_RGMII_ID); +#endif +} +#endif -- cgit v1.1