From e984db0f9b2cf562cbf878d363e00203725c7bfe Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 14 Sep 2021 05:25:29 +0200 Subject: arm: socfpga: vining: Drop meaningless comment The comment is no longer meaningful due to DT conversion, drop it. Signed-off-by: Marek Vasut Cc: Siew Chin Lim Cc: Simon Goldschmidt Cc: Tien Fong Chee --- include/configs/socfpga_vining_fpga.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/include/configs/socfpga_vining_fpga.h b/include/configs/socfpga_vining_fpga.h index 06976d8..38a7753 100644 --- a/include/configs/socfpga_vining_fpga.h +++ b/include/configs/socfpga_vining_fpga.h @@ -17,8 +17,6 @@ #define CONFIG_LOADADDR 0x01000000 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -/* Ethernet on SoC (EMAC) */ - /* Extra Environment */ #define CONFIG_HOSTNAME "socfpga_vining_fpga" -- cgit v1.1 From 513f7d1c5d65a0be1d19b1898eeb4c8a24e05e4e Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 14 Sep 2021 05:25:30 +0200 Subject: arm: socfpga: vining: Increase environment size Increase the environment size from 4k to 16k to prevent environment from becoming full. Signed-off-by: Marek Vasut Cc: Siew Chin Lim Cc: Simon Goldschmidt Cc: Tien Fong Chee --- configs/socfpga_vining_fpga_defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configs/socfpga_vining_fpga_defconfig b/configs/socfpga_vining_fpga_defconfig index b418efb..452e5b4 100644 --- a/configs/socfpga_vining_fpga_defconfig +++ b/configs/socfpga_vining_fpga_defconfig @@ -1,6 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_SOCFPGA=y -CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_OFFSET=0x100000 CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_DM_GPIO=y -- cgit v1.1 From 3cb04b895df7b18b32ce9d91b82a9cb82047b795 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 14 Sep 2021 05:25:31 +0200 Subject: arm: socfpga: vining: Set USB gadget manufacturer to Softing with capital S This was configured in downstream, so it is likely that most of the custom software used around the device depends on it. Make upstream compatible. Signed-off-by: Marek Vasut Cc: Siew Chin Lim Cc: Simon Goldschmidt Cc: Tien Fong Chee --- configs/socfpga_vining_fpga_defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configs/socfpga_vining_fpga_defconfig b/configs/socfpga_vining_fpga_defconfig index 452e5b4..5d8970e5 100644 --- a/configs/socfpga_vining_fpga_defconfig +++ b/configs/socfpga_vining_fpga_defconfig @@ -91,7 +91,7 @@ CONFIG_DESIGNWARE_SPI=y CONFIG_USB=y CONFIG_USB_DWC2=y CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_MANUFACTURER="softing" +CONFIG_USB_GADGET_MANUFACTURER="Softing" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_USB_GADGET_DWC2_OTG=y -- cgit v1.1 From 4e106ef9efd7d309c5f830c5ee0e99e62a96a508 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 14 Sep 2021 05:25:32 +0200 Subject: arm: socfpga: vining: Set default SPI NOR mode and frequency The SPI NOR bus mode is 0 on this system, update it accordingly. Increase frequency to 40 MHz and enable SFDP parsing, since the flashes on this system support that and it is a huge performance improvement. Signed-off-by: Marek Vasut Cc: Siew Chin Lim Cc: Simon Goldschmidt Cc: Tien Fong Chee --- configs/socfpga_vining_fpga_defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/configs/socfpga_vining_fpga_defconfig b/configs/socfpga_vining_fpga_defconfig index 5d8970e5..4dcf4f7 100644 --- a/configs/socfpga_vining_fpga_defconfig +++ b/configs/socfpga_vining_fpga_defconfig @@ -74,6 +74,9 @@ CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=70 CONFIG_MMC_DW=y CONFIG_MTD=y +CONFIG_SF_DEFAULT_MODE=0x0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SPI_FLASH_SFDP_SUPPORT=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set -- cgit v1.1 From e21bbffa1d6d2634dabee393dd342764e2931441 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 14 Sep 2021 05:25:33 +0200 Subject: arm: socfpga: vining: Un-disable WDT in DT The WDT on this system should be enabled, make it so. Signed-off-by: Marek Vasut Cc: Siew Chin Lim Cc: Simon Goldschmidt Cc: Tien Fong Chee --- arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi b/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi index 2e4468e..9e8be28 100644 --- a/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi +++ b/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi @@ -15,10 +15,6 @@ }; }; -&watchdog0 { - status = "disabled"; -}; - &mmc { status = "disabled"; }; -- cgit v1.1 From c3880e65975bd40ba025b9fafa5732a98ea9e736 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 14 Sep 2021 05:25:34 +0200 Subject: arm: socfpga: vining: Fix UDC controller phandle in DT The USB peripheral controller is the DWC2 controller 1, not 0. Update the phandle to fix UDC support on this board. Signed-off-by: Marek Vasut Cc: Siew Chin Lim Cc: Simon Goldschmidt Cc: Tien Fong Chee --- arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi b/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi index 9e8be28..fb05c31 100644 --- a/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi +++ b/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi @@ -11,7 +11,7 @@ /{ aliases { spi0 = "/soc/spi@ff705000"; - udc0 = &usb0; + udc0 = &usb1; }; }; -- cgit v1.1 From cb3ed86cf1f4ba97250cf3649a2d43012dd661fd Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 14 Sep 2021 05:25:35 +0200 Subject: arm: socfpga: vining: Enable DW I2C driver The Designware I2C IP is used to communicate with I2C peripherals on SoCFPGA, and required to access I2C EEPROM on this board. Enable it. Signed-off-by: Marek Vasut Cc: Siew Chin Lim Cc: Simon Goldschmidt Cc: Tien Fong Chee --- configs/socfpga_vining_fpga_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/socfpga_vining_fpga_defconfig b/configs/socfpga_vining_fpga_defconfig index 4dcf4f7..cbdb897 100644 --- a/configs/socfpga_vining_fpga_defconfig +++ b/configs/socfpga_vining_fpga_defconfig @@ -56,6 +56,7 @@ CONFIG_DFU_SF=y CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1000000 CONFIG_DWAPB_GPIO=y CONFIG_DM_I2C=y +CONFIG_SYS_I2C_DW=y CONFIG_LED_STATUS=y CONFIG_LED_STATUS_GPIO=y CONFIG_LED_STATUS0=y -- cgit v1.1 From b207cc92a2e74774f05df2b281a7f530e76d1f61 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 14 Sep 2021 05:25:36 +0200 Subject: arm: socfpga: vining: Let DWMAC configure PHY reset GPIO The DM DWMAC driver is perfectly capable of configuring the ethernet PHY reset GPIO, let the driver do it instead of doing it in the board file. Signed-off-by: Marek Vasut Cc: Siew Chin Lim Cc: Simon Goldschmidt Cc: Tien Fong Chee --- board/softing/vining_fpga/socfpga.c | 7 ------- 1 file changed, 7 deletions(-) diff --git a/board/softing/vining_fpga/socfpga.c b/board/softing/vining_fpga/socfpga.c index aaedf03..2299227 100644 --- a/board/softing/vining_fpga/socfpga.c +++ b/board/softing/vining_fpga/socfpga.c @@ -23,7 +23,6 @@ DECLARE_GLOBAL_DATA_PTR; */ int board_late_init(void) { - const unsigned int phy_nrst_gpio = 0; const unsigned int usb_nrst_gpio = 35; int ret; @@ -33,12 +32,6 @@ int board_late_init(void) /* Address of boot parameters for ATAG (if ATAG is used) */ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - ret = gpio_request(phy_nrst_gpio, "phy_nrst_gpio"); - if (!ret) - gpio_direction_output(phy_nrst_gpio, 1); - else - printf("Cannot remove PHY from reset!\n"); - ret = gpio_request(usb_nrst_gpio, "usb_nrst_gpio"); if (!ret) gpio_direction_output(usb_nrst_gpio, 1); -- cgit v1.1 From 532010da67329a1c3dbe92a167486df6e61d4f4a Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 14 Sep 2021 05:20:19 +0200 Subject: ddr: altera: use KBUILD_BASENAME instead of __FILE__ The KBUILD_BASENAME contains just the name of the compiled module, in this case 'sequencer', rather than a full path to the compiled file. Use it to prevent pulling the full path into the U-Boot binary, which is useless and annoying. Signed-off-by: Marek Vasut Cc: Siew Chin Lim Cc: Simon Goldschmidt Cc: Tien Fong Chee --- drivers/ddr/altera/sequencer.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c index 6b9b2e9..8a016f0 100644 --- a/drivers/ddr/altera/sequencer.c +++ b/drivers/ddr/altera/sequencer.c @@ -3714,7 +3714,7 @@ static void debug_mem_calibrate(struct socfpga_sdrseq *seq, int pass) u32 debug_info; if (pass) { - debug("%s: CALIBRATION PASSED\n", __FILE__); + debug(KBUILD_BASENAME ": CALIBRATION PASSED\n"); seq->gbl.fom_in /= 2; seq->gbl.fom_out /= 2; @@ -3733,7 +3733,7 @@ static void debug_mem_calibrate(struct socfpga_sdrseq *seq, int pass) writel(debug_info, &phy_mgr_cfg->cal_debug_info); writel(PHY_MGR_CAL_SUCCESS, &phy_mgr_cfg->cal_status); } else { - debug("%s: CALIBRATION FAILED\n", __FILE__); + debug(KBUILD_BASENAME ": CALIBRATION FAILED\n"); debug_info = seq->gbl.error_stage; debug_info |= seq->gbl.error_substage << 8; @@ -3750,7 +3750,7 @@ static void debug_mem_calibrate(struct socfpga_sdrseq *seq, int pass) writel(debug_info, &sdr_reg_file->failing_stage); } - debug("%s: Calibration complete\n", __FILE__); + debug(KBUILD_BASENAME ": Calibration complete\n"); } /** @@ -3934,7 +3934,7 @@ int sdram_calibration_full(struct socfpga_sdr *sdr) initialize_tracking(&seq); - debug("%s: Preparing to start memory calibration\n", __FILE__); + debug(KBUILD_BASENAME ": Preparing to start memory calibration\n"); debug("%s:%d\n", __func__, __LINE__); debug_cond(DLEVEL >= 1, -- cgit v1.1