From cdf21a8696a4ce6cb3103b175665fdc458b04d57 Mon Sep 17 00:00:00 2001 From: Elaine Zhang Date: Wed, 11 Oct 2023 18:29:45 +0800 Subject: clk: rockchip: rk3588: support aclk_top_root set 750M aclk_top_root choose a parent clock that does not change. Signed-off-by: Elaine Zhang Reviewed-by: Kever Yang --- drivers/clk/rockchip/clk_rk3588.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/clk/rockchip/clk_rk3588.c b/drivers/clk/rockchip/clk_rk3588.c index c861762..7ba037a 100644 --- a/drivers/clk/rockchip/clk_rk3588.c +++ b/drivers/clk/rockchip/clk_rk3588.c @@ -306,12 +306,18 @@ static ulong rk3588_top_set_clk(struct rk3588_clk_priv *priv, switch (clk_id) { case ACLK_TOP_ROOT: - src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); + if (!(priv->cpll_hz % rate)) { + src_clk = ACLK_TOP_ROOT_SRC_SEL_CPLL; + src_clk_div = DIV_ROUND_UP(priv->cpll_hz, rate); + } else { + src_clk = ACLK_TOP_ROOT_SRC_SEL_GPLL; + src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); + } assert(src_clk_div - 1 <= 31); rk_clrsetreg(&cru->clksel_con[8], ACLK_TOP_ROOT_DIV_MASK | ACLK_TOP_ROOT_SRC_SEL_MASK, - (ACLK_TOP_ROOT_SRC_SEL_GPLL << + (src_clk << ACLK_TOP_ROOT_SRC_SEL_SHIFT) | (src_clk_div - 1) << ACLK_TOP_ROOT_DIV_SHIFT); break; -- cgit v1.1