From fb4e64ef9daefba6c98e6a9620e28ffee741c075 Mon Sep 17 00:00:00 2001 From: Manish Tomar Date: Tue, 13 Apr 2021 12:38:34 +0530 Subject: configs: ls1046afrwy: Add secure boot config Add required CONFIG_NXP_ESBC for ls1046afrwy to enable ESBC Chain of Trust. Signed-off-by: Manish Tomar Reviewed-by: Priyanka Jain --- configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig b/configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig index f953106..33308aa 100644 --- a/configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig @@ -60,3 +60,4 @@ CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_ASIX88179=y CONFIG_USB_ETHER_RTL8152=y CONFIG_RSA=y +CONFIG_NXP_ESBC=y -- cgit v1.1 From 2bf4658b8c5e5f4f43dc1888fe39ea61e6eeba64 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Tue, 13 Apr 2021 17:54:17 +0200 Subject: board: sl28: fix RGMII clock and voltage It was noticed that the clock isn't continuously enabled when there is no link. This is because the 125MHz clock is derived from the internal PLL which seems to go into some kind of power-down mode every once in a while. The LS1028A expects a contiuous clock. Thus enable the PLL all the time. Also, the RGMII pad voltage is wrong, it was configured to 2.5V (that is the VDDH regulator). The correct voltage is 1.8V, i.e. the VDDIO regulator. Signed-off-by: Michael Walle Reviewed-by: Priyanka Jain --- arch/arm/dts/fsl-ls1028a-kontron-sl28-var1.dts | 3 ++- arch/arm/dts/fsl-ls1028a-kontron-sl28-var4.dts | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var1.dts b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var1.dts index fe708bd..33d85ed 100644 --- a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var1.dts +++ b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var1.dts @@ -41,8 +41,9 @@ qca,clk-out-frequency = <125000000>; qca,clk-out-strength = ; + qca,keep-pll-enabled; - vddio-supply = <&vddh>; + vddio-supply = <&vddio>; vddio: vddio-regulator { regulator-name = "VDDIO"; diff --git a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var4.dts b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var4.dts index 33b1630..b95e082 100644 --- a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var4.dts +++ b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var4.dts @@ -32,8 +32,9 @@ qca,clk-out-frequency = <125000000>; qca,clk-out-strength = ; + qca,keep-pll-enabled; - vddio-supply = <&vddh>; + vddio-supply = <&vddio>; vddio: vddio-regulator { regulator-name = "VDDIO"; -- cgit v1.1 From 864c3dbc0affea081264ff31c229232fbd45945a Mon Sep 17 00:00:00 2001 From: Mian Yousaf Kaukab Date: Wed, 14 Apr 2021 12:33:58 +0200 Subject: ls1012a: net: pfe: remove pfe stop from bootcmd When using bootefi to boot a EFI binary, u-boot is supposed to provide networking service for EFI application. Currently, 'pfe stop' command is called from bootcmd before running bootefi. As a result network stops working for EFI applications and console is flooded with "Rx pkt not on expected port" messages. Implement board_quiesce_devices() for ls1012a boards and call pfe_command_stop() from it instead of calling 'pfe stop' from *_bootcmd and bootcmd. Tested-by: Anji Jagarlmudi Signed-off-by: Mian Yousaf Kaukab Reviewed-by: Ramon Fried [Fixed checkpatch space error] Signed-off-by: Priyanka Jain --- board/freescale/ls1012afrdm/ls1012afrdm.c | 8 ++++++++ board/freescale/ls1012aqds/ls1012aqds.c | 8 ++++++++ board/freescale/ls1012ardb/ls1012ardb.c | 8 ++++++++ drivers/net/pfe_eth/pfe_cmd.c | 2 +- include/configs/ls1012a2g5rdb.h | 6 +++--- include/configs/ls1012a_common.h | 4 ++-- include/configs/ls1012afrdm.h | 6 +++--- include/configs/ls1012afrwy.h | 6 +++--- include/configs/ls1012aqds.h | 6 +++--- include/configs/ls1012ardb.h | 6 +++--- include/net/pfe_eth/pfe/pfe_hw.h | 6 ++++++ 11 files changed, 48 insertions(+), 18 deletions(-) diff --git a/board/freescale/ls1012afrdm/ls1012afrdm.c b/board/freescale/ls1012afrdm/ls1012afrdm.c index 2cd651b..6473ee0 100644 --- a/board/freescale/ls1012afrdm/ls1012afrdm.c +++ b/board/freescale/ls1012afrdm/ls1012afrdm.c @@ -23,6 +23,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -185,6 +186,13 @@ int board_init(void) return 0; } +#ifdef CONFIG_FSL_PFE +void board_quiesce_devices(void) +{ + pfe_command_stop(0, NULL); +} +#endif + int ft_board_setup(void *blob, struct bd_info *bd) { arch_fixup_fdt(blob); diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c index cfe3f33..33a0910 100644 --- a/board/freescale/ls1012aqds/ls1012aqds.c +++ b/board/freescale/ls1012aqds/ls1012aqds.c @@ -32,6 +32,7 @@ #include "../common/qixis.h" #include "ls1012aqds_qixis.h" #include "ls1012aqds_pfe.h" +#include DECLARE_GLOBAL_DATA_PTR; @@ -163,6 +164,13 @@ int board_init(void) return 0; } +#ifdef CONFIG_FSL_PFE +void board_quiesce_devices(void) +{ + pfe_command_stop(0, NULL); +} +#endif + int esdhc_status_fixup(void *blob, const char *compat) { char esdhc0_path[] = "/soc/esdhc@1560000"; diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c index 41bcf6f..62e8af4 100644 --- a/board/freescale/ls1012ardb/ls1012ardb.c +++ b/board/freescale/ls1012ardb/ls1012ardb.c @@ -28,6 +28,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -186,6 +187,13 @@ int board_init(void) return 0; } +#ifdef CONFIG_FSL_PFE +void board_quiesce_devices(void) +{ + pfe_command_stop(0, NULL); +} +#endif + #ifdef CONFIG_TARGET_LS1012ARDB int esdhc_status_fixup(void *blob, const char *compat) { diff --git a/drivers/net/pfe_eth/pfe_cmd.c b/drivers/net/pfe_eth/pfe_cmd.c index 1e69525..364750f 100644 --- a/drivers/net/pfe_eth/pfe_cmd.c +++ b/drivers/net/pfe_eth/pfe_cmd.c @@ -418,7 +418,7 @@ static void send_dummy_pkt_to_hif(void) writel(buf, TMU_PHY_INQ_PKTINFO); } -static void pfe_command_stop(int argc, char *const argv[]) +void pfe_command_stop(int argc, char *const argv[]) { int pfe_pe_id, hif_stop_loop = 10; u32 rx_status; diff --git a/include/configs/ls1012a2g5rdb.h b/include/configs/ls1012a2g5rdb.h index 9962b98..9fbeecf 100644 --- a/include/configs/ls1012a2g5rdb.h +++ b/include/configs/ls1012a2g5rdb.h @@ -72,7 +72,7 @@ "installer=load mmc 0:2 $load_addr " \ "/flex_installer_arm64.itb; " \ "bootm $load_addr#$board\0" \ - "qspi_bootcmd=pfe stop; echo Trying load from qspi..;" \ + "qspi_bootcmd=echo Trying load from qspi..;" \ "sf probe && sf read $load_addr " \ "$kernel_addr $kernel_size; env exists secureboot " \ "&& sf read $kernelheader_addr_r $kernelheader_addr " \ @@ -82,11 +82,11 @@ #undef CONFIG_BOOTCOMMAND #ifdef CONFIG_TFABOOT #undef QSPI_NOR_BOOTCOMMAND -#define QSPI_NOR_BOOTCOMMAND "pfe stop;run distro_bootcmd; run qspi_bootcmd; " \ +#define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \ "env exists secureboot && esbc_halt;" #else #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) -#define CONFIG_BOOTCOMMAND "pfe stop;run distro_bootcmd; run qspi_bootcmd; " \ +#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \ "env exists secureboot && esbc_halt;" #endif #endif diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h index a908b0a..6f55acc 100644 --- a/include/configs/ls1012a_common.h +++ b/include/configs/ls1012a_common.h @@ -102,11 +102,11 @@ #undef CONFIG_BOOTCOMMAND #ifdef CONFIG_TFABOOT -#define QSPI_NOR_BOOTCOMMAND "pfe stop; sf probe 0:0; sf read $kernel_load "\ +#define QSPI_NOR_BOOTCOMMAND "sf probe 0:0; sf read $kernel_load "\ "$kernel_start $kernel_size && "\ "bootm $kernel_load" #else -#define CONFIG_BOOTCOMMAND "pfe stop; sf probe 0:0; sf read $kernel_load "\ +#define CONFIG_BOOTCOMMAND "sf probe 0:0; sf read $kernel_load "\ "$kernel_start $kernel_size && "\ "bootm $kernel_load" #endif diff --git a/include/configs/ls1012afrdm.h b/include/configs/ls1012afrdm.h index 02dd598..2711f65 100644 --- a/include/configs/ls1012afrdm.h +++ b/include/configs/ls1012afrdm.h @@ -50,16 +50,16 @@ "installer=load usb 0:2 $load_addr " \ "/flex_installer_arm64.itb; " \ "bootm $load_addr#$board\0" \ - "qspi_bootcmd=pfe stop; echo Trying load from qspi..;" \ + "qspi_bootcmd=echo Trying load from qspi..;" \ "sf probe && sf read $load_addr " \ "$kernel_addr $kernel_size && bootm $load_addr#$board\0" #undef CONFIG_BOOTCOMMAND #ifdef CONFIG_TFABOOT #undef QSPI_NOR_BOOTCOMMAND -#define QSPI_NOR_BOOTCOMMAND "pfe stop;run distro_bootcmd;run qspi_bootcmd" +#define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd;run qspi_bootcmd" #else -#define CONFIG_BOOTCOMMAND "pfe stop;run distro_bootcmd;run qspi_bootcmd" +#define CONFIG_BOOTCOMMAND "run distro_bootcmd;run qspi_bootcmd" #endif #endif /* __LS1012ARDB_H__ */ diff --git a/include/configs/ls1012afrwy.h b/include/configs/ls1012afrwy.h index ba15283..beb7440 100644 --- a/include/configs/ls1012afrwy.h +++ b/include/configs/ls1012afrwy.h @@ -89,7 +89,7 @@ "env exists secureboot " \ "&& esbc_validate ${scripthdraddr};" \ "source ${scriptaddr}\0" \ - "sd_bootcmd=pfe stop; echo Trying load from sd card..;" \ + "sd_bootcmd=echo Trying load from sd card..;" \ "mmcinfo; mmc read $load_addr " \ "$kernel_addr_sd $kernel_size_sd ;" \ "env exists secureboot && mmc read $kernelheader_addr_r "\ @@ -100,10 +100,10 @@ #undef CONFIG_BOOTCOMMAND #ifdef CONFIG_TFABOOT #undef QSPI_NOR_BOOTCOMMAND -#define QSPI_NOR_BOOTCOMMAND "pfe stop; run distro_bootcmd; run sd_bootcmd; "\ +#define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; "\ "env exists secureboot && esbc_halt;" #else -#define CONFIG_BOOTCOMMAND "pfe stop; run distro_bootcmd; run sd_bootcmd; "\ +#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; "\ "env exists secureboot && esbc_halt;" #endif diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h index 36be8f4..bdcb8d6 100644 --- a/include/configs/ls1012aqds.h +++ b/include/configs/ls1012aqds.h @@ -140,7 +140,7 @@ "env exists secureboot " \ "&& esbc_validate ${scripthdraddr};" \ "source ${scriptaddr}\0" \ - "qspi_bootcmd=pfe stop; echo Trying load from qspi..;" \ + "qspi_bootcmd=echo Trying load from qspi..;" \ "sf probe 0:0 && sf read $load_addr " \ "$kernel_addr $kernel_size; env exists secureboot " \ "&& sf read $kernelheader_addr_r $kernelheader_addr " \ @@ -150,10 +150,10 @@ #undef CONFIG_BOOTCOMMAND #ifdef CONFIG_TFABOOT #undef QSPI_NOR_BOOTCOMMAND -#define QSPI_NOR_BOOTCOMMAND "pfe stop; run distro_bootcmd; run qspi_bootcmd; "\ +#define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; "\ "env exists secureboot && esbc_halt;" #else -#define CONFIG_BOOTCOMMAND "pfe stop; run distro_bootcmd; run qspi_bootcmd; "\ +#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; "\ "env exists secureboot && esbc_halt;" #endif diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h index 582945b..efa0284 100644 --- a/include/configs/ls1012ardb.h +++ b/include/configs/ls1012ardb.h @@ -91,7 +91,7 @@ "installer=load mmc 0:2 $load_addr " \ "/flex_installer_arm64.itb; " \ "bootm $load_addr#$board\0" \ - "qspi_bootcmd=pfe stop; echo Trying load from qspi..;" \ + "qspi_bootcmd=echo Trying load from qspi..;" \ "sf probe && sf read $load_addr " \ "$kernel_addr $kernel_size; env exists secureboot " \ "&& sf read $kernelheader_addr_r $kernelheader_addr " \ @@ -101,10 +101,10 @@ #undef CONFIG_BOOTCOMMAND #ifdef CONFIG_TFABOOT #undef QSPI_NOR_BOOTCOMMAND -#define QSPI_NOR_BOOTCOMMAND "pfe stop; run distro_bootcmd; run qspi_bootcmd; "\ +#define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; "\ "env exists secureboot && esbc_halt;" #else -#define CONFIG_BOOTCOMMAND "pfe stop; run distro_bootcmd; run qspi_bootcmd; "\ +#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; "\ "env exists secureboot && esbc_halt;" #endif diff --git a/include/net/pfe_eth/pfe/pfe_hw.h b/include/net/pfe_eth/pfe/pfe_hw.h index c69fc69..71e4115 100644 --- a/include/net/pfe_eth/pfe/pfe_hw.h +++ b/include/net/pfe_eth/pfe/pfe_hw.h @@ -160,4 +160,10 @@ void hif_rx_enable(void); void hif_rx_disable(void); void hif_rx_desc_disable(void); +#ifdef PFE_RESET_WA +void pfe_command_stop(int argc, char *const argv[]); +#else +static void pfe_command_stop(int argc, char *const argv[]) {} +#endif + #endif /* _PFE_H_ */ -- cgit v1.1 From c0eeb730f8038565a168a73f74b3ed56d8eac16c Mon Sep 17 00:00:00 2001 From: Priyanka Singh Date: Mon, 19 Apr 2021 11:15:04 +0530 Subject: board: freescale: vid.c: Add check for return value of adjust_vdd() Add check for return value of adjust_vdd() Signed-off-by: Biwen Li Signed-off-by: Priyanka Singh Reviewed-by: Priyanka Jain --- board/freescale/common/vid.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/board/freescale/common/vid.c b/board/freescale/common/vid.c index 6e82962..13ef101 100644 --- a/board/freescale/common/vid.c +++ b/board/freescale/common/vid.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2014 Freescale Semiconductor, Inc. - * Copyright 2020 NXP + * Copyright 2020-21 NXP * Copyright 2020 Stephen Carlson */ @@ -793,13 +793,16 @@ static int do_vdd_override(struct cmd_tbl *cmdtp, char *const argv[]) { ulong override; + int ret = 0; if (argc < 2) return CMD_RET_USAGE; - if (!strict_strtoul(argv[1], 10, &override)) - adjust_vdd(override); /* the value is checked by callee */ - else + if (!strict_strtoul(argv[1], 10, &override)) { + ret = adjust_vdd(override); + if (ret < 0) + return CMD_RET_FAILURE; + } else return CMD_RET_USAGE; return 0; } -- cgit v1.1 From 84c2e044a9372945c5ef6b83ab49f9cb2ba74c0d Mon Sep 17 00:00:00 2001 From: Jiafei Pan Date: Wed, 21 Apr 2021 12:12:49 +0800 Subject: armv8: layerscape: add PSCI support for cpu release For cpu release command, check whether PSCI is supported firstly, if supported, use PSCI to kick off secondary cores, otherwise still use spin table. Signed-off-by: Jiafei Pan [Fixed checkpatch alignment CHECKs] Signed-off-by: Priyanka Jain --- arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 2 +- arch/arm/cpu/armv8/fsl-layerscape/cpu.h | 1 + arch/arm/cpu/armv8/fsl-layerscape/mp.c | 49 +++++++++++++++++++++++---------- 3 files changed, 36 insertions(+), 16 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index 270a72e..d0103fc 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -1063,7 +1063,7 @@ int cpu_eth_init(struct bd_info *bis) return error; } -static inline int check_psci(void) +int check_psci(void) { unsigned int psci_ver; diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.h b/arch/arm/cpu/armv8/fsl-layerscape/cpu.h index dca5fd0..45da958 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.h +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.h @@ -6,3 +6,4 @@ int fsl_qoriq_core_to_cluster(unsigned int core); u32 initiator_type(u32 cluster, int init_id); u32 cpu_mask(void); +int check_psci(void); diff --git a/arch/arm/cpu/armv8/fsl-layerscape/mp.c b/arch/arm/cpu/armv8/fsl-layerscape/mp.c index 5ac545f..730d766 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/mp.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/mp.c @@ -10,10 +10,12 @@ #include #include #include +#include #include #include #include #include +#include #include "cpu.h" #include #include @@ -301,24 +303,41 @@ int cpu_release(u32 nr, int argc, char *const argv[]) u64 *table = get_spin_tbl_addr(); int pos; - pos = core_to_pos(nr); - if (pos <= 0) - return -1; - - table += pos * WORDS_PER_SPIN_TABLE_ENTRY; boot_addr = simple_strtoull(argv[0], NULL, 16); - table[SPIN_TABLE_ELEM_ENTRY_ADDR_IDX] = boot_addr; - flush_dcache_range((unsigned long)table, + + if (check_psci()) { + /* SPIN Table is used */ + pos = core_to_pos(nr); + if (pos <= 0) + return -1; + + table += pos * WORDS_PER_SPIN_TABLE_ENTRY; + table[SPIN_TABLE_ELEM_ENTRY_ADDR_IDX] = boot_addr; + flush_dcache_range((unsigned long)table, (unsigned long)table + SPIN_TABLE_ELEM_SIZE); - asm volatile("dsb st"); + asm volatile("dsb st"); - /* - * The secondary CPUs polling the spin-table above for a non-zero - * value. To save power "wfe" is called. Thus call "sev" here to - * wake the CPUs and let them check the spin-table again (see - * slave_cpu loop in lowlevel.S) - */ - asm volatile("sev"); + /* + * The secondary CPUs polling the spin-table above for a non-zero + * value. To save power "wfe" is called. Thus call "sev" here to + * wake the CPUs and let them check the spin-table again (see + * slave_cpu loop in lowlevel.S) + */ + asm volatile("sev"); + } else { + /* Use PSCI to kick the core */ + struct pt_regs regs; + + printf("begin to kick cpu core #%d to address %llx\n", + nr, boot_addr); + regs.regs[0] = PSCI_0_2_FN64_CPU_ON; + regs.regs[1] = nr; + regs.regs[2] = boot_addr; + regs.regs[3] = 0; + smc_call(®s); + if (regs.regs[0]) + return -1; + } return 0; } -- cgit v1.1 From addec3511f7c389353884026435488d3d552e6a9 Mon Sep 17 00:00:00 2001 From: Yangbo Lu Date: Tue, 27 Apr 2021 16:42:11 +0800 Subject: armv8: layerscape: enable eMMC HS400 workarounds for LX2160A/LX2162A Enable eMMC HS400 workarounds for LX2160A/LX2162A. Signed-off-by: Yangbo Lu Reviewed-by: Priyanka Jain --- arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 9d1ba4c..395e5cc 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -224,6 +224,8 @@ config ARCH_LX2162A select SYS_FSL_EC1 select SYS_FSL_EC2 select SYS_FSL_ERRATUM_A050106 + select SYS_FSL_ERRATUM_A011334 + select SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND select SYS_FSL_HAS_RGMII select SYS_FSL_HAS_SEC select SYS_FSL_HAS_CCN508 @@ -254,6 +256,8 @@ config ARCH_LX2160A select SYS_FSL_EC1 select SYS_FSL_EC2 select SYS_FSL_ERRATUM_A050106 + select SYS_FSL_ERRATUM_A011334 + select SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND select SYS_FSL_HAS_RGMII select SYS_FSL_HAS_SEC select SYS_FSL_HAS_CCN508 -- cgit v1.1 From ff64e9a9f0f48107a46536c251951885df63d63f Mon Sep 17 00:00:00 2001 From: Chaitanya Sakinam Date: Fri, 7 May 2021 12:22:05 +0800 Subject: armv8: ls1012a: Pass PPFE firmware to Linux through FDT Read Linux PPFE firmware from flash partition and pass it to Linux through FDT entry. So that we can avoid placing PPFE firmware in Linux rootfs. (FDT may increase at max by 64KB) Signed-off-by: Chaitanya Sakinam Signed-off-by: Anji J Signed-off-by: Biwen Li Reviewed-by: Priyanka Jain --- arch/arm/cpu/armv8/fsl-layerscape/fdt.c | 150 +++++++++++++++++++++++++++++++- drivers/net/pfe_eth/pfe_firmware.c | 60 ++++++++++++- 2 files changed, 207 insertions(+), 3 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c index 7f29aa4..f1624ff 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2014-2015 Freescale Semiconductor, Inc. - * Copyright 2020 NXP + * Copyright 2020-2021 NXP */ #include @@ -478,6 +478,151 @@ static bool crypto_is_disabled(unsigned int svr) return false; } +#ifdef CONFIG_FSL_PFE +void pfe_set_firmware_in_fdt(void *blob, int pfenode, void *pfw, char *pename, + unsigned int len) +{ + int rc, fwnode; + unsigned int phandle; + char subnode_str[32], prop_str[32], phandle_str[32], s[64]; + + sprintf(subnode_str, "pfe-%s-firmware", pename); + sprintf(prop_str, "fsl,pfe-%s-firmware", pename); + sprintf(phandle_str, "fsl,%s-firmware", pename); + + /*Add PE FW to fdt.*/ + /* Increase the size of the fdt to make room for the node. */ + rc = fdt_increase_size(blob, len); + if (rc < 0) { + printf("Unable to make room for %s firmware: %s\n", pename, + fdt_strerror(rc)); + return; + } + + /* Create the firmware node. */ + fwnode = fdt_add_subnode(blob, pfenode, subnode_str); + if (fwnode < 0) { + fdt_get_path(blob, pfenode, s, sizeof(s)); + printf("Could not add firmware node to %s: %s\n", s, + fdt_strerror(fwnode)); + return; + } + + rc = fdt_setprop_string(blob, fwnode, "compatible", prop_str); + if (rc < 0) { + fdt_get_path(blob, fwnode, s, sizeof(s)); + printf("Could not add compatible property to node %s: %s\n", s, + fdt_strerror(rc)); + return; + } + + rc = fdt_setprop_u32(blob, fwnode, "length", len); + if (rc < 0) { + fdt_get_path(blob, fwnode, s, sizeof(s)); + printf("Could not add compatible property to node %s: %s\n", s, + fdt_strerror(rc)); + return; + } + + /*create phandle and set the property*/ + phandle = fdt_create_phandle(blob, fwnode); + if (!phandle) { + fdt_get_path(blob, fwnode, s, sizeof(s)); + printf("Could not add phandle property to node %s: %s\n", s, + fdt_strerror(rc)); + return; + } + + rc = fdt_setprop(blob, fwnode, phandle_str, pfw, len); + if (rc < 0) { + fdt_get_path(blob, fwnode, s, sizeof(s)); + printf("Could not add firmware property to node %s: %s\n", s, + fdt_strerror(rc)); + return; + } +} + +void fdt_fixup_pfe_firmware(void *blob) +{ + int pfenode; + unsigned int len_class = 0, len_tmu = 0, len_util = 0; + const char *p; + void *pclassfw, *ptmufw, *putilfw; + + /* The first PFE we find, will contain the actual firmware. */ + pfenode = fdt_node_offset_by_compatible(blob, -1, "fsl,pfe"); + if (pfenode < 0) + /* Exit silently if there are no PFE devices */ + return; + + /* If we already have a firmware node, then also exit silently. */ + if (fdt_node_offset_by_compatible(blob, -1, + "fsl,pfe-class-firmware") > 0) + return; + + /* If the environment variable is not set, then exit silently */ + p = env_get("class_elf_firmware"); + if (!p) + return; + + pclassfw = (void *)simple_strtoul(p, NULL, 16); + if (!pclassfw) + return; + + p = env_get("class_elf_size"); + if (!p) + return; + len_class = simple_strtoul(p, NULL, 16); + + /* If the environment variable is not set, then exit silently */ + p = env_get("tmu_elf_firmware"); + if (!p) + return; + + ptmufw = (void *)simple_strtoul(p, NULL, 16); + if (!ptmufw) + return; + + p = env_get("tmu_elf_size"); + if (!p) + return; + len_tmu = simple_strtoul(p, NULL, 16); + + if (len_class == 0 || len_tmu == 0) { + printf("PFE FW corrupted. CLASS FW size %d, TMU FW size %d\n", + len_class, len_tmu); + return; + } + + /*Add CLASS FW to fdt.*/ + pfe_set_firmware_in_fdt(blob, pfenode, pclassfw, "class", len_class); + + /*Add TMU FW to fdt.*/ + pfe_set_firmware_in_fdt(blob, pfenode, ptmufw, "tmu", len_tmu); + + /* Util PE firmware is handled separately as it is not a usual case*/ + p = env_get("util_elf_firmware"); + if (!p) + return; + + putilfw = (void *)simple_strtoul(p, NULL, 16); + if (!putilfw) + return; + + p = env_get("util_elf_size"); + if (!p) + return; + len_util = simple_strtoul(p, NULL, 16); + + if (len_util) { + printf("PFE Util PE firmware is not added to FDT.\n"); + return; + } + + pfe_set_firmware_in_fdt(blob, pfenode, putilfw, "util", len_util); +} +#endif + void ft_cpu_setup(void *blob, struct bd_info *bd) { struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); @@ -534,6 +679,9 @@ void ft_cpu_setup(void *blob, struct bd_info *bd) #ifdef CONFIG_SYS_DPAA_FMAN fdt_fixup_fman_firmware(blob); #endif +#ifdef CONFIG_FSL_PFE + fdt_fixup_pfe_firmware(blob); +#endif #ifndef CONFIG_ARCH_LS1012A fsl_fdt_disable_usb(blob); #endif diff --git a/drivers/net/pfe_eth/pfe_firmware.c b/drivers/net/pfe_eth/pfe_firmware.c index eee70a2..ac86e33 100644 --- a/drivers/net/pfe_eth/pfe_firmware.c +++ b/drivers/net/pfe_eth/pfe_firmware.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2015-2016 Freescale Semiconductor, Inc. - * Copyright 2017 NXP + * Copyright 2017,2021 NXP */ /* @@ -262,7 +262,8 @@ int pfe_firmware_init(void) uintptr_t pfe_img_addr = 0; #endif int ret = 0; - int fw_count; + int fw_count, max_fw_count; + const char *p; ret = pfe_spi_flash_init(); if (ret) @@ -293,6 +294,61 @@ int pfe_firmware_init(void) } #endif + p = env_get("load_util"); + if (!p) { + max_fw_count = 2; + } else { + max_fw_count = simple_strtoul(p, NULL, 10); + if (max_fw_count) + max_fw_count = 3; + else + max_fw_count = 2; + } + + for (fw_count = 0; fw_count < max_fw_count; fw_count++) { + switch (fw_count) { + case 0: + pfe_firmware_name = "class_slowpath"; + break; + case 1: + pfe_firmware_name = "tmu_slowpath"; + break; + case 2: + pfe_firmware_name = "util_slowpath"; + break; + } + + if (pfe_get_fw(&raw_image_addr, &raw_image_size, + pfe_firmware_name)) { + printf("%s firmware couldn't be found in FIT image\n", + pfe_firmware_name); + break; + } + pfe_firmware = malloc(raw_image_size); + if (!pfe_firmware) + return -ENOMEM; + memcpy((void *)pfe_firmware, (void *)raw_image_addr, + raw_image_size); + + switch (fw_count) { + case 0: + env_set_addr("class_elf_firmware", pfe_firmware); + env_set_addr("class_elf_size", (void *)raw_image_size); + break; + case 1: + env_set_addr("tmu_elf_firmware", pfe_firmware); + env_set_addr("tmu_elf_size", (void *)raw_image_size); + break; + case 2: + env_set_addr("util_elf_firmware", pfe_firmware); + env_set_addr("util_elf_size", (void *)raw_image_size); + break; + } + } + + raw_image_addr = NULL; + pfe_firmware = NULL; + raw_image_size = 0; for (fw_count = 0; fw_count < 2; fw_count++) { if (fw_count == 0) pfe_firmware_name = "class"; -- cgit v1.1 From 8e221b4a1c3144bbc0fcbb5a6c40ba63d618f02f Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Thu, 13 May 2021 14:54:32 +0800 Subject: pci: layerscape-ep: Add check of the PCIe controller enablement Stop to initialize the PCIe controller if it's disabled by RCW. Fixes: 118e58e26eba ("pci: layerscape: Split the EP and RC driver") Signed-off-by: Hou Zhiqiang Reviewed-by: Priyanka Jain --- drivers/pci/pcie_layerscape_ep.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/pci/pcie_layerscape_ep.c b/drivers/pci/pcie_layerscape_ep.c index c723163..f2813ae 100644 --- a/drivers/pci/pcie_layerscape_ep.c +++ b/drivers/pci/pcie_layerscape_ep.c @@ -269,6 +269,10 @@ static int ls_pcie_ep_probe(struct udevice *dev) pcie->idx = ((unsigned long)pcie->dbi - PCIE_SYS_BASE_ADDR) / PCIE_CCSR_SIZE; + /* This controller is disabled by RCW */ + if (!is_serdes_configured(PCIE_SRDS_PRTCL(pcie->idx))) + return 0; + pcie->big_endian = fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev), "big-endian"); -- cgit v1.1 From 38d1a187501e245e9b8479c1999015dbd352f2de Mon Sep 17 00:00:00 2001 From: Yangbo Lu Date: Fri, 14 May 2021 10:33:57 +0800 Subject: arm: dts: lx2162aqds: support eMMC HS400 mode on esdhc1 Add properties related to eMMC HS400 mode for esdhc1. Signed-off-by: Yangbo Lu Reviewed-by: Priyanka Jain --- arch/arm/dts/fsl-lx2162a-qds-sd1-17.dtsi | 8 +++++++- arch/arm/dts/fsl-lx2162a-qds-sd1-18.dtsi | 8 +++++++- arch/arm/dts/fsl-lx2162a-qds-sd1-20.dtsi | 8 +++++++- arch/arm/dts/fsl-lx2162a-qds.dts | 8 +++++++- 4 files changed, 28 insertions(+), 4 deletions(-) diff --git a/arch/arm/dts/fsl-lx2162a-qds-sd1-17.dtsi b/arch/arm/dts/fsl-lx2162a-qds-sd1-17.dtsi index 60f5a4e..d1e4a85 100644 --- a/arch/arm/dts/fsl-lx2162a-qds-sd1-17.dtsi +++ b/arch/arm/dts/fsl-lx2162a-qds-sd1-17.dtsi @@ -5,7 +5,7 @@ * Some assumptions are made: * * mezzanine card M8 is connected to IO SLOT1 (25g-aui for DPMAC 3,4,5,6) * - * Copyright 2020 NXP + * Copyright 2020-2021 NXP * */ @@ -56,3 +56,9 @@ reg = <0x3>; }; }; + +&esdhc1 { + mmc-hs200-1_8v; + mmc-hs400-1_8v; + bus-width = <8>; +}; diff --git a/arch/arm/dts/fsl-lx2162a-qds-sd1-18.dtsi b/arch/arm/dts/fsl-lx2162a-qds-sd1-18.dtsi index 8e11b06..e9a743b 100644 --- a/arch/arm/dts/fsl-lx2162a-qds-sd1-18.dtsi +++ b/arch/arm/dts/fsl-lx2162a-qds-sd1-18.dtsi @@ -6,7 +6,7 @@ * * mezzanine card M11 is connected to IO SLOT1 (usxgmii for DPMAC 3,4) * * mezzanine card M13/M8 is connected to IO SLOT6 (25g-aui for DPMAC 5,6) * - * Copyright 2020 NXP + * Copyright 2020-2021 NXP * */ @@ -59,3 +59,9 @@ reg = <0x1>; }; }; + +&esdhc1 { + mmc-hs200-1_8v; + mmc-hs400-1_8v; + bus-width = <8>; +}; diff --git a/arch/arm/dts/fsl-lx2162a-qds-sd1-20.dtsi b/arch/arm/dts/fsl-lx2162a-qds-sd1-20.dtsi index faf4285..d9ad1c6 100644 --- a/arch/arm/dts/fsl-lx2162a-qds-sd1-20.dtsi +++ b/arch/arm/dts/fsl-lx2162a-qds-sd1-20.dtsi @@ -6,7 +6,7 @@ * * Mezzanine card M8 is connected to IO SLOT1 * (xlaui4 for DPMAC 1) * - * Copyright 2020 NXP + * Copyright 2020-2021 NXP * */ @@ -24,3 +24,9 @@ reg = <0x0>; }; }; + +&esdhc1 { + mmc-hs200-1_8v; + mmc-hs400-1_8v; + bus-width = <8>; +}; diff --git a/arch/arm/dts/fsl-lx2162a-qds.dts b/arch/arm/dts/fsl-lx2162a-qds.dts index 341610c..0ca30df 100644 --- a/arch/arm/dts/fsl-lx2162a-qds.dts +++ b/arch/arm/dts/fsl-lx2162a-qds.dts @@ -2,7 +2,7 @@ /* * NXP LX2162AQDS device tree source * - * Copyright 2020 NXP + * Copyright 2020-2021 NXP * */ @@ -135,3 +135,9 @@ reg = <2>; }; }; + +&esdhc1 { + mmc-hs200-1_8v; + mmc-hs400-1_8v; + bus-width = <8>; +}; -- cgit v1.1 From effcb1ebe44a82df6670b7cdb4d9605e3a2a3207 Mon Sep 17 00:00:00 2001 From: Kuldeep Singh Date: Wed, 19 May 2021 16:40:12 +0530 Subject: configs: ls1088a: Enable CONFIG_SYS_RELOC_ENV_ADDR Signed-off-by: Kuldeep Singh Reviewed-by: Priyanka Jain --- configs/ls1088aqds_tfa_defconfig | 1 + configs/ls1088ardb_tfa_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/configs/ls1088aqds_tfa_defconfig b/configs/ls1088aqds_tfa_defconfig index 5229a35..ea308ca 100644 --- a/configs/ls1088aqds_tfa_defconfig +++ b/configs/ls1088aqds_tfa_defconfig @@ -48,6 +48,7 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_IS_IN_NAND=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_ADDR=0x20500000 +CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SCSI_AHCI=y diff --git a/configs/ls1088ardb_tfa_defconfig b/configs/ls1088ardb_tfa_defconfig index 007a80c..e557858 100644 --- a/configs/ls1088ardb_tfa_defconfig +++ b/configs/ls1088ardb_tfa_defconfig @@ -45,6 +45,7 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_ADDR=0x20500000 +CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SCSI_AHCI=y -- cgit v1.1 From 8bb20852eb4f503da921b1e1c67f1193c0ad5317 Mon Sep 17 00:00:00 2001 From: Biwen Li Date: Fri, 21 May 2021 15:15:06 +0800 Subject: configs: ls2088aqds: fix synchronous exception IFC NOR flash base address of ls2088a is 0x580000000, and offset of env crc is 0x500000, so fix the macro CONFIG_ENV_ADDR to fix synchronous exception(access illegal address) Fixes: 59071804c1 ("configs: ls2080a: Correct ENV_ADDR value") Signed-off-by: Biwen Li Reviewed-by: Priyanka Jain --- configs/ls2088aqds_tfa_defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configs/ls2088aqds_tfa_defconfig b/configs/ls2088aqds_tfa_defconfig index 5620e8a..5d14b55 100644 --- a/configs/ls2088aqds_tfa_defconfig +++ b/configs/ls2088aqds_tfa_defconfig @@ -42,7 +42,7 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_FLASH=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_ENV_ADDR=0x20500000 +CONFIG_ENV_ADDR=0x580500000 CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y -- cgit v1.1 From 6bc2419cc25dd89f889c1ede88c68c046c64d943 Mon Sep 17 00:00:00 2001 From: Matt Merhar Date: Sun, 30 May 2021 00:16:17 +0000 Subject: board: freescale: p2041rdb: use correct EEPROM address length These boards, according to the schematic and per the board I own, use an M24256-BWDW6TP I2C EEPROM which requires two address bytes. This fixes the 'mac' command which is used to program, among other things, the MAC addresses for the ethernet interfaces on the board. Signed-off-by: Matt Merhar Reviewed-by: Priyanka Jain --- include/configs/P2041RDB.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index 3895c2d..715154a 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -92,7 +92,7 @@ unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_I2C_EEPROM_NXID #define CONFIG_SYS_EEPROM_BUS_NUM 0 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* * DDR Setup -- cgit v1.1 From ae7020b435883f48f944d6682914a511044703ae Mon Sep 17 00:00:00 2001 From: Yangbo Lu Date: Thu, 3 Jun 2021 10:51:17 +0800 Subject: mmc: fsl_esdhc: convert to CONFIG_FSL_ESDHC_VS33_NOT_SUPPORT For eSDHC, power supply is through peripheral circuit. Some eSDHC versions have value 0 of the bit but that does not reflect the truth. 3.3V is common for SD/MMC, and is supported for all boards with eSDHC in current u-boot. So, make 3.3V is supported in default in code. CONFIG_FSL_ESDHC_VS33_NOT_SUPPORT can be enabled if future board does not support 3.3V. This is also a fix-up for one previous patch, which converted to use IS_ENABLED() for CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 that is not a Kconfig option. Fixes: 52faec31827e ("mmc: fsl_esdhc: replace most #ifdefs by IS_ENABLED()") Signed-off-by: Yangbo Lu Reviewed-by: Jaehoon Chung Reviewed-by: Priyanka Jain --- drivers/mmc/Kconfig | 7 +++++++ drivers/mmc/fsl_esdhc.c | 17 ++++++++++++++--- 2 files changed, 21 insertions(+), 3 deletions(-) diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index 8901456..0909f50 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -798,6 +798,13 @@ config FSL_ESDHC_33V_IO_RELIABILITY_WORKAROUND This option assumes no hotplug, and u-boot has to make all the way to to linux to use 1.8v UHS-I speed mode if has card. +config FSL_ESDHC_VS33_NOT_SUPPORT + bool "3.3V power supply not supported" + depends on FSL_ESDHC + help + For eSDHC, power supply is through peripheral circuit. 3.3V support is + common. Select this if 3.3V power supply not supported. + config FSL_ESDHC_IMX bool "Freescale/NXP i.MX eSDHC controller support" help diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 7501fdb..1d98fa6 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc - * Copyright 2019-2020 NXP + * Copyright 2019-2021 NXP * Andy Fleming * * Based vaguely on the pxa mmc code: @@ -795,10 +795,21 @@ static void fsl_esdhc_get_cfg_common(struct fsl_esdhc_priv *priv, u32 caps; caps = esdhc_read32(®s->hostcapblt); + + /* + * For eSDHC, power supply is through peripheral circuit. Some eSDHC + * versions have value 0 of the bit but that does not reflect the + * truth. 3.3V is common for SD/MMC, and is supported for all boards + * with eSDHC in current u-boot. So, make 3.3V is supported in + * default in code. CONFIG_FSL_ESDHC_VS33_NOT_SUPPORT can be enabled + * if future board does not support 3.3V. + */ + caps |= HOSTCAPBLT_VS33; + if (IS_ENABLED(CONFIG_FSL_ESDHC_VS33_NOT_SUPPORT)) + caps &= ~HOSTCAPBLT_VS33; + if (IS_ENABLED(CONFIG_SYS_FSL_ERRATUM_ESDHC135)) caps &= ~(HOSTCAPBLT_SRS | HOSTCAPBLT_VS18 | HOSTCAPBLT_VS30); - if (IS_ENABLED(CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33)) - caps |= HOSTCAPBLT_VS33; if (caps & HOSTCAPBLT_VS18) cfg->voltages |= MMC_VDD_165_195; if (caps & HOSTCAPBLT_VS30) -- cgit v1.1 From b1d59867e5c2bc0cf7308348fcf35529833f57cd Mon Sep 17 00:00:00 2001 From: Yangbo Lu Date: Thu, 3 Jun 2021 10:51:18 +0800 Subject: mmc: fsl_esdhc_imx: drop CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 There is no i.MX board using such option. Drop it. Signed-off-by: Yangbo Lu Reviewed-by: Priyanka Jain --- drivers/mmc/fsl_esdhc_imx.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c index a467583..566ce046 100644 --- a/drivers/mmc/fsl_esdhc_imx.c +++ b/drivers/mmc/fsl_esdhc_imx.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc - * Copyright 2019 NXP Semiconductors + * Copyright 2019, 2021 NXP * Andy Fleming * Yangbo Lu * @@ -1234,11 +1234,6 @@ static int fsl_esdhc_init(struct fsl_esdhc_priv *priv, ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30); #endif -/* T4240 host controller capabilities register should have VS33 bit */ -#ifdef CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 - caps = caps | ESDHC_HOSTCAPBLT_VS33; -#endif - if (caps & ESDHC_HOSTCAPBLT_VS18) voltage_caps |= MMC_VDD_165_195; if (caps & ESDHC_HOSTCAPBLT_VS30) -- cgit v1.1 From 34f39ce882d2ad214bc16341823ffba4476fde2a Mon Sep 17 00:00:00 2001 From: Yangbo Lu Date: Thu, 3 Jun 2021 10:51:19 +0800 Subject: armv8: layerscape: drop CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 Drop CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33. CONFIG_FSL_ESDHC_VS33_NOT_SUPPORT is used instead. Signed-off-by: Yangbo Lu Acked-by: Michael Walle [for kontron-sl28] Reviewed-by: Priyanka Jain --- include/configs/T208xQDS.h | 3 +-- include/configs/T208xRDB.h | 3 +-- include/configs/T4240RDB.h | 3 +-- include/configs/kontron_sl28.h | 5 ----- include/configs/ls1012a2g5rdb.h | 7 +------ include/configs/ls1012afrwy.h | 7 +------ include/configs/ls1012aqds.h | 6 +----- include/configs/ls1012ardb.h | 8 +------- include/configs/ls1028a_common.h | 7 +------ include/configs/ls1043a_common.h | 9 +-------- include/configs/ls1046a_common.h | 9 +-------- include/configs/ls1088aqds.h | 3 +-- include/configs/ls1088ardb.h | 7 +------ include/configs/ls2080aqds.h | 7 +------ include/configs/ls2080ardb.h | 7 +------ include/configs/lx2160a_common.h | 7 +------ scripts/config_whitelist.txt | 1 - 17 files changed, 15 insertions(+), 84 deletions(-) diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index b1acb56..7bc792b 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2011-2013 Freescale Semiconductor, Inc. - * Copyright 2020 NXP + * Copyright 2020-2021 NXP */ /* @@ -618,7 +618,6 @@ unsigned long get_board_ddr_clk(void); #ifdef CONFIG_MMC #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT -#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 #endif /* diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index e467ef4..b5197b3 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2014 Freescale Semiconductor, Inc. - * Copyright 2020 NXP + * Copyright 2020-2021 NXP */ /* @@ -574,7 +574,6 @@ unsigned long get_board_ddr_clk(void); #ifdef CONFIG_MMC #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT -#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 #endif /* diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index a04d913..139beae 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2014 Freescale Semiconductor, Inc. - * Copyright 2020 NXP + * Copyright 2020-2021 NXP */ /* @@ -585,7 +585,6 @@ unsigned long get_board_ddr_clk(void); #ifdef CONFIG_MMC #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT -#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 #endif diff --git a/include/configs/kontron_sl28.h b/include/configs/kontron_sl28.h index 5f11205..bfb4e67 100644 --- a/include/configs/kontron_sl28.h +++ b/include/configs/kontron_sl28.h @@ -56,11 +56,6 @@ #define CONFIG_DDR_CLK_FREQ 100000000 #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ / 4) -/* MMC */ -#ifdef CONFIG_MMC -#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 -#endif - /* ethernet */ #define CONFIG_SYS_RX_ETH_BUFFER 8 diff --git a/include/configs/ls1012a2g5rdb.h b/include/configs/ls1012a2g5rdb.h index 9fbeecf..44f9da7 100644 --- a/include/configs/ls1012a2g5rdb.h +++ b/include/configs/ls1012a2g5rdb.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright 2017 NXP + * Copyright 2017, 2021 NXP */ #ifndef __LS1012A2G5RDB_H__ @@ -13,11 +13,6 @@ #define CONFIG_CHIP_SELECTS_PER_CTRL 1 #define CONFIG_SYS_SDRAM_SIZE 0x40000000 -/* MMC */ -#ifdef CONFIG_MMC -#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 -#endif - /* SATA */ #define CONFIG_LIBATA #define CONFIG_SCSI_AHCI diff --git a/include/configs/ls1012afrwy.h b/include/configs/ls1012afrwy.h index beb7440..f8b3861 100644 --- a/include/configs/ls1012afrwy.h +++ b/include/configs/ls1012afrwy.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright 2018 NXP + * Copyright 2018, 2021 NXP */ #ifndef __LS1012AFRWY_H__ @@ -33,11 +33,6 @@ func(DHCP, dhcp, na) #endif -/* MMC */ -#ifdef CONFIG_MMC -#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 -#endif - #define CONFIG_PCIE1 /* PCIE controller 1 */ #define CONFIG_PCI_SCAN_SHOW diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h index bdcb8d6..3e5fdad 100644 --- a/include/configs/ls1012aqds.h +++ b/include/configs/ls1012aqds.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2021 NXP */ #ifndef __LS1012AQDS_H__ @@ -93,11 +94,6 @@ DSPI_CTAR_DT(0)) #define CONFIG_SPI_FLASH_EON /* cs3 */ -/* MMC */ -#ifdef CONFIG_MMC -#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 -#endif - #define CONFIG_PCIE1 /* PCIE controller 1 */ #define CONFIG_PCI_SCAN_SHOW diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h index efa0284..c8a2f12 100644 --- a/include/configs/ls1012ardb.h +++ b/include/configs/ls1012ardb.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright 2020 NXP + * Copyright 2020-2021 NXP * Copyright 2016 Freescale Semiconductor, Inc. */ @@ -38,12 +38,6 @@ #define __PHY_ETH2_MASK 0xFB #define __PHY_ETH1_MASK 0xFD -/* MMC */ -#ifdef CONFIG_MMC -#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 -#endif - - #define CONFIG_PCIE1 /* PCIE controller 1 */ #define CONFIG_PCI_SCAN_SHOW diff --git a/include/configs/ls1028a_common.h b/include/configs/ls1028a_common.h index 31fcdae..5900b8f 100644 --- a/include/configs/ls1028a_common.h +++ b/include/configs/ls1028a_common.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright 2019-2020 NXP + * Copyright 2019-2021 NXP */ #ifndef __L1028A_COMMON_H @@ -93,11 +93,6 @@ #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ -/* MMC */ -#ifdef CONFIG_MMC -#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 -#endif - #define OCRAM_NONSECURE_SIZE 0x00010000 #define CONFIG_SYS_FSL_QSPI_BASE 0x20000000 diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index 29a3790..65d63e2 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright (C) 2015 Freescale Semiconductor - * Copyright 2019-2020 NXP + * Copyright 2019-2021 NXP */ #ifndef __LS1043A_COMMON_H @@ -171,13 +171,6 @@ #endif #endif -/* MMC */ -#ifndef SPL_NO_MMC -#ifdef CONFIG_MMC -#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 -#endif -#endif - /* DSPI */ #ifndef SPL_NO_DSPI #ifdef CONFIG_FSL_DSPI diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h index 0c3978a..11e1a18 100644 --- a/include/configs/ls1046a_common.h +++ b/include/configs/ls1046a_common.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2016 Freescale Semiconductor - * Copyright 2019-2020 NXP + * Copyright 2019-2021 NXP */ #ifndef __LS1046A_COMMON_H @@ -165,13 +165,6 @@ CONFIG_SYS_SCSI_MAX_LUN) #endif -/* MMC */ -#ifndef SPL_NO_MMC -#ifdef CONFIG_MMC -#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 -#endif -#endif - /* FMan ucode */ #ifndef SPL_NO_FMAN #define CONFIG_SYS_DPAA_FMAN diff --git a/include/configs/ls1088aqds.h b/include/configs/ls1088aqds.h index 4d04833..d032a3d 100644 --- a/include/configs/ls1088aqds.h +++ b/include/configs/ls1088aqds.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright 2017, 2020 NXP + * Copyright 2017, 2020-2021 NXP */ #ifndef __LS1088A_QDS_H @@ -361,7 +361,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_FSL_MEMAC /* MMC */ -#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 #define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \ QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER) diff --git a/include/configs/ls1088ardb.h b/include/configs/ls1088ardb.h index 6f36dd4..5ade0eb 100644 --- a/include/configs/ls1088ardb.h +++ b/include/configs/ls1088ardb.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright 2017, 2020 NXP + * Copyright 2017, 2020-2021 NXP */ #ifndef __LS1088A_RDB_H @@ -507,11 +507,6 @@ #endif #endif -/* MMC */ -#ifdef CONFIG_MMC -#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 -#endif - #ifndef SPL_NO_ENV #define BOOT_TARGET_DEVICES(func) \ diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h index b3fce1b..41c1a86 100644 --- a/include/configs/ls2080aqds.h +++ b/include/configs/ls2080aqds.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright 2017, 2019-2020 NXP + * Copyright 2017, 2019-2021 NXP * Copyright 2015 Freescale Semiconductor */ @@ -318,11 +318,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_PCI_SCAN_SHOW #endif -/* MMC */ -#ifdef CONFIG_MMC -#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 -#endif - /* Initial environment variables */ #undef CONFIG_EXTRA_ENV_SETTINGS #ifdef CONFIG_NXP_ESBC diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h index 8626a1d..f2dc495 100644 --- a/include/configs/ls2080ardb.h +++ b/include/configs/ls2080ardb.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright 2017, 2019-2020 NXP + * Copyright 2017, 2019-2021 NXP * Copyright 2015 Freescale Semiconductor */ @@ -300,11 +300,6 @@ unsigned long get_board_sys_clk(void); #define CONFIG_PCI_SCAN_SHOW #endif -/* MMC */ -#ifdef CONFIG_MMC -#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 -#endif - #define BOOT_TARGET_DEVICES(func) \ func(USB, usb, 0) \ func(MMC, mmc, 0) \ diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h index 9f2b899..15ea0e4 100644 --- a/include/configs/lx2160a_common.h +++ b/include/configs/lx2160a_common.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright 2018-2020 NXP + * Copyright 2018-2021 NXP */ #ifndef __LX2_COMMON_H @@ -129,11 +129,6 @@ #define CONFIG_PCI_SCAN_SHOW #endif -/* MMC */ -#ifdef CONFIG_MMC -#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 -#endif - /* SATA */ #ifdef CONFIG_SCSI diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 8f92b82..3dbcc04 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -2307,7 +2307,6 @@ CONFIG_SYS_FSL_MAX_NUM_OF_SEC CONFIG_SYS_FSL_MC9SDZ60_I2C_ADDR CONFIG_SYS_FSL_MC_BASE CONFIG_SYS_FSL_MC_SIZE -CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 CONFIG_SYS_FSL_NI_BASE CONFIG_SYS_FSL_NI_SIZE CONFIG_SYS_FSL_NO_SERDES -- cgit v1.1 From 058c08dc606435c5df129be7443dba348bcbf6a3 Mon Sep 17 00:00:00 2001 From: Aleksandar Gerasimovski Date: Fri, 4 Jun 2021 09:17:56 +0000 Subject: configs: seli8: set envsize to 0x4000 During the mainlining of the board this was by mistake set to sector size. Our user space env scripts are expecting envsize of 0x4000, and setting this differently will break our cross-platform compatibility. Signed-off-by: Aleksandar Gerasimovski Reviewed-by: Priyanka Jain --- configs/pg_wcom_seli8_defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configs/pg_wcom_seli8_defconfig b/configs/pg_wcom_seli8_defconfig index a61b826..a00334b 100644 --- a/configs/pg_wcom_seli8_defconfig +++ b/configs/pg_wcom_seli8_defconfig @@ -7,7 +7,7 @@ CONFIG_KM_COMMON_ETH_INIT=y CONFIG_PIGGY_MAC_ADDRESS_OFFSET=3 CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff -CONFIG_ENV_SIZE=0x20000 +CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_SYS_I2C_MXC_I2C1=y CONFIG_SYS_I2C_MXC_I2C2=y -- cgit v1.1 From 0753603e25dff5189ff4ba397b0625cc2d9a16c3 Mon Sep 17 00:00:00 2001 From: Aleksandar Gerasimovski Date: Fri, 4 Jun 2021 09:25:00 +0000 Subject: keymile: common: fix hexadecimal env variable format MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Commit df86d32 breaks linux kernel and product application boot. Linux kernel and our product application scripts are expecting 0x prefix for hexadecimal values, while env_set_hex writes them without a prefix. This patch partially revert env_set_hex usage for affected env variables. Signed-off-by: Aleksandar Gerasimovski Reviewed-by: Priyanka Jain --- board/keymile/common/common.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/board/keymile/common/common.c b/board/keymile/common/common.c index 2ce7462..016806a 100644 --- a/board/keymile/common/common.c +++ b/board/keymile/common/common.c @@ -46,12 +46,14 @@ int set_km_env(void) unsigned int pram; unsigned int varaddr; unsigned int kernelmem; - char *p; unsigned long rootfssize = 0; + char envval[16]; + char *p; pnvramaddr = CONFIG_SYS_SDRAM_BASE + gd->ram_size - CONFIG_KM_RESERVED_PRAM - CONFIG_KM_PHRAM - CONFIG_KM_PNVRAM; - env_set_hex("pnvramaddr", pnvramaddr); + sprintf(envval, "0x%x", pnvramaddr); + env_set("pnvramaddr", envval); /* try to read rootfssize (ram image) from environment */ p = env_get("rootfssize"); @@ -64,9 +66,12 @@ int set_km_env(void) varaddr = CONFIG_SYS_SDRAM_BASE + gd->ram_size - CONFIG_KM_RESERVED_PRAM - CONFIG_KM_PHRAM; env_set_hex("varaddr", varaddr); + sprintf(envval, "0x%x", varaddr); + env_set("varaddr", envval); kernelmem = gd->ram_size - 0x400 * pram; - env_set_hex("kernelmem", kernelmem); + sprintf(envval, "0x%x", kernelmem); + env_set("kernelmem", envval); return 0; } -- cgit v1.1 From 50dae8eb3a442cf9f98e78e24e52aa2f0acc3f56 Mon Sep 17 00:00:00 2001 From: Aleksandar Gerasimovski Date: Fri, 4 Jun 2021 13:40:58 +0000 Subject: net: tsec: add option to set device max-speed via dts Current tsec adapter sets adapter gigabit capabilities by default, and in reality this must not always be the case. It is possible that tsec adapter is used for 100Mbps connection, and in this case setting 1000Mbps capabilities can lead to some side effects such longer autoneg process. In our ls102x designs this problem leads to long autoneg times (> 4 sec) in case board rgmii link is 100Mbps capable only. Limiting the rgmii link capabilities provides faster and smoother link establishment. Signed-off-by: Aleksandar Gerasimovski Reviewed-by: Vladimir Oltean Reviewed-by: Bin Meng Reviewed-by: Priyanka Jain --- drivers/net/tsec.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c index c68e4b7..ee820aa 100644 --- a/drivers/net/tsec.c +++ b/drivers/net/tsec.c @@ -828,6 +828,7 @@ int tsec_probe(struct udevice *dev) const char *phy_mode; ofnode parent, child; fdt_addr_t reg; + u32 max_speed; int ret; data = (struct tsec_data *)dev_get_driver_data(dev); @@ -893,8 +894,12 @@ int tsec_probe(struct udevice *dev) } priv->interface = pdata->phy_interface; + /* Check for speed limit, default is 1000Mbps */ + max_speed = dev_read_u32_default(dev, "max-speed", 1000); + /* Initialize flags */ - priv->flags = TSEC_GIGABIT; + if (max_speed == 1000) + priv->flags = TSEC_GIGABIT; if (priv->interface == PHY_INTERFACE_MODE_SGMII) priv->flags |= TSEC_SGMII; -- cgit v1.1 From fb6c96f14ea711a8d3c013142def8bc52f562576 Mon Sep 17 00:00:00 2001 From: Lasse Klok Mikkelsen Date: Tue, 8 Jun 2021 08:39:12 +0200 Subject: arm: dts: ls1021a.dtsi: Fix invalid reg on gpio nodes Address and size cells on SOC are set to 1. But gpio nodes are specified with 2 cells. This fixes the gpio nodes to correct cells. Signed-off-by: Lasse Klok Mikkelsen Reviewed-by: Rasmus Villemoes Reviewed-by: Priyanka Jain --- arch/arm/dts/ls1021a.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/dts/ls1021a.dtsi b/arch/arm/dts/ls1021a.dtsi index 7b99ce0..7ba2dd2 100644 --- a/arch/arm/dts/ls1021a.dtsi +++ b/arch/arm/dts/ls1021a.dtsi @@ -100,7 +100,7 @@ gpio0: gpio@2300000 { compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio"; - reg = <0x0 0x2300000 0x0 0x10000>; + reg = <0x2300000 0x10000>; interrupts = ; gpio-controller; #gpio-cells = <2>; @@ -110,7 +110,7 @@ gpio1: gpio@2310000 { compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio"; - reg = <0x0 0x2310000 0x0 0x10000>; + reg = <0x2310000 0x10000>; interrupts = ; gpio-controller; #gpio-cells = <2>; @@ -120,7 +120,7 @@ gpio2: gpio@2320000 { compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio"; - reg = <0x0 0x2320000 0x0 0x10000>; + reg = <0x2320000 0x10000>; interrupts = ; gpio-controller; #gpio-cells = <2>; @@ -130,7 +130,7 @@ gpio3: gpio@2330000 { compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio"; - reg = <0x0 0x2330000 0x0 0x10000>; + reg = <0x2330000 0x10000>; interrupts = ; gpio-controller; #gpio-cells = <2>; -- cgit v1.1 From 0eb946ec28251272f297fcec566b9392bdad2ec6 Mon Sep 17 00:00:00 2001 From: Priyanka Jain Date: Tue, 8 Jun 2021 13:36:58 +0530 Subject: board: freescale: t4rdb: Add MAINTAINER Add "Priyanka Jain " as MAINTAINER for t4rdb board. Signed-off-by: Priyanka Jain --- board/freescale/t4rdb/MAINTAINERS | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/freescale/t4rdb/MAINTAINERS b/board/freescale/t4rdb/MAINTAINERS index 4ba5c3a..7380408 100644 --- a/board/freescale/t4rdb/MAINTAINERS +++ b/board/freescale/t4rdb/MAINTAINERS @@ -1,6 +1,6 @@ T4RDB BOARD -#M: Chunhe Lan -S: Orphan (since 2018-05) +M: Priyanka Jain +S: Maintained F: board/freescale/t4rdb/ F: include/configs/T4240RDB.h F: configs/T4160RDB_defconfig -- cgit v1.1 From 6d1657b998f761ecdac50a259f61f554a6337a58 Mon Sep 17 00:00:00 2001 From: Priyanka Jain Date: Tue, 8 Jun 2021 13:36:59 +0530 Subject: board: freescale: p1_p2_rdb_pc: Add MAINTAINER Add "Priyanka Jain " as MAINTAINER for p1_p2_rdb_pc board. Signed-off-by: Priyanka Jain --- board/freescale/p1_p2_rdb_pc/MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/freescale/p1_p2_rdb_pc/MAINTAINERS b/board/freescale/p1_p2_rdb_pc/MAINTAINERS index b737b09..0004d71 100644 --- a/board/freescale/p1_p2_rdb_pc/MAINTAINERS +++ b/board/freescale/p1_p2_rdb_pc/MAINTAINERS @@ -1,5 +1,5 @@ P1_P2_RDB_PC BOARD -#M: - +M: Priyanka Jain S: Maintained F: board/freescale/p1_p2_rdb_pc/ F: include/configs/p1_p2_rdb_pc.h -- cgit v1.1 From eccf98f8d85d4c4928b8e5656124b2527ba259d1 Mon Sep 17 00:00:00 2001 From: Priyanka Jain Date: Tue, 8 Jun 2021 13:37:00 +0530 Subject: board: freescale: p2041rdb: Add MAINTAINER Add "Priyanka Jain " as MAINTAINER for p2041rdb board. Signed-off-by: Priyanka Jain --- board/freescale/p2041rdb/MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/freescale/p2041rdb/MAINTAINERS b/board/freescale/p2041rdb/MAINTAINERS index d93cb0b..2121243 100644 --- a/board/freescale/p2041rdb/MAINTAINERS +++ b/board/freescale/p2041rdb/MAINTAINERS @@ -1,5 +1,5 @@ P2041RDB BOARD -#M: - +M: Priyanka Jain S: Maintained F: board/freescale/p2041rdb/ F: include/configs/P2041RDB.h -- cgit v1.1 From 0b036d4c1b685aa73b58167e942dc6bff43e3a10 Mon Sep 17 00:00:00 2001 From: Priyanka Jain Date: Tue, 8 Jun 2021 13:37:01 +0530 Subject: board: freescale: t102xrdb: Add MAINTAINER Add "Priyanka Jain " as MAINTAINER for t102xrdb board. Signed-off-by: Priyanka Jain --- board/freescale/t102xrdb/MAINTAINERS | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/freescale/t102xrdb/MAINTAINERS b/board/freescale/t102xrdb/MAINTAINERS index ebb17b8..471ea07 100644 --- a/board/freescale/t102xrdb/MAINTAINERS +++ b/board/freescale/t102xrdb/MAINTAINERS @@ -1,6 +1,6 @@ T102XRDB BOARD -#M: Shengzhou Liu -S: Orphan (since 2018-05) +M: Priyanka Jain +S: Maintained F: board/freescale/t102xrdb/ F: include/configs/T102xRDB.h F: configs/T1024RDB_defconfig -- cgit v1.1 From a7fd6fa1c277ed667d61de4e366fe034def4800a Mon Sep 17 00:00:00 2001 From: Aleksandar Gerasimovski Date: Tue, 8 Jun 2021 14:16:28 +0000 Subject: board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung Signed-off-by: Aleksandar Gerasimovski [Fixed new line error at EOF] Signed-off-by: Priyanka Jain --- arch/arm/Kconfig | 18 ++++ arch/arm/dts/Makefile | 1 + arch/arm/dts/ls1021a-pg-wcom-expu1.dts | 130 ++++++++++++++++++++++++ board/keymile/Kconfig | 7 ++ board/keymile/pg-wcom-ls102xa/Kconfig | 20 ++++ board/keymile/pg-wcom-ls102xa/MAINTAINERS | 3 + board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c | 29 ++++-- configs/pg_wcom_expu1_defconfig | 70 +++++++++++++ include/configs/pg-wcom-expu1.h | 53 ++++++++++ 9 files changed, 323 insertions(+), 8 deletions(-) create mode 100644 arch/arm/dts/ls1021a-pg-wcom-expu1.dts create mode 100644 configs/pg_wcom_expu1_defconfig create mode 100644 include/configs/pg-wcom-expu1.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 31d687e..c3e8bd7 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1491,6 +1491,24 @@ config TARGET_PG_WCOM_SELI8 SELI8 is a QorIQ LS1021a based service unit card used in XMC20 and FOX615 product families. +config TARGET_PG_WCOM_EXPU1 + bool "Support Hitachi-Powergrids EXPU1 service unit card" + select ARCH_LS1021A + select ARCH_SUPPORT_PSCI + select BOARD_EARLY_INIT_F + select BOARD_LATE_INIT + select CPU_V7A + select CPU_V7_HAS_NONSEC + select CPU_V7_HAS_VIRT + select SYS_FSL_DDR + select FSL_DDR_INTERACTIVE + select VENDOR_KM + imply SCSI + help + Support for Hitachi-Powergrids EXPU1 service unit card. + EXPU1 is a QorIQ LS1021a based service unit card used + in XMC20 and FOX615 product families. + config TARGET_LS1021ATSN bool "Support ls1021atsn" select ARCH_LS1021A diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 0960682..0d14394 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -411,6 +411,7 @@ dtb-$(CONFIG_ARCH_LS1021A) += ls1021a-qds-duart.dtb \ ls1021a-twr-duart.dtb ls1021a-twr-lpuart.dtb \ ls1021a-iot-duart.dtb ls1021a-tsn.dtb dtb-$(CONFIG_TARGET_PG_WCOM_SELI8) += ls1021a-pg-wcom-seli8.dtb +dtb-$(CONFIG_TARGET_PG_WCOM_EXPU1) += ls1021a-pg-wcom-expu1.dtb dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \ fsl-ls2080a-qds-42-x.dtb \ diff --git a/arch/arm/dts/ls1021a-pg-wcom-expu1.dts b/arch/arm/dts/ls1021a-pg-wcom-expu1.dts new file mode 100644 index 0000000..33456b7 --- /dev/null +++ b/arch/arm/dts/ls1021a-pg-wcom-expu1.dts @@ -0,0 +1,130 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Hitachi ABB Power Grids EXPU1 board device tree source + * + * Copyright 2020 Hitachi ABB Power Grids + * + * Copyright 2013-2015 Freescale Semiconductor, Inc. + */ + +/dts-v1/; +#include "ls1021a.dtsi" + +/ { + model = "EXPU1 Service Unit for XMC and FOX"; + + aliases { + enet2-rgmii-debug-phy = &debug_phy; + }; + + chosen { + stdout-path = &uart0; + }; +}; + +&enet0 { + status = "okay"; + tbi-handle = <&tbi0>; + phy-connection-type = "sgmii"; + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&enet1 { + status = "okay"; + tbi-handle = <&tbi1>; + phy-connection-type = "sgmii"; + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&enet2 { + phy-handle = <&debug_phy>; + phy-connection-type = "rgmii-id"; + max-speed = <100>; + status = "okay"; +}; + +&i2c0 { + status = "okay"; +}; + +&dspi1 { + bus-num = <0>; + status = "okay"; + zl30343@0 { + compatible = "gen,spidev", "zarlink,zl30343"; + reg = <0>; + spi-max-frequency = <8000000>; + }; +}; + +&ifc { + #address-cells = <2>; + #size-cells = <1>; + /* NOR Flash on board */ + ranges = <0x0 0x0 0x60000000 0x04000000>; + status = "okay"; + + nor@0,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "cfi-flash"; + reg = <0x0 0x0 0x4000000>; + bank-width = <2>; + device-width = <1>; + + partition@0 { + label = "rcw"; + reg = <0x0 0x20000>; + read-only; + }; + partition@20000 { + label = "qe"; + reg = <0x20000 0x20000>; + }; + /* ZL30343 init data to be added here */ + partition@40000 { + label = "envred"; + reg = <0x40000 0x20000>; + }; + partition@60000 { + label = "env"; + reg = <0x60000 0x20000>; + }; + partition@100000 { + label = "u-boot"; + reg = <0x100000 0x100000>; + }; + partition@200000 { + label = "ubi0"; + reg = <0x200000 0x3E00000>; + }; + }; +}; + +&mdio0 { + debug_phy: ethernet-phy@11 { + reg = <0x11>; + }; + + tbi0: tbi-phy@0xb { + reg = <0xb>; + device_type = "tbi-phy"; + }; +}; + +&mdio1 { + tbi1: tbi-phy@0xd { + reg = <0xd>; + device_type = "tbi-phy"; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/board/keymile/Kconfig b/board/keymile/Kconfig index 86a6670..3a6c63b 100644 --- a/board/keymile/Kconfig +++ b/board/keymile/Kconfig @@ -64,6 +64,13 @@ config SYS_PAX_BASE help IFC Base Address for PAXx FPGA. +config SYS_CLIPS_BASE + hex "CLIPS IFC Base Address" + default 0x78000000 + depends on ARCH_LS1021A + help + IFC Base Address for CLIPS FPGA. + config KM_CONSOLE_TTY string "KM Console" default "ttyS0" diff --git a/board/keymile/pg-wcom-ls102xa/Kconfig b/board/keymile/pg-wcom-ls102xa/Kconfig index 15c009d..f0b5cea 100644 --- a/board/keymile/pg-wcom-ls102xa/Kconfig +++ b/board/keymile/pg-wcom-ls102xa/Kconfig @@ -17,3 +17,23 @@ config BOARD_SPECIFIC_OPTIONS imply FS_CRAMFS endif + +if TARGET_PG_WCOM_EXPU1 + +config SYS_BOARD + default "pg-wcom-ls102xa" + +config SYS_VENDOR + default "keymile" + +config SYS_SOC + default "ls102xa" + +config SYS_CONFIG_NAME + default "pg-wcom-expu1" + +config BOARD_SPECIFIC_OPTIONS + def_bool y + imply FS_CRAMFS + +endif diff --git a/board/keymile/pg-wcom-ls102xa/MAINTAINERS b/board/keymile/pg-wcom-ls102xa/MAINTAINERS index e1bc90a..26b2023 100644 --- a/board/keymile/pg-wcom-ls102xa/MAINTAINERS +++ b/board/keymile/pg-wcom-ls102xa/MAINTAINERS @@ -6,5 +6,8 @@ S: Maintained F: board/keymile/pg-wcom-ls102xa/ F: include/configs/km/pg-wcom-ls102xa.h F: include/configs/pg-wcom-seli8.h +F: include/configs/pg-wcom-expu1.h F: configs/pg_wcom_seli8_defconfig +F: configs/pg_wcom_expu1_defconfig F: arch/arm/dts/ls1021a-pg-wcom-seli8.dts +F: arch/arm/dts/ls1021a-pg-wcom-expu1.dts diff --git a/board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c b/board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c index 6b0e963..69b5d21 100644 --- a/board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c +++ b/board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c @@ -70,16 +70,29 @@ int board_early_init_f(void) /* QRIO Configuration */ qrio_uprstreq(UPREQ_CORE_RST); - if (IS_ENABLED(CONFIG_TARGET_PG_WCOM_SELI8)) { - qrio_prstcfg(KM_LIU_RST, PRSTCFG_POWUP_UNIT_RST); - qrio_wdmask(KM_LIU_RST, true); +#if CONFIG_IS_ENABLED(TARGET_PG_WCOM_SELI8) + qrio_prstcfg(KM_LIU_RST, PRSTCFG_POWUP_UNIT_RST); + qrio_wdmask(KM_LIU_RST, true); - qrio_prstcfg(KM_PAXK_RST, PRSTCFG_POWUP_UNIT_RST); - qrio_wdmask(KM_PAXK_RST, true); + qrio_prstcfg(KM_PAXK_RST, PRSTCFG_POWUP_UNIT_RST); + qrio_wdmask(KM_PAXK_RST, true); +#endif - qrio_prstcfg(KM_DBG_ETH_RST, PRSTCFG_POWUP_UNIT_CORE_RST); - qrio_prst(KM_DBG_ETH_RST, false, false); - } +#if CONFIG_IS_ENABLED(TARGET_PG_WCOM_EXPU1) + qrio_prstcfg(WCOM_TMG_RST, PRSTCFG_POWUP_UNIT_RST); + qrio_wdmask(WCOM_TMG_RST, true); + + qrio_prstcfg(WCOM_PHY_RST, PRSTCFG_POWUP_UNIT_RST); + qrio_prst(WCOM_PHY_RST, false, false); + + qrio_prstcfg(WCOM_QSFP_RST, PRSTCFG_POWUP_UNIT_RST); + qrio_wdmask(WCOM_QSFP_RST, true); + + qrio_prstcfg(WCOM_CLIPS_RST, PRSTCFG_POWUP_UNIT_RST); + qrio_prst(WCOM_CLIPS_RST, false, false); +#endif + qrio_prstcfg(KM_DBG_ETH_RST, PRSTCFG_POWUP_UNIT_CORE_RST); + qrio_prst(KM_DBG_ETH_RST, false, false); i2c_deblock_gpio_cfg(); diff --git a/configs/pg_wcom_expu1_defconfig b/configs/pg_wcom_expu1_defconfig new file mode 100644 index 0000000..65ab4fb --- /dev/null +++ b/configs/pg_wcom_expu1_defconfig @@ -0,0 +1,70 @@ +CONFIG_ARM=y +CONFIG_TARGET_PG_WCOM_EXPU1=y +CONFIG_SYS_TEXT_BASE=0x60100000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_KM_DEF_NETDEV="eth2" +CONFIG_KM_COMMON_ETH_INIT=y +CONFIG_PIGGY_MAC_ADDRESS_OFFSET=3 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff +CONFIG_ENV_SIZE=0x4000 +CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_BOOTCOUNT_BOOTLIMIT=3 +CONFIG_SYS_BOOTCOUNT_ADDR=0x70000020 +CONFIG_DEFAULT_DEVICE_TREE="ls1021a-pg-wcom-expu1" +CONFIG_AHCI=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_BOOTDELAY=3 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0" +CONFIG_SILENT_CONSOLE=y +CONFIG_MISC_INIT_R=y +CONFIG_LAST_STAGE_INIT=y +CONFIG_CMD_IMLS=y +CONFIG_CMD_GREPENV=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_NAND=y +CONFIG_CMD_NAND_TRIMFFS=y +CONFIG_CMD_CRAMFS=y +CONFIG_CMD_MTDPARTS=y +CONFIG_MTDIDS_DEFAULT="nor0=60000000.nor,nand0=68000000.flash" +CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:128k(rcw),128k(qe),128k(envred),128k(env),512k(res),1m(u-boot),-(ubi0);68000000.flash:-(ubi1)" +CONFIG_CMD_UBI=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_IS_IN_FLASH=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_ADDR=0x60060000 +CONFIG_ENV_ADDR_REDUND=0x60040000 +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_DM=y +CONFIG_BOOTCOUNT_LIMIT=y +CONFIG_SYS_FSL_DDR3=y +# CONFIG_MMC is not set +CONFIG_SYS_I2C_MXC=y +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_MTD=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_CFI_DRIVER=y +CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y +CONFIG_FLASH_CFI_MTD=y +CONFIG_SYS_FLASH_CFI=y +CONFIG_MTD_RAW_NAND=y +CONFIG_PHY_MARVELL=y +CONFIG_PHY_FIXED=y +CONFIG_DM_ETH=y +CONFIG_DM_MDIO=y +CONFIG_PHY_GIGE=y +CONFIG_MII=y +CONFIG_TSEC_ENET=y +CONFIG_SPECIFY_CONSOLE_INDEX=y +CONFIG_DM_SERIAL=y +CONFIG_SYS_NS16550=y diff --git a/include/configs/pg-wcom-expu1.h b/include/configs/pg-wcom-expu1.h new file mode 100644 index 0000000..e08d941 --- /dev/null +++ b/include/configs/pg-wcom-expu1.h @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2020 Hitachi ABB Power Grids + */ + +#ifndef __CONFIG_PG_WCOM_EXPU1_H +#define __CONFIG_PG_WCOM_EXPU1_H + +#define WCOM_EXPU1 +#define CONFIG_HOSTNAME "EXPU1" + +#define CONFIG_KM_UBI_PARTITION_NAME_BOOT "ubi0" +#define CONFIG_KM_UBI_PARTITION_NAME_APP "ubi1" + +/* CLIPS FPGA Definitions */ +#define CONFIG_SYS_CSPR3_EXT (0x00) +#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CLIPS_BASE) | \ + CSPR_PORT_SIZE_8 | \ + CSPR_MSEL_GPCM | \ + CSPR_V) +#define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024) +#define CONFIG_SYS_CSOR3 (CSOR_GPCM_ADM_SHIFT(0x4) | \ + CSOR_GPCM_TRHZ_40) +#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x6) | \ + FTIM0_GPCM_TEADC(0x7) | \ + FTIM0_GPCM_TEAHC(0x2)) +#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x2) | \ + FTIM1_GPCM_TRAD(0x12)) +#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x3) | \ + FTIM2_GPCM_TCH(0x1) | \ + FTIM2_GPCM_TWP(0x12)) +#define CONFIG_SYS_CS3_FTIM3 0x04000000 + +/* PRST */ +#define WCOM_CLIPS_RST 0 +#define WCOM_QSFP_RST 1 +#define WCOM_PHY_RST 2 +#define WCOM_TMG_RST 3 +#define KM_DBG_ETH_RST 15 + +/* QRIO GPIOs used for deblocking */ +#define KM_I2C_DEBLOCK_PORT QRIO_GPIO_A +#define KM_I2C_DEBLOCK_SCL 20 +#define KM_I2C_DEBLOCK_SDA 21 + +/* ZL30343 on SPI */ +#define WCOM_ZL30343_CFG_ADDR 0xe8070000 +#define WCOM_ZL30343_SPI_BUS 0 +#define WCOM_ZL30343_CS 0 + +#include "km/pg-wcom-ls102xa.h" + +#endif /* __CONFIG_PG_WCOM_EXPU1_H */ -- cgit v1.1 From 3aea3ddf21a29145176189b55eca7a833b8f7a4d Mon Sep 17 00:00:00 2001 From: Aleksandar Gerasimovski Date: Tue, 8 Jun 2021 14:17:34 +0000 Subject: km/ls102xa: add support for u-boot POST memory test MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski Reviewed-by: Priyanka Jain --- board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c | 34 +++++++++++++++++++++++++ include/configs/km/pg-wcom-ls102xa.h | 4 +++ 2 files changed, 38 insertions(+) diff --git a/board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c b/board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c index 69b5d21..97915f9 100644 --- a/board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c +++ b/board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c @@ -141,6 +141,40 @@ int ft_board_setup(void *blob, struct bd_info *bd) return 0; } +#if defined(CONFIG_POST) +int post_hotkeys_pressed(void) +{ + /* DIC26_SELFTEST: GPRTA0, GPA0 */ + qrio_gpio_direction_input(QRIO_GPIO_A, 0); + return qrio_get_gpio(QRIO_GPIO_A, 0); +} + +ulong post_word_load(void) +{ + /* POST word is located at the beginning of reserved physical RAM */ + void *addr = (void *)(CONFIG_SYS_SDRAM_BASE + + gd->ram_size - CONFIG_KM_RESERVED_PRAM + 8); + return in_le32(addr); +} + +void post_word_store(ulong value) +{ + /* POST word is located at the beginning of reserved physical RAM */ + void *addr = (void *)(CONFIG_SYS_SDRAM_BASE + + gd->ram_size - CONFIG_KM_RESERVED_PRAM + 8); + out_le32(addr, value); +} + +int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset) +{ + /* Define only 1MiB range for mem_regions at the middle of the RAM */ + /* For 1GiB range mem_regions takes approx. 4min */ + *vstart = CONFIG_SYS_SDRAM_BASE + (gd->ram_size >> 1); + *size = 1 << 20; + return 0; +} +#endif + u8 flash_read8(void *addr) { return __raw_readb(addr + 1); diff --git a/include/configs/km/pg-wcom-ls102xa.h b/include/configs/km/pg-wcom-ls102xa.h index 3d7519c..35bfa45 100644 --- a/include/configs/km/pg-wcom-ls102xa.h +++ b/include/configs/km/pg-wcom-ls102xa.h @@ -43,6 +43,10 @@ #define CONFIG_SYS_SPD_BUS_NUM 0 #define SPD_EEPROM_ADDRESS 0x54 +/* POST memory regions test */ +#define CONFIG_POST (CONFIG_SYS_POST_MEM_REGIONS) +#define CONFIG_POST_EXTERNAL_WORD_FUNCS + /* * IFC Definitions */ -- cgit v1.1 From a09806498c2dcaf02a8f2fd41ab3bb595fc13ca4 Mon Sep 17 00:00:00 2001 From: Aleksandar Gerasimovski Date: Tue, 8 Jun 2021 14:19:08 +0000 Subject: km: ls102xa: add missing define for PRAM regions In our designs we reserve PRAM area at the end of the RAM, and in order this area to be visible and taken into account by the u-boot memory mgmt CONFIG_PRAM has to be defined. Signed-off-by: Aleksandar Gerasimovski Reviewed-by: Priyanka Jain --- include/configs/km/pg-wcom-ls102xa.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/configs/km/pg-wcom-ls102xa.h b/include/configs/km/pg-wcom-ls102xa.h index 35bfa45..1e06a5b 100644 --- a/include/configs/km/pg-wcom-ls102xa.h +++ b/include/configs/km/pg-wcom-ls102xa.h @@ -21,6 +21,10 @@ #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE +#define CONFIG_PRAM ((CONFIG_KM_PNVRAM + \ + CONFIG_KM_PHRAM + \ + CONFIG_KM_RESERVED_PRAM) >> 10) + #define CONFIG_SYS_CLK_FREQ 66666666 /* * Take into account default implementation where DDR_FDBK_MULTI is consider as -- cgit v1.1 From fbb0e15a42e816e4b81b96d5c4d1303584afe1c0 Mon Sep 17 00:00:00 2001 From: Aleksandar Gerasimovski Date: Tue, 8 Jun 2021 14:20:13 +0000 Subject: km/scripts: fix saveenv command syntax This is most probably a typo, and in older u-uboot versions is same as 'saveenv', in the newer uboot versions there is a separate 'save' command that is different from 'saveenv'. Signed-off-by: Aleksandar Gerasimovski Reviewed-by: Priyanka Jain --- board/keymile/scripts/ramfs-common.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/keymile/scripts/ramfs-common.txt b/board/keymile/scripts/ramfs-common.txt index e590a2b..0a4a9c8 100644 --- a/board/keymile/scripts/ramfs-common.txt +++ b/board/keymile/scripts/ramfs-common.txt @@ -3,7 +3,7 @@ boot_bank=-1 altbootcmd=run ${subbootcmds} bootcmd=run ${subbootcmds} subbootcmds=save_and_reset_once tftpfdt tftpkernel setrootfsaddr tftpramfs flashargs add_default addpanic addramfs boot -save_and_reset_once=setenv save_and_reset_once true && save && reset +save_and_reset_once=setenv save_and_reset_once true && saveenv && reset nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} configure=run set_uimage; run set_tftppath; km_setboardid && run try_import_rootfssize && saveenv && reset setrootfsaddr=setexpr value ${pnvramaddr} - ${rootfssize} && setenv rootfsaddr 0x${value} -- cgit v1.1 From fd49502d0fe30ff5f7d63b572eb8871d013ebec6 Mon Sep 17 00:00:00 2001 From: Aleksandar Gerasimovski Date: Tue, 8 Jun 2021 14:21:15 +0000 Subject: km: ls102x: set ethrotate envvar to no MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The default behavior in the latest u-boot revisions is to rotate the active net device to the next available if the requested link is not established. For our ls102x based devices this would mean that if active debug net device is not available, u-boot will rotate and set the next net device that is one of the estar adapters. To return from this situation manual action to set correct ethact adapter will be needed and this can be annoying when working in debug mode. Setting ethrotate=no will disable net adapter rotation and will make sure that the primary adapter is always used. Signed-off-by: Aleksandar Gerasimovski Reviewed-by: Priyanka Jain --- include/configs/km/pg-wcom-ls102xa.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/km/pg-wcom-ls102xa.h b/include/configs/km/pg-wcom-ls102xa.h index 1e06a5b..644da3b 100644 --- a/include/configs/km/pg-wcom-ls102xa.h +++ b/include/configs/km/pg-wcom-ls102xa.h @@ -292,6 +292,7 @@ CONFIG_KM_NEW_ENV \ CONFIG_KM_DEF_ENV \ "EEprom_ivm=pca9547:70:9\0" \ + "ethrotate=no\0" \ "" #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ -- cgit v1.1 From ccbd2ced73d1ad310c34e75dca3ce30f1d515c85 Mon Sep 17 00:00:00 2001 From: Aleksandar Gerasimovski Date: Tue, 8 Jun 2021 14:23:34 +0000 Subject: km: ls102x: update device disable configuration acc hw design desc In order to improve power consumption ls102x allows to disable peripherals that are not in use. This patch follows SELI8 HW design description and disables peripherals that are not in use in our designs, the same configuration is applicable and for EXPU1. This patch uses available hwconfig option for updating ls102x device disable configuration. Signed-off-by: Aleksandar Gerasimovski Reviewed-by: Priyanka Jain --- include/configs/km/pg-wcom-ls102xa.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/include/configs/km/pg-wcom-ls102xa.h b/include/configs/km/pg-wcom-ls102xa.h index 644da3b..e337b92 100644 --- a/include/configs/km/pg-wcom-ls102xa.h +++ b/include/configs/km/pg-wcom-ls102xa.h @@ -288,9 +288,15 @@ "protect on " __stringify(ENV_DEL_ADDR) \ " +" __stringify(CONFIG_ENV_TOTAL_SIZE) "\0" +#define CONFIG_HW_ENV_SETTINGS \ + "hwconfig=devdis:esdhc,usb3,usb2,sata,sec,dcu,duart2,qspi," \ + "can1,can2_4,ftm2_8,i2c2_3,sai1_4,lpuart2_6," \ + "asrc,spdif,lpuart1,ftm1\0" + #define CONFIG_EXTRA_ENV_SETTINGS \ CONFIG_KM_NEW_ENV \ CONFIG_KM_DEF_ENV \ + CONFIG_HW_ENV_SETTINGS \ "EEprom_ivm=pca9547:70:9\0" \ "ethrotate=no\0" \ "" -- cgit v1.1 From 02802eb89e85696d9cd2276c2842255d5ad7edf6 Mon Sep 17 00:00:00 2001 From: Aleksandar Gerasimovski Date: Tue, 8 Jun 2021 14:24:32 +0000 Subject: pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung Signed-off-by: Aleksandar Gerasimovski Reviewed-by: Priyanka Jain --- board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c b/board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c index 97915f9..db49e8f 100644 --- a/board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c +++ b/board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c @@ -96,6 +96,12 @@ int board_early_init_f(void) i2c_deblock_gpio_cfg(); + /* enable the Unit LED (red) & Boot LED (on) */ + qrio_set_leds(); + + /* enable Application Buffer */ + qrio_enable_app_buffer(); + arch_soc_init(); return 0; -- cgit v1.1 From 11eeeef7b02ad276c7593ef0f280dff477e8ba7b Mon Sep 17 00:00:00 2001 From: Aleksandar Gerasimovski Date: Tue, 8 Jun 2021 14:25:21 +0000 Subject: pg-wcom-ls102xa: fix sys counter frequency A system clock of 66MHz was chosen for the pg-wcom-ls102xa. Compared to the Evalboard, this corresponds to a reduction of 1/3. The system counter clock should have been reduced accordingly, but that was not the case, so we had a system time that was 1/3 behind the real time. This patch corrects the system counter clock to 8.333MHz = 66.667MHz / 8. Signed-off-by: Rainer Boschung Signed-off-by: Aleksandar Gerasimovski Reviewed-by: Priyanka Jain --- include/configs/km/pg-wcom-ls102xa.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/km/pg-wcom-ls102xa.h b/include/configs/km/pg-wcom-ls102xa.h index e337b92..eb480a3 100644 --- a/include/configs/km/pg-wcom-ls102xa.h +++ b/include/configs/km/pg-wcom-ls102xa.h @@ -214,7 +214,7 @@ #define CONFIG_LAYERSCAPE_NS_ACCESS #define CONFIG_SMP_PEN_ADDR 0x01ee0200 -#define COUNTER_FREQUENCY 12500000 +#define COUNTER_FREQUENCY 8333333 #define CONFIG_HWCONFIG #define HWCONFIG_BUFFER_SIZE 256 -- cgit v1.1 From a484f7c4869723451c1ca98e8b2e9dbee0e8ff16 Mon Sep 17 00:00:00 2001 From: Camelia Groza Date: Fri, 11 Jun 2021 15:28:05 +0300 Subject: board: freescale: t208xrdb: remove the legacy non-DM_ETH code Both DM_ETH and DM_PCI are enabled for the T2080RDB board. Remove the board_eth_init() callback and the non-DM_ETH code paths since they are not needed anymore. Signed-off-by: Camelia Groza Reviewed-by: Tom Rini Reviewed-by: Priyanka Jain --- board/freescale/t208xrdb/eth_t208xrdb.c | 79 --------------------------------- board/freescale/t208xrdb/t208xrdb.c | 4 -- 2 files changed, 83 deletions(-) diff --git a/board/freescale/t208xrdb/eth_t208xrdb.c b/board/freescale/t208xrdb/eth_t208xrdb.c index b0ff4b1..4b44b16 100644 --- a/board/freescale/t208xrdb/eth_t208xrdb.c +++ b/board/freescale/t208xrdb/eth_t208xrdb.c @@ -26,85 +26,6 @@ #include #include -int board_eth_init(struct bd_info *bis) -{ -#if defined(CONFIG_FMAN_ENET) - int i, interface; - struct memac_mdio_info dtsec_mdio_info; - struct memac_mdio_info tgec_mdio_info; - struct mii_dev *dev; - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - u32 srds_s1; - - srds_s1 = in_be32(&gur->rcwsr[4]) & - FSL_CORENET2_RCWSR4_SRDS1_PRTCL; - srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; - - dtsec_mdio_info.regs = - (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR; - - dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; - - /* Register the 1G MDIO bus */ - fm_memac_mdio_init(bis, &dtsec_mdio_info); - - tgec_mdio_info.regs = - (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR; - tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; - - /* Register the 10G MDIO bus */ - fm_memac_mdio_init(bis, &tgec_mdio_info); - - /* Set the two on-board RGMII PHY address */ - fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR); - fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR); - - switch (srds_s1) { - case 0x66: - case 0x6b: - fm_info_set_phy_address(FM1_10GEC1, CORTINA_PHY_ADDR1); - fm_info_set_phy_address(FM1_10GEC2, CORTINA_PHY_ADDR2); - fm_info_set_phy_address(FM1_10GEC3, FM1_10GEC3_PHY_ADDR); - fm_info_set_phy_address(FM1_10GEC4, FM1_10GEC4_PHY_ADDR); - break; - default: - printf("SerDes1 protocol 0x%x is not supported on T208xRDB\n", - srds_s1); - break; - } - - for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { - interface = fm_info_get_enet_if(i); - switch (interface) { - case PHY_INTERFACE_MODE_RGMII: - case PHY_INTERFACE_MODE_RGMII_TXID: - case PHY_INTERFACE_MODE_RGMII_RXID: - case PHY_INTERFACE_MODE_RGMII_ID: - dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); - fm_info_set_mdio(i, dev); - break; - default: - break; - } - } - - for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) { - switch (fm_info_get_enet_if(i)) { - case PHY_INTERFACE_MODE_XGMII: - dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); - fm_info_set_mdio(i, dev); - break; - default: - break; - } - } - - cpu_eth_init(bis); -#endif /* CONFIG_FMAN_ENET */ - - return pci_eth_init(bis); -} - /* Disable the MAC5 and MAC6 "fsl,fman-memac" nodes and the two * "fsl,dpa-ethernet" nodes that reference them. */ diff --git a/board/freescale/t208xrdb/t208xrdb.c b/board/freescale/t208xrdb/t208xrdb.c index 7ccb205..35f5dff 100644 --- a/board/freescale/t208xrdb/t208xrdb.c +++ b/board/freescale/t208xrdb/t208xrdb.c @@ -136,11 +136,7 @@ int ft_board_setup(void *blob, struct bd_info *bd) fsl_fdt_fixup_dr_usb(blob, bd); #ifdef CONFIG_SYS_DPAA_FMAN -#ifndef CONFIG_DM_ETH - fdt_fixup_fman_ethernet(blob); -#else fdt_fixup_board_fman_ethernet(blob); -#endif fdt_fixup_board_enet(blob); #endif -- cgit v1.1 From c91b1305547ee72c0b0e5995c3b47d2b56ad698f Mon Sep 17 00:00:00 2001 From: Camelia Groza Date: Fri, 11 Jun 2021 15:28:06 +0300 Subject: board: freescale: t208xrdb: detect the board revision version Detect and print the board revision version based on the CPLD registers. Signed-off-by: Camelia Groza Reviewed-by: Priyanka Jain --- board/freescale/t208xrdb/t208xrdb.c | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/board/freescale/t208xrdb/t208xrdb.c b/board/freescale/t208xrdb/t208xrdb.c index 35f5dff..f7fa65d 100644 --- a/board/freescale/t208xrdb/t208xrdb.c +++ b/board/freescale/t208xrdb/t208xrdb.c @@ -27,14 +27,29 @@ DECLARE_GLOBAL_DATA_PTR; +u8 get_hw_revision(void) +{ + u8 ver = CPLD_READ(hw_ver); + + switch (ver) { + default: + case 0x1: + return 'C'; + case 0x0: + return 'D'; + case 0x2: + return 'E'; + } +} + int checkboard(void) { struct cpu_type *cpu = gd->arch.cpu; static const char *freq[3] = {"100.00MHZ", "125.00MHz", "156.25MHZ"}; printf("Board: %sRDB, ", cpu->name); - printf("Board rev: 0x%02x CPLD ver: 0x%02x, boot from ", - CPLD_READ(hw_ver), CPLD_READ(sw_ver)); + printf("Board rev: %c CPLD ver: 0x%02x, boot from ", + get_hw_revision(), CPLD_READ(sw_ver)); #ifdef CONFIG_SDCARD puts("SD/MMC\n"); -- cgit v1.1 From 4e21a555c1dc2eacee9e3ad07f3b112c20b0f7a2 Mon Sep 17 00:00:00 2001 From: Camelia Groza Date: Wed, 16 Jun 2021 17:47:31 +0530 Subject: board: freescale: t208xrdb: add Linux fdt fix-ups for rev D The T2080RDB boards revisions D and up have updated 10G Aquantia PHYs connected to MAC1 and MAC2. The second Aquantia PHY is located at a different address on the MDIO bus compared to rev C (0x8 instead of 0x1). Fix-up the Linux device tree to update the PHY address for the second Aquantia PHY on boards revisions D and up. Also rename the PHY node to reflect the changes. Signed-off-by: Camelia Groza [Rebased] Signed-off-by: Priyanka Jain --- board/freescale/t208xrdb/eth_t208xrdb.c | 35 +++++++++++++++++++++++++++++++++ board/freescale/t208xrdb/t208xrdb.c | 1 + board/freescale/t208xrdb/t208xrdb.h | 1 + include/configs/T208xRDB.h | 6 +++++- 4 files changed, 42 insertions(+), 1 deletion(-) diff --git a/board/freescale/t208xrdb/eth_t208xrdb.c b/board/freescale/t208xrdb/eth_t208xrdb.c index 4b44b16..e4592ea 100644 --- a/board/freescale/t208xrdb/eth_t208xrdb.c +++ b/board/freescale/t208xrdb/eth_t208xrdb.c @@ -26,6 +26,8 @@ #include #include +extern u8 get_hw_revision(void); + /* Disable the MAC5 and MAC6 "fsl,fman-memac" nodes and the two * "fsl,dpa-ethernet" nodes that reference them. */ @@ -60,6 +62,39 @@ void fdt_fixup_board_fman_ethernet(void *fdt) } } +/* Update the address of the second Aquantia PHY on boards revision D and up. + * Also rename the PHY node to align with the address change. + */ +void fdt_fixup_board_phy(void *fdt) +{ + const char phy_path[] = + "/soc@ffe000000/fman@400000/mdio@fd000/ethernet-phy@1"; + int ret, offset, new_addr = AQR113C_PHY_ADDR2; + char new_name[] = "ethernet-phy@00"; + + if (get_hw_revision() == 'C') + return; + + offset = fdt_path_offset(fdt, phy_path); + if (offset < 0) { + printf("ethernet-phy@1 node not found in the dts\n"); + return; + } + + ret = fdt_setprop(fdt, offset, "reg", &new_addr, sizeof(new_addr)); + if (ret < 0) { + printf("Unable to set 'reg' for node ethernet-phy@1: %s\n", + fdt_strerror(ret)); + return; + } + + sprintf(new_name, "ethernet-phy@%x", new_addr); + ret = fdt_set_name(fdt, offset, new_name); + if (ret < 0) + printf("Unable to rename node ethernet-phy@1: %s\n", + fdt_strerror(ret)); +} + void fdt_fixup_board_enet(void *fdt) { return; diff --git a/board/freescale/t208xrdb/t208xrdb.c b/board/freescale/t208xrdb/t208xrdb.c index f7fa65d..1f0cdee 100644 --- a/board/freescale/t208xrdb/t208xrdb.c +++ b/board/freescale/t208xrdb/t208xrdb.c @@ -153,6 +153,7 @@ int ft_board_setup(void *blob, struct bd_info *bd) #ifdef CONFIG_SYS_DPAA_FMAN fdt_fixup_board_fman_ethernet(blob); fdt_fixup_board_enet(blob); + fdt_fixup_board_phy(blob); #endif return 0; diff --git a/board/freescale/t208xrdb/t208xrdb.h b/board/freescale/t208xrdb/t208xrdb.h index cd0a9f4..edbc860 100644 --- a/board/freescale/t208xrdb/t208xrdb.h +++ b/board/freescale/t208xrdb/t208xrdb.h @@ -10,5 +10,6 @@ void fdt_fixup_board_enet(void *blob); void pci_of_setup(void *blob, struct bd_info *bd); void fdt_fixup_board_fman_ethernet(void *blob); +void fdt_fixup_board_phy(void *blob); #endif diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index b5197b3..9449e30 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -537,8 +537,12 @@ unsigned long get_board_ddr_clk(void); #define RGMII_PHY2_ADDR 0x02 #define CORTINA_PHY_ADDR1 0x0c /* Cortina CS4315 */ #define CORTINA_PHY_ADDR2 0x0d -#define FM1_10GEC3_PHY_ADDR 0x00 /* Aquantia AQ1202 10G Base-T */ +/* Aquantia AQ1202 10G Base-T used by board revisions up to C */ +#define FM1_10GEC3_PHY_ADDR 0x00 #define FM1_10GEC4_PHY_ADDR 0x01 +/* Aquantia AQR113C 10G Base-T used by board revisions D and up */ +#define AQR113C_PHY_ADDR1 0x00 +#define AQR113C_PHY_ADDR2 0x08 #endif #ifdef CONFIG_FMAN_ENET -- cgit v1.1 From 13ea307f799ba76164354325a0c76c11b7b9c494 Mon Sep 17 00:00:00 2001 From: Camelia Groza Date: Fri, 11 Jun 2021 15:28:08 +0300 Subject: board: freescale: t208xrdb: add a config option for rev D dts fixups Under DM, we rely on u-boot's device tree to provide the correct PHY addresses. The board_fix_fdt callback is intended to be used for device tree fixups before relocation. Unfortunately, this isn't an option when booting from flash since the device tree isn't writable before relocation. This patch introduces the CONFIG_T2080RDB_REV_D option to signal that a board revision D or up is the target. The config option is used to set the correct Aquantia PHY address in the board's u-boot device tree. Defconfig files with the option enable explicitly are added for convenience. Signed-off-by: Camelia Groza Reviewed-by: Priyanka Jain --- arch/powerpc/dts/t2080rdb.dts | 7 +++ board/freescale/t208xrdb/Kconfig | 4 ++ configs/T2080RDB_revD_NAND_defconfig | 93 ++++++++++++++++++++++++++++++++ configs/T2080RDB_revD_SDCARD_defconfig | 90 +++++++++++++++++++++++++++++++ configs/T2080RDB_revD_SPIFLASH_defconfig | 92 +++++++++++++++++++++++++++++++ configs/T2080RDB_revD_defconfig | 77 ++++++++++++++++++++++++++ 6 files changed, 363 insertions(+) create mode 100644 configs/T2080RDB_revD_NAND_defconfig create mode 100644 configs/T2080RDB_revD_SDCARD_defconfig create mode 100644 configs/T2080RDB_revD_SPIFLASH_defconfig create mode 100644 configs/T2080RDB_revD_defconfig diff --git a/arch/powerpc/dts/t2080rdb.dts b/arch/powerpc/dts/t2080rdb.dts index 25f8c97..4de814e 100644 --- a/arch/powerpc/dts/t2080rdb.dts +++ b/arch/powerpc/dts/t2080rdb.dts @@ -77,10 +77,17 @@ reg = <0x0>; }; +#ifdef CONFIG_T2080RDB_REV_D + xg_aq1202_phy4: ethernet-phy@8 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x8>; + }; +#else xg_aq1202_phy4: ethernet-phy@1 { compatible = "ethernet-phy-ieee802.3-c45"; reg = <0x1>; }; +#endif }; }; }; diff --git a/board/freescale/t208xrdb/Kconfig b/board/freescale/t208xrdb/Kconfig index 6f0b012..8249c5d 100644 --- a/board/freescale/t208xrdb/Kconfig +++ b/board/freescale/t208xrdb/Kconfig @@ -9,6 +9,10 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "T208xRDB" +config T2080RDB_REV_D + bool "Support for T2080RDB revisions D and up" + default n + source "board/freescale/common/Kconfig" endif diff --git a/configs/T2080RDB_revD_NAND_defconfig b/configs/T2080RDB_revD_NAND_defconfig new file mode 100644 index 0000000..3b533a3 --- /dev/null +++ b/configs/T2080RDB_revD_NAND_defconfig @@ -0,0 +1,93 @@ +CONFIG_PPC=y +CONFIG_SYS_TEXT_BASE=0x00201000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MEMTEST_START=0x00200000 +CONFIG_SYS_MEMTEST_END=0x00400000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0x100000 +CONFIG_SPL_TEXT_BASE=0xFFFD8000 +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL=y +CONFIG_DEFAULT_DEVICE_TREE="t2080rdb" +CONFIG_MPC85xx=y +CONFIG_TARGET_T2080RDB=y +CONFIG_T2080RDB_REV_D=y +CONFIG_SYS_CUSTOM_LDSCRIPT=y +CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL" +CONFIG_BOOTDELAY=10 +CONFIG_BOARD_EARLY_INIT_R=y +# CONFIG_SPL_FRAMEWORK is not set +CONFIG_SPL_NAND_BOOT=y +CONFIG_SPL_FSL_PBL=y +CONFIG_SPL_ENV_SUPPORT=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y +CONFIG_SPL_NAND_SUPPORT=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_IMLS=y +CONFIG_CMD_MEMTEST=y +CONFIG_SYS_ALT_MEMTEST=y +CONFIG_CMD_DM=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_MP=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_FAT=y +CONFIG_CMD_MTDPARTS=y +CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.1" +CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.1:1m(uboot),5m(kernel),128k(dtb),-(user)" +# CONFIG_CMD_IRQ is not set +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_NAND=y +CONFIG_DM=y +CONFIG_FSL_CAAM=y +CONFIG_DM_I2C=y +CONFIG_FSL_ESDHC=y +CONFIG_MTD=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_CFI_DRIVER=y +CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y +CONFIG_FLASH_CFI_MTD=y +CONFIG_SYS_FLASH_CFI=y +CONFIG_MTD_RAW_NAND=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=10000000 +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHYLIB=y +CONFIG_PHY_AQUANTIA=y +CONFIG_PHY_CORTINA=y +CONFIG_SYS_CORTINA_FW_IN_NAND=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH=y +CONFIG_DM_MDIO=y +CONFIG_E1000=y +CONFIG_FMAN_ENET=y +CONFIG_MII=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y +CONFIG_SYS_QE_FMAN_FW_IN_NAND=y +CONFIG_DM_RTC=y +CONFIG_RTC_DS1307=y +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_FSL_ESPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_ADDR_MAP=y +CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/T2080RDB_revD_SDCARD_defconfig b/configs/T2080RDB_revD_SDCARD_defconfig new file mode 100644 index 0000000..7b9013e --- /dev/null +++ b/configs/T2080RDB_revD_SDCARD_defconfig @@ -0,0 +1,90 @@ +CONFIG_PPC=y +CONFIG_SYS_TEXT_BASE=0x00201000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MEMTEST_START=0x00200000 +CONFIG_SYS_MEMTEST_END=0x00400000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0x100000 +CONFIG_SPL_TEXT_BASE=0xFFFD8000 +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL=y +CONFIG_DEFAULT_DEVICE_TREE="t2080rdb" +CONFIG_MPC85xx=y +CONFIG_TARGET_T2080RDB=y +CONFIG_T2080RDB_REV_D=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD" +CONFIG_BOOTDELAY=10 +CONFIG_BOARD_EARLY_INIT_R=y +# CONFIG_SPL_FRAMEWORK is not set +CONFIG_SPL_MMC_BOOT=y +CONFIG_SPL_FSL_PBL=y +CONFIG_SPL_ENV_SUPPORT=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_IMLS=y +CONFIG_CMD_MEMTEST=y +CONFIG_SYS_ALT_MEMTEST=y +CONFIG_CMD_DM=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_MP=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_FAT=y +CONFIG_CMD_MTDPARTS=y +CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.1" +CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.1:1m(uboot),5m(kernel),128k(dtb),-(user)" +# CONFIG_CMD_IRQ is not set +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_DM=y +CONFIG_FSL_CAAM=y +CONFIG_DM_I2C=y +CONFIG_FSL_ESDHC=y +CONFIG_MTD=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_CFI_DRIVER=y +CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y +CONFIG_FLASH_CFI_MTD=y +CONFIG_SYS_FLASH_CFI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=10000000 +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHYLIB=y +CONFIG_PHY_AQUANTIA=y +CONFIG_PHY_CORTINA=y +CONFIG_SYS_CORTINA_FW_IN_MMC=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH=y +CONFIG_DM_MDIO=y +CONFIG_E1000=y +CONFIG_FMAN_ENET=y +CONFIG_MII=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y +CONFIG_SYS_QE_FMAN_FW_IN_MMC=y +CONFIG_DM_RTC=y +CONFIG_RTC_DS1307=y +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_FSL_ESPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_ADDR_MAP=y +CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/T2080RDB_revD_SPIFLASH_defconfig b/configs/T2080RDB_revD_SPIFLASH_defconfig new file mode 100644 index 0000000..af85fa6 --- /dev/null +++ b/configs/T2080RDB_revD_SPIFLASH_defconfig @@ -0,0 +1,92 @@ +CONFIG_PPC=y +CONFIG_SYS_TEXT_BASE=0x00201000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MEMTEST_START=0x00200000 +CONFIG_SYS_MEMTEST_END=0x00400000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0x100000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SPL_TEXT_BASE=0xFFFD8000 +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL=y +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI_SUPPORT=y +CONFIG_DEFAULT_DEVICE_TREE="t2080rdb" +CONFIG_MPC85xx=y +CONFIG_TARGET_T2080RDB=y +CONFIG_T2080RDB_REV_D=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH" +CONFIG_BOOTDELAY=10 +CONFIG_BOARD_EARLY_INIT_R=y +# CONFIG_SPL_FRAMEWORK is not set +CONFIG_SPL_SPI_BOOT=y +CONFIG_SPL_FSL_PBL=y +CONFIG_SPL_ENV_SUPPORT=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_IMLS=y +CONFIG_CMD_MEMTEST=y +CONFIG_SYS_ALT_MEMTEST=y +CONFIG_CMD_DM=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_MP=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_FAT=y +CONFIG_CMD_MTDPARTS=y +CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.1" +CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.1:1m(uboot),5m(kernel),128k(dtb),-(user)" +# CONFIG_CMD_IRQ is not set +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_DM=y +CONFIG_FSL_CAAM=y +CONFIG_DM_I2C=y +CONFIG_FSL_ESDHC=y +CONFIG_MTD=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_CFI_DRIVER=y +CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y +CONFIG_FLASH_CFI_MTD=y +CONFIG_SYS_FLASH_CFI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=10000000 +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHYLIB=y +CONFIG_PHY_AQUANTIA=y +CONFIG_PHY_CORTINA=y +CONFIG_SYS_CORTINA_FW_IN_SPIFLASH=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH=y +CONFIG_DM_MDIO=y +CONFIG_E1000=y +CONFIG_FMAN_ENET=y +CONFIG_MII=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y +CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y +CONFIG_DM_RTC=y +CONFIG_RTC_DS1307=y +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_FSL_ESPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_ADDR_MAP=y +CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/T2080RDB_revD_defconfig b/configs/T2080RDB_revD_defconfig new file mode 100644 index 0000000..79397ab --- /dev/null +++ b/configs/T2080RDB_revD_defconfig @@ -0,0 +1,77 @@ +CONFIG_PPC=y +CONFIG_SYS_TEXT_BASE=0xEFF40000 +CONFIG_SYS_MEMTEST_START=0x00200000 +CONFIG_SYS_MEMTEST_END=0x00400000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_DEFAULT_DEVICE_TREE="t2080rdb" +CONFIG_MPC85xx=y +CONFIG_TARGET_T2080RDB=y +CONFIG_MPC85XX_HAVE_RESET_VECTOR=y +CONFIG_T2080RDB_REV_D=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_BOOTDELAY=10 +CONFIG_BOARD_EARLY_INIT_R=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_IMLS=y +CONFIG_CMD_MEMTEST=y +CONFIG_SYS_ALT_MEMTEST=y +CONFIG_CMD_DM=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_MP=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_FAT=y +CONFIG_CMD_MTDPARTS=y +CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.1" +CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.1:1m(uboot),5m(kernel),128k(dtb),-(user)" +# CONFIG_CMD_IRQ is not set +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_FLASH=y +CONFIG_ENV_ADDR=0xEFF20000 +CONFIG_DM=y +CONFIG_FSL_CAAM=y +CONFIG_DM_I2C=y +CONFIG_FSL_ESDHC=y +CONFIG_MTD=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_CFI_DRIVER=y +CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y +CONFIG_FLASH_CFI_MTD=y +CONFIG_SYS_FLASH_CFI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=10000000 +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHYLIB=y +CONFIG_PHY_AQUANTIA=y +CONFIG_PHY_CORTINA=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH=y +CONFIG_DM_MDIO=y +CONFIG_E1000=y +CONFIG_FMAN_ENET=y +CONFIG_MII=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y +CONFIG_SYS_QE_FMAN_FW_IN_NOR=y +CONFIG_DM_RTC=y +CONFIG_RTC_DS1307=y +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_FSL_ESPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_ADDR_MAP=y +CONFIG_SYS_NUM_ADDR_MAP=64 -- cgit v1.1 From 390c73b41757f7a69987ed75dc0b44d630d67700 Mon Sep 17 00:00:00 2001 From: Ran Wang Date: Wed, 16 Jun 2021 17:53:19 +0530 Subject: armv8: Update erratum number to align with doc MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change the USB erratum number A-050106 to A-050204 as A-050106 is a duplicate and never be published. Fixes 0cfa00cdb94 (“armv8: Add workaround for USB erratum A-050106”) Signed-off-by: Ran Wang [Rebased] Signed-off-by: Priyanka Jain --- arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 8 ++++---- arch/arm/cpu/armv8/fsl-layerscape/soc.c | 6 +++--- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 395e5cc..9c58f69 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -223,7 +223,7 @@ config ARCH_LX2162A select SYS_FSL_DDR_VER_50 select SYS_FSL_EC1 select SYS_FSL_EC2 - select SYS_FSL_ERRATUM_A050106 + select SYS_FSL_ERRATUM_A050204 select SYS_FSL_ERRATUM_A011334 select SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND select SYS_FSL_HAS_RGMII @@ -255,7 +255,7 @@ config ARCH_LX2160A select SYS_FSL_DDR_VER_50 select SYS_FSL_EC1 select SYS_FSL_EC2 - select SYS_FSL_ERRATUM_A050106 + select SYS_FSL_ERRATUM_A050204 select SYS_FSL_ERRATUM_A011334 select SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND select SYS_FSL_HAS_RGMII @@ -375,8 +375,8 @@ config SYS_FSL_ERRATUM_A009008 config SYS_FSL_ERRATUM_A009798 bool "Workaround for USB PHY erratum A009798" -config SYS_FSL_ERRATUM_A050106 - bool "Workaround for USB PHY erratum A050106" +config SYS_FSL_ERRATUM_A050204 + bool "Workaround for USB PHY erratum A050204" help USB3.0 Receiver needs to enable fixed equalization for each of PHY instances in an SOC. This is similar diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 7553b5b..c3cd6c7 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2014-2015 Freescale Semiconductor - * Copyright 2019-2020 NXP + * Copyright 2019-2021 NXP */ #include @@ -218,7 +218,7 @@ static void erratum_a009007(void) } #if defined(CONFIG_FSL_LSCH3) -static void erratum_a050106(void) +static void erratum_a050204(void) { #if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A) void __iomem *dcsr = (void __iomem *)DCSR_BASE; @@ -378,7 +378,7 @@ void fsl_lsch3_early_init_f(void) erratum_a009798(); erratum_a008997(); erratum_a009007(); - erratum_a050106(); + erratum_a050204(); #ifdef CONFIG_CHAIN_OF_TRUST /* In case of Secure Boot, the IBR configures the SMMU * to allow only Secure transactions. -- cgit v1.1 From b7efcaff8bb5196b9271bcfaeb0a5f100b3867c2 Mon Sep 17 00:00:00 2001 From: Priyanka Jain Date: Thu, 17 Jun 2021 12:52:46 +0530 Subject: board: freescale: t1028xrdb: Add MAINTAINER for revD Add Priyanka Jain as MAINTAINER for T2080RDB_revD_defconfig, T2080RDB_revD_NAND_defconfig, T2080RDB_revD_SDCARD_defconfig and T2080RDB_revD_SPIFLASH_defconfig Signed-off-by: Priyanka Jain --- board/freescale/t208xrdb/MAINTAINERS | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/board/freescale/t208xrdb/MAINTAINERS b/board/freescale/t208xrdb/MAINTAINERS index f894f77..6e9b25f 100644 --- a/board/freescale/t208xrdb/MAINTAINERS +++ b/board/freescale/t208xrdb/MAINTAINERS @@ -8,6 +8,10 @@ F: configs/T2080RDB_NAND_defconfig F: configs/T2080RDB_SDCARD_defconfig F: configs/T2080RDB_SPIFLASH_defconfig F: configs/T2080RDB_SRIO_PCIE_BOOT_defconfig +F: configs/T2080RDB_revD_defconfig +F: configs/T2080RDB_revD_NAND_defconfig +F: configs/T2080RDB_revD_SDCARD_defconfig +F: configs/T2080RDB_revD_SPIFLASH_defconfig T2080RDB_SECURE_BOOT BOARD M: Ruchika Gupta -- cgit v1.1