From a257f6263b51321ecacc69ac1effbcbe2158fe15 Mon Sep 17 00:00:00 2001
From: Paul Burton <paul.burton@imgtec.com>
Date: Fri, 8 Nov 2013 11:18:49 +0000
Subject: malta: setup super I/O UARTs

On a real Malta the Super I/O needs to be configured before we are able
to access the UARTs. This patch performs that configuration, setting up
the UARTs in the same way that YAMON would.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
---
 board/imgtec/malta/Makefile  |  1 +
 board/imgtec/malta/malta.c   | 10 +++++++
 board/imgtec/malta/superio.c | 63 ++++++++++++++++++++++++++++++++++++++++++++
 board/imgtec/malta/superio.h | 15 +++++++++++
 4 files changed, 89 insertions(+)
 create mode 100644 board/imgtec/malta/superio.c
 create mode 100644 board/imgtec/malta/superio.h

diff --git a/board/imgtec/malta/Makefile b/board/imgtec/malta/Makefile
index 091830d..19dd3a3 100644
--- a/board/imgtec/malta/Makefile
+++ b/board/imgtec/malta/Makefile
@@ -7,3 +7,4 @@
 
 obj-y	= malta.o
 obj-y	+= lowlevel_init.o
+obj-y	+= superio.o
diff --git a/board/imgtec/malta/malta.c b/board/imgtec/malta/malta.c
index 7eddf1c..09da9ea 100644
--- a/board/imgtec/malta/malta.c
+++ b/board/imgtec/malta/malta.c
@@ -12,6 +12,8 @@
 #include <asm/malta.h>
 #include <pci_gt64120.h>
 
+#include "superio.h"
+
 phys_size_t initdram(int board_type)
 {
 	return CONFIG_SYS_MEM_SIZE;
@@ -36,6 +38,14 @@ void _machine_restart(void)
 	__raw_writel(GORESET, reset_base);
 }
 
+int board_early_init_f(void)
+{
+	/* setup FDC37M817 super I/O controller */
+	malta_superio_init((void *)CKSEG1ADDR(MALTA_IO_PORT_BASE));
+
+	return 0;
+}
+
 void pci_init_board(void)
 {
 	set_io_port_base(CKSEG1ADDR(MALTA_IO_PORT_BASE));
diff --git a/board/imgtec/malta/superio.c b/board/imgtec/malta/superio.c
new file mode 100644
index 0000000..eaa14df
--- /dev/null
+++ b/board/imgtec/malta/superio.c
@@ -0,0 +1,63 @@
+/*
+ * Copyright (C) 2013 Imagination Technologies
+ * Author: Paul Burton <paul.burton@imgtec.com>
+ *
+ * Setup code for the FDC37M817 super I/O controller
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+
+#define SIO_CONF_PORT		0x3f0
+#define SIO_DATA_PORT		0x3f1
+
+enum sio_conf_key {
+	SIOCONF_DEVNUM		= 0x07,
+	SIOCONF_ACTIVATE	= 0x30,
+	SIOCONF_ENTER_SETUP	= 0x55,
+	SIOCONF_BASE_HIGH	= 0x60,
+	SIOCONF_BASE_LOW	= 0x61,
+	SIOCONF_PRIMARY_INT	= 0x70,
+	SIOCONF_EXIT_SETUP	= 0xaa,
+	SIOCONF_MODE		= 0xf0,
+};
+
+static struct {
+	u8 key;
+	u8 data;
+} sio_config[] = {
+	/* tty0 */
+	{ SIOCONF_DEVNUM,	0x04 },
+	{ SIOCONF_BASE_HIGH,	0x03 },
+	{ SIOCONF_BASE_LOW,	0xf8 },
+	{ SIOCONF_MODE,		0x02 },
+	{ SIOCONF_PRIMARY_INT,	0x04 },
+	{ SIOCONF_ACTIVATE,	0x01 },
+
+	/* tty1 */
+	{ SIOCONF_DEVNUM,	0x05 },
+	{ SIOCONF_BASE_HIGH,	0x02 },
+	{ SIOCONF_BASE_LOW,	0xf8 },
+	{ SIOCONF_MODE,		0x02 },
+	{ SIOCONF_PRIMARY_INT,	0x03 },
+	{ SIOCONF_ACTIVATE,	0x01 },
+};
+
+void malta_superio_init(void *io_base)
+{
+	unsigned i;
+
+	/* enter config state */
+	writeb(SIOCONF_ENTER_SETUP, io_base + SIO_CONF_PORT);
+
+	/* configure peripherals */
+	for (i = 0; i < ARRAY_SIZE(sio_config); i++) {
+		writeb(sio_config[i].key, io_base + SIO_CONF_PORT);
+		writeb(sio_config[i].data, io_base + SIO_DATA_PORT);
+	}
+
+	/* exit config state */
+	writeb(SIOCONF_EXIT_SETUP, io_base + SIO_CONF_PORT);
+}
diff --git a/board/imgtec/malta/superio.h b/board/imgtec/malta/superio.h
new file mode 100644
index 0000000..1450da5
--- /dev/null
+++ b/board/imgtec/malta/superio.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright (C) 2013 Imagination Technologies
+ * Author: Paul Burton <paul.burton@imgtec.com>
+ *
+ * Setup code for the FDC37M817 super I/O controller
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __BOARD_MALTA_SUPERIO_H__
+#define __BOARD_MALTA_SUPERIO_H__
+
+extern void malta_superio_init(void *io_base);
+
+#endif /* __BOARD_MALTA_SUPERIO_H__ */
-- 
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