From 0e1b54247d7e3e69e0af5c4dc7a3b26acf9e8451 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Sat, 11 Jun 2022 20:20:54 +0800 Subject: imx: drop CONFIG_MXC_UART_BASE Since these boards has CONFIG_DM_SERIAL and/or CONFIG_SPL_DM_SERIAL, the legacy macro no need to be defined. Reviewed-by: Heiko Schocher Reviewed-by: Fabio Estevam Signed-off-by: Peng Fan Acked-by: Soeren Moch Acked-by: Tim Harvey --- include/configs/aristainetos2.h | 2 -- include/configs/imx8mm_evk.h | 2 -- include/configs/imx8mm_venice.h | 3 --- include/configs/imx8mn_bsh_smm_s2_common.h | 4 ---- include/configs/imx8mn_evk.h | 2 -- include/configs/imx8mn_venice.h | 3 --- include/configs/imx8mp_evk.h | 2 -- include/configs/imx8mp_venice.h | 3 --- include/configs/mx7dsabresd.h | 1 - include/configs/somlabs_visionsom_6ull.h | 1 - include/configs/tbs2910.h | 3 --- include/configs/verdin-imx8mm.h | 3 --- include/configs/verdin-imx8mp.h | 3 --- 13 files changed, 32 deletions(-) diff --git a/include/configs/aristainetos2.h b/include/configs/aristainetos2.h index 026775d..de4f440 100644 --- a/include/configs/aristainetos2.h +++ b/include/configs/aristainetos2.h @@ -14,10 +14,8 @@ #define CONFIG_HOSTNAME "aristainetos2" #if (CONFIG_SYS_BOARD_VERSION == 5) -#define CONFIG_MXC_UART_BASE UART2_BASE #define CONSOLE_DEV "ttymxc1" #elif (CONFIG_SYS_BOARD_VERSION == 6) -#define CONFIG_MXC_UART_BASE UART1_BASE #define CONSOLE_DEV "ttymxc0" #endif diff --git a/include/configs/imx8mm_evk.h b/include/configs/imx8mm_evk.h index 983743b..6da09de 100644 --- a/include/configs/imx8mm_evk.h +++ b/include/configs/imx8mm_evk.h @@ -57,8 +57,6 @@ #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ -#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(2) - #define CONFIG_FEC_MXC_PHYADDR 0 #endif diff --git a/include/configs/imx8mm_venice.h b/include/configs/imx8mm_venice.h index 595c107..7a2ef8f 100644 --- a/include/configs/imx8mm_venice.h +++ b/include/configs/imx8mm_venice.h @@ -90,9 +90,6 @@ #define PHYS_SDRAM_SIZE SZ_4G #define CONFIG_SYS_BOOTM_LEN SZ_256M -/* UART */ -#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(2) - /* FEC */ #define CONFIG_FEC_MXC_PHYADDR 0 #define FEC_QUIRK_ENET_MAC diff --git a/include/configs/imx8mn_bsh_smm_s2_common.h b/include/configs/imx8mn_bsh_smm_s2_common.h index 5bdbd37..63f7da7 100644 --- a/include/configs/imx8mn_bsh_smm_s2_common.h +++ b/include/configs/imx8mn_bsh_smm_s2_common.h @@ -32,8 +32,4 @@ #define CONFIG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 -#define CONFIG_MXC_UART_BASE UART4_BASE_ADDR - -/* I2C */ - #endif /* __IMX8MN_BSH_SMM_S2_COMMON_H */ diff --git a/include/configs/imx8mn_evk.h b/include/configs/imx8mn_evk.h index 73ba49b..506d1ff 100644 --- a/include/configs/imx8mn_evk.h +++ b/include/configs/imx8mn_evk.h @@ -64,6 +64,4 @@ #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ -#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(2) - #endif diff --git a/include/configs/imx8mn_venice.h b/include/configs/imx8mn_venice.h index 8565ba7..8c45c84 100644 --- a/include/configs/imx8mn_venice.h +++ b/include/configs/imx8mn_venice.h @@ -86,9 +86,6 @@ #define PHYS_SDRAM_SIZE SZ_4G #define CONFIG_SYS_BOOTM_LEN SZ_256M -/* UART */ -#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(2) - /* FEC */ #define CONFIG_FEC_MXC_PHYADDR 0 #define FEC_QUIRK_ENET_MAC diff --git a/include/configs/imx8mp_evk.h b/include/configs/imx8mp_evk.h index 65c1616..465e1cb 100644 --- a/include/configs/imx8mp_evk.h +++ b/include/configs/imx8mp_evk.h @@ -69,6 +69,4 @@ #define PHYS_SDRAM_2 0x100000000 #define PHYS_SDRAM_2_SIZE 0xC0000000 /* 3 GB */ -#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(2) - #endif diff --git a/include/configs/imx8mp_venice.h b/include/configs/imx8mp_venice.h index e1d3355..d9baffb 100644 --- a/include/configs/imx8mp_venice.h +++ b/include/configs/imx8mp_venice.h @@ -86,9 +86,6 @@ #define PHYS_SDRAM_SIZE SZ_4G #define CONFIG_SYS_BOOTM_LEN SZ_256M -/* UART */ -#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR - /* FEC */ #define FEC_QUIRK_ENET_MAC diff --git a/include/configs/mx7dsabresd.h b/include/configs/mx7dsabresd.h index 36cef25..a6b8c27 100644 --- a/include/configs/mx7dsabresd.h +++ b/include/configs/mx7dsabresd.h @@ -12,7 +12,6 @@ #define PHYS_SDRAM_SIZE SZ_1G -#define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR #ifdef CONFIG_IMX_BOOTAUX /* Set to QSPI1 A flash at default */ diff --git a/include/configs/somlabs_visionsom_6ull.h b/include/configs/somlabs_visionsom_6ull.h index 98966cf..f1886cb 100644 --- a/include/configs/somlabs_visionsom_6ull.h +++ b/include/configs/somlabs_visionsom_6ull.h @@ -16,7 +16,6 @@ /* SPL options */ #include "imx6_spl.h" -#define CONFIG_MXC_UART_BASE UART1_BASE /* MMC Configs */ #ifdef CONFIG_FSL_USDHC diff --git a/include/configs/tbs2910.h b/include/configs/tbs2910.h index 1ebe28b..c355083 100644 --- a/include/configs/tbs2910.h +++ b/include/configs/tbs2910.h @@ -20,9 +20,6 @@ #define CONFIG_SYS_BOOTMAPSZ 0x10000000 -/* Serial console */ -#define CONFIG_MXC_UART_BASE UART1_BASE /* select UART1/UART2 */ - /* Framebuffer */ #define CONFIG_IMX_HDMI #define CONFIG_IMX_VIDEO_SKIP diff --git a/include/configs/verdin-imx8mm.h b/include/configs/verdin-imx8mm.h index 8f464dd..4fb0d69 100644 --- a/include/configs/verdin-imx8mm.h +++ b/include/configs/verdin-imx8mm.h @@ -72,9 +72,6 @@ #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE SZ_2G /* 2GB DDR */ -/* UART */ -#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(1) - /* ENET */ #define CONFIG_FEC_MXC_PHYADDR 7 diff --git a/include/configs/verdin-imx8mp.h b/include/configs/verdin-imx8mp.h index 906a20f..704a053 100644 --- a/include/configs/verdin-imx8mp.h +++ b/include/configs/verdin-imx8mp.h @@ -89,7 +89,4 @@ #define PHYS_SDRAM_2 0x100000000 #define PHYS_SDRAM_2_SIZE (SZ_4G + SZ_1G) -/* UART */ -#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(3) - #endif /* __VERDIN_IMX8MP_H */ -- cgit v1.1 From d35130fef8a1c6a43a76fdcc5100d5d794084e93 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Sat, 11 Jun 2022 20:20:55 +0800 Subject: imx: imx8m[m/n]_beacon: Enable SPL_DM_SERIAL Enable CONFIG_SPL_DM_SERIAL. uart2 and its pinmux was already marked with u-boot,dm-spl. Move preloader_console_init after spl_init to make sure driver model work. Signed-off-by: Peng Fan Tested-by: Adam Ford #imx8mm_beacon Reviewed-by: Fabio Estevam Tested-by: Adam Ford #imx8mn_beacon --- board/beacon/imx8mm/spl.c | 12 ++---------- board/beacon/imx8mn/spl.c | 11 ++--------- configs/imx8mm_beacon_defconfig | 1 - configs/imx8mn_beacon_2g_defconfig | 1 - configs/imx8mn_beacon_defconfig | 1 - include/configs/imx8mm_beacon.h | 2 -- include/configs/imx8mn_beacon.h | 2 -- 7 files changed, 4 insertions(+), 26 deletions(-) diff --git a/board/beacon/imx8mm/spl.c b/board/beacon/imx8mm/spl.c index 12266b2..f92b4c3 100644 --- a/board/beacon/imx8mm/spl.c +++ b/board/beacon/imx8mm/spl.c @@ -59,14 +59,8 @@ int board_fit_config_name_match(const char *name) } #endif -#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE) -static iomux_v3_cfg_t const uart_pads[] = { - IMX8MM_PAD_UART2_RXD_UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL), - IMX8MM_PAD_UART2_TXD_UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - static iomux_v3_cfg_t const wdog_pads[] = { IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), }; @@ -79,8 +73,6 @@ int board_early_init_f(void) set_wdog_reset(wdog); - imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); - return 0; } @@ -128,8 +120,6 @@ void board_init_f(ulong dummy) timer_init(); - preloader_console_init(); - /* Clear the BSS. */ memset(__bss_start, 0, __bss_end - __bss_start); @@ -139,6 +129,8 @@ void board_init_f(ulong dummy) hang(); } + preloader_console_init(); + ret = uclass_get_device_by_name(UCLASS_CLK, "clock-controller@30380000", &dev); diff --git a/board/beacon/imx8mn/spl.c b/board/beacon/imx8mn/spl.c index bb51be0..4563446 100644 --- a/board/beacon/imx8mn/spl.c +++ b/board/beacon/imx8mn/spl.c @@ -68,7 +68,6 @@ int board_fit_config_name_match(const char *name) } #endif -#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE) #define PWM1_PAD_CTRL (PAD_CTL_FSEL2 | PAD_CTL_DSE6) @@ -76,11 +75,6 @@ static iomux_v3_cfg_t const pwm_pads[] = { IMX8MN_PAD_GPIO1_IO01__PWM1_OUT | MUX_PAD_CTRL(PWM1_PAD_CTRL), }; -static iomux_v3_cfg_t const uart_pads[] = { - IMX8MN_PAD_UART2_RXD__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), - IMX8MN_PAD_UART2_TXD__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - static iomux_v3_cfg_t const wdog_pads[] = { IMX8MN_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), }; @@ -95,7 +89,6 @@ int board_early_init_f(void) imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); set_wdog_reset(wdog); - imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); init_uart_clk(1); return 0; @@ -114,14 +107,14 @@ void board_init_f(ulong dummy) timer_init(); - preloader_console_init(); - ret = spl_init(); if (ret) { debug("spl_init() failed: %d\n", ret); hang(); } + preloader_console_init(); + enable_tzc380(); /* DDR initialization */ diff --git a/configs/imx8mm_beacon_defconfig b/configs/imx8mm_beacon_defconfig index 417ece1..e1acf7e 100644 --- a/configs/imx8mm_beacon_defconfig +++ b/configs/imx8mm_beacon_defconfig @@ -125,7 +125,6 @@ CONFIG_SPL_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_CONS_INDEX=2 CONFIG_DM_SERIAL=y -# CONFIG_SPL_DM_SERIAL is not set CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/imx8mn_beacon_2g_defconfig b/configs/imx8mn_beacon_2g_defconfig index 5b9b371..cadef45 100644 --- a/configs/imx8mn_beacon_2g_defconfig +++ b/configs/imx8mn_beacon_2g_defconfig @@ -127,7 +127,6 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_DM_RESET=y CONFIG_DM_SERIAL=y -# CONFIG_SPL_DM_SERIAL is not set CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/imx8mn_beacon_defconfig b/configs/imx8mn_beacon_defconfig index b296898..357109e 100644 --- a/configs/imx8mn_beacon_defconfig +++ b/configs/imx8mn_beacon_defconfig @@ -131,7 +131,6 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_DM_RESET=y CONFIG_DM_SERIAL=y -# CONFIG_SPL_DM_SERIAL is not set CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/include/configs/imx8mm_beacon.h b/include/configs/imx8mm_beacon.h index 897eac6..899d2ec 100644 --- a/include/configs/imx8mm_beacon.h +++ b/include/configs/imx8mm_beacon.h @@ -80,6 +80,4 @@ #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ -#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(2) - #endif diff --git a/include/configs/imx8mn_beacon.h b/include/configs/imx8mn_beacon.h index 99cbc1d..cadad05 100644 --- a/include/configs/imx8mn_beacon.h +++ b/include/configs/imx8mn_beacon.h @@ -96,6 +96,4 @@ #define PHYS_SDRAM_SIZE 0x40000000 /* 1GB DDR */ #endif -#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(2) - #endif -- cgit v1.1 From 37750505b90ab762e9305d8e49fa4a7c6a24954d Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Sat, 11 Jun 2022 20:20:56 +0800 Subject: imx: imx8mm-cl-iot-gate: Enable DM_SERIAL Enable CONFIG_DM_SERIAL. uart3 and its pinmux was already marked with u-boot,dm-spl. Move preloader_console_init after spl_early_init to make sure driver model work. Signed-off-by: Peng Fan Reviewed-by: Fabio Estevam --- board/compulab/imx8mm-cl-iot-gate/spl.c | 12 ++---------- configs/imx8mm-cl-iot-gate-optee_defconfig | 1 + configs/imx8mm-cl-iot-gate_defconfig | 1 + include/configs/imx8mm-cl-iot-gate.h | 2 -- 4 files changed, 4 insertions(+), 12 deletions(-) diff --git a/board/compulab/imx8mm-cl-iot-gate/spl.c b/board/compulab/imx8mm-cl-iot-gate/spl.c index 2dc62d6..f183704 100644 --- a/board/compulab/imx8mm-cl-iot-gate/spl.c +++ b/board/compulab/imx8mm-cl-iot-gate/spl.c @@ -83,14 +83,8 @@ int board_fit_config_name_match(const char *name) } #endif -#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE) -static iomux_v3_cfg_t const uart_pads[] = { - IMX8MM_PAD_UART3_RXD_UART3_RX | MUX_PAD_CTRL(UART_PAD_CTRL), - IMX8MM_PAD_UART3_TXD_UART3_TX | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - static iomux_v3_cfg_t const wdog_pads[] = { IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), }; @@ -103,8 +97,6 @@ int board_early_init_f(void) set_wdog_reset(wdog); - imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); - return 0; } @@ -155,8 +147,6 @@ void board_init_f(ulong dummy) timer_init(); - preloader_console_init(); - /* Clear the BSS. */ memset(__bss_start, 0, __bss_end - __bss_start); @@ -166,6 +156,8 @@ void board_init_f(ulong dummy) hang(); } + preloader_console_init(); + ret = uclass_get_device_by_name(UCLASS_CLK, "clock-controller@30380000", &dev); diff --git a/configs/imx8mm-cl-iot-gate-optee_defconfig b/configs/imx8mm-cl-iot-gate-optee_defconfig index 57ecd7b..8005591 100644 --- a/configs/imx8mm-cl-iot-gate-optee_defconfig +++ b/configs/imx8mm-cl-iot-gate-optee_defconfig @@ -121,6 +121,7 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_DM_RTC=y CONFIG_RTC_ABX80X=y +CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/imx8mm-cl-iot-gate_defconfig b/configs/imx8mm-cl-iot-gate_defconfig index 67f7576..dae7ddc 100644 --- a/configs/imx8mm-cl-iot-gate_defconfig +++ b/configs/imx8mm-cl-iot-gate_defconfig @@ -124,6 +124,7 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_DM_RTC=y CONFIG_RTC_ABX80X=y +CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/include/configs/imx8mm-cl-iot-gate.h b/include/configs/imx8mm-cl-iot-gate.h index 297d56b..fc738ed 100644 --- a/include/configs/imx8mm-cl-iot-gate.h +++ b/include/configs/imx8mm-cl-iot-gate.h @@ -134,8 +134,6 @@ #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ -#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(3) - /* USDHC */ #define CONFIG_SYS_FSL_USDHC_NUM 2 -- cgit v1.1 From 4ebb9a589852841c65ae68e2f3f3d160df40d55e Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Sat, 11 Jun 2022 20:20:57 +0800 Subject: imx: imx8mm_icore: Enable SPL_DM_SERIAL Enable CONFIG_SPL_DM_SERIAL. uart2 and its pinmux was already marked with u-boot,dm-spl. Move preloader_console_init after spl_early_init to make sure driver model work. Signed-off-by: Peng Fan Reviewed-by: Fabio Estevam --- board/engicam/imx8mm/spl.c | 14 +++----------- configs/imx8mm-icore-mx8mm-ctouch2_defconfig | 1 - configs/imx8mm-icore-mx8mm-edimm2.2_defconfig | 1 - include/configs/imx8mm_icore_mx8mm.h | 3 --- 4 files changed, 3 insertions(+), 16 deletions(-) diff --git a/board/engicam/imx8mm/spl.c b/board/engicam/imx8mm/spl.c index f9be769..f75f2dc 100644 --- a/board/engicam/imx8mm/spl.c +++ b/board/engicam/imx8mm/spl.c @@ -54,19 +54,11 @@ int board_fit_config_name_match(const char *name) } #endif -#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE) -static iomux_v3_cfg_t const uart_pads[] = { - IMX8MM_PAD_UART2_RXD_UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL), - IMX8MM_PAD_UART2_TXD_UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - int board_early_init_f(void) { - imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); - - return 0; + return 0; } void board_init_f(ulong dummy) @@ -81,8 +73,6 @@ void board_init_f(ulong dummy) timer_init(); - preloader_console_init(); - /* Clear the BSS. */ memset(__bss_start, 0, __bss_end - __bss_start); @@ -92,6 +82,8 @@ void board_init_f(ulong dummy) hang(); } + preloader_console_init(); + enable_tzc380(); /* DDR initialization */ diff --git a/configs/imx8mm-icore-mx8mm-ctouch2_defconfig b/configs/imx8mm-icore-mx8mm-ctouch2_defconfig index c95ff3e..b831adb 100644 --- a/configs/imx8mm-icore-mx8mm-ctouch2_defconfig +++ b/configs/imx8mm-icore-mx8mm-ctouch2_defconfig @@ -87,7 +87,6 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_CONS_INDEX=2 CONFIG_DM_SERIAL=y -# CONFIG_SPL_DM_SERIAL is not set CONFIG_MXC_UART=y CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y diff --git a/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig b/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig index 62d2394..614bacb 100644 --- a/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig +++ b/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig @@ -87,7 +87,6 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_CONS_INDEX=2 CONFIG_DM_SERIAL=y -# CONFIG_SPL_DM_SERIAL is not set CONFIG_MXC_UART=y CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y diff --git a/include/configs/imx8mm_icore_mx8mm.h b/include/configs/imx8mm_icore_mx8mm.h index e664293..a3db850 100644 --- a/include/configs/imx8mm_icore_mx8mm.h +++ b/include/configs/imx8mm_icore_mx8mm.h @@ -54,9 +54,6 @@ #define PHYS_SDRAM_SIZE SZ_2G /* 2GB DDR */ #define CONFIG_SYS_BOOTM_LEN SZ_256M -/* UART */ -#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(2) - /* USDHC */ #define CONFIG_SYS_FSL_USDHC_NUM 2 #define CONFIG_SYS_FSL_ESDHC_ADDR 0 -- cgit v1.1 From 64d118b27f96aed81c2922e20d2b5db9e32a465f Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Sat, 11 Jun 2022 20:20:58 +0800 Subject: imx: imx8m[m/p]_phycore: Enable DM_SERIAL Enable CONFIG_DM_SERIAL. uart and its pinmux was already marked with u-boot,dm-spl. Move preloader_console_init after spl_early_init to make sure driver model work. Signed-off-by: Peng Fan Tested-by: Teresa Remmet Reviewed-by: Fabio Estevam --- board/phytec/phycore_imx8mm/spl.c | 12 ++---------- board/phytec/phycore_imx8mp/spl.c | 8 -------- configs/phycore-imx8mm_defconfig | 1 + configs/phycore-imx8mp_defconfig | 1 + include/configs/phycore_imx8mm.h | 3 --- include/configs/phycore_imx8mp.h | 3 --- 6 files changed, 4 insertions(+), 24 deletions(-) diff --git a/board/phytec/phycore_imx8mm/spl.c b/board/phytec/phycore_imx8mm/spl.c index d54145e..7f24a3a 100644 --- a/board/phytec/phycore_imx8mm/spl.c +++ b/board/phytec/phycore_imx8mm/spl.c @@ -57,14 +57,8 @@ int board_fit_config_name_match(const char *name) return 0; } -#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE) -static iomux_v3_cfg_t const uart_pads[] = { - IMX8MM_PAD_UART3_RXD_UART3_RX | MUX_PAD_CTRL(UART_PAD_CTRL), - IMX8MM_PAD_UART3_TXD_UART3_TX | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - static iomux_v3_cfg_t const wdog_pads[] = { IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), }; @@ -77,8 +71,6 @@ int board_early_init_f(void) set_wdog_reset(wdog); - imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); - return 0; } @@ -92,8 +84,6 @@ void board_init_f(ulong dummy) board_early_init_f(); - preloader_console_init(); - /* Clear the BSS. */ memset(__bss_start, 0, __bss_end - __bss_start); @@ -103,6 +93,8 @@ void board_init_f(ulong dummy) hang(); } + preloader_console_init(); + enable_tzc380(); /* DDR initialization */ diff --git a/board/phytec/phycore_imx8mp/spl.c b/board/phytec/phycore_imx8mp/spl.c index 19c486e..38a581b 100644 --- a/board/phytec/phycore_imx8mp/spl.c +++ b/board/phytec/phycore_imx8mp/spl.c @@ -89,14 +89,8 @@ int board_fit_config_name_match(const char *name) return 0; } -#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE) -static iomux_v3_cfg_t const uart_pads[] = { - MX8MP_PAD_UART1_RXD__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), - MX8MP_PAD_UART1_TXD__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - static iomux_v3_cfg_t const wdog_pads[] = { MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), }; @@ -109,8 +103,6 @@ int board_early_init_f(void) set_wdog_reset(wdog); - imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); - return 0; } diff --git a/configs/phycore-imx8mm_defconfig b/configs/phycore-imx8mm_defconfig index b8cda9f..0316d45 100644 --- a/configs/phycore-imx8mm_defconfig +++ b/configs/phycore-imx8mm_defconfig @@ -120,6 +120,7 @@ CONFIG_PINCTRL_IMX8M=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/phycore-imx8mp_defconfig b/configs/phycore-imx8mp_defconfig index d10ab2a..2c53a5f 100644 --- a/configs/phycore-imx8mp_defconfig +++ b/configs/phycore-imx8mp_defconfig @@ -111,6 +111,7 @@ CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_SPL_POWER_I2C=y +CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y diff --git a/include/configs/phycore_imx8mm.h b/include/configs/phycore_imx8mm.h index 1d01104..a14a076 100644 --- a/include/configs/phycore_imx8mm.h +++ b/include/configs/phycore_imx8mm.h @@ -72,7 +72,4 @@ #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE SZ_2G /* 2GB DDR */ -/* UART */ -#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(3) - #endif /* __PHYCORE_IMX8MM_H */ diff --git a/include/configs/phycore_imx8mp.h b/include/configs/phycore_imx8mp.h index 75ddcf4..9c7331a 100644 --- a/include/configs/phycore_imx8mp.h +++ b/include/configs/phycore_imx8mp.h @@ -72,7 +72,4 @@ #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0x80000000 -/* UART */ -#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(1) - #endif /* __PHYCORE_IMX8MP_H */ -- cgit v1.1 From bb9e14cfd0e8adc3e8a5a5d112cd7a4ca5c39472 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Sat, 11 Jun 2022 20:20:59 +0800 Subject: imx: imx8mn_var_som: enable DM_SERIAL Enable CONFIG_DM_SERIAL. uart and its pinmux was already marked with u-boot,dm-spl. Move preloader_console_init after spl_init to make sure driver model work. Signed-off-by: Peng Fan Reviewed-by: Ariel D'Alessandro Reviewed-by: Fabio Estevam --- board/variscite/imx8mn_var_som/spl.c | 11 ++--------- configs/imx8mn_var_som_defconfig | 1 + include/configs/imx8mn_var_som.h | 2 -- 3 files changed, 3 insertions(+), 11 deletions(-) diff --git a/board/variscite/imx8mn_var_som/spl.c b/board/variscite/imx8mn_var_som/spl.c index 32703c5..1a8b64f 100644 --- a/board/variscite/imx8mn_var_som/spl.c +++ b/board/variscite/imx8mn_var_som/spl.c @@ -40,14 +40,8 @@ void spl_board_init(void) puts("Failed to find clock node. Check device tree\n"); } -#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE) -static const iomux_v3_cfg_t uart_pads[] = { - IMX8MN_PAD_UART4_RXD__UART4_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), - IMX8MN_PAD_UART4_TXD__UART4_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - static const iomux_v3_cfg_t wdog_pads[] = { IMX8MN_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), }; @@ -59,7 +53,6 @@ int board_early_init_f(void) imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); set_wdog_reset(wdog); - imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); init_uart_clk(3); return 0; @@ -78,14 +71,14 @@ void board_init_f(ulong dummy) timer_init(); - preloader_console_init(); - ret = spl_init(); if (ret) { debug("spl_init() failed: %d\n", ret); hang(); } + preloader_console_init(); + /* DDR initialization */ spl_dram_init(); diff --git a/configs/imx8mn_var_som_defconfig b/configs/imx8mn_var_som_defconfig index 898f3f2..889bcf7 100644 --- a/configs/imx8mn_var_som_defconfig +++ b/configs/imx8mn_var_som_defconfig @@ -96,6 +96,7 @@ CONFIG_SPL_DM_PMIC_BD71837=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_SYSRESET=y CONFIG_SYSRESET_PSCI=y diff --git a/include/configs/imx8mn_var_som.h b/include/configs/imx8mn_var_som.h index ce67909..ccf8312 100644 --- a/include/configs/imx8mn_var_som.h +++ b/include/configs/imx8mn_var_som.h @@ -53,8 +53,6 @@ #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE SZ_1G /* 1GB DDR */ -#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(4) - /* USDHC */ #define CONFIG_SYS_FSL_ESDHC_ADDR 0 -- cgit v1.1 From 0a16da8079a86a566c62bfb4ec2d12bd9d6cb306 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Sat, 11 Jun 2022 20:21:00 +0800 Subject: imx: kontron-sl-mx8mm: enable DM_SERIAL Enable CONFIG_DM_SERIAL. uart and its pinmux was already marked with u-boot,dm-spl. Move preloader_console_init after spl_init to make sure driver model work. Signed-off-by: Peng Fan Acked-by: Frieder Schrempf Reviewed-by: Fabio Estevam Tested-by: Frieder Schrempf --- board/kontron/sl-mx8mm/spl.c | 12 ++---------- configs/kontron-sl-mx8mm_defconfig | 1 + include/configs/kontron-sl-mx8mm.h | 1 - 3 files changed, 3 insertions(+), 11 deletions(-) diff --git a/board/kontron/sl-mx8mm/spl.c b/board/kontron/sl-mx8mm/spl.c index 4ef03c8..a58a75d 100644 --- a/board/kontron/sl-mx8mm/spl.c +++ b/board/kontron/sl-mx8mm/spl.c @@ -32,7 +32,6 @@ enum { #define GPIO_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE) #define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE) -#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE) #define TOUCH_RESET_GPIO IMX_GPIO_NR(3, 23) @@ -51,11 +50,6 @@ static iomux_v3_cfg_t const touch_gpio[] = { IMX8MM_PAD_SAI5_RXD2_GPIO3_IO23 | MUX_PAD_CTRL(GPIO_PAD_CTRL) }; -static iomux_v3_cfg_t const uart_pads[] = { - IMX8MM_PAD_UART3_RXD_UART3_RX | MUX_PAD_CTRL(UART_PAD_CTRL), - IMX8MM_PAD_UART3_TXD_UART3_TX | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - static iomux_v3_cfg_t const wdog_pads[] = { IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), }; @@ -230,8 +224,6 @@ int board_early_init_f(void) set_wdog_reset(wdog); - imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); - return 0; } @@ -273,8 +265,6 @@ void board_init_f(ulong dummy) timer_init(); - preloader_console_init(); - /* Clear the BSS. */ memset(__bss_start, 0, __bss_end - __bss_start); @@ -284,6 +274,8 @@ void board_init_f(ulong dummy) hang(); } + preloader_console_init(); + enable_tzc380(); /* PMIC initialization */ diff --git a/configs/kontron-sl-mx8mm_defconfig b/configs/kontron-sl-mx8mm_defconfig index 0fceb60..d508bcb 100644 --- a/configs/kontron-sl-mx8mm_defconfig +++ b/configs/kontron-sl-mx8mm_defconfig @@ -114,6 +114,7 @@ CONFIG_DM_REGULATOR=y CONFIG_DM_RTC=y CONFIG_RTC_RV8803=y CONFIG_CONS_INDEX=2 +CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/include/configs/kontron-sl-mx8mm.h b/include/configs/kontron-sl-mx8mm.h index 95b836c..c4be62c 100644 --- a/include/configs/kontron-sl-mx8mm.h +++ b/include/configs/kontron-sl-mx8mm.h @@ -23,7 +23,6 @@ #define CONFIG_SYS_INIT_RAM_SIZE 0x200000 /* Board and environment settings */ -#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(3) #define CONFIG_HOSTNAME "kontron-mx8mm" #ifdef CONFIG_USB_EHCI_HCD -- cgit v1.1 From ca3369df71d8ff03054965a00968e9ddee607389 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Sat, 11 Jun 2022 20:21:01 +0800 Subject: configs: drop CONFIG_SPL_ABORT_ON_RAW_IMAGE CONFIG_SPL_RAW_IMAGE_SUPPORT default y has been used to replace CONFIG_SPL_ABORT_ON_RAW_IMAGE for quite some time, so drop CONFIG_SPL_ABORT_ON_RAW_IMAGE. Signed-off-by: Peng Fan --- include/configs/capricorn-common.h | 1 - include/configs/cgtqmx8.h | 1 - include/configs/imx8mm-cl-iot-gate.h | 1 - include/configs/imx8mm_beacon.h | 1 - include/configs/imx8mm_data_modul_edm_sbc.h | 1 - include/configs/imx8mm_evk.h | 1 - include/configs/imx8mm_icore_mx8mm.h | 1 - include/configs/imx8mm_venice.h | 1 - include/configs/imx8mn_beacon.h | 1 - include/configs/imx8mn_evk.h | 1 - include/configs/imx8mn_venice.h | 1 - include/configs/imx8mp_evk.h | 1 - include/configs/imx8mp_rsb3720.h | 1 - include/configs/imx8mp_venice.h | 1 - include/configs/imx8mq_cm.h | 1 - include/configs/imx8mq_evk.h | 1 - include/configs/imx8mq_phanbell.h | 1 - include/configs/imx8qm_mek.h | 1 - include/configs/imx8qxp_mek.h | 1 - include/configs/imx8ulp_evk.h | 1 - include/configs/kontron_pitx_imx8m.h | 1 - include/configs/phycore_imx8mm.h | 1 - include/configs/phycore_imx8mp.h | 1 - include/configs/pico-imx8mq.h | 1 - include/configs/verdin-imx8mm.h | 1 - include/configs/verdin-imx8mp.h | 1 - 26 files changed, 26 deletions(-) diff --git a/include/configs/capricorn-common.h b/include/configs/capricorn-common.h index 933fcfc..0bbfe0c 100644 --- a/include/configs/capricorn-common.h +++ b/include/configs/capricorn-common.h @@ -20,7 +20,6 @@ #define CONFIG_MALLOC_F_ADDR 0x00120000 #define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE -#define CONFIG_SPL_ABORT_ON_RAW_IMAGE #endif /* CONFIG_SPL_BUILD */ diff --git a/include/configs/cgtqmx8.h b/include/configs/cgtqmx8.h index 0266d69..a8ff0a1 100644 --- a/include/configs/cgtqmx8.h +++ b/include/configs/cgtqmx8.h @@ -19,7 +19,6 @@ #define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE -#define CONFIG_SPL_ABORT_ON_RAW_IMAGE #endif /* Flat Device Tree Definitions */ diff --git a/include/configs/imx8mm-cl-iot-gate.h b/include/configs/imx8mm-cl-iot-gate.h index fc738ed..7135a83 100644 --- a/include/configs/imx8mm-cl-iot-gate.h +++ b/include/configs/imx8mm-cl-iot-gate.h @@ -20,7 +20,6 @@ /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ #define CONFIG_MALLOC_F_ADDR 0x912000 /* For RAW image gives a error info not panic */ -#define CONFIG_SPL_ABORT_ON_RAW_IMAGE #endif diff --git a/include/configs/imx8mm_beacon.h b/include/configs/imx8mm_beacon.h index 899d2ec..79ed397 100644 --- a/include/configs/imx8mm_beacon.h +++ b/include/configs/imx8mm_beacon.h @@ -17,7 +17,6 @@ /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ #define CONFIG_MALLOC_F_ADDR 0x930000 /* For RAW image gives a error info not panic */ -#define CONFIG_SPL_ABORT_ON_RAW_IMAGE #endif diff --git a/include/configs/imx8mm_data_modul_edm_sbc.h b/include/configs/imx8mm_data_modul_edm_sbc.h index bb19aa2..282b295 100644 --- a/include/configs/imx8mm_data_modul_edm_sbc.h +++ b/include/configs/imx8mm_data_modul_edm_sbc.h @@ -18,7 +18,6 @@ #define CONFIG_MALLOC_F_ADDR 0x930000 /* For RAW image gives a error info not panic */ -#define CONFIG_SPL_ABORT_ON_RAW_IMAGE #endif diff --git a/include/configs/imx8mm_evk.h b/include/configs/imx8mm_evk.h index 6da09de..e4b2544 100644 --- a/include/configs/imx8mm_evk.h +++ b/include/configs/imx8mm_evk.h @@ -19,7 +19,6 @@ /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ #define CONFIG_MALLOC_F_ADDR 0x930000 /* For RAW image gives a error info not panic */ -#define CONFIG_SPL_ABORT_ON_RAW_IMAGE #endif diff --git a/include/configs/imx8mm_icore_mx8mm.h b/include/configs/imx8mm_icore_mx8mm.h index a3db850..dfe6966 100644 --- a/include/configs/imx8mm_icore_mx8mm.h +++ b/include/configs/imx8mm_icore_mx8mm.h @@ -18,7 +18,6 @@ /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ # define CONFIG_MALLOC_F_ADDR 0x930000 /* For RAW image gives a error info not panic */ -# define CONFIG_SPL_ABORT_ON_RAW_IMAGE #endif /* CONFIG_SPL_BUILD */ #ifndef CONFIG_SPL_BUILD diff --git a/include/configs/imx8mm_venice.h b/include/configs/imx8mm_venice.h index 7a2ef8f..8a6cc69 100644 --- a/include/configs/imx8mm_venice.h +++ b/include/configs/imx8mm_venice.h @@ -17,7 +17,6 @@ /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ #define CONFIG_MALLOC_F_ADDR 0x930000 /* For RAW image gives a error info not panic */ -#define CONFIG_SPL_ABORT_ON_RAW_IMAGE #endif diff --git a/include/configs/imx8mn_beacon.h b/include/configs/imx8mn_beacon.h index cadad05..6faecbd 100644 --- a/include/configs/imx8mn_beacon.h +++ b/include/configs/imx8mn_beacon.h @@ -18,7 +18,6 @@ #define CONFIG_MALLOC_F_ADDR 0x184000 /* For RAW image gives a error info not panic */ -#define CONFIG_SPL_ABORT_ON_RAW_IMAGE #endif /* CONFIG_SPL_BUILD */ diff --git a/include/configs/imx8mn_evk.h b/include/configs/imx8mn_evk.h index 506d1ff..1396ae1 100644 --- a/include/configs/imx8mn_evk.h +++ b/include/configs/imx8mn_evk.h @@ -18,7 +18,6 @@ #ifdef CONFIG_SPL_BUILD /* For RAW image gives a error info not panic */ -#define CONFIG_SPL_ABORT_ON_RAW_IMAGE #endif diff --git a/include/configs/imx8mn_venice.h b/include/configs/imx8mn_venice.h index 8c45c84..8ef55aa 100644 --- a/include/configs/imx8mn_venice.h +++ b/include/configs/imx8mn_venice.h @@ -15,7 +15,6 @@ #ifdef CONFIG_SPL_BUILD /* For RAW image gives a error info not panic */ -#define CONFIG_SPL_ABORT_ON_RAW_IMAGE #endif #define MEM_LAYOUT_ENV_SETTINGS \ diff --git a/include/configs/imx8mp_evk.h b/include/configs/imx8mp_evk.h index 465e1cb..618010d 100644 --- a/include/configs/imx8mp_evk.h +++ b/include/configs/imx8mp_evk.h @@ -18,7 +18,6 @@ #ifdef CONFIG_SPL_BUILD /*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/ -#define CONFIG_SPL_ABORT_ON_RAW_IMAGE #define CONFIG_POWER_PCA9450 diff --git a/include/configs/imx8mp_rsb3720.h b/include/configs/imx8mp_rsb3720.h index efff6b9..1d4c057 100644 --- a/include/configs/imx8mp_rsb3720.h +++ b/include/configs/imx8mp_rsb3720.h @@ -32,7 +32,6 @@ * set \ */ -#define CONFIG_SPL_ABORT_ON_RAW_IMAGE #if defined(CONFIG_NAND_BOOT) #define CONFIG_SPL_NAND_MXS diff --git a/include/configs/imx8mp_venice.h b/include/configs/imx8mp_venice.h index d9baffb..fce87b1 100644 --- a/include/configs/imx8mp_venice.h +++ b/include/configs/imx8mp_venice.h @@ -15,7 +15,6 @@ #ifdef CONFIG_SPL_BUILD /* For RAW image gives a error info not panic */ -#define CONFIG_SPL_ABORT_ON_RAW_IMAGE #endif #define MEM_LAYOUT_ENV_SETTINGS \ diff --git a/include/configs/imx8mq_cm.h b/include/configs/imx8mq_cm.h index a242d5e..a5d6adf 100644 --- a/include/configs/imx8mq_cm.h +++ b/include/configs/imx8mq_cm.h @@ -20,7 +20,6 @@ /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ #define CONFIG_MALLOC_F_ADDR 0x182000 /* For RAW image gives a error info not panic */ -#define CONFIG_SPL_ABORT_ON_RAW_IMAGE #endif diff --git a/include/configs/imx8mq_evk.h b/include/configs/imx8mq_evk.h index 98ddb06..182f45b 100644 --- a/include/configs/imx8mq_evk.h +++ b/include/configs/imx8mq_evk.h @@ -21,7 +21,6 @@ /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ #define CONFIG_MALLOC_F_ADDR 0x182000 /* For RAW image gives a error info not panic */ -#define CONFIG_SPL_ABORT_ON_RAW_IMAGE #define CONFIG_POWER_PFUZE100 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 diff --git a/include/configs/imx8mq_phanbell.h b/include/configs/imx8mq_phanbell.h index 1b3c049..97bd504 100644 --- a/include/configs/imx8mq_phanbell.h +++ b/include/configs/imx8mq_phanbell.h @@ -18,7 +18,6 @@ /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ #define CONFIG_MALLOC_F_ADDR 0x182000 /* For RAW image gives a error info not panic */ -#define CONFIG_SPL_ABORT_ON_RAW_IMAGE #endif /* ENET Config */ diff --git a/include/configs/imx8qm_mek.h b/include/configs/imx8qm_mek.h index f4d19f8..b59502e 100644 --- a/include/configs/imx8qm_mek.h +++ b/include/configs/imx8qm_mek.h @@ -20,7 +20,6 @@ #define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE -#define CONFIG_SPL_ABORT_ON_RAW_IMAGE #endif #ifdef CONFIG_AHAB_BOOT diff --git a/include/configs/imx8qxp_mek.h b/include/configs/imx8qxp_mek.h index a6aabc7..511f6c8 100644 --- a/include/configs/imx8qxp_mek.h +++ b/include/configs/imx8qxp_mek.h @@ -18,7 +18,6 @@ #define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE -#define CONFIG_SPL_ABORT_ON_RAW_IMAGE #endif #ifdef CONFIG_AHAB_BOOT diff --git a/include/configs/imx8ulp_evk.h b/include/configs/imx8ulp_evk.h index 9870694..f908021 100644 --- a/include/configs/imx8ulp_evk.h +++ b/include/configs/imx8ulp_evk.h @@ -16,7 +16,6 @@ #ifdef CONFIG_SPL_BUILD #define CONFIG_MALLOC_F_ADDR 0x22040000 -#define CONFIG_SPL_ABORT_ON_RAW_IMAGE /* For RAW image gives a error info not panic */ #endif diff --git a/include/configs/kontron_pitx_imx8m.h b/include/configs/kontron_pitx_imx8m.h index 88aaa55..bf336b9 100644 --- a/include/configs/kontron_pitx_imx8m.h +++ b/include/configs/kontron_pitx_imx8m.h @@ -22,7 +22,6 @@ /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ #define CONFIG_MALLOC_F_ADDR 0x182000 /* For RAW image gives a error info not panic */ -#define CONFIG_SPL_ABORT_ON_RAW_IMAGE #define CONFIG_POWER_PFUZE100 diff --git a/include/configs/phycore_imx8mm.h b/include/configs/phycore_imx8mm.h index a14a076..f8c3e1f 100644 --- a/include/configs/phycore_imx8mm.h +++ b/include/configs/phycore_imx8mm.h @@ -20,7 +20,6 @@ /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ #define CONFIG_MALLOC_F_ADDR 0x930000 /* For RAW image gives a error info not panic */ -#define CONFIG_SPL_ABORT_ON_RAW_IMAGE #endif #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/phycore_imx8mp.h b/include/configs/phycore_imx8mp.h index 9c7331a..dd0b108 100644 --- a/include/configs/phycore_imx8mp.h +++ b/include/configs/phycore_imx8mp.h @@ -17,7 +17,6 @@ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) #ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_ABORT_ON_RAW_IMAGE #define CONFIG_POWER_PCA9450 diff --git a/include/configs/pico-imx8mq.h b/include/configs/pico-imx8mq.h index 25ad936..a587570 100644 --- a/include/configs/pico-imx8mq.h +++ b/include/configs/pico-imx8mq.h @@ -18,7 +18,6 @@ /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ #define CONFIG_MALLOC_F_ADDR 0x182000 /* For RAW image gives a error info not panic */ -#define CONFIG_SPL_ABORT_ON_RAW_IMAGE #endif /* ENET Config */ diff --git a/include/configs/verdin-imx8mm.h b/include/configs/verdin-imx8mm.h index 4fb0d69..afc507b 100644 --- a/include/configs/verdin-imx8mm.h +++ b/include/configs/verdin-imx8mm.h @@ -19,7 +19,6 @@ /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ #define CONFIG_MALLOC_F_ADDR 0x930000 /* For RAW image gives a error info not panic */ -#define CONFIG_SPL_ABORT_ON_RAW_IMAGE #endif #define MEM_LAYOUT_ENV_SETTINGS \ diff --git a/include/configs/verdin-imx8mp.h b/include/configs/verdin-imx8mp.h index 704a053..97f537e 100644 --- a/include/configs/verdin-imx8mp.h +++ b/include/configs/verdin-imx8mp.h @@ -19,7 +19,6 @@ /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ #define CONFIG_MALLOC_F_ADDR 0x184000 /* For RAW image gives a error info not panic */ -#define CONFIG_SPL_ABORT_ON_RAW_IMAGE #define CONFIG_POWER_PCA9450 -- cgit v1.1 From ee106eda7e93670214f4cf654fbc2b79ef22851d Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Sat, 11 Jun 2022 20:21:02 +0800 Subject: imx: imx8mm_beacon: enable pinctrl_wdog in SPL Mark pinctrl_wdog as u-boot,dm-spl to clean up board code, The set_wdog_reset() function is not necessary as this is handled by the imx_watchdog.c driver due to the 'fsl,ext-reset-output' property being set. Signed-off-by: Peng Fan --- arch/arm/dts/imx8mm-beacon-kit-u-boot.dtsi | 4 ++++ board/beacon/imx8mm/spl.c | 19 ------------------- 2 files changed, 4 insertions(+), 19 deletions(-) diff --git a/arch/arm/dts/imx8mm-beacon-kit-u-boot.dtsi b/arch/arm/dts/imx8mm-beacon-kit-u-boot.dtsi index e33e10a..c94b4ff 100644 --- a/arch/arm/dts/imx8mm-beacon-kit-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-beacon-kit-u-boot.dtsi @@ -73,6 +73,10 @@ u-boot,dm-spl; }; +&pinctrl_wdog { + u-boot,dm-spl; +}; + &uart2 { u-boot,dm-spl; }; diff --git a/board/beacon/imx8mm/spl.c b/board/beacon/imx8mm/spl.c index f92b4c3..a93cc93 100644 --- a/board/beacon/imx8mm/spl.c +++ b/board/beacon/imx8mm/spl.c @@ -59,23 +59,6 @@ int board_fit_config_name_match(const char *name) } #endif -#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE) - -static iomux_v3_cfg_t const wdog_pads[] = { - IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), -}; - -int board_early_init_f(void) -{ - struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; - - imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); - - set_wdog_reset(wdog); - - return 0; -} - static int power_init_board(void) { struct udevice *dev; @@ -116,8 +99,6 @@ void board_init_f(ulong dummy) init_uart_clk(1); - board_early_init_f(); - timer_init(); /* Clear the BSS. */ -- cgit v1.1 From 2d7f40cad589bb2b457f2e6a4f704f4a4967c61b Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Sat, 11 Jun 2022 20:21:03 +0800 Subject: imx: imx8mm-cl-iot-gate: enable pinctrl_wdog in SPL Mark pinctrl_wdog as u-boot,dm-spl to clean up board code, The set_wdog_reset() function is not necessary as this is handled by the imx_watchdog.c driver due to the 'fsl,ext-reset-output' property being set. Signed-off-by: Peng Fan --- arch/arm/dts/imx8mm-cl-iot-gate-u-boot.dtsi | 4 ++++ board/compulab/imx8mm-cl-iot-gate/spl.c | 19 ------------------- 2 files changed, 4 insertions(+), 19 deletions(-) diff --git a/arch/arm/dts/imx8mm-cl-iot-gate-u-boot.dtsi b/arch/arm/dts/imx8mm-cl-iot-gate-u-boot.dtsi index 433b02c..a7044b6 100644 --- a/arch/arm/dts/imx8mm-cl-iot-gate-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-cl-iot-gate-u-boot.dtsi @@ -84,6 +84,10 @@ u-boot,dm-spl; }; +&pinctrl_wdog { + u-boot,dm-spl; +}; + &uart3 { u-boot,dm-spl; }; diff --git a/board/compulab/imx8mm-cl-iot-gate/spl.c b/board/compulab/imx8mm-cl-iot-gate/spl.c index f183704..d2d2026 100644 --- a/board/compulab/imx8mm-cl-iot-gate/spl.c +++ b/board/compulab/imx8mm-cl-iot-gate/spl.c @@ -83,23 +83,6 @@ int board_fit_config_name_match(const char *name) } #endif -#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE) - -static iomux_v3_cfg_t const wdog_pads[] = { - IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), -}; - -int board_early_init_f(void) -{ - struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; - - imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); - - set_wdog_reset(wdog); - - return 0; -} - static int power_init_board(void) { struct udevice *dev; @@ -141,8 +124,6 @@ void board_init_f(ulong dummy) arch_cpu_init(); - board_early_init_f(); - init_uart_clk(2); timer_init(); -- cgit v1.1 From 333a6fa12f23bce206ccc9b06b00458f26486e26 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Sat, 11 Jun 2022 20:21:04 +0800 Subject: imx: engicam-imx8mm: drop unused macro Drop unused WDOG macro Signed-off-by: Peng Fan Reviewed-by: Michael Trimarchi --- board/engicam/imx8mm/spl.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/board/engicam/imx8mm/spl.c b/board/engicam/imx8mm/spl.c index f75f2dc..1846134 100644 --- a/board/engicam/imx8mm/spl.c +++ b/board/engicam/imx8mm/spl.c @@ -54,8 +54,6 @@ int board_fit_config_name_match(const char *name) } #endif -#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE) - int board_early_init_f(void) { return 0; -- cgit v1.1 From 6692cd967dbf343eb033153431f3d9290ce2d80f Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Sat, 11 Jun 2022 20:21:05 +0800 Subject: imx: imx8mm/n/p-venice: enable pinctrl_wdog in SPL Mark pinctrl_wdog as u-boot,dm-spl to clean up board code, The set_wdog_reset() function is not necessary as this is handled by the imx_watchdog.c driver due to the 'fsl,ext-reset-output' property being set. Signed-off-by: Peng Fan --- arch/arm/dts/imx8mm-venice-u-boot.dtsi | 4 ++++ arch/arm/dts/imx8mn-venice-u-boot.dtsi | 4 ++++ arch/arm/dts/imx8mp-venice-u-boot.dtsi | 4 ++++ board/gateworks/venice/spl.c | 29 ----------------------------- 4 files changed, 12 insertions(+), 29 deletions(-) diff --git a/arch/arm/dts/imx8mm-venice-u-boot.dtsi b/arch/arm/dts/imx8mm-venice-u-boot.dtsi index c61c6de..68978a0 100644 --- a/arch/arm/dts/imx8mm-venice-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-venice-u-boot.dtsi @@ -72,3 +72,7 @@ &wdog1 { u-boot,dm-spl; }; + +&pinctrl_wdog { + u-boot,dm-spl; +}; diff --git a/arch/arm/dts/imx8mn-venice-u-boot.dtsi b/arch/arm/dts/imx8mn-venice-u-boot.dtsi index 4f23da3..3581955 100644 --- a/arch/arm/dts/imx8mn-venice-u-boot.dtsi +++ b/arch/arm/dts/imx8mn-venice-u-boot.dtsi @@ -110,6 +110,10 @@ u-boot,dm-spl; }; +&pinctrl_wdog { + u-boot,dm-spl; +}; + &binman { u-boot-spl-ddr { align = <4>; diff --git a/arch/arm/dts/imx8mp-venice-u-boot.dtsi b/arch/arm/dts/imx8mp-venice-u-boot.dtsi index 37f3edc..96b9fa8 100644 --- a/arch/arm/dts/imx8mp-venice-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-venice-u-boot.dtsi @@ -72,3 +72,7 @@ &wdog1 { u-boot,dm-spl; }; + +&pinctrl_wdog { + u-boot,dm-spl; +}; diff --git a/board/gateworks/venice/spl.c b/board/gateworks/venice/spl.c index 6e6ce01..4c0feb4 100644 --- a/board/gateworks/venice/spl.c +++ b/board/gateworks/venice/spl.c @@ -87,33 +87,6 @@ static void spl_dram_init(int size) ddr_init(dram_timing); } -#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE) - -#ifdef CONFIG_IMX8MM -static iomux_v3_cfg_t const wdog_pads[] = { - IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), -}; -#elif CONFIG_IMX8MN -static const iomux_v3_cfg_t wdog_pads[] = { - IMX8MN_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), -}; -#elif CONFIG_IMX8MP -static const iomux_v3_cfg_t wdog_pads[] = { - MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), -}; -#endif - -int board_early_init_f(void) -{ - struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; - - imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); - - set_wdog_reset(wdog); - - return 0; -} - /* * Model specific PMIC adjustments necessary prior to DRAM init * @@ -253,8 +226,6 @@ void board_init_f(ulong dummy) init_uart_clk(1); - board_early_init_f(); - timer_init(); /* Clear the BSS. */ -- cgit v1.1 From cbda080ae95c029a40a8d6a3641451900dffed9e Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Sat, 11 Jun 2022 20:21:06 +0800 Subject: imx: imx8mn-beacon: enable pinctrl_wdog in SPL Mark pinctrl_wdog as u-boot,dm-spl to clean up board code, The set_wdog_reset() function is not necessary as this is handled by the imx_watchdog.c driver due to the 'fsl,ext-reset-output' property being set. Signed-off-by: Peng Fan --- arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi | 4 ++++ board/beacon/imx8mn/spl.c | 10 ---------- 2 files changed, 4 insertions(+), 10 deletions(-) diff --git a/arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi b/arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi index 69fd69c..eb1dd8d 100644 --- a/arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi +++ b/arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi @@ -132,6 +132,10 @@ u-boot,dm-spl; }; +&pinctrl_wdog { + u-boot,dm-spl; +}; + &binman { u-boot-spl-ddr { filename = "u-boot-spl-ddr.bin"; diff --git a/board/beacon/imx8mn/spl.c b/board/beacon/imx8mn/spl.c index 4563446..029f71b 100644 --- a/board/beacon/imx8mn/spl.c +++ b/board/beacon/imx8mn/spl.c @@ -68,27 +68,17 @@ int board_fit_config_name_match(const char *name) } #endif -#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE) #define PWM1_PAD_CTRL (PAD_CTL_FSEL2 | PAD_CTL_DSE6) static iomux_v3_cfg_t const pwm_pads[] = { IMX8MN_PAD_GPIO1_IO01__PWM1_OUT | MUX_PAD_CTRL(PWM1_PAD_CTRL), }; -static iomux_v3_cfg_t const wdog_pads[] = { - IMX8MN_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), -}; - int board_early_init_f(void) { - struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; - /* Claiming pwm pins prevents LCD flicker during startup*/ imx_iomux_v3_setup_multiple_pads(pwm_pads, ARRAY_SIZE(pwm_pads)); - imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); - set_wdog_reset(wdog); - init_uart_clk(1); return 0; -- cgit v1.1 From ae75489c48132efc6c9ece91773a0cd1c7a59e15 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Sat, 11 Jun 2022 20:21:07 +0800 Subject: imx: imx8mn_var_som: clean up board watchdog code pinctrl_wdog already marked u-boot,dm-spl, so clean up board code. The set_wdog_reset() function is not necessary as this is handled by the imx_watchdog.c driver due to the 'fsl,ext-reset-output' property being set. Signed-off-by: Peng Fan Tested-by: Ariel D'Alessandro --- board/variscite/imx8mn_var_som/spl.c | 11 ----------- 1 file changed, 11 deletions(-) diff --git a/board/variscite/imx8mn_var_som/spl.c b/board/variscite/imx8mn_var_som/spl.c index 1a8b64f..41e7050 100644 --- a/board/variscite/imx8mn_var_som/spl.c +++ b/board/variscite/imx8mn_var_som/spl.c @@ -40,19 +40,8 @@ void spl_board_init(void) puts("Failed to find clock node. Check device tree\n"); } -#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE) - -static const iomux_v3_cfg_t wdog_pads[] = { - IMX8MN_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), -}; - int board_early_init_f(void) { - struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; - - imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); - set_wdog_reset(wdog); - init_uart_clk(3); return 0; -- cgit v1.1 From 722e2b9a2b154cd05495b19b799ab784bfb3ab53 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Sat, 11 Jun 2022 20:21:08 +0800 Subject: imx: imx8mp_rsb7320a1: enable wdog driver model in SPL Mark wdog1/pinctrl_wdog as u-boot,dm-spl to clean up board code, The set_wdog_reset() function is not necessary as this is handled by the imx_watchdog.c driver due to the 'fsl,ext-reset-output' property being set. Signed-off-by: Peng Fan --- arch/arm/dts/imx8mp-rsb3720-a1-u-boot.dtsi | 8 ++++++++ board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c | 12 ------------ 2 files changed, 8 insertions(+), 12 deletions(-) diff --git a/arch/arm/dts/imx8mp-rsb3720-a1-u-boot.dtsi b/arch/arm/dts/imx8mp-rsb3720-a1-u-boot.dtsi index 2848b24..4419967 100644 --- a/arch/arm/dts/imx8mp-rsb3720-a1-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-rsb3720-a1-u-boot.dtsi @@ -89,6 +89,14 @@ u-boot,dm-spl; }; +&wdog1 { + u-boot,dm-spl; +}; + +&pinctrl_wdog { + u-boot,dm-spl; +}; + &pinctrl_i2c1 { u-boot,dm-spl; }; diff --git a/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c b/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c index f129ebd..0a1b2c9 100644 --- a/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c +++ b/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c @@ -28,12 +28,6 @@ DECLARE_GLOBAL_DATA_PTR; -#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE) - -static const iomux_v3_cfg_t wdog_pads[] = { - MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), -}; - #ifdef CONFIG_NAND_MXS static void setup_gpmi_nand(void) { @@ -69,12 +63,6 @@ u8 num_image_type_guids = ARRAY_SIZE(fw_images); int board_early_init_f(void) { - struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; - - imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); - - set_wdog_reset(wdog); - init_uart_clk(2); return 0; -- cgit v1.1 From 4152ea24f2f2aabcbcfd584c474fb9bb19243bbe Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Sat, 11 Jun 2022 20:21:09 +0800 Subject: imx: imx8mn-kontron-n801x: enable pinctrl_wdog in SPL Mark pinctrl_wdog as u-boot,dm-spl to clean up board code, The set_wdog_reset() function is not necessary as this is handled by the imx_watchdog.c driver due to the 'fsl,ext-reset-output' property being set. Signed-off-by: Peng Fan Reviewed-by: Frieder Schrempf Tested-by: Frieder Schrempf --- arch/arm/dts/imx8mm-kontron-n801x-u-boot.dtsi | 4 ++++ board/kontron/sl-mx8mm/spl.c | 18 ------------------ 2 files changed, 4 insertions(+), 18 deletions(-) diff --git a/arch/arm/dts/imx8mm-kontron-n801x-u-boot.dtsi b/arch/arm/dts/imx8mm-kontron-n801x-u-boot.dtsi index 22d18e6..6882513 100644 --- a/arch/arm/dts/imx8mm-kontron-n801x-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-kontron-n801x-u-boot.dtsi @@ -126,3 +126,7 @@ &wdog1 { u-boot,dm-spl; }; + +&pinctrl_wdog { + u-boot,dm-spl; +}; diff --git a/board/kontron/sl-mx8mm/spl.c b/board/kontron/sl-mx8mm/spl.c index a58a75d..63361f1 100644 --- a/board/kontron/sl-mx8mm/spl.c +++ b/board/kontron/sl-mx8mm/spl.c @@ -32,7 +32,6 @@ enum { #define GPIO_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE) #define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE) -#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE) #define TOUCH_RESET_GPIO IMX_GPIO_NR(3, 23) @@ -50,10 +49,6 @@ static iomux_v3_cfg_t const touch_gpio[] = { IMX8MM_PAD_SAI5_RXD2_GPIO3_IO23 | MUX_PAD_CTRL(GPIO_PAD_CTRL) }; -static iomux_v3_cfg_t const wdog_pads[] = { - IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), -}; - int spl_board_boot_device(enum boot_device boot_dev_spl) { switch (boot_dev_spl) { @@ -216,17 +211,6 @@ void spl_board_init(void) printf("Failed to find clock node. Check device tree\n"); } -int board_early_init_f(void) -{ - struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; - - imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); - - set_wdog_reset(wdog); - - return 0; -} - static int power_init_board(void) { struct udevice *dev; @@ -261,8 +245,6 @@ void board_init_f(ulong dummy) init_uart_clk(2); - board_early_init_f(); - timer_init(); /* Clear the BSS. */ -- cgit v1.1 From e8780d2380ac51c824c3bb3b1e07aee37babda9e Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Sat, 11 Jun 2022 20:21:10 +0800 Subject: imx: phycore_imx8mm/p: clean up board watchdog code pinctrl_wdog already marked u-boot,dm-spl, so clean up board code. The set_wdog_reset() function is not necessary as this is handled by the imx_watchdog.c driver due to the 'fsl,ext-reset-output' property being set. Signed-off-by: Peng Fan Tested-by: Teresa Remmet --- board/phytec/phycore_imx8mm/spl.c | 19 ------------------- board/phytec/phycore_imx8mp/spl.c | 19 ------------------- 2 files changed, 38 deletions(-) diff --git a/board/phytec/phycore_imx8mm/spl.c b/board/phytec/phycore_imx8mm/spl.c index 7f24a3a..d87ab6d 100644 --- a/board/phytec/phycore_imx8mm/spl.c +++ b/board/phytec/phycore_imx8mm/spl.c @@ -57,23 +57,6 @@ int board_fit_config_name_match(const char *name) return 0; } -#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE) - -static iomux_v3_cfg_t const wdog_pads[] = { - IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), -}; - -int board_early_init_f(void) -{ - struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; - - imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); - - set_wdog_reset(wdog); - - return 0; -} - void board_init_f(ulong dummy) { int ret; @@ -82,8 +65,6 @@ void board_init_f(ulong dummy) init_uart_clk(2); - board_early_init_f(); - /* Clear the BSS. */ memset(__bss_start, 0, __bss_end - __bss_start); diff --git a/board/phytec/phycore_imx8mp/spl.c b/board/phytec/phycore_imx8mp/spl.c index 38a581b..faed6fc 100644 --- a/board/phytec/phycore_imx8mp/spl.c +++ b/board/phytec/phycore_imx8mp/spl.c @@ -89,23 +89,6 @@ int board_fit_config_name_match(const char *name) return 0; } -#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE) - -static iomux_v3_cfg_t const wdog_pads[] = { - MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), -}; - -int board_early_init_f(void) -{ - struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; - - imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); - - set_wdog_reset(wdog); - - return 0; -} - void board_init_f(ulong dummy) { int ret; @@ -114,8 +97,6 @@ void board_init_f(ulong dummy) init_uart_clk(0); - board_early_init_f(); - ret = spl_early_init(); if (ret) { debug("spl_early_init() failed: %d\n", ret); -- cgit v1.1