From 9fc5e19c2e6f9cc71c66faea67accaf77f0c13e8 Mon Sep 17 00:00:00 2001 From: Bryan Brattlof Date: Thu, 7 Dec 2023 10:52:10 -0600 Subject: arm: mach-k3: j72xx: add new 'virtual' mux In order for the Cortex-A72s to operate at different frequencies other than the default 2GHz, add in a new 'virtual' mux (a mux that does not physically exist in the clock tree) that can be selected. CC: Vishal Mahaveer Signed-off-by: Bryan Brattlof Signed-off-by: Apurva Nandan Signed-off-by: Reid Tonking Reviewed-by: Udit Kumar --- arch/arm/mach-k3/j7200/clk-data.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-k3/j7200/clk-data.c b/arch/arm/mach-k3/j7200/clk-data.c index 9b45786..eb8436d 100644 --- a/arch/arm/mach-k3/j7200/clk-data.c +++ b/arch/arm/mach-k3/j7200/clk-data.c @@ -141,6 +141,11 @@ static const char * const k3_pll_ctrl_wrap_main_0_sysclkout_clk_parents[] = { "hsdiv4_16fft_main_0_hsdivout0_clk", }; +static const char * const main_pll8_sel_extwave_out0_parents[] = { + "pllfracf_ssmod_16fft_main_8_foutvcop_clk", + "hsdiv0_16fft_main_8_hsdivout0_clk", +}; + static const char * const mcu_obsclk_outmux_out0_parents[] = { "mcu_obsclk_div_out0", "gluelogic_hfosc0_clkout", @@ -396,6 +401,7 @@ static const struct clk_data clk_list[] = { CLK_DIV("hsdiv4_16fft_main_3_hsdivout2_clk", "pllfracf_ssmod_16fft_main_3_foutvcop_clk", 0x683088, 0, 7, 0, 0), CLK_MUX_PLLCTRL("k3_pll_ctrl_wrap_main_0_sysclkout_clk", k3_pll_ctrl_wrap_main_0_sysclkout_clk_parents, 2, 0x410000, 0), CLK_DIV("k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk", "k3_pll_ctrl_wrap_main_0_sysclkout_clk", 0x410118, 0, 5, 0, 0), + CLK_MUX("main_pll8_sel_extwave_out0", main_pll8_sel_extwave_out0_parents, 2, 0x688040, 0, 1, 0), CLK_DIV("mcu_obsclk_div_out0", "wkup_obsclk_mux_out0", 0x43008000, 8, 4, 0, 0), CLK_MUX("mcu_obsclk_outmux_out0", mcu_obsclk_outmux_out0_parents, 2, 0x43008000, 24, 1, 0), CLK_PLL("pllfracf_ssmod_16fft_main_4_foutvcop_clk", "main_pll4_xref_sel_out0", 0x684000, 0), @@ -545,11 +551,14 @@ static const struct dev_clk soc_dev_clk_data[] = { DEV_CLK(288, 14, "board_0_hfosc1_clk_out"), DEV_CLK(288, 15, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), DEV_CLK(288, 17, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(323, 0, "main_pll8_sel_extwave_out0"), + DEV_CLK(323, 1, "pllfracf_ssmod_16fft_main_8_foutvcop_clk"), + DEV_CLK(323, 2, "hsdiv0_16fft_main_8_hsdivout0_clk"), }; const struct ti_k3_clk_platdata j7200_clk_platdata = { .clk_list = clk_list, - .clk_list_cnt = 109, + .clk_list_cnt = ARRAY_SIZE(clk_list), .soc_dev_clk_data = soc_dev_clk_data, - .soc_dev_clk_data_cnt = 129, + .soc_dev_clk_data_cnt = ARRAY_SIZE(soc_dev_clk_data), }; -- cgit v1.1 From 3d6cb0390557b7cbc90c5e548072f3c3497f3873 Mon Sep 17 00:00:00 2001 From: Reid Tonking Date: Thu, 7 Dec 2023 10:52:11 -0600 Subject: arm: dts: k3-j7200-r5-common-proc-board: Set parent clock for clock ID 323 Previously, dynamic frequency scaling supported rates only through fixed divison. This virtual clock mux configuration enables more varied rates on A72 clock ID 202 by setting up the required register. Reviewed-by: Udit Kumar Signed-off-by: Apurva Nandan Signed-off-by: Reid Tonking --- arch/arm/dts/k3-j7200-r5-common-proc-board.dts | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts index f0a7360..018faaa 100644 --- a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts +++ b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts @@ -24,7 +24,8 @@ <&k3_pds 4 TI_SCI_PD_EXCLUSIVE>; resets = <&k3_reset 202 0>; clocks = <&k3_clks 61 1>; - assigned-clocks = <&k3_clks 202 2>, <&k3_clks 61 1>; + assigned-clocks = <&k3_clks 202 2>, <&k3_clks 61 1>, <&k3_clks 323 0>; + assigned-clock-parents= <0>, <0>, <&k3_clks 323 2>; assigned-clock-rates = <2000000000>, <200000000>; ti,sci = <&dmsc>; ti,sci-proc-id = <32>; -- cgit v1.1