From 1b7de4f9efd7df1c82948c2b7b7a8cc4ed1577e3 Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Fri, 28 Jul 2023 15:54:15 +0200 Subject: riscv: qemu: imply CONFIG_DM_RNG The EFI_RNG_PROTOCOL is needed for Linux' KASLR. QEMU can provide a virtio-rng device to emulate a hardware random number generator which is supported by our virtio_rng driver. Enabling CONFIG_DM_RNG will enable CONFIG_VIRTIO_RNG and CONFIG_EFI_RNG_PROTOCOL by default too. Signed-off-by: Heinrich Schuchardt Reviewed-by: Bin Meng --- board/emulation/qemu-riscv/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/board/emulation/qemu-riscv/Kconfig b/board/emulation/qemu-riscv/Kconfig index b503578..d56b4b5 100644 --- a/board/emulation/qemu-riscv/Kconfig +++ b/board/emulation/qemu-riscv/Kconfig @@ -57,6 +57,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy imply NVME imply PCI imply PCIE_ECAM_GENERIC + imply DM_RNG imply SCSI imply DM_SCSI imply SYS_NS16550 -- cgit v1.1 From 6982e6b04672440fce0eed93679aea89a024779f Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Wed, 2 Aug 2023 22:39:46 +0200 Subject: cmd/sbi: display new extensions The SBI specification v2.0-rc2 defines new extensions: * Nested Acceleration Extension (NACL) * Steal Time Accounting (STA) Allow the sbi command to display these. Add missing implementation IDs. Signed-off-by: Heinrich Schuchardt Reviewed-by: Leo Yu-Chi Liang --- arch/riscv/include/asm/sbi.h | 2 ++ cmd/riscv/sbi.c | 4 ++++ 2 files changed, 6 insertions(+) diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index 7693699..009a268 100644 --- a/arch/riscv/include/asm/sbi.h +++ b/arch/riscv/include/asm/sbi.h @@ -31,6 +31,8 @@ enum sbi_ext_id { SBI_EXT_DBCN = 0x4442434E, SBI_EXT_SUSP = 0x53555350, SBI_EXT_CPPC = 0x43505043, + SBI_EXT_NACL = 0x4E41434C, + SBI_EXT_STA = 0x535441, }; enum sbi_ext_base_fid { diff --git a/cmd/riscv/sbi.c b/cmd/riscv/sbi.c index c4707fe..32761c5 100644 --- a/cmd/riscv/sbi.c +++ b/cmd/riscv/sbi.c @@ -27,6 +27,8 @@ static struct sbi_imp implementations[] = { { 4, "RustSBI" }, { 5, "Diosix" }, { 6, "Coffer" }, + { 7, "Xen Project" }, + { 8, "PolarFire Hart Software Services" }, }; static struct sbi_ext extensions[] = { @@ -49,6 +51,8 @@ static struct sbi_ext extensions[] = { { SBI_EXT_DBCN, "Debug Console Extension" }, { SBI_EXT_SUSP, "System Suspend Extension" }, { SBI_EXT_CPPC, "Collaborative Processor Performance Control Extension" }, + { SBI_EXT_NACL, "Nested Acceleration Extension" }, + { SBI_EXT_STA, "Steal-time Accounting Extension" }, }; static int do_sbi(struct cmd_tbl *cmdtp, int flag, int argc, -- cgit v1.1 From 8d184d4b652bad455e17d2d0e451c0e08e112f34 Mon Sep 17 00:00:00 2001 From: Minda Chen Date: Mon, 7 Aug 2023 16:53:35 +0800 Subject: pci: plda: Get correct ECAM offset in multiple PCIe RC case Get the correct ECAM offset and record the secondary bus number in Multiple RC case. Signed-off-by: Minda Chen Reviewed-by: Leo Yu-Chi Liang --- drivers/pci/pcie_plda_common.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/pci/pcie_plda_common.c b/drivers/pci/pcie_plda_common.c index 005b926..cd74bb4 100644 --- a/drivers/pci/pcie_plda_common.c +++ b/drivers/pci/pcie_plda_common.c @@ -36,8 +36,8 @@ static int plda_pcie_conf_address(const struct udevice *udev, pci_dev_t bdf, uint offset, void **paddr) { struct pcie_plda *priv = dev_get_priv(udev); - int where = PCIE_ECAM_OFFSET(PCI_BUS(bdf), PCI_DEV(bdf), - PCI_FUNC(bdf), offset); + int where = PCIE_ECAM_OFFSET(PCI_BUS(bdf) - dev_seq(udev), + PCI_DEV(bdf), PCI_FUNC(bdf), offset); if (!plda_pcie_addr_valid(priv, bdf)) return -ENODEV; @@ -71,6 +71,7 @@ int plda_pcie_config_write(struct udevice *udev, pci_dev_t bdf, (offset == PCI_PRIMARY_BUS && size != PCI_SIZE_8))) { priv->sec_busno = ((offset == PCI_PRIMARY_BUS) ? (value >> 8) : value) & 0xff; + priv->sec_busno += dev_seq(udev); debug("Secondary bus number was changed to %d\n", priv->sec_busno); } -- cgit v1.1 From 1037c5ba3702996d854becb3e719d44d2178c1bf Mon Sep 17 00:00:00 2001 From: Minda Chen Date: Mon, 7 Aug 2023 16:53:36 +0800 Subject: riscv: dts: starfive: Enable pcie0 dts node In StarFive VF2 board. pcie0 connect to VTI usb controller. Enable it to support usb host. Signed-off-by: Minda Chen Reviewed-by: Leo Yu-Chi Liang --- arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi index bf7fdb4..e40f57a 100644 --- a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi +++ b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi @@ -311,7 +311,7 @@ &pcie0 { reset-gpios = <&sysgpio 26 GPIO_ACTIVE_LOW>; - status = "disabled"; + status = "okay"; }; &pcie1 { -- cgit v1.1 From eca2d41c681466c229fc0b4372432db71745c826 Mon Sep 17 00:00:00 2001 From: Minda Chen Date: Mon, 7 Aug 2023 16:53:37 +0800 Subject: riscv: starfive: Add SYS_CACHE_SHIFT_6 to enable SYS_CACHELINE_SIZE Some device driver need SYS_CACHELINE_SIZE macro. Add StarFive SYS_CACHE_SHIFT_6 to enable it. Signed-off-by: Minda Chen Reviewed-by: Bin Meng Reviewed-by: Leo Yu-Chi Liang --- arch/riscv/cpu/jh7110/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/cpu/jh7110/Kconfig b/arch/riscv/cpu/jh7110/Kconfig index 4d95811..c1d3e6a 100644 --- a/arch/riscv/cpu/jh7110/Kconfig +++ b/arch/riscv/cpu/jh7110/Kconfig @@ -13,6 +13,7 @@ config STARFIVE_JH7110 select SUPPORT_SPL select SPL_RAM if SPL select SPL_STARFIVE_DDR + select SYS_CACHE_SHIFT_6 select PINCTRL_STARFIVE_JH7110 imply MMC imply MMC_BROKEN_CD -- cgit v1.1 From 0665621386cd907d6a3e3527a3c6636aee10ed04 Mon Sep 17 00:00:00 2001 From: Minda Chen Date: Mon, 7 Aug 2023 16:53:38 +0800 Subject: configs: riscv: starfive: Add VF2 PCIe USB3 XHCI support Add XHCI_PCI to enable usb3-host functions. Also add usb command and keyboard config. Signed-off-by: Minda Chen Reviewed-by: Leo Yu-Chi Liang --- configs/starfive_visionfive2_defconfig | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/configs/starfive_visionfive2_defconfig b/configs/starfive_visionfive2_defconfig index 5d8a8e2..a70ada3 100644 --- a/configs/starfive_visionfive2_defconfig +++ b/configs/starfive_visionfive2_defconfig @@ -65,6 +65,7 @@ CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_MEMINFO=y CONFIG_CMD_I2C=y CONFIG_CMD_PCI=y +CONFIG_CMD_USB=y CONFIG_CMD_TFTPPUT=y CONFIG_OF_BOARD=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y @@ -111,3 +112,7 @@ CONFIG_PINCTRL_STARFIVE=y CONFIG_SYS_NS16550=y CONFIG_CADENCE_QSPI=y CONFIG_TIMER_EARLY=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_PCI=y +CONFIG_USB_KEYBOARD=y -- cgit v1.1 From 7d79bed00c9e02187a09e74e90c5bd5a927a6a61 Mon Sep 17 00:00:00 2001 From: Shengyu Qu Date: Tue, 8 Aug 2023 21:14:36 +0800 Subject: configs: starfive: Enable environment in SPI flash support On Starfive Visionfive 2, the u-boot environment settings are saved to on-board SPI flash. Enable relative configs by default and set offset and size according to upstream linux dts. Signed-off-by: Shengyu Qu Reviewed-by: Leo Yu-Chi Liang --- configs/starfive_visionfive2_defconfig | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/configs/starfive_visionfive2_defconfig b/configs/starfive_visionfive2_defconfig index a70ada3..e9b63e5 100644 --- a/configs/starfive_visionfive2_defconfig +++ b/configs/starfive_visionfive2_defconfig @@ -6,6 +6,15 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80000000 CONFIG_SF_DEFAULT_SPEED=100000000 +CONFIG_ENV_SUPPORT=y +CONFIG_SAVEENV=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_ENV_SECT_SIZE_AUTO=y +CONFIG_ENV_SIZE=0x10000 +CONFIG_ENV_OFFSET=0xf0000 +CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_SPL_DM_SPI=y CONFIG_DEFAULT_DEVICE_TREE="jh7110-starfive-visionfive-2" CONFIG_SPL_TEXT_BASE=0x8000000 -- cgit v1.1 From d365f6646aa4ecaabc58c07ecc432a3177f13138 Mon Sep 17 00:00:00 2001 From: Shengyu Qu Date: Wed, 9 Aug 2023 21:11:31 +0800 Subject: riscv: Kconfig: Add SPL_ZERO_MEM_BEFORE_USE Add a Kconfig item to allow SPL to clear stack/GD/malloc area before using them. Signed-off-by: Bo Gan Signed-off-by: Shengyu Qu Reviewed-by: Leo Yu-Chi Liang --- arch/riscv/Kconfig | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 867cbcb..6771d8d 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -64,6 +64,14 @@ config SPL_SYS_DCACHE_OFF help Do not enable data cache in SPL. +config SPL_ZERO_MEM_BEFORE_USE + bool "Zero memory before use" + depends on SPL + default n + help + Zero stack/GD/malloc area in SPL before using them, this is needed for + Sifive core devices that uses L2 cache to store SPL. + # board-specific options below source "board/AndesTech/ae350/Kconfig" source "board/emulation/qemu-riscv/Kconfig" -- cgit v1.1 From 6419f8e9fdc63ee411e1f012d412f8ae17283432 Mon Sep 17 00:00:00 2001 From: Shengyu Qu Date: Wed, 9 Aug 2023 21:11:32 +0800 Subject: riscv: Add SPL_ZERO_MEM_BEFORE_USE implementation Add the actual support code for SPL_ZERO_MEM_BEFORE_USE and remove existing Starfive JH7110's L2 LIM clean code, since existing code has following issues: 1. Each hart (in the middle of a function call) overwriting its own stack and other harts' stacks. (data-race and data-corruption) 2. Lottery winner hart can be doing "board_init_f_init_reserve", while other harts are in the middle of zeroing L2 LIM. (data-race) Signed-off-by: Bo Gan Signed-off-by: Shengyu Qu Reviewed-by: Leo Yu-Chi Liang --- arch/riscv/cpu/jh7110/spl.c | 25 ------------------------- arch/riscv/cpu/start.S | 12 ++++++++++++ common/init/board_init.c | 3 +++ 3 files changed, 15 insertions(+), 25 deletions(-) diff --git a/arch/riscv/cpu/jh7110/spl.c b/arch/riscv/cpu/jh7110/spl.c index 72adcef..4047b10 100644 --- a/arch/riscv/cpu/jh7110/spl.c +++ b/arch/riscv/cpu/jh7110/spl.c @@ -13,7 +13,6 @@ #include #define CSR_U74_FEATURE_DISABLE 0x7c1 -#define L2_LIM_MEM_END 0x81FFFFFUL DECLARE_GLOBAL_DATA_PTR; @@ -59,9 +58,6 @@ int spl_soc_init(void) void harts_early_init(void) { - ulong *ptr; - u8 *tmp; - ulong len, remain; /* * Feature Disable CSR * @@ -70,25 +66,4 @@ void harts_early_init(void) */ if (CONFIG_IS_ENABLED(RISCV_MMODE)) csr_write(CSR_U74_FEATURE_DISABLE, 0); - - /* clear L2 LIM memory - * set __bss_end to 0x81FFFFF region to zero - * The L2 Cache Controller supports ECC. ECC is applied to SRAM. - * If it is not cleared, the ECC part is invalid, and an ECC error - * will be reported when reading data. - */ - ptr = (ulong *)&__bss_end; - len = L2_LIM_MEM_END - (ulong)&__bss_end; - remain = len % sizeof(ulong); - len /= sizeof(ulong); - - while (len--) - *ptr++ = 0; - - /* clear the remain bytes */ - if (remain) { - tmp = (u8 *)ptr; - while (remain--) - *tmp++ = 0; - } } diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index 59d58a5..30cf674 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -111,6 +111,18 @@ call_board_init_f: * It's essential before any function call, otherwise, we get data-race. */ +/* clear stack if necessary */ +#if CONFIG_IS_ENABLED(ZERO_MEM_BEFORE_USE) +clear_stack: + li t1, 1 + slli t1, t1, CONFIG_STACK_SIZE_SHIFT + sub t1, sp, t1 +clear_stack_loop: + SREG zero, 0(t1) /* t1 is always 16 byte aligned */ + addi t1, t1, REGBYTES + blt t1, sp, clear_stack_loop +#endif + call_board_init_f_0: /* find top of reserve space */ #if CONFIG_IS_ENABLED(SMP) diff --git a/common/init/board_init.c b/common/init/board_init.c index 96ffb79..ab8c508 100644 --- a/common/init/board_init.c +++ b/common/init/board_init.c @@ -162,6 +162,9 @@ void board_init_f_init_reserve(ulong base) #if CONFIG_VAL(SYS_MALLOC_F_LEN) /* go down one 'early malloc arena' */ gd->malloc_base = base; +#if CONFIG_IS_ENABLED(ZERO_MEM_BEFORE_USE) + memset((void *)base, '\0', CONFIG_VAL(SYS_MALLOC_F_LEN)); +#endif #endif if (CONFIG_IS_ENABLED(SYS_REPORT_STACK_F_USAGE)) -- cgit v1.1 From 47ed15125cccd98e041cdff3b6bbe675a2418ec2 Mon Sep 17 00:00:00 2001 From: Shengyu Qu Date: Wed, 9 Aug 2023 21:11:33 +0800 Subject: riscv: cpu: jh7110: Select SPL_ZERO_MEM_BEFORE_USE Add Kconfig item for Starfive JH7110 to select SPL_ZERO_MEM_BEFORE_USE. Signed-off-by: Bo Gan Signed-off-by: Shengyu Qu Reviewed-by: Leo Yu-Chi Liang --- arch/riscv/cpu/jh7110/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/cpu/jh7110/Kconfig b/arch/riscv/cpu/jh7110/Kconfig index c1d3e6a..8469ee7 100644 --- a/arch/riscv/cpu/jh7110/Kconfig +++ b/arch/riscv/cpu/jh7110/Kconfig @@ -14,6 +14,7 @@ config STARFIVE_JH7110 select SPL_RAM if SPL select SPL_STARFIVE_DDR select SYS_CACHE_SHIFT_6 + select SPL_ZERO_MEM_BEFORE_USE select PINCTRL_STARFIVE_JH7110 imply MMC imply MMC_BROKEN_CD -- cgit v1.1