From b168591c899e869dc4fcd71752cbe32c91355348 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 3 May 2018 09:30:16 +0200 Subject: usb: xhci: zynqmp: Fix header location There is no reason to specify header with full soc name. Symlink is setup automatically (arch -> arch-zynqmp) Signed-off-by: Michal Simek --- drivers/usb/host/xhci-zynqmp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/usb/host/xhci-zynqmp.c b/drivers/usb/host/xhci-zynqmp.c index 7fe5428..e44e1ae 100644 --- a/drivers/usb/host/xhci-zynqmp.c +++ b/drivers/usb/host/xhci-zynqmp.c @@ -13,7 +13,7 @@ #include #include #include -#include +#include #include #include #include "xhci.h" -- cgit v1.1 From d348beaa63fa86d298e76d18c6699b14cbcc0f0f Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 17 May 2018 14:06:06 +0200 Subject: arm64: zynqmp: Show reset reason Read reset reason reg and show it in log and also save it as variable. Clearing reset reason when it is read to show only one status Signed-off-by: Michal Simek --- arch/arm/include/asm/arch-zynqmp/hardware.h | 12 +++++++- board/xilinx/zynqmp/zynqmp.c | 43 +++++++++++++++++++++++++++++ 2 files changed, 54 insertions(+), 1 deletion(-) diff --git a/arch/arm/include/asm/arch-zynqmp/hardware.h b/arch/arm/include/asm/arch-zynqmp/hardware.h index acc6825..f317250 100644 --- a/arch/arm/include/asm/arch-zynqmp/hardware.h +++ b/arch/arm/include/asm/arch-zynqmp/hardware.h @@ -30,6 +30,14 @@ #define PS_MODE2 BIT(2) #define PS_MODE3 BIT(3) +#define RESET_REASON_DEBUG_SYS BIT(6) +#define RESET_REASON_SOFT BIT(5) +#define RESET_REASON_SRST BIT(4) +#define RESET_REASON_PSONLY BIT(3) +#define RESET_REASON_PMU BIT(2) +#define RESET_REASON_INTERNAL BIT(1) +#define RESET_REASON_EXTERNAL BIT(0) + struct crlapb_regs { u32 reserved0[36]; u32 cpu_r5_ctrl; /* 0x90 */ @@ -37,7 +45,9 @@ struct crlapb_regs { u32 timestamp_ref_ctrl; /* 0x128 */ u32 reserved2[53]; u32 boot_mode; /* 0x200 */ - u32 reserved3[14]; + u32 reserved3_0[7]; + u32 reset_reason; /* 0x220 */ + u32 reserved3_1[6]; u32 rst_lpd_top; /* 0x23C */ u32 reserved4[4]; u32 boot_pin_ctrl; /* 0x250 */ diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index e41fec3..d3450ef 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -449,6 +449,47 @@ void reset_cpu(ulong addr) { } +static const struct { + u32 bit; + const char *name; +} reset_reasons[] = { + { RESET_REASON_DEBUG_SYS, "DEBUG" }, + { RESET_REASON_SOFT, "SOFT" }, + { RESET_REASON_SRST, "SRST" }, + { RESET_REASON_PSONLY, "PS-ONLY" }, + { RESET_REASON_PMU, "PMU" }, + { RESET_REASON_INTERNAL, "INTERNAL" }, + { RESET_REASON_EXTERNAL, "EXTERNAL" }, + {} +}; + +static u32 reset_reason(void) +{ + u32 ret; + int i; + const char *reason = NULL; + + ret = readl(&crlapb_base->reset_reason); + + puts("Reset reason:\t"); + + for (i = 0; i < ARRAY_SIZE(reset_reasons); i++) { + if (ret & reset_reasons[i].bit) { + reason = reset_reasons[i].name; + printf("%s ", reset_reasons[i].name); + break; + } + } + + puts("\n"); + + env_set("reset_reason", reason); + + writel(~0, &crlapb_base->reset_reason); + + return ret; +} + int board_late_init(void) { u32 reg = 0; @@ -540,6 +581,8 @@ int board_late_init(void) env_set("boot_targets", new_targets); + reset_reason(); + return 0; } -- cgit v1.1 From 8dd94a8fe5d344208a170080a388f0cf4e9ae2ef Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 14 May 2018 15:33:22 +0200 Subject: arm64: zynqmp: Get rid of emulation platforms ZynqMP emulation platforms are no longer tested and supported that's why remove macros and code around. Signed-off-by: Michal Simek --- arch/arm/cpu/armv8/zynqmp/clk.c | 10 +--------- arch/arm/cpu/armv8/zynqmp/cpu.c | 4 ---- arch/arm/include/asm/arch-zynqmp/hardware.h | 2 -- 3 files changed, 1 insertion(+), 15 deletions(-) diff --git a/arch/arm/cpu/armv8/zynqmp/clk.c b/arch/arm/cpu/armv8/zynqmp/clk.c index 13e1977..0593b63 100644 --- a/arch/arm/cpu/armv8/zynqmp/clk.c +++ b/arch/arm/cpu/armv8/zynqmp/clk.c @@ -16,10 +16,6 @@ unsigned long zynqmp_get_system_timer_freq(void) u32 ver = zynqmp_get_silicon_version(); switch (ver) { - case ZYNQMP_CSU_VERSION_VELOCE: - return 10000; - case ZYNQMP_CSU_VERSION_EP108: - return 4000000; case ZYNQMP_CSU_VERSION_QEMU: return 50000000; } @@ -40,11 +36,7 @@ int set_cpu_clk_info(void) { gd->cpu_clk = get_tbclk(); - /* Support Veloce to show at least 1MHz via bdi */ - if (gd->cpu_clk > 1000000) - gd->bd->bi_arm_freq = gd->cpu_clk / 1000000; - else - gd->bd->bi_arm_freq = 1; + gd->bd->bi_arm_freq = gd->cpu_clk / 1000000; gd->bd->bi_dsp_freq = 0; diff --git a/arch/arm/cpu/armv8/zynqmp/cpu.c b/arch/arm/cpu/armv8/zynqmp/cpu.c index 2748d65..792a3e1 100644 --- a/arch/arm/cpu/armv8/zynqmp/cpu.c +++ b/arch/arm/cpu/armv8/zynqmp/cpu.c @@ -135,12 +135,8 @@ unsigned int zynqmp_get_silicon_version(void) gd->cpu_clk = get_tbclk(); switch (gd->cpu_clk) { - case 0 ... 1000000: - return ZYNQMP_CSU_VERSION_VELOCE; case 50000000: return ZYNQMP_CSU_VERSION_QEMU; - case 4000000: - return ZYNQMP_CSU_VERSION_EP108; } return ZYNQMP_CSU_VERSION_SILICON; diff --git a/arch/arm/include/asm/arch-zynqmp/hardware.h b/arch/arm/include/asm/arch-zynqmp/hardware.h index f317250..8a505ed 100644 --- a/arch/arm/include/asm/arch-zynqmp/hardware.h +++ b/arch/arm/include/asm/arch-zynqmp/hardware.h @@ -130,8 +130,6 @@ struct apu_regs { /* Board version value */ #define ZYNQMP_CSU_BASEADDR 0xFFCA0000 #define ZYNQMP_CSU_VERSION_SILICON 0x0 -#define ZYNQMP_CSU_VERSION_EP108 0x1 -#define ZYNQMP_CSU_VERSION_VELOCE 0x2 #define ZYNQMP_CSU_VERSION_QEMU 0x3 #define ZYNQMP_CSU_VERSION_EMPTY_SHIFT 20 -- cgit v1.1 From 6189f76ae8fb3549349443d1d702d3d652d1244b Mon Sep 17 00:00:00 2001 From: Rajan Vaja Date: Wed, 7 Feb 2018 06:49:21 -0800 Subject: soc: zynqmp: Update required API version to 1.0 Existing EEMI version is to as 1.0 (available from xilinx v2018.1 version). Update required API version to match with EEMI API version. New PMUFW version is required for operations with programmable logic. Signed-off-by: Rajan Vaja Signed-off-by: Michal Simek --- arch/arm/cpu/armv8/zynqmp/cpu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/cpu/armv8/zynqmp/cpu.c b/arch/arm/cpu/armv8/zynqmp/cpu.c index 792a3e1..e122be5 100644 --- a/arch/arm/cpu/armv8/zynqmp/cpu.c +++ b/arch/arm/cpu/armv8/zynqmp/cpu.c @@ -173,8 +173,8 @@ int __maybe_unused invoke_smc(u32 pm_api_id, u32 arg0, u32 arg1, u32 arg2, #define ZYNQMP_SIP_SVC_GET_API_VERSION 0xC2000001 -#define ZYNQMP_PM_VERSION_MAJOR 0 -#define ZYNQMP_PM_VERSION_MINOR 3 +#define ZYNQMP_PM_VERSION_MAJOR 1 +#define ZYNQMP_PM_VERSION_MINOR 0 #define ZYNQMP_PM_VERSION_MAJOR_SHIFT 16 #define ZYNQMP_PM_VERSION_MINOR_MASK 0xFFFF -- cgit v1.1 From 2882b39d564bfa531d86aa22900658285483107d Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 25 Apr 2018 11:20:43 +0200 Subject: arm64: zynqmp: Setup the first boot_target at run time Detect mmc alias at run time for setting up proper boot_targets sequence. The first target has to correspond with boot mode. The purpose of this patch is to get rid of CONFIG_ZYNQ_SDHCI0/1 parameters in full U-Boot. Unfortunately this patch can't remove it because there is missing mmc implementation for SPL_DM_SEQ_ALIAS. Also xilinx_zynqmp.h only setup boot commands for mmc0 and mmc1. It means using aliases with higher number won't work. But switching between mmc0 and mmc1 should work properly. Signed-off-by: Michal Simek Reviewed-by: Alexander Graf --- board/xilinx/zynqmp/zynqmp.c | 45 ++++++++++++++++++++++++++++++++++---------- 1 file changed, 35 insertions(+), 10 deletions(-) diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index d3450ef..080fb59 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -494,6 +495,9 @@ int board_late_init(void) { u32 reg = 0; u8 bootmode; + struct udevice *dev; + int bootseq = -1; + int bootseq_len = 0; int env_targets_len = 0; const char *mode; char *new_targets; @@ -539,7 +543,15 @@ int board_late_init(void) break; case SD_MODE: puts("SD_MODE\n"); - mode = "mmc0"; + if (uclass_get_device_by_name(UCLASS_MMC, + "sdhci@ff160000", &dev)) { + puts("Boot from SD0 but without SD0 enabled!\n"); + return -1; + } + debug("mmc0 device found at %p, seq %d\n", dev, dev->seq); + + mode = "mmc"; + bootseq = dev->seq; env_set("modeboot", "sdboot"); break; case SD1_LSHFT_MODE: @@ -547,12 +559,15 @@ int board_late_init(void) /* fall through */ case SD_MODE1: puts("SD_MODE1\n"); -#if defined(CONFIG_ZYNQ_SDHCI0) && defined(CONFIG_ZYNQ_SDHCI1) - mode = "mmc1"; - env_set("sdbootdev", "1"); -#else - mode = "mmc0"; -#endif + if (uclass_get_device_by_name(UCLASS_MMC, + "sdhci@ff170000", &dev)) { + puts("Boot from SD1 but without SD1 enabled!\n"); + return -1; + } + debug("mmc1 device found at %p, seq %d\n", dev, dev->seq); + + mode = "mmc"; + bootseq = dev->seq; env_set("modeboot", "sdboot"); break; case NAND_MODE: @@ -566,6 +581,11 @@ int board_late_init(void) break; } + if (bootseq >= 0) { + bootseq_len = snprintf(NULL, 0, "%i", bootseq); + debug("Bootseq len: %x\n", bootseq_len); + } + /* * One terminating char + one byte for space between mode * and default boot_targets @@ -574,10 +594,15 @@ int board_late_init(void) if (env_targets) env_targets_len = strlen(env_targets); - new_targets = calloc(1, strlen(mode) + env_targets_len + 2); + new_targets = calloc(1, strlen(mode) + env_targets_len + 2 + + bootseq_len); - sprintf(new_targets, "%s %s", mode, - env_targets ? env_targets : ""); + if (bootseq >= 0) + sprintf(new_targets, "%s%x %s", mode, bootseq, + env_targets ? env_targets : ""); + else + sprintf(new_targets, "%s %s", mode, + env_targets ? env_targets : ""); env_set("boot_targets", new_targets); -- cgit v1.1 From ce69030eb9d600173d6ce801c3158f685721fe79 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 16 May 2018 10:56:43 +0200 Subject: serial: zynq: Use live-tree functions Use live-tree functions. Signed-off-by: Michal Simek Reviewed-by: Simon Glass --- drivers/serial/serial_zynq.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/serial/serial_zynq.c b/drivers/serial/serial_zynq.c index 06f0a48..3650af2 100644 --- a/drivers/serial/serial_zynq.c +++ b/drivers/serial/serial_zynq.c @@ -175,7 +175,9 @@ static int zynq_serial_ofdata_to_platdata(struct udevice *dev) { struct zynq_uart_priv *priv = dev_get_priv(dev); - priv->regs = (struct uart_zynq *)devfdt_get_addr(dev); + priv->regs = (struct uart_zynq *)dev_read_addr(dev); + if (IS_ERR(priv->regs)) + return PTR_ERR(priv->regs); return 0; } -- cgit v1.1 From 458e8d8071f2db7addbfe1fa67951a95c05d28b6 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 16 May 2018 10:57:07 +0200 Subject: mmc: zynq: Use live-tree functions Use live-tree functions. Signed-off-by: Michal Simek Reviewed-by: Simon Glass --- drivers/mmc/zynq_sdhci.c | 22 +++++++++------------- 1 file changed, 9 insertions(+), 13 deletions(-) diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c index f99731f..1f6d053 100644 --- a/drivers/mmc/zynq_sdhci.c +++ b/drivers/mmc/zynq_sdhci.c @@ -283,25 +283,21 @@ static int arasan_sdhci_ofdata_to_platdata(struct udevice *dev) return -1; priv->host->name = dev->name; - priv->host->ioaddr = (void *)devfdt_get_addr(dev); - - priv->deviceid = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), - "xlnx,device_id", -1); - priv->bank = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), - "xlnx,mio_bank", -1); - if (fdt_get_property(gd->fdt_blob, dev_of_offset(dev), - "no-1-8-v", NULL)) - priv->no_1p8 = 1; - else - priv->no_1p8 = 0; #if defined(CONFIG_DM_MMC) && defined(CONFIG_ARCH_ZYNQMP) priv->host->ops = &arasan_ops; #endif - plat->f_max = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), - "max-frequency", CONFIG_ZYNQ_SDHCI_MAX_FREQ); + priv->host->ioaddr = (void *)dev_read_addr(dev); + if (IS_ERR(priv->host->ioaddr)) + return PTR_ERR(priv->host->ioaddr); + priv->deviceid = dev_read_u32_default(dev, "xlnx,device_id", -1); + priv->bank = dev_read_u32_default(dev, "xlnx,mio_bank", -1); + priv->no_1p8 = dev_read_bool(dev, "no-1-8-v"); + + plat->f_max = dev_read_u32_default(dev, "max-frequency", + CONFIG_ZYNQ_SDHCI_MAX_FREQ); return 0; } -- cgit v1.1 From f01ef0ae63fa82ac1a73d5e3d70e7dbc38b18a7d Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 16 May 2018 10:57:27 +0200 Subject: watchdog: cadence: Use live-tree functions Use live-tree functions. Signed-off-by: Michal Simek Reviewed-by: Simon Glass --- drivers/watchdog/cdns_wdt.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/watchdog/cdns_wdt.c b/drivers/watchdog/cdns_wdt.c index 9a07fa1..f7618f8 100644 --- a/drivers/watchdog/cdns_wdt.c +++ b/drivers/watchdog/cdns_wdt.c @@ -231,17 +231,16 @@ static int cdns_wdt_probe(struct udevice *dev) static int cdns_wdt_ofdata_to_platdata(struct udevice *dev) { - int node = dev_of_offset(dev); struct cdns_wdt_priv *priv = dev_get_priv(dev); - priv->regs = devfdt_get_addr_ptr(dev); + priv->regs = (struct cdns_regs *)dev_read_addr(dev); if (IS_ERR(priv->regs)) return PTR_ERR(priv->regs); - priv->timeout = fdtdec_get_int(gd->fdt_blob, node, "timeout-sec", - CDNS_WDT_DEFAULT_TIMEOUT); + priv->timeout = dev_read_u32_default(dev, "timeout-sec", + CDNS_WDT_DEFAULT_TIMEOUT); - priv->rst = fdtdec_get_bool(gd->fdt_blob, node, "reset-on-timeout"); + priv->rst = dev_read_bool(dev, "reset-on-timeout"); debug("%s: timeout %d, reset %d\n", __func__, priv->timeout, priv->rst); -- cgit v1.1 From 72b88103bb9b6bf8f4e9864200bb1811e32f878c Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 16 May 2018 10:56:09 +0200 Subject: timer: cadence: Use live-tree functions Use live-tree functions. Reported-by: Simon Glass Signed-off-by: Michal Simek Reviewed-by: Simon Glass --- drivers/timer/cadence-ttc.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/timer/cadence-ttc.c b/drivers/timer/cadence-ttc.c index 5b91c8a..3541e5c 100644 --- a/drivers/timer/cadence-ttc.c +++ b/drivers/timer/cadence-ttc.c @@ -64,8 +64,10 @@ static int cadence_ttc_ofdata_to_platdata(struct udevice *dev) { struct cadence_ttc_priv *priv = dev_get_priv(dev); - priv->regs = map_physmem(devfdt_get_addr(dev), + priv->regs = map_physmem(dev_read_addr(dev), sizeof(struct cadence_ttc_regs), MAP_NOCACHE); + if (IS_ERR(priv->regs)) + return PTR_ERR(priv->regs); return 0; } -- cgit v1.1 From 35f051ab666b71214873257577f7c9926120e2c4 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 18 May 2018 11:15:09 +0200 Subject: arm64: zynqmp: Remove empty configuration file There is no reason to keep empty config file in the tree that's why remove it. Signed-off-by: Michal Simek --- configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig | 1 - include/configs/xilinx_zynqmp_zc1751_xm016_dc2.h | 14 -------------- 2 files changed, 15 deletions(-) delete mode 100644 include/configs/xilinx_zynqmp_zc1751_xm016_dc2.h diff --git a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig index 7f7ee55..65fe29c 100644 --- a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig @@ -1,5 +1,4 @@ CONFIG_ARM=y -CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zc1751_xm016_dc2" CONFIG_ARCH_ZYNQMP=y CONFIG_SYS_TEXT_BASE=0x8000000 CONFIG_SYS_MALLOC_F_LEN=0x8000 diff --git a/include/configs/xilinx_zynqmp_zc1751_xm016_dc2.h b/include/configs/xilinx_zynqmp_zc1751_xm016_dc2.h deleted file mode 100644 index bfebbb3..0000000 --- a/include/configs/xilinx_zynqmp_zc1751_xm016_dc2.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuration for Xilinx ZynqMP zc1751 XM016 DC2 - * - * (C) Copyright 2015 Xilinx, Inc. - * Michal Simek - */ - -#ifndef __CONFIG_ZYNQMP_ZC1751_XM016_DC2_H -#define __CONFIG_ZYNQMP_ZC1751_XM016_DC2_H - -#include - -#endif /* __CONFIG_ZYNQMP_ZC1751_XM016_DC2_H */ -- cgit v1.1 From 95d565fdc246ba43de8f51aa799e33b0811d2823 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 21 May 2018 13:33:47 +0200 Subject: arm64: zynqmp: Remove CMD_UNZIP for mini configuration CMD_UNZIP is already disabled via Kconfig. Signed-off-by: Michal Simek --- include/configs/xilinx_zynqmp_mini.h | 1 - 1 file changed, 1 deletion(-) diff --git a/include/configs/xilinx_zynqmp_mini.h b/include/configs/xilinx_zynqmp_mini.h index 947d308..96ff6c9 100644 --- a/include/configs/xilinx_zynqmp_mini.h +++ b/include/configs/xilinx_zynqmp_mini.h @@ -32,7 +32,6 @@ /* BOOTP options */ #undef CONFIG_BOOTP_BOOTFILESIZE #undef CONFIG_BOOTP_MAY_FAIL -#undef CONFIG_CMD_UNZIP #undef CONFIG_NR_DRAM_BANKS -- cgit v1.1 From 7483969c550a931aa7b2441025a99c2fc878582e Mon Sep 17 00:00:00 2001 From: Ibai Erkiaga Date: Tue, 22 May 2018 17:03:04 +0100 Subject: arm: zynq: Add initial support for Avnet MiniZed Initial support for Avnet MiniZed board. Tested UART1 (serial console), QSPI(Flash), SDHCI1 (eMMC), USB. Signed-off-by: Ibai Erkiaga Signed-off-by: Michal Simek --- arch/arm/dts/Makefile | 1 + arch/arm/dts/zynq-minized.dts | 106 +++++++++++++++++++++++++++++++++++++++++ configs/zynq_minized_defconfig | 66 +++++++++++++++++++++++++ 3 files changed, 173 insertions(+) create mode 100644 arch/arm/dts/zynq-minized.dts create mode 100644 configs/zynq_minized_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index a0349a8..197639c 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -130,6 +130,7 @@ dtb-$(CONFIG_ARCH_ZYNQ) += \ zynq-cc108.dtb \ zynq-cse-qspi-single.dtb \ zynq-microzed.dtb \ + zynq-minized.dtb \ zynq-picozed.dtb \ zynq-syzygy-hub.dtb \ zynq-topic-miami.dtb \ diff --git a/arch/arm/dts/zynq-minized.dts b/arch/arm/dts/zynq-minized.dts new file mode 100644 index 0000000..525921e --- /dev/null +++ b/arch/arm/dts/zynq-minized.dts @@ -0,0 +1,106 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * dts file for Avnet MiniZed board + * + * (C) Copyright 2017 - 2018, Xilinx, Inc. + * + * Ibai Erkiaga + */ + +/dts-v1/; +#include "zynq-7000.dtsi" + +/ { + model = "Avnet Zynq MiniZed Development Board"; + compatible = "avnet,minized", "xlnx,zynq-7000"; + + aliases { + serial0 = &uart1; + serial1 = &uart0; + spi0 = &qspi; + mmc0 = &sdhci0; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x20000000>; + }; + + chosen { + bootargs = ""; + stdout-path = "serial0:115200n8"; + }; + + usb_phy0: phy0 { + compatible = "usb-nop-xceiv"; + #phy-cells = <0>; + }; +}; + +&qspi { + status = "okay"; + is-dual = <0>; + num-cs = <1>; + flash@0 { + compatible = "micron,m25p128"; + reg = <0x0>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + spi-max-frequency = <50000000>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "boot"; + reg = <0x0 0xff0000>; + }; + + partition@270000 { + label = "kernel"; + reg = <0x270000 0xd80000>; + }; + + partition@ff0000 { + label = "bootenv"; + reg = <0xff0000 0x10000>; + }; + + partition@1000000 { + label = "spare"; + reg = <0x1000000 0x0>; + }; + }; + }; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&usb0 { + status = "okay"; + dr_mode = "host"; + usb-phy = <&usb_phy0>; + usb-reset = <&gpio0 7 0>; /* USB_RST_N-MIO7 */ +}; + +&sdhci1 { + status = "okay"; + non-removable; + bus-width = <4>; + max-frequency = <12000000>; + + #address-cells = <1>; + #size-cells = <0>; + mmccard: mmccard@0 { + compatible = "mmc-card"; + reg = <0>; + broken-hpi; + }; +}; diff --git a/configs/zynq_minized_defconfig b/configs/zynq_minized_defconfig new file mode 100644 index 0000000..8cf3215 --- /dev/null +++ b/configs/zynq_minized_defconfig @@ -0,0 +1,66 @@ +CONFIG_ARM=y +CONFIG_ARCH_ZYNQ=y +CONFIG_SYS_TEXT_BASE=0x4000000 +CONFIG_SPL=y +CONFIG_SPL_STACK_R_ADDR=0x200000 +CONFIG_DEFAULT_DEVICE_TREE="zynq-minized" +CONFIG_DEBUG_UART=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_FIT_VERBOSE=y +CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd" +CONFIG_SPL_STACK_R=y +CONFIG_SPL_OS_BOOT=y +CONFIG_SYS_PROMPT="Zynq> " +CONFIG_CMD_THOR_DOWNLOAD=y +CONFIG_CMD_DFU=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_FPGA_LOADBP=y +CONFIG_CMD_FPGA_LOADFS=y +CONFIG_CMD_FPGA_LOADMK=y +CONFIG_CMD_FPGA_LOADP=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_DFU_MMC=y +CONFIG_DFU_RAM=y +CONFIG_FPGA_XILINX=y +CONFIG_FPGA_ZYNQPL=y +CONFIG_DM_GPIO=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ZYNQ=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_PHY_MARVELL=y +CONFIG_PHY_REALTEK=y +CONFIG_PHY_XILINX=y +CONFIG_ZYNQ_GEM=y +CONFIG_DEBUG_UART_ZYNQ=y +CONFIG_DEBUG_UART_BASE=0xe0001000 +CONFIG_DEBUG_UART_CLOCK=50000000 +CONFIG_ZYNQ_SERIAL=y +CONFIG_ZYNQ_QSPI=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_ULPI_VIEWPORT=y +CONFIG_USB_ULPI=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Xilinx" +CONFIG_USB_GADGET_VENDOR_NUM=0x03fd +CONFIG_USB_GADGET_PRODUCT_NUM=0x0300 +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_FUNCTION_THOR=y -- cgit v1.1 From 5dd84a3fbd18bb16520d8ce35183b7fa2fe10d37 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 23 May 2018 10:24:44 +0200 Subject: arm64: zynqmp: Sync defconfigs with latest Kconfig layout Sync defconfigs. Signed-off-by: Michal Simek --- configs/xilinx_zynqmp_zc1232_revA_defconfig | 2 +- configs/xilinx_zynqmp_zc1254_revA_defconfig | 2 +- configs/xilinx_zynqmp_zc1275_revA_defconfig | 2 +- configs/xilinx_zynqmp_zc1275_revB_defconfig | 2 +- configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/configs/xilinx_zynqmp_zc1232_revA_defconfig b/configs/xilinx_zynqmp_zc1232_revA_defconfig index 70dc870..d5c0838 100644 --- a/configs/xilinx_zynqmp_zc1232_revA_defconfig +++ b/configs/xilinx_zynqmp_zc1232_revA_defconfig @@ -2,9 +2,9 @@ CONFIG_ARM=y CONFIG_ARCH_ZYNQMP=y CONFIG_SYS_TEXT_BASE=0x8000000 CONFIG_SYS_MALLOC_F_LEN=0x8000 -# CONFIG_SPL_LIBDISK_SUPPORT is not set CONFIG_SPL=y # CONFIG_SPL_FAT_SUPPORT is not set +# CONFIG_SPL_LIBDISK_SUPPORT is not set CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1232-revA" CONFIG_DEBUG_UART=y CONFIG_DISTRO_DEFAULTS=y diff --git a/configs/xilinx_zynqmp_zc1254_revA_defconfig b/configs/xilinx_zynqmp_zc1254_revA_defconfig index 09de18d..40baccc 100644 --- a/configs/xilinx_zynqmp_zc1254_revA_defconfig +++ b/configs/xilinx_zynqmp_zc1254_revA_defconfig @@ -2,9 +2,9 @@ CONFIG_ARM=y CONFIG_ARCH_ZYNQMP=y CONFIG_SYS_TEXT_BASE=0x8000000 CONFIG_SYS_MALLOC_F_LEN=0x8000 -# CONFIG_SPL_LIBDISK_SUPPORT is not set CONFIG_SPL=y # CONFIG_SPL_FAT_SUPPORT is not set +# CONFIG_SPL_LIBDISK_SUPPORT is not set CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1254-revA" CONFIG_DEBUG_UART=y CONFIG_DISTRO_DEFAULTS=y diff --git a/configs/xilinx_zynqmp_zc1275_revA_defconfig b/configs/xilinx_zynqmp_zc1275_revA_defconfig index a7e79f5..542bfe2 100644 --- a/configs/xilinx_zynqmp_zc1275_revA_defconfig +++ b/configs/xilinx_zynqmp_zc1275_revA_defconfig @@ -2,9 +2,9 @@ CONFIG_ARM=y CONFIG_ARCH_ZYNQMP=y CONFIG_SYS_TEXT_BASE=0x8000000 CONFIG_SYS_MALLOC_F_LEN=0x8000 -# CONFIG_SPL_LIBDISK_SUPPORT is not set CONFIG_SPL=y # CONFIG_SPL_FAT_SUPPORT is not set +# CONFIG_SPL_LIBDISK_SUPPORT is not set CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1275-revA" CONFIG_DEBUG_UART=y CONFIG_DISTRO_DEFAULTS=y diff --git a/configs/xilinx_zynqmp_zc1275_revB_defconfig b/configs/xilinx_zynqmp_zc1275_revB_defconfig index 823b503..92bb15a 100644 --- a/configs/xilinx_zynqmp_zc1275_revB_defconfig +++ b/configs/xilinx_zynqmp_zc1275_revB_defconfig @@ -3,9 +3,9 @@ CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zc1275_revB" CONFIG_ARCH_ZYNQMP=y CONFIG_SYS_TEXT_BASE=0x8000000 CONFIG_SYS_MALLOC_F_LEN=0x8000 -# CONFIG_SPL_LIBDISK_SUPPORT is not set CONFIG_SPL=y # CONFIG_SPL_FAT_SUPPORT is not set +# CONFIG_SPL_LIBDISK_SUPPORT is not set CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1275-revB" CONFIG_DEBUG_UART=y CONFIG_DISTRO_DEFAULTS=y diff --git a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig index 65fe29c..d710266 100644 --- a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig @@ -2,9 +2,9 @@ CONFIG_ARM=y CONFIG_ARCH_ZYNQMP=y CONFIG_SYS_TEXT_BASE=0x8000000 CONFIG_SYS_MALLOC_F_LEN=0x8000 -# CONFIG_SPL_LIBDISK_SUPPORT is not set CONFIG_SPL=y # CONFIG_SPL_FAT_SUPPORT is not set +# CONFIG_SPL_LIBDISK_SUPPORT is not set CONFIG_ZYNQMP_USB=y CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm016-dc2" CONFIG_DEBUG_UART=y -- cgit v1.1 From c66f5620e6a63b1912c017781c7eec6400dde292 Mon Sep 17 00:00:00 2001 From: Ezequiel Garcia Date: Fri, 12 Jan 2018 12:33:50 -0300 Subject: arm: zynq: Add support for Bitmain Antminer S9 control board This is control board on Bitmain Antminer S9. There are 3 board variables with 256MB, 512MB and 1024MB DDR. DDR memory is automatically detected with using get_with using get_ram_size(). Bitmain is using 16MB space for FPGA which is handled via reserved-memory. Also U-Boot is allocating 16B for storing bootcounts. Watchdog is started but never service in U-Boot. SPL MMC is working. SPL NAND is not working because it is not supported as of now. Signed-off-by: Ezequiel Garcia Signed-off-by: Michal Simek Signed-off-by: Michal Simek --- arch/arm/dts/bitmain-antminer-s9.dts | 78 ++++++ board/bitmain/antminer_s9/MAINTAINERS | 6 + board/bitmain/antminer_s9/Makefile | 8 + .../antminer_s9/bitmain-antminer-s9/ps7_init_gpl.c | 280 +++++++++++++++++++++ board/bitmain/antminer_s9/board.c | 2 + configs/bitmain_antminer_s9_defconfig | 66 +++++ include/configs/bitmain_antminer_s9.h | 30 +++ 7 files changed, 470 insertions(+) create mode 100644 arch/arm/dts/bitmain-antminer-s9.dts create mode 100644 board/bitmain/antminer_s9/MAINTAINERS create mode 100644 board/bitmain/antminer_s9/Makefile create mode 100644 board/bitmain/antminer_s9/bitmain-antminer-s9/ps7_init_gpl.c create mode 100644 board/bitmain/antminer_s9/board.c create mode 100644 configs/bitmain_antminer_s9_defconfig create mode 100644 include/configs/bitmain_antminer_s9.h diff --git a/arch/arm/dts/bitmain-antminer-s9.dts b/arch/arm/dts/bitmain-antminer-s9.dts new file mode 100644 index 0000000..7362ad4 --- /dev/null +++ b/arch/arm/dts/bitmain-antminer-s9.dts @@ -0,0 +1,78 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Bitmain Antminer S9 board DTS + * + * Copyright (C) 2018 Michal Simek + * Copyright (C) 2018 VanguardiaSur + */ +/dts-v1/; +#include "zynq-7000.dtsi" + +/ { + model = "Bitmain Antminer S9 Board"; + compatible = "bitmain,antminer-s9", "xlnx,zynq-7000"; + + aliases { + ethernet0 = &gem0; + serial0 = &uart1; + mmc0 = &sdhci0; + gpio0 = &gpio0; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x40000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + bootcount@efffff0 { + reg = <0xefffff0 0x10>; + no-map; + }; + + fpga_space@f000000 { + reg = <0xf000000 0x1000000>; + no-map; + }; + }; + + chosen { + bootargs = "earlycon"; + stdout-path = "serial0:115200n8"; + }; +}; + +&clkc { + ps-clk-frequency = <33333333>; +}; + +&gem0 { + status = "okay"; + phy-mode = "rgmii-id"; + phy-handle = <ðernet_phy>; + + /* 0362/5e62 */ + ethernet_phy: ethernet-phy@1 { + reg = <1>; + }; +}; + +&sdhci0 { + u-boot,dm-pre-reloc; + status = "okay"; + disable-wp; +}; + +&uart1 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&watchdog0 { + reset-on-timeout; + timeout-sec = <200>; +}; diff --git a/board/bitmain/antminer_s9/MAINTAINERS b/board/bitmain/antminer_s9/MAINTAINERS new file mode 100644 index 0000000..302dd48 --- /dev/null +++ b/board/bitmain/antminer_s9/MAINTAINERS @@ -0,0 +1,6 @@ +Bitmain Antminer S9 +M: Michal Simek +S: Maintained +F: board/bitmain/antminer_s9 +F: include/configs/bitmain_antminer_s9.h +F: configs/bitmain_antminer_s9_defconfig diff --git a/board/bitmain/antminer_s9/Makefile b/board/bitmain/antminer_s9/Makefile new file mode 100644 index 0000000..93a1e77 --- /dev/null +++ b/board/bitmain/antminer_s9/Makefile @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0 + +obj-y := board.o + +# Remove quotes +hw-platform-y :=$(shell echo $(CONFIG_DEFAULT_DEVICE_TREE)) + +obj-$(CONFIG_SPL_BUILD) += $(hw-platform-y)/ps7_init_gpl.o diff --git a/board/bitmain/antminer_s9/bitmain-antminer-s9/ps7_init_gpl.c b/board/bitmain/antminer_s9/bitmain-antminer-s9/ps7_init_gpl.c new file mode 100644 index 0000000..aee2029 --- /dev/null +++ b/board/bitmain/antminer_s9/bitmain-antminer-s9/ps7_init_gpl.c @@ -0,0 +1,280 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * (C) Copyright 2018 Michal Simek + */ + +#include + +static unsigned long ps7_pll_init_data_3_0[] = { + EMIT_MASKWRITE(0xf8000008, 0x0000ffff, 0x0000df0d), + EMIT_MASKWRITE(0xf8000110, 0x003ffff0, 0x000fa220), + EMIT_MASKWRITE(0xf8000100, 0x0007f000, 0x00028000), + EMIT_MASKWRITE(0xf8000100, 0x00000010, 0x00000010), + EMIT_MASKWRITE(0xf8000100, 0x00000001, 0x00000001), + EMIT_MASKWRITE(0xf8000100, 0x00000001, 0x00000000), + EMIT_MASKPOLL(0xf800010c, 0x00000001), + EMIT_MASKWRITE(0xf8000100, 0x00000010, 0x00000000), + EMIT_MASKWRITE(0xf8000120, 0x1f003f30, 0x1f000200), + EMIT_MASKWRITE(0xf8000114, 0x003ffff0, 0x0012c220), + EMIT_MASKWRITE(0xf8000104, 0x0007f000, 0x00020000), + EMIT_MASKWRITE(0xf8000104, 0x00000010, 0x00000010), + EMIT_MASKWRITE(0xf8000104, 0x00000001, 0x000000), + EMIT_MASKWRITE(0xf8000104, 0x00000001, 0x00000000), + EMIT_MASKPOLL(0xf800010c, 0x00000002), + EMIT_MASKWRITE(0xf8000104, 0x00000010, 0x00000000), + EMIT_MASKWRITE(0xf8000124, 0xfff00003, 0x0c200003), + EMIT_MASKWRITE(0xf8000118, 0x003ffff0, 0x001452c0), + EMIT_MASKWRITE(0xf8000108, 0x0007f000, 0x0001e000), + EMIT_MASKWRITE(0xf8000108, 0x00000010, 0x00000010), + EMIT_MASKWRITE(0xf8000108, 0x00000001, 0x00000001), + EMIT_MASKWRITE(0xf8000108, 0x00000001, 0x00000000), + EMIT_MASKPOLL(0xf800010c, 0x00000004), + EMIT_MASKWRITE(0xf8000108, 0x00000010, 0x00000000), + EMIT_MASKWRITE(0xf8000004, 0x0000ffff, 0x0000767b), + EMIT_EXIT(), +}; + +static unsigned long ps7_clock_init_data_3_0[] = { + EMIT_MASKWRITE(0xf8000008, 0x0000ffff, 0x0000df0d), + EMIT_MASKWRITE(0xf8000128, 0x03f03f01, 0x00302301), + EMIT_MASKWRITE(0xf8000138, 0x00000011, 0x00000001), + EMIT_MASKWRITE(0xf8000140, 0x03f03f71, 0x00100801), + EMIT_MASKWRITE(0xf8000148, 0x00003f31, 0x00000a01), + EMIT_MASKWRITE(0xf8000150, 0x00003f33, 0x00002801), + EMIT_MASKWRITE(0xf8000154, 0x00003f33, 0x00001402), + EMIT_MASKWRITE(0xf8000168, 0x00003f31, 0x00000501), + EMIT_MASKWRITE(0xf8000170, 0x03f03f30, 0x00101400), + EMIT_MASKWRITE(0xf8000180, 0x03f03f30, 0x00100a00), + EMIT_MASKWRITE(0xf8000190, 0x03f03f30, 0x00101e00), + EMIT_MASKWRITE(0xf80001a0, 0x03f03f30, 0x00101400), + EMIT_MASKWRITE(0xf80001c4, 0x00000001, 0x00000001), + EMIT_MASKWRITE(0xf800012c, 0x01ffcccd, 0x016c044d), + EMIT_MASKWRITE(0xf8000004, 0x0000ffff, 0x0000767b), + EMIT_EXIT(), +}; + +static unsigned long ps7_ddr_init_data_3_0[] = { + EMIT_MASKWRITE(0xf8006000, 0x0001ffff, 0x00000080), + EMIT_MASKWRITE(0xf8006004, 0x0007ffff, 0x00001081), + EMIT_MASKWRITE(0xf8006008, 0x03ffffff, 0x03c0780f), + EMIT_MASKWRITE(0xf800600c, 0x03ffffff, 0x02001001), + EMIT_MASKWRITE(0xf8006010, 0x03ffffff, 0x00014001), + EMIT_MASKWRITE(0xf8006014, 0x001fffff, 0x0004281b), + EMIT_MASKWRITE(0xf8006018, 0xf7ffffff, 0x44e458d1), + EMIT_MASKWRITE(0xf800601c, 0xffffffff, 0xb2023584), + EMIT_MASKWRITE(0xf8006020, 0x7fdffffc, 0x2b08b2d0), + EMIT_MASKWRITE(0xf8006024, 0x0fffffc3, 0x00000000), + EMIT_MASKWRITE(0xf8006028, 0x00003fff, 0x00002007), + EMIT_MASKWRITE(0xf800602c, 0xffffffff, 0x00000000), + EMIT_MASKWRITE(0xf8006030, 0xffffffff, 0x00040970), + EMIT_MASKWRITE(0xf8006034, 0x13ff3fff, 0x000116d4), + EMIT_MASKWRITE(0xf8006038, 0x00000003, 0x00000000), + EMIT_MASKWRITE(0xf800603c, 0x000fffff, 0x00000777), + EMIT_MASKWRITE(0xf8006040, 0xffffffff, 0xfff00000), + EMIT_MASKWRITE(0xf8006044, 0x0fffffff, 0x0f666666), + EMIT_MASKWRITE(0xf8006048, 0x0003f03f, 0x0003c008), + EMIT_MASKWRITE(0xf8006050, 0xff0f8fff, 0x77010800), + EMIT_MASKWRITE(0xf8006058, 0x00010000, 0x00000000), + EMIT_MASKWRITE(0xf800605c, 0x0000ffff, 0x00005003), + EMIT_MASKWRITE(0xf8006060, 0x000017ff, 0x0000003e), + EMIT_MASKWRITE(0xf8006064, 0x00021fe0, 0x00020000), + EMIT_MASKWRITE(0xf8006068, 0x03ffffff, 0x00284545), + EMIT_MASKWRITE(0xf800606c, 0x0000ffff, 0x00001610), + EMIT_MASKWRITE(0xf8006078, 0x03ffffff, 0x00466111), + EMIT_MASKWRITE(0xf800607c, 0x000fffff, 0x00032222), + EMIT_MASKWRITE(0xf80060a4, 0xffffffff, 0x10200802), + EMIT_MASKWRITE(0xf80060a8, 0x0fffffff, 0x0690cb73), + EMIT_MASKWRITE(0xf80060ac, 0x000001ff, 0x000001fe), + EMIT_MASKWRITE(0xf80060b0, 0x1fffffff, 0x1cffffff), + EMIT_MASKWRITE(0xf80060b4, 0x00000200, 0x00000200), + EMIT_MASKWRITE(0xf80060b8, 0x01ffffff, 0x0020006a), + EMIT_MASKWRITE(0xf80060c4, 0x00000003, 0x00000003), + EMIT_MASKWRITE(0xf80060c4, 0x00000003, 0x00000000), + EMIT_MASKWRITE(0xf80060c8, 0x000000ff, 0x00000000), + EMIT_MASKWRITE(0xf80060dc, 0x00000001, 0x00000000), + EMIT_MASKWRITE(0xf80060f0, 0x0000ffff, 0x00000000), + EMIT_MASKWRITE(0xf80060f4, 0x0000000f, 0x00000008), + EMIT_MASKWRITE(0xf8006114, 0x000000ff, 0x00000000), + EMIT_MASKWRITE(0xf8006118, 0x7fffffcf, 0x40000001), + EMIT_MASKWRITE(0xf800611c, 0x7fffffcf, 0x40000001), + EMIT_MASKWRITE(0xf8006120, 0x7fffffcf, 0x40000001), + EMIT_MASKWRITE(0xf8006124, 0x7fffffcf, 0x40000001), + EMIT_MASKWRITE(0xf800612c, 0x000fffff, 0x0002c000), + EMIT_MASKWRITE(0xf8006130, 0x000fffff, 0x0002c400), + EMIT_MASKWRITE(0xf8006134, 0x000fffff, 0x0002f003), + EMIT_MASKWRITE(0xf8006138, 0x000fffff, 0x0002ec03), + EMIT_MASKWRITE(0xf8006140, 0x000fffff, 0x00000035), + EMIT_MASKWRITE(0xf8006144, 0x000fffff, 0x00000035), + EMIT_MASKWRITE(0xf8006148, 0x000fffff, 0x00000035), + EMIT_MASKWRITE(0xf800614c, 0x000fffff, 0x00000035), + EMIT_MASKWRITE(0xf8006154, 0x000fffff, 0x00000077), + EMIT_MASKWRITE(0xf8006158, 0x000fffff, 0x00000077), + EMIT_MASKWRITE(0xf800615c, 0x000fffff, 0x00000083), + EMIT_MASKWRITE(0xf8006160, 0x000fffff, 0x00000083), + EMIT_MASKWRITE(0xf8006168, 0x001fffff, 0x00000105), + EMIT_MASKWRITE(0xf800616c, 0x001fffff, 0x00000106), + EMIT_MASKWRITE(0xf8006170, 0x001fffff, 0x00000111), + EMIT_MASKWRITE(0xf8006174, 0x001fffff, 0x00000110), + EMIT_MASKWRITE(0xf800617c, 0x000fffff, 0x000000b7), + EMIT_MASKWRITE(0xf8006180, 0x000fffff, 0x000000b7), + EMIT_MASKWRITE(0xf8006184, 0x000fffff, 0x000000c3), + EMIT_MASKWRITE(0xf8006188, 0x000fffff, 0x000000c3), + EMIT_MASKWRITE(0xf8006190, 0x6ffffefe, 0x00040080), + EMIT_MASKWRITE(0xf8006194, 0x000fffff, 0x0001fd01), + EMIT_MASKWRITE(0xf8006204, 0xffffffff, 0x00000000), + EMIT_MASKWRITE(0xf8006208, 0x000703ff, 0x000003ff), + EMIT_MASKWRITE(0xf800620c, 0x000703ff, 0x000003ff), + EMIT_MASKWRITE(0xf8006210, 0x000703ff, 0x000003ff), + EMIT_MASKWRITE(0xf8006214, 0x000703ff, 0x000003ff), + EMIT_MASKWRITE(0xf8006218, 0x000f03ff, 0x000003ff), + EMIT_MASKWRITE(0xf800621c, 0x000f03ff, 0x000003ff), + EMIT_MASKWRITE(0xf8006220, 0x000f03ff, 0x000003ff), + EMIT_MASKWRITE(0xf8006224, 0x000f03ff, 0x000003ff), + EMIT_MASKWRITE(0xf80062a8, 0x00000ff5, 0x00000000), + EMIT_MASKWRITE(0xf80062ac, 0xffffffff, 0x00000000), + EMIT_MASKWRITE(0xf80062b0, 0x003fffff, 0x00005125), + EMIT_MASKWRITE(0xf80062b4, 0x0003ffff, 0x000012a8), + EMIT_MASKPOLL(0xf8000b74, 0x00002000), + EMIT_MASKWRITE(0xf8006000, 0x0001ffff, 0x00000081), + EMIT_MASKPOLL(0xf8006054, 0x00000007), + EMIT_EXIT(), +}; + +static unsigned long ps7_mio_init_data_3_0[] = { + EMIT_MASKWRITE(0xf8000008, 0x0000ffff, 0x0000df0d), + EMIT_MASKWRITE(0xf8000b40, 0x00000fff, 0x00000600), + EMIT_MASKWRITE(0xf8000b44, 0x00000fff, 0x00000600), + EMIT_MASKWRITE(0xf8000b48, 0x00000fff, 0x00000672), + EMIT_MASKWRITE(0xf8000b4c, 0x00000fff, 0x00000672), + EMIT_MASKWRITE(0xf8000b50, 0x00000fff, 0x00000674), + EMIT_MASKWRITE(0xf8000b54, 0x00000fff, 0x00000674), + EMIT_MASKWRITE(0xf8000b58, 0x00000fff, 0x00000600), + EMIT_MASKWRITE(0xf8000b5c, 0xffffffff, 0x0018c068), + EMIT_MASKWRITE(0xf8000b60, 0xffffffff, 0x00f98068), + EMIT_MASKWRITE(0xf8000b64, 0xffffffff, 0x00f98068), + EMIT_MASKWRITE(0xf8000b68, 0xffffffff, 0x00f98068), + EMIT_MASKWRITE(0xf8000b6c, 0x00007fff, 0x00000205), + EMIT_MASKWRITE(0xf8000b70, 0x00000001, 0x00000001), + EMIT_MASKWRITE(0xf8000b70, 0x00000021, 0x00000020), + EMIT_MASKWRITE(0xf8000b70, 0x07feffff, 0x00000823), + EMIT_MASKWRITE(0xf8000700, 0x00003fff, 0x00000610), + EMIT_MASKWRITE(0xf8000704, 0x00003fff, 0x00000600), + EMIT_MASKWRITE(0xf8000708, 0x00003fff, 0x00000610), + EMIT_MASKWRITE(0xf800070c, 0x00003fff, 0x00000610), + EMIT_MASKWRITE(0xf8000710, 0x00003fff, 0x00000610), + EMIT_MASKWRITE(0xf8000714, 0x00003fff, 0x00000610), + EMIT_MASKWRITE(0xf8000718, 0x00003fff, 0x00000610), + EMIT_MASKWRITE(0xf800071c, 0x00003fff, 0x00000610), + EMIT_MASKWRITE(0xf8000720, 0x00003fff, 0x00000610), + EMIT_MASKWRITE(0xf8000724, 0x00003fff, 0x00000610), + EMIT_MASKWRITE(0xf8000728, 0x00003fff, 0x00000610), + EMIT_MASKWRITE(0xf800072c, 0x00003fff, 0x00000610), + EMIT_MASKWRITE(0xf8000730, 0x00003fff, 0x00000610), + EMIT_MASKWRITE(0xf8000734, 0x00003fff, 0x00000610), + EMIT_MASKWRITE(0xf8000738, 0x00003fff, 0x00000611), + EMIT_MASKWRITE(0xf800073c, 0x00003fff, 0x00000600), + EMIT_MASKWRITE(0xf8000740, 0x00003fff, 0x00000202), + EMIT_MASKWRITE(0xf8000744, 0x00003fff, 0x00000202), + EMIT_MASKWRITE(0xf8000748, 0x00003fff, 0x00000202), + EMIT_MASKWRITE(0xf800074c, 0x00003fff, 0x00000202), + EMIT_MASKWRITE(0xf8000750, 0x00003fff, 0x00000202), + EMIT_MASKWRITE(0xf8000754, 0x00003fff, 0x00000202), + EMIT_MASKWRITE(0xf8000758, 0x00003fff, 0x00000203), + EMIT_MASKWRITE(0xf800075c, 0x00003fff, 0x00000203), + EMIT_MASKWRITE(0xf8000760, 0x00003fff, 0x00000203), + EMIT_MASKWRITE(0xf8000764, 0x00003fff, 0x00000203), + EMIT_MASKWRITE(0xf8000768, 0x00003fff, 0x00000203), + EMIT_MASKWRITE(0xf800076c, 0x00003fff, 0x00000203), + EMIT_MASKWRITE(0xf8000770, 0x00003fff, 0x00000200), + EMIT_MASKWRITE(0xf8000774, 0x00003fff, 0x00000200), + EMIT_MASKWRITE(0xf8000778, 0x00003fff, 0x00000200), + EMIT_MASKWRITE(0xf800077c, 0x00003fff, 0x00000200), + EMIT_MASKWRITE(0xf8000780, 0x00003fff, 0x00000200), + EMIT_MASKWRITE(0xf8000784, 0x00003fff, 0x00000200), + EMIT_MASKWRITE(0xf8000788, 0x00003fff, 0x00000200), + EMIT_MASKWRITE(0xf800078c, 0x00003fff, 0x00000200), + EMIT_MASKWRITE(0xf8000790, 0x00003fff, 0x00000200), + EMIT_MASKWRITE(0xf8000794, 0x00003fff, 0x00000200), + EMIT_MASKWRITE(0xf8000798, 0x00003fff, 0x00000200), + EMIT_MASKWRITE(0xf800079c, 0x00003fff, 0x00000200), + EMIT_MASKWRITE(0xf80007a0, 0x00003fff, 0x00000280), + EMIT_MASKWRITE(0xf80007a4, 0x00003fff, 0x00000280), + EMIT_MASKWRITE(0xf80007a8, 0x00003fff, 0x00000280), + EMIT_MASKWRITE(0xf80007ac, 0x00003fff, 0x00000280), + EMIT_MASKWRITE(0xf80007b0, 0x00003fff, 0x00000280), + EMIT_MASKWRITE(0xf80007b4, 0x00003fff, 0x00000280), + EMIT_MASKWRITE(0xf80007b8, 0x00003f01, 0x00000201), + EMIT_MASKWRITE(0xf80007bc, 0x00003fff, 0x00000200), + EMIT_MASKWRITE(0xf80007c0, 0x00003fff, 0x000002e0), + EMIT_MASKWRITE(0xf80007c4, 0x00003fff, 0x000002e1), + EMIT_MASKWRITE(0xf80007c8, 0x00003f01, 0x00000201), + EMIT_MASKWRITE(0xf80007cc, 0x00003fff, 0x00000200), + EMIT_MASKWRITE(0xf80007d0, 0x00003fff, 0x00000280), + EMIT_MASKWRITE(0xf80007d4, 0x00003fff, 0x00000280), + EMIT_MASKWRITE(0xf8000830, 0x003f003f, 0x002e0032), + EMIT_MASKWRITE(0xf8000004, 0x0000ffff, 0x0000767b), + EMIT_EXIT(), +}; + +static unsigned long ps7_peripherals_init_data_3_0[] = { + EMIT_MASKWRITE(0xf8000008, 0x0000ffff, 0x0000df0d), + EMIT_MASKWRITE(0xf8000b48, 0x00000180, 0x00000180), + EMIT_MASKWRITE(0xf8000b4c, 0x00000180, 0x00000180), + EMIT_MASKWRITE(0xf8000b50, 0x00000180, 0x00000180), + EMIT_MASKWRITE(0xf8000b54, 0x00000180, 0x00000180), + EMIT_MASKWRITE(0xf8000004, 0x0000ffff, 0x0000767b), + EMIT_MASKWRITE(0xe0001034, 0x000000ff, 0x00000006), + EMIT_MASKWRITE(0xe0001018, 0x0000ffff, 0x0000003e), + EMIT_MASKWRITE(0xe0001000, 0x000001ff, 0x00000017), + EMIT_MASKWRITE(0xe0001004, 0x000003ff, 0x00000020), + EMIT_MASKWRITE(0xe000d000, 0x00080000, 0x00080000), + EMIT_MASKWRITE(0xf8007000, 0x20000000, 0x00000000), + EMIT_MASKWRITE(0xe000e014, 0x00ffffff, 0x00449144), + EMIT_MASKWRITE(0xe000e018, 0x00000003, 0x00000000), + EMIT_MASKWRITE(0xe000e010, 0x03e00000, 0x02400000), + EMIT_MASKDELAY(0xf8f00200, 0x00000001), + EMIT_MASKDELAY(0xf8f00200, 0x00000001), + EMIT_MASKDELAY(0xf8f00200, 0x00000001), + EMIT_MASKDELAY(0xf8f00200, 0x00000001), + EMIT_MASKDELAY(0xf8f00200, 0x00000001), + EMIT_MASKDELAY(0xf8f00200, 0x00000001), + EMIT_EXIT(), +}; + +static unsigned long ps7_post_config_3_0[] = { + EMIT_MASKWRITE(0xf8000008, 0x0000ffff, 0x0000df0d), + EMIT_MASKWRITE(0xf8000900, 0x0000000f, 0x0000000f), + EMIT_MASKWRITE(0xf8000240, 0xffffffff, 0x00000000), + EMIT_MASKWRITE(0xf8008000, 0x00000001, 0x00000001), + EMIT_MASKWRITE(0xf8008014, 0x00000001, 0x00000001), + EMIT_MASKWRITE(0xf8000004, 0x0000ffff, 0x0000767b), + EMIT_EXIT(), +}; + +int ps7_init(void) +{ + int ret; + + ret = ps7_config(ps7_mio_init_data_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + ret = ps7_config(ps7_pll_init_data_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + ret = ps7_config(ps7_clock_init_data_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + ret = ps7_config(ps7_ddr_init_data_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + ret = ps7_config(ps7_peripherals_init_data_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + + return PS7_INIT_SUCCESS; +} + +int ps7_post_config(void) +{ + return ps7_config(ps7_post_config_3_0); +} diff --git a/board/bitmain/antminer_s9/board.c b/board/bitmain/antminer_s9/board.c new file mode 100644 index 0000000..bb7cef3 --- /dev/null +++ b/board/bitmain/antminer_s9/board.c @@ -0,0 +1,2 @@ +// SPDX-License-Identifier: GPL-2.0 +#include "../../xilinx/zynq/board.c" diff --git a/configs/bitmain_antminer_s9_defconfig b/configs/bitmain_antminer_s9_defconfig new file mode 100644 index 0000000..fc52da0 --- /dev/null +++ b/configs/bitmain_antminer_s9_defconfig @@ -0,0 +1,66 @@ +CONFIG_ARM=y +CONFIG_SYS_VENDOR="bitmain" +CONFIG_SYS_BOARD="antminer_s9" +CONFIG_SYS_CONFIG_NAME="bitmain_antminer_s9" +CONFIG_ARCH_ZYNQ=y +CONFIG_SYS_TEXT_BASE=0x4000000 +CONFIG_SPL=y +CONFIG_SPL_STACK_R_ADDR=0x200000 +CONFIG_DEFAULT_DEVICE_TREE="bitmain-antminer-s9" +CONFIG_DEBUG_UART=y +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_FIT_VERBOSE=y +CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_SPL_STACK_R=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="antminer> " +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_DM is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_FPGA_LOADBP=y +CONFIG_CMD_FPGA_LOADFS=y +CONFIG_CMD_FPGA_LOADMK=y +CONFIG_CMD_FPGA_LOADP=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_MMC=y +CONFIG_CMD_NAND_LOCK_UNLOCK=y +CONFIG_CMD_PART=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +# CONFIG_CMD_NFS is not set +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_PXE=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_EMBED=y +CONFIG_ENV_IS_IN_NAND=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_BOOTCOUNT_LIMIT=y +CONFIG_SYS_BOOTCOUNT_ADDR=0xEFFFFF0 +CONFIG_FPGA_XILINX=y +CONFIG_FPGA_ZYNQPL=y +CONFIG_DM_GPIO=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ZYNQ=y +CONFIG_NAND=y +CONFIG_NAND_ZYNQ=y +CONFIG_NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS=y +CONFIG_ZYNQ_GEM=y +CONFIG_DEBUG_UART_ZYNQ=y +CONFIG_DEBUG_UART_BASE=0xe0001000 +CONFIG_DEBUG_UART_CLOCK=50000000 +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_ZYNQ_SERIAL=y +# CONFIG_WATCHDOG is not set +CONFIG_WDT=y +CONFIG_WDT_CDNS=y +# CONFIG_EFI_LOADER is not set diff --git a/include/configs/bitmain_antminer_s9.h b/include/configs/bitmain_antminer_s9.h new file mode 100644 index 0000000..2267502 --- /dev/null +++ b/include/configs/bitmain_antminer_s9.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * (C) Copyright 2018 Michal Simek + */ + +#ifndef __CONFIG_BITMAIN_ANTMINER_S9_H +#define __CONFIG_BITMAIN_ANTMINER_S9_H + +#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_SIZE 0x40000000 + +#define CONFIG_ENV_SIZE 0x20000 +#define CONFIG_ENV_OFFSET 0x300000 + +#define CONFIG_BOOTP_SERVERIP + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "autoload=no\0" \ + "pxefile_addr_r=0x2000000\0" \ + "scriptaddr=0x3000000\0" \ + "kernel_addr_r=0x2000000\0" \ + "fdt_high=0xefff000\0" \ + "initrd_high=0xefff000\0" \ + "devnum=0\0" \ + "wdstop=mw f8005000 ABC000\0" \ + BOOTENV + +#include + +#endif /* __CONFIG_BITMAIN_ANTMINER_S9_H */ -- cgit v1.1 From 3705dae164f807bf4fb993c5fe2eae3c86f95b9e Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 29 May 2018 14:45:13 +0200 Subject: arm64: zynqmp: Add ina226 to zcu104 revC Add new ina226 chip present on i2c bus which wasn't on revA. Signed-off-by: Michal Simek --- arch/arm/dts/zynqmp-zcu104-revC.dts | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/arch/arm/dts/zynqmp-zcu104-revC.dts b/arch/arm/dts/zynqmp-zcu104-revC.dts index 6e3cf5a..f3ab99a 100644 --- a/arch/arm/dts/zynqmp-zcu104-revC.dts +++ b/arch/arm/dts/zynqmp-zcu104-revC.dts @@ -145,10 +145,15 @@ }; }; - i2c@4 { + i2c@3 { #address-cells = <1>; #size-cells = <0>; - reg = <4>; + reg = <3>; + ina226@40 { /* u183 */ + compatible = "ti,ina226"; + reg = <0x40>; + shunt-resistor = <5000>; + }; }; i2c@5 { @@ -163,7 +168,7 @@ reg = <7>; }; - /* 3, 6 not connected */ + /* 4, 6 not connected */ }; }; -- cgit v1.1 From ce236dce56a826805bcf83f9ef2efcb7cf6eeb5b Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 29 May 2018 15:28:43 +0200 Subject: arm64: zynqmp: Fix address for tca6416_u97 chip on zcu104 I2c address is not 0x21 but 0x20. This patch is fixing both revA and revC boards. Signed-off-by: Michal Simek --- arch/arm/dts/zynqmp-zcu104-revA.dts | 4 ++-- arch/arm/dts/zynqmp-zcu104-revC.dts | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/dts/zynqmp-zcu104-revA.dts b/arch/arm/dts/zynqmp-zcu104-revA.dts index a0e13d8..6a4b701 100644 --- a/arch/arm/dts/zynqmp-zcu104-revA.dts +++ b/arch/arm/dts/zynqmp-zcu104-revA.dts @@ -130,9 +130,9 @@ #address-cells = <1>; #size-cells = <0>; reg = <4>; - tca6416_u97: gpio@21 { + tca6416_u97: gpio@20 { compatible = "ti,tca6416"; - reg = <0x21>; + reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* diff --git a/arch/arm/dts/zynqmp-zcu104-revC.dts b/arch/arm/dts/zynqmp-zcu104-revC.dts index f3ab99a..fe742b8 100644 --- a/arch/arm/dts/zynqmp-zcu104-revC.dts +++ b/arch/arm/dts/zynqmp-zcu104-revC.dts @@ -74,9 +74,9 @@ status = "okay"; clock-frequency = <400000>; - tca6416_u97: gpio@21 { + tca6416_u97: gpio@20 { compatible = "ti,tca6416"; - reg = <0x21>; + reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* -- cgit v1.1 From 3e98a9c4167299cc3c6a608681a8b48e4a5bdefa Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 28 May 2018 15:19:02 +0200 Subject: arm64: zynqmp: Remove broken-cd from zcu100-revC Card detect bit was broken on revA and it is working fine with revC board that's why this property can be removed. Signed-off-by: Michal Simek --- arch/arm/dts/zynqmp-zcu100-revC.dts | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/dts/zynqmp-zcu100-revC.dts b/arch/arm/dts/zynqmp-zcu100-revC.dts index bcd9c39..c6aaa08 100644 --- a/arch/arm/dts/zynqmp-zcu100-revC.dts +++ b/arch/arm/dts/zynqmp-zcu100-revC.dts @@ -252,7 +252,6 @@ &sdhci0 { status = "okay"; no-1-8-v; - broken-cd; /* CD has to be enabled by default */ disable-wp; xlnx,mio_bank = <0>; }; -- cgit v1.1 From f0d56145d934b560ee9ef8ba6b4655a214696b75 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 4 Apr 2018 14:08:24 +0200 Subject: arm64: zynqmp: Disable WP on zcu111 On this board there is SD slot without WP connected. Signed-off-by: Michal Simek --- arch/arm/dts/zynqmp-zcu111-revA.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/dts/zynqmp-zcu111-revA.dts b/arch/arm/dts/zynqmp-zcu111-revA.dts index 4002d78..aa9055b 100644 --- a/arch/arm/dts/zynqmp-zcu111-revA.dts +++ b/arch/arm/dts/zynqmp-zcu111-revA.dts @@ -500,6 +500,7 @@ &sdhci1 { status = "okay"; no-1-8-v; + disable-wp; xlnx,mio_bank = <1>; }; -- cgit v1.1 From ecb4d7481e78af2f0ae67236f82f091b87112180 Mon Sep 17 00:00:00 2001 From: Rajan Vaja Date: Wed, 25 Apr 2018 05:34:04 -0700 Subject: arm64: zynqmp: Add TTC clocks PS clock(LPD_APB_CLK) is default clock for TTC. Add this clock entry in TTC nodes. Signed-off-by: Rajan Vaja Signed-off-by: Michal Simek --- arch/arm/dts/zynqmp-clk-ccf.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm/dts/zynqmp-clk-ccf.dtsi b/arch/arm/dts/zynqmp-clk-ccf.dtsi index b18d8d1..247a35f 100644 --- a/arch/arm/dts/zynqmp-clk-ccf.dtsi +++ b/arch/arm/dts/zynqmp-clk-ccf.dtsi @@ -248,6 +248,22 @@ clocks = <&clkc 59>, <&clkc 31>; }; +&ttc0 { + clocks = <&clkc 31>; +}; + +&ttc1 { + clocks = <&clkc 31>; +}; + +&ttc2 { + clocks = <&clkc 31>; +}; + +&ttc3 { + clocks = <&clkc 31>; +}; + &uart0 { clocks = <&clkc 56>, <&clkc 31>; }; -- cgit v1.1 From 434f9d454eb1a17bb7f5cdb21167ccbe7e41da39 Mon Sep 17 00:00:00 2001 From: Siva Durga Prasad Paladugu Date: Tue, 29 May 2018 20:03:10 +0530 Subject: mmc: sdhci: Update sdhci_send_command() to handle HS200 This patch updates sdhci_send_command() to handle MMC HS200 tuning command. Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek --- drivers/mmc/sdhci.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c index 400f87e..40e28ab 100644 --- a/drivers/mmc/sdhci.c +++ b/drivers/mmc/sdhci.c @@ -161,7 +161,8 @@ static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd, /* We shouldn't wait for data inihibit for stop commands, even though they might use busy signaling */ if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION || - cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK) + cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK || + cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) mask &= ~SDHCI_DATA_INHIBIT; while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) { @@ -183,7 +184,8 @@ static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd, sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS); mask = SDHCI_INT_RESPONSE; - if (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK) + if (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK || + cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) mask = SDHCI_INT_DATA_AVAIL; if (!(cmd->resp_type & MMC_RSP_PRESENT)) @@ -201,7 +203,8 @@ static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd, flags |= SDHCI_CMD_CRC; if (cmd->resp_type & MMC_RSP_OPCODE) flags |= SDHCI_CMD_INDEX; - if (data || cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK) + if (data || cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK || + cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) flags |= SDHCI_CMD_DATA; /* Set Transfer mode regarding to data flag */ -- cgit v1.1 From 843337089ea7002173ad8f522a8cbe396abd312c Mon Sep 17 00:00:00 2001 From: Siva Durga Prasad Paladugu Date: Tue, 29 May 2018 20:03:11 +0530 Subject: mmc: zynqmp: Add HS200 modes support for ZynqMP This patch adds HS200 suuport for ZynqMP and enables the same for ZC1751 DC1 board which has eMMC on it. Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek --- configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig | 1 + drivers/mmc/zynq_sdhci.c | 25 ++++++++++++++++-------- 2 files changed, 18 insertions(+), 8 deletions(-) diff --git a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig index f5a3334..96abf61 100644 --- a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig @@ -54,6 +54,7 @@ CONFIG_DM_I2C=y CONFIG_SYS_I2C_CADENCE=y CONFIG_MISC=y CONFIG_DM_MMC=y +CONFIG_MMC_HS200_SUPPORT=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y CONFIG_SPI_FLASH=y diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c index 1f6d053..5b6d525 100644 --- a/drivers/mmc/zynq_sdhci.c +++ b/drivers/mmc/zynq_sdhci.c @@ -32,12 +32,21 @@ struct arasan_sdhci_priv { }; #if defined(CONFIG_ARCH_ZYNQMP) +#define MMC_HS200_BUS_SPEED 5 + static const u8 mode2timing[] = { - [UHS_SDR12] = UHS_SDR12_BUS_SPEED, - [UHS_SDR25] = UHS_SDR25_BUS_SPEED, - [UHS_SDR50] = UHS_SDR50_BUS_SPEED, - [UHS_SDR104] = UHS_SDR104_BUS_SPEED, - [UHS_DDR50] = UHS_DDR50_BUS_SPEED, + [MMC_LEGACY] = UHS_SDR12_BUS_SPEED, + [SD_LEGACY] = UHS_SDR12_BUS_SPEED, + [MMC_HS] = HIGH_SPEED_BUS_SPEED, + [SD_HS] = HIGH_SPEED_BUS_SPEED, + [MMC_HS_52] = HIGH_SPEED_BUS_SPEED, + [MMC_DDR_52] = HIGH_SPEED_BUS_SPEED, + [UHS_SDR12] = UHS_SDR12_BUS_SPEED, + [UHS_SDR25] = UHS_SDR25_BUS_SPEED, + [UHS_SDR50] = UHS_SDR50_BUS_SPEED, + [UHS_DDR50] = UHS_DDR50_BUS_SPEED, + [UHS_SDR104] = UHS_SDR104_BUS_SPEED, + [MMC_HS_200] = MMC_HS200_BUS_SPEED, }; #define SDHCI_HOST_CTRL2 0x3E @@ -160,9 +169,6 @@ static void arasan_sdhci_set_tapdelay(struct sdhci_host *host) struct mmc *mmc = (struct mmc *)host->mmc; u8 uhsmode; - if (!IS_SD(mmc)) - return; - uhsmode = mode2timing[mmc->selected_mode]; if (uhsmode >= UHS_SDR25_BUS_SPEED) @@ -175,6 +181,9 @@ static void arasan_sdhci_set_control_reg(struct sdhci_host *host) struct mmc *mmc = (struct mmc *)host->mmc; u32 reg; + if (!IS_SD(mmc)) + return; + if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180) { reg = sdhci_readw(host, SDHCI_HOST_CTRL2); reg |= SDHCI_18V_SIGNAL; -- cgit v1.1 From f5953610bf9198a585e39c8074ef9dea1106da9c Mon Sep 17 00:00:00 2001 From: Siva Durga Prasad Paladugu Date: Thu, 31 May 2018 15:10:21 +0530 Subject: cmd: fpga: Reorder the arguments parsing code This patch modifies the arguments parsing code by parsing based on requested operation for fpga loadfs and then parses the most common/basic args for other fpga load commands. This makes it easy for new command extensions or additions especially the commands with more args. Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek --- cmd/fpga.c | 31 +++++++++++++++++++------------ 1 file changed, 19 insertions(+), 12 deletions(-) diff --git a/cmd/fpga.c b/cmd/fpga.c index 14ad4e5..3f09d42 100644 --- a/cmd/fpga.c +++ b/cmd/fpga.c @@ -60,15 +60,31 @@ int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) if (datastr) fpga_data = (void *)simple_strtoul(datastr, NULL, 16); - switch (argc) { + if (argc > 9 || argc < 2) { + debug("%s: Too many or too few args (%d)\n", __func__, argc); + return CMD_RET_USAGE; + } + + op = (int)fpga_get_op(argv[1]); + + switch (op) { #if defined(CONFIG_CMD_FPGA_LOADFS) - case 9: + case FPGA_LOADFS: + if (argc < 9) + return CMD_RET_USAGE; fpga_fsinfo.blocksize = (unsigned int) - simple_strtoul(argv[5], NULL, 16); + simple_strtoul(argv[5], NULL, 16); fpga_fsinfo.interface = argv[6]; fpga_fsinfo.dev_part = argv[7]; fpga_fsinfo.filename = argv[8]; + argc = 5; + break; #endif + default: + break; + } + + switch (argc) { case 5: /* fpga */ data_size = simple_strtoul(argv[4], NULL, 16); @@ -117,15 +133,6 @@ int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) __func__, (ulong)fpga_data); dev = FPGA_INVALID_DEVICE; /* reset device num */ } - - case 2: /* fpga */ - op = (int)fpga_get_op(argv[1]); - break; - - default: - debug("%s: Too many or too few args (%d)\n", __func__, argc); - op = FPGA_NONE; /* force usage display */ - break; } if (dev == FPGA_INVALID_DEVICE) { -- cgit v1.1 From cedd48e2cdb752444444a97157025f16e63ee446 Mon Sep 17 00:00:00 2001 From: Siva Durga Prasad Paladugu Date: Thu, 31 May 2018 15:10:22 +0530 Subject: cmd: fpga: Add support to load secure bitstreams This patch adds support to load secure bitstreams(authenticated or encrypted or both). As of now, this feature is added and tested only for xilinx bitstreams and the secure bitstream was generated using xilinx bootgen tool, but the command is defined in more generic way. Command example to load authenticated and device key encrypted bitstream is as follows "fpga loads 0 100000 2000000 0 1" Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek --- cmd/Kconfig | 7 ++++++ cmd/fpga.c | 62 ++++++++++++++++++++++++++++++++++++++++++++++++++++- drivers/fpga/fpga.c | 29 +++++++++++++++++++++++++ include/fpga.h | 11 ++++++++++ 4 files changed, 108 insertions(+), 1 deletion(-) diff --git a/cmd/Kconfig b/cmd/Kconfig index d532c9f..c4e831e 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -697,6 +697,13 @@ config CMD_FPGA_LOADP Supports loading an FPGA device from a bitstream buffer containing a partial bitstream. +config CMD_FPGA_LOAD_SECURE + bool "fpga loads - loads secure bitstreams (Xilinx only)" + depends on CMD_FPGA + help + Enables the fpga loads command which is used to load secure + (authenticated or encrypted or both) bitstreams on to FPGA. + config CMD_FPGAD bool "fpgad - dump FPGA registers" help diff --git a/cmd/fpga.c b/cmd/fpga.c index 3f09d42..74ae80c 100644 --- a/cmd/fpga.c +++ b/cmd/fpga.c @@ -27,6 +27,7 @@ enum { FPGA_LOADP, FPGA_LOADBP, FPGA_LOADFS, + FPGA_LOADS, }; /* ------------------------------------------------------------------------- */ @@ -54,6 +55,11 @@ int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) fpga_fs_info fpga_fsinfo; fpga_fsinfo.fstype = FS_TYPE_ANY; #endif +#if defined(CONFIG_CMD_FPGA_LOAD_SECURE) + struct fpga_secure_info fpga_sec_info; + + memset(&fpga_sec_info, 0, sizeof(fpga_sec_info)); +#endif if (devstr) dev = (int) simple_strtoul(devstr, NULL, 16); @@ -80,6 +86,19 @@ int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) argc = 5; break; #endif +#if defined(CONFIG_CMD_FPGA_LOAD_SECURE) + case FPGA_LOADS: + if (argc < 7) + return CMD_RET_USAGE; + if (argc == 8) + fpga_sec_info.userkey_addr = (u8 *)(uintptr_t) + simple_strtoull(argv[7], + NULL, 16); + fpga_sec_info.encflag = (u8)simple_strtoul(argv[6], NULL, 16); + fpga_sec_info.authflag = (u8)simple_strtoul(argv[5], NULL, 16); + argc = 5; + break; +#endif default: break; } @@ -150,6 +169,22 @@ int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) if (!fpga_fsinfo.interface || !fpga_fsinfo.dev_part || !fpga_fsinfo.filename) wrong_parms = 1; + break; +#endif +#if defined(CONFIG_CMD_FPGA_LOAD_SECURE) + case FPGA_LOADS: + if (fpga_sec_info.authflag >= FPGA_NO_ENC_OR_NO_AUTH && + fpga_sec_info.encflag >= FPGA_NO_ENC_OR_NO_AUTH) { + puts("ERR: use for NonSecure bitstream\n"); + wrong_parms = 1; + } + + if (fpga_sec_info.encflag == FPGA_ENC_USR_KEY && + !fpga_sec_info.userkey_addr) { + wrong_parms = 1; + puts("ERR:User key not provided\n"); + } + break; #endif case FPGA_LOAD: case FPGA_LOADP: @@ -206,6 +241,12 @@ int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) break; #endif +#if defined(CONFIG_CMD_FPGA_LOAD_SECURE) + case FPGA_LOADS: + rc = fpga_loads(dev, fpga_data, data_size, &fpga_sec_info); + break; +#endif + #if defined(CONFIG_CMD_FPGA_LOADMK) case FPGA_LOADMK: switch (genimg_get_format(fpga_data)) { @@ -339,6 +380,10 @@ static int fpga_get_op(char *opstr) #endif else if (!strcmp("dump", opstr)) op = FPGA_DUMP; +#if defined(CONFIG_CMD_FPGA_LOAD_SECURE) + else if (!strcmp("loads", opstr)) + op = FPGA_LOADS; +#endif if (op == FPGA_NONE) printf("Unknown fpga operation \"%s\"\n", opstr); @@ -346,7 +391,7 @@ static int fpga_get_op(char *opstr) return op; } -#if defined(CONFIG_CMD_FPGA_LOADFS) +#if defined(CONFIG_CMD_FPGA_LOADFS) || defined(CONFIG_CMD_FPGA_LOAD_SECURE) U_BOOT_CMD(fpga, 9, 1, do_fpga, #else U_BOOT_CMD(fpga, 6, 1, do_fpga, @@ -381,4 +426,19 @@ U_BOOT_CMD(fpga, 6, 1, do_fpga, "\tsubimage unit name in the form of addr:" #endif #endif +#if defined(CONFIG_CMD_FPGA_LOAD_SECURE) + "Load encrypted bitstream (Xilinx only)\n" + " loads [dev] [address] [size] [auth-OCM-0/DDR-1/noauth-2]\n" + " [enc-devkey(0)/userkey(1)/nenc(2) [Userkey address]\n" + "Loads the secure bistreams(authenticated/encrypted/both\n" + "authenticated and encrypted) of [size] from [address].\n" + "The auth-OCM/DDR flag specifies to perform authentication\n" + "in OCM or in DDR. 0 for OCM, 1 for DDR, 2 for no authentication.\n" + "The enc flag specifies which key to be used for decryption\n" + "0-device key, 1-user key, 2-no encryption.\n" + "The optional Userkey address specifies from which address key\n" + "has to be used for decryption if user key is selected.\n" + "NOTE: the sceure bitstream has to be created using xilinx\n" + "bootgen tool only.\n" +#endif ); diff --git a/drivers/fpga/fpga.c b/drivers/fpga/fpga.c index 55bdf9e..7e8bd7e 100644 --- a/drivers/fpga/fpga.c +++ b/drivers/fpga/fpga.c @@ -217,6 +217,35 @@ int fpga_fsload(int devnum, const void *buf, size_t size, } #endif +#if defined(CONFIG_CMD_FPGA_LOAD_SECURE) +int fpga_loads(int devnum, const void *buf, size_t size, + struct fpga_secure_info *fpga_sec_info) +{ + int ret_val = FPGA_FAIL; + + const fpga_desc *desc = fpga_validate(devnum, buf, size, + (char *)__func__); + + if (desc) { + switch (desc->devtype) { + case fpga_xilinx: +#if defined(CONFIG_FPGA_XILINX) + ret_val = xilinx_loads(desc->devdesc, buf, size, + fpga_sec_info); +#else + fpga_no_sup((char *)__func__, "Xilinx devices"); +#endif + break; + default: + printf("%s: Invalid or unsupported device type %d\n", + __func__, desc->devtype); + } + } + + return ret_val; +} +#endif + /* * Generic multiplexing code */ diff --git a/include/fpga.h b/include/fpga.h index f444093..195f0bd 100644 --- a/include/fpga.h +++ b/include/fpga.h @@ -20,6 +20,9 @@ /* device numbers must be non-negative */ #define FPGA_INVALID_DEVICE -1 +#define FPGA_ENC_USR_KEY 1 +#define FPGA_NO_ENC_OR_NO_AUTH 2 + /* root data type defintions */ typedef enum { /* typedef fpga_type */ fpga_min_type, /* range check value */ @@ -42,6 +45,12 @@ typedef struct { /* typedef fpga_desc */ int fstype; } fpga_fs_info; +struct fpga_secure_info { + u8 *userkey_addr; + u8 authflag; + u8 encflag; +}; + typedef enum { BIT_FULL = 0, BIT_PARTIAL, @@ -58,6 +67,8 @@ int fpga_load(int devnum, const void *buf, size_t bsize, bitstream_type bstype); int fpga_fsload(int devnum, const void *buf, size_t size, fpga_fs_info *fpga_fsinfo); +int fpga_loads(int devnum, const void *buf, size_t size, + struct fpga_secure_info *fpga_sec_info); int fpga_loadbitstream(int devnum, char *fpgadata, size_t size, bitstream_type bstype); int fpga_dump(int devnum, const void *buf, size_t bsize); -- cgit v1.1 From a18d09ea384fb66105fbfa24fd2d1288754b8f07 Mon Sep 17 00:00:00 2001 From: Siva Durga Prasad Paladugu Date: Thu, 31 May 2018 15:10:23 +0530 Subject: fpga: zynqmp: Add secure bitstream loading for ZynqMP This patch adds support for loading secure bitstreams on ZynqMP platforms. The secure bitstream images has to be generated using Xilinx bootgen tool. Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek --- arch/arm/include/asm/arch-zynqmp/sys_proto.h | 6 ++++ configs/xilinx_zynqmp_zcu102_rev1_0_defconfig | 1 + drivers/fpga/xilinx.c | 18 ++++++++++ drivers/fpga/zynqmppl.c | 48 +++++++++++++++++++++++++++ include/xilinx.h | 4 +++ include/zynqmppl.h | 3 ++ 6 files changed, 80 insertions(+) diff --git a/arch/arm/include/asm/arch-zynqmp/sys_proto.h b/arch/arm/include/asm/arch-zynqmp/sys_proto.h index 6056bc6..773b930 100644 --- a/arch/arm/include/asm/arch-zynqmp/sys_proto.h +++ b/arch/arm/include/asm/arch-zynqmp/sys_proto.h @@ -13,8 +13,14 @@ #define ZYNQMP_SIP_SVC_PM_SECURE_IMG_LOAD 0xC200002D #define KEY_PTR_LEN 32 +#define ZYNQMP_FPGA_BIT_AUTH_DDR 1 +#define ZYNQMP_FPGA_BIT_AUTH_OCM 2 +#define ZYNQMP_FPGA_BIT_ENC_USR_KEY 3 +#define ZYNQMP_FPGA_BIT_ENC_DEV_KEY 4 #define ZYNQMP_FPGA_BIT_NS 5 +#define ZYNQMP_FPGA_AUTH_DDR 1 + enum { IDCODE, VERSION, diff --git a/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig b/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig index 4cb3959..1379f14 100644 --- a/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig +++ b/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig @@ -31,6 +31,7 @@ CONFIG_CMD_DFU=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_FPGA_LOADBP=y CONFIG_CMD_FPGA_LOADP=y +CONFIG_CMD_FPGA_LOAD_SECURE=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y diff --git a/drivers/fpga/xilinx.c b/drivers/fpga/xilinx.c index 724304a..f513550 100644 --- a/drivers/fpga/xilinx.c +++ b/drivers/fpga/xilinx.c @@ -171,6 +171,24 @@ int xilinx_loadfs(xilinx_desc *desc, const void *buf, size_t bsize, } #endif +#if defined(CONFIG_CMD_FPGA_LOAD_SECURE) +int xilinx_loads(xilinx_desc *desc, const void *buf, size_t bsize, + struct fpga_secure_info *fpga_sec_info) +{ + if (!xilinx_validate(desc, (char *)__func__)) { + printf("%s: Invalid device descriptor\n", __func__); + return FPGA_FAIL; + } + + if (!desc->operations || !desc->operations->loads) { + printf("%s: Missing loads operation\n", __func__); + return FPGA_FAIL; + } + + return desc->operations->loads(desc, buf, bsize, fpga_sec_info); +} +#endif + int xilinx_dump(xilinx_desc *desc, const void *buf, size_t bsize) { if (!xilinx_validate (desc, (char *)__FUNCTION__)) { diff --git a/drivers/fpga/zynqmppl.c b/drivers/fpga/zynqmppl.c index b57623b..03ffa8c 100644 --- a/drivers/fpga/zynqmppl.c +++ b/drivers/fpga/zynqmppl.c @@ -223,6 +223,51 @@ static int zynqmp_load(xilinx_desc *desc, const void *buf, size_t bsize, return ret; } +#if defined(CONFIG_CMD_FPGA_LOAD_SECURE) && !defined(CONFIG_SPL_BUILD) +static int zynqmp_loads(xilinx_desc *desc, const void *buf, size_t bsize, + struct fpga_secure_info *fpga_sec_info) +{ + int ret; + u32 buf_lo, buf_hi; + u32 ret_payload[PAYLOAD_ARG_CNT]; + u8 flag = 0; + + flush_dcache_range((ulong)buf, (ulong)buf + + ALIGN(bsize, CONFIG_SYS_CACHELINE_SIZE)); + + if (!fpga_sec_info->encflag) + flag |= BIT(ZYNQMP_FPGA_BIT_ENC_DEV_KEY); + + if (fpga_sec_info->userkey_addr && + fpga_sec_info->encflag == FPGA_ENC_USR_KEY) { + flush_dcache_range((ulong)fpga_sec_info->userkey_addr, + (ulong)fpga_sec_info->userkey_addr + + ALIGN(KEY_PTR_LEN, + CONFIG_SYS_CACHELINE_SIZE)); + flag |= BIT(ZYNQMP_FPGA_BIT_ENC_USR_KEY); + } + + if (!fpga_sec_info->authflag) + flag |= BIT(ZYNQMP_FPGA_BIT_AUTH_OCM); + + if (fpga_sec_info->authflag == ZYNQMP_FPGA_AUTH_DDR) + flag |= BIT(ZYNQMP_FPGA_BIT_AUTH_DDR); + + buf_lo = lower_32_bits((ulong)buf); + buf_hi = upper_32_bits((ulong)buf); + + ret = invoke_smc(ZYNQMP_SIP_SVC_PM_FPGA_LOAD, buf_lo, buf_hi, + (u32)(uintptr_t)fpga_sec_info->userkey_addr, + flag, ret_payload); + if (ret) + puts("PL FPGA LOAD fail\n"); + else + puts("Bitstream successfully loaded\n"); + + return ret; +} +#endif + static int zynqmp_pcap_info(xilinx_desc *desc) { int ret; @@ -238,5 +283,8 @@ static int zynqmp_pcap_info(xilinx_desc *desc) struct xilinx_fpga_op zynqmp_op = { .load = zynqmp_load, +#if defined CONFIG_CMD_FPGA_LOAD_SECURE + .loads = zynqmp_loads, +#endif .info = zynqmp_pcap_info, }; diff --git a/include/xilinx.h b/include/xilinx.h index 9429f51..af40bef 100644 --- a/include/xilinx.h +++ b/include/xilinx.h @@ -48,6 +48,8 @@ typedef struct { /* typedef xilinx_desc */ struct xilinx_fpga_op { int (*load)(xilinx_desc *, const void *, size_t, bitstream_type); int (*loadfs)(xilinx_desc *, const void *, size_t, fpga_fs_info *); + int (*loads)(xilinx_desc *desc, const void *buf, size_t bsize, + struct fpga_secure_info *fpga_sec_info); int (*dump)(xilinx_desc *, const void *, size_t); int (*info)(xilinx_desc *); }; @@ -60,6 +62,8 @@ int xilinx_dump(xilinx_desc *desc, const void *buf, size_t bsize); int xilinx_info(xilinx_desc *desc); int xilinx_loadfs(xilinx_desc *desc, const void *buf, size_t bsize, fpga_fs_info *fpga_fsinfo); +int xilinx_loads(xilinx_desc *desc, const void *buf, size_t bsize, + struct fpga_secure_info *fpga_sec_info); /* Board specific implementation specific function types *********************************************************************/ diff --git a/include/zynqmppl.h b/include/zynqmppl.h index a0f4e68..5214db9 100644 --- a/include/zynqmppl.h +++ b/include/zynqmppl.h @@ -16,6 +16,9 @@ #define ZYNQMP_FPGA_OP_LOAD (1 << 1) #define ZYNQMP_FPGA_OP_DONE (1 << 2) +#define ZYNQMP_FPGA_FLAG_AUTHENTICATED BIT(2) +#define ZYNQMP_FPGA_FLAG_ENCRYPTED BIT(3) + #define ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT 15 #define ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK (0xf << \ ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT) -- cgit v1.1