From e0f907efa529a2fe106cd585bd94730b1cf0410c Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Mon, 12 Aug 2019 20:02:29 +0800 Subject: ram: rk3399: update cap and ddrconfig for each channel after init We need to store all the ram related cap/map info back to register for each channel after all the init has been done in case some of register was reset during the process. Signed-off-by: YouMin Chen Signed-off-by: Kever Yang --- drivers/ram/rockchip/sdram_rk3399.c | 159 ++++++++++++++++++------------------ 1 file changed, 81 insertions(+), 78 deletions(-) diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index 81fc71c..ed70137 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -1488,6 +1488,84 @@ static void dram_all_config(struct dram_info *dram, clrsetbits_le32(&dram->cru->glb_rst_con, 0x3, 0x3); } +static void set_cap_relate_config(const struct chan_info *chan, + struct rk3399_sdram_params *params, + unsigned int channel) +{ + u32 *denali_ctl = chan->pctl->denali_ctl; + u32 tmp; + struct rk3399_msch_timings *noc_timing; + + if (params->base.dramtype == LPDDR3) { + tmp = (8 << params->ch[channel].cap_info.bw) / + (8 << params->ch[channel].cap_info.dbw); + + /** + * memdata_ratio + * 1 -> 0, 2 -> 1, 4 -> 2 + */ + clrsetbits_le32(&denali_ctl[197], 0x7, + (tmp >> 1)); + clrsetbits_le32(&denali_ctl[198], 0x7 << 8, + (tmp >> 1) << 8); + } + + noc_timing = ¶ms->ch[channel].noc_timings; + + /* + * noc timing bw relate timing is 32 bit, and real bw is 16bit + * actually noc reg is setting at function dram_all_config + */ + if (params->ch[channel].cap_info.bw == 16 && + noc_timing->ddrmode.b.mwrsize == 2) { + if (noc_timing->ddrmode.b.burstsize) + noc_timing->ddrmode.b.burstsize -= 1; + noc_timing->ddrmode.b.mwrsize -= 1; + noc_timing->ddrtimingc0.b.burstpenalty *= 2; + noc_timing->ddrtimingc0.b.wrtomwr *= 2; + } +} + +static u32 calculate_ddrconfig(struct rk3399_sdram_params *params, u32 channel) +{ + unsigned int cs0_row = params->ch[channel].cap_info.cs0_row; + unsigned int col = params->ch[channel].cap_info.col; + unsigned int bw = params->ch[channel].cap_info.bw; + u16 ddr_cfg_2_rbc[] = { + /* + * [6] highest bit col + * [5:3] max row(14+n) + * [2] insertion row + * [1:0] col(9+n),col, data bus 32bit + * + * highbitcol, max_row, insertion_row, col + */ + ((0 << 6) | (2 << 3) | (0 << 2) | 0), /* 0 */ + ((0 << 6) | (2 << 3) | (0 << 2) | 1), /* 1 */ + ((0 << 6) | (1 << 3) | (0 << 2) | 2), /* 2 */ + ((0 << 6) | (0 << 3) | (0 << 2) | 3), /* 3 */ + ((0 << 6) | (2 << 3) | (1 << 2) | 1), /* 4 */ + ((0 << 6) | (1 << 3) | (1 << 2) | 2), /* 5 */ + ((1 << 6) | (0 << 3) | (0 << 2) | 2), /* 6 */ + ((1 << 6) | (1 << 3) | (0 << 2) | 2), /* 7 */ + }; + u32 i; + + col -= (bw == 2) ? 0 : 1; + col -= 9; + + for (i = 0; i < 4; i++) { + if ((col == (ddr_cfg_2_rbc[i] & 0x3)) && + (cs0_row <= (((ddr_cfg_2_rbc[i] >> 3) & 0x7) + 14))) + break; + } + + if (i >= 4) + i = -EINVAL; + + return i; +} + #if !defined(CONFIG_RAM_RK3399_LPDDR4) static int default_data_training(struct dram_info *dram, u32 channel, u8 rank, struct rk3399_sdram_params *params) @@ -1588,84 +1666,6 @@ static void set_ddr_stride(struct rk3399_pmusgrf_regs *pmusgrf, u32 stride) rk_clrsetreg(&pmusgrf->soc_con4, 0x1f << 10, stride << 10); } -static void set_cap_relate_config(const struct chan_info *chan, - struct rk3399_sdram_params *params, - unsigned int channel) -{ - u32 *denali_ctl = chan->pctl->denali_ctl; - u32 tmp; - struct rk3399_msch_timings *noc_timing; - - if (params->base.dramtype == LPDDR3) { - tmp = (8 << params->ch[channel].cap_info.bw) / - (8 << params->ch[channel].cap_info.dbw); - - /** - * memdata_ratio - * 1 -> 0, 2 -> 1, 4 -> 2 - */ - clrsetbits_le32(&denali_ctl[197], 0x7, - (tmp >> 1)); - clrsetbits_le32(&denali_ctl[198], 0x7 << 8, - (tmp >> 1) << 8); - } - - noc_timing = ¶ms->ch[channel].noc_timings; - - /* - * noc timing bw relate timing is 32 bit, and real bw is 16bit - * actually noc reg is setting at function dram_all_config - */ - if (params->ch[channel].cap_info.bw == 16 && - noc_timing->ddrmode.b.mwrsize == 2) { - if (noc_timing->ddrmode.b.burstsize) - noc_timing->ddrmode.b.burstsize -= 1; - noc_timing->ddrmode.b.mwrsize -= 1; - noc_timing->ddrtimingc0.b.burstpenalty *= 2; - noc_timing->ddrtimingc0.b.wrtomwr *= 2; - } -} - -static u32 calculate_ddrconfig(struct rk3399_sdram_params *params, u32 channel) -{ - unsigned int cs0_row = params->ch[channel].cap_info.cs0_row; - unsigned int col = params->ch[channel].cap_info.col; - unsigned int bw = params->ch[channel].cap_info.bw; - u16 ddr_cfg_2_rbc[] = { - /* - * [6] highest bit col - * [5:3] max row(14+n) - * [2] insertion row - * [1:0] col(9+n),col, data bus 32bit - * - * highbitcol, max_row, insertion_row, col - */ - ((0 << 6) | (2 << 3) | (0 << 2) | 0), /* 0 */ - ((0 << 6) | (2 << 3) | (0 << 2) | 1), /* 1 */ - ((0 << 6) | (1 << 3) | (0 << 2) | 2), /* 2 */ - ((0 << 6) | (0 << 3) | (0 << 2) | 3), /* 3 */ - ((0 << 6) | (2 << 3) | (1 << 2) | 1), /* 4 */ - ((0 << 6) | (1 << 3) | (1 << 2) | 2), /* 5 */ - ((1 << 6) | (0 << 3) | (0 << 2) | 2), /* 6 */ - ((1 << 6) | (1 << 3) | (0 << 2) | 2), /* 7 */ - }; - u32 i; - - col -= (bw == 2) ? 0 : 1; - col -= 9; - - for (i = 0; i < 4; i++) { - if ((col == (ddr_cfg_2_rbc[i] & 0x3)) && - (cs0_row <= (((ddr_cfg_2_rbc[i] >> 3) & 0x7) + 14))) - break; - } - - if (i >= 4) - i = -EINVAL; - - return i; -} - /** * read mr_num mode register * rank = 1: cs0 @@ -2592,8 +2592,11 @@ static int sdram_init(struct dram_info *dram, } sdram_print_ddr_info(cap_info, ¶ms->base); + set_memory_map(chan, channel, params); + cap_info->ddrconfig = calculate_ddrconfig(params, channel); set_ddrconfig(chan, params, channel, cap_info->ddrconfig); + set_cap_relate_config(chan, params, channel); } if (params->base.num_channels == 0) { -- cgit v1.1 From 2fcff365e0d1a9620081f7f949ada04de84b8a5e Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Thu, 15 Aug 2019 15:37:31 +0800 Subject: rockchip: clk: rk3328: add clk_enable ops for HCLK_HOST0 Required to successfully probe the ehci generic driver Signed-off-by: Kever Yang --- drivers/clk/rockchip/clk_rk3328.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/clk/rockchip/clk_rk3328.c b/drivers/clk/rockchip/clk_rk3328.c index a89e2ec..5957a00 100644 --- a/drivers/clk/rockchip/clk_rk3328.c +++ b/drivers/clk/rockchip/clk_rk3328.c @@ -745,10 +745,22 @@ static int rk3328_clk_set_parent(struct clk *clk, struct clk *parent) return -ENOENT; } +static int rk3328_clk_enable(struct clk *clk) +{ + switch (clk->id) { + case HCLK_HOST0: + /* Required to successfully probe the ehci generic driver */ + return 0; + } + + return -ENOENT; +} + static struct clk_ops rk3328_clk_ops = { .get_rate = rk3328_clk_get_rate, .set_rate = rk3328_clk_set_rate, .set_parent = rk3328_clk_set_parent, + .enable = rk3328_clk_enable, }; static int rk3328_clk_probe(struct udevice *dev) -- cgit v1.1 From 8e5c8571fee9ff5f1c9ca43d43cc2dc78a5181a4 Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Thu, 15 Aug 2019 11:28:31 +0800 Subject: rockchip: dts: rk3328-rock64: enable usb3 xhci controller Rock64 has a USB3.0 port, enable the controller so that we can use it. Signed-off-by: Kever Yang --- arch/arm/dts/rk3328-rock64-u-boot.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/dts/rk3328-rock64-u-boot.dtsi b/arch/arm/dts/rk3328-rock64-u-boot.dtsi index dbcce6a..21c2afc 100644 --- a/arch/arm/dts/rk3328-rock64-u-boot.dtsi +++ b/arch/arm/dts/rk3328-rock64-u-boot.dtsi @@ -32,3 +32,7 @@ &sdmmc { u-boot,dm-pre-reloc; }; + +&usb_host0_xhci { + status = "okay"; +}; -- cgit v1.1 From 2e91e2025c1bb5ab3769aa21677c423aefb2c0ea Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Thu, 15 Aug 2019 11:40:56 +0800 Subject: rockchip: rk3328: migrate u-boot node to -u-boot.dtsi Move all the nodes only shown in u-boot to -u-boot.dtsi to make rk3328.dtsi clean. Signed-off-by: Kever Yang --- arch/arm/dts/rk3328-evb-u-boot.dtsi | 31 +++--------------- arch/arm/dts/rk3328-evb.dts | 5 --- arch/arm/dts/rk3328-rock64-u-boot.dtsi | 33 ++----------------- arch/arm/dts/rk3328-u-boot.dtsi | 58 ++++++++++++++++++++++++++++++++++ arch/arm/dts/rk3328.dtsi | 24 -------------- 5 files changed, 66 insertions(+), 85 deletions(-) create mode 100644 arch/arm/dts/rk3328-u-boot.dtsi diff --git a/arch/arm/dts/rk3328-evb-u-boot.dtsi b/arch/arm/dts/rk3328-evb-u-boot.dtsi index 58ebf52..4a82706 100644 --- a/arch/arm/dts/rk3328-evb-u-boot.dtsi +++ b/arch/arm/dts/rk3328-evb-u-boot.dtsi @@ -1,33 +1,12 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * (C) Copyright 2016-2019 Rockchip Electronics Co., Ltd */ +#include "rk3328-u-boot.dtsi" #include "rk3328-sdram-ddr3-666.dtsi" -/ { - aliases { - mmc0 = &emmc; - mmc1 = &sdmmc; - }; - - chosen { - u-boot,spl-boot-order = &emmc, &sdmmc; - }; -}; - -&cru { - u-boot,dm-pre-reloc; -}; - -&uart2 { - u-boot,dm-pre-reloc; -}; - -&emmc { - u-boot,dm-pre-reloc; -}; - -&sdmmc { - u-boot,dm-pre-reloc; +&usb_host0_xhci { + vbus-supply = <&vcc5v0_host_xhci>; + status = "okay"; }; diff --git a/arch/arm/dts/rk3328-evb.dts b/arch/arm/dts/rk3328-evb.dts index ec594a8..a2ee838 100644 --- a/arch/arm/dts/rk3328-evb.dts +++ b/arch/arm/dts/rk3328-evb.dts @@ -116,11 +116,6 @@ status = "okay"; }; -&usb_host0_xhci { - vbus-supply = <&vcc5v0_host_xhci>; - status = "okay"; -}; - &i2c1 { clock-frequency = <400000>; i2c-scl-rising-time-ns = <168>; diff --git a/arch/arm/dts/rk3328-rock64-u-boot.dtsi b/arch/arm/dts/rk3328-rock64-u-boot.dtsi index 21c2afc..1d441f7 100644 --- a/arch/arm/dts/rk3328-rock64-u-boot.dtsi +++ b/arch/arm/dts/rk3328-rock64-u-boot.dtsi @@ -1,38 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0+ /* - * (C) Copyright 2018 Rockchip Electronics Co., Ltd - * - * SPDX-License-Identifier: GPL-2.0+ + * (C) Copyright 2018-2019 Rockchip Electronics Co., Ltd */ +#include "rk3328-u-boot.dtsi" #include "rk3328-sdram-lpddr3-1600.dtsi" -/ { - aliases { - mmc0 = &emmc; - mmc1 = &sdmmc; - }; - - chosen { - u-boot,spl-boot-order = &emmc, &sdmmc; - }; -}; - -&cru { - u-boot,dm-pre-reloc; -}; - -&uart2 { - u-boot,dm-pre-reloc; -}; - -&emmc { - u-boot,dm-pre-reloc; -}; - -&sdmmc { - u-boot,dm-pre-reloc; -}; - &usb_host0_xhci { status = "okay"; }; diff --git a/arch/arm/dts/rk3328-u-boot.dtsi b/arch/arm/dts/rk3328-u-boot.dtsi new file mode 100644 index 0000000..ffbd657 --- /dev/null +++ b/arch/arm/dts/rk3328-u-boot.dtsi @@ -0,0 +1,58 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd + */ + +/ { + aliases { + mmc0 = &emmc; + mmc1 = &sdmmc; + }; + + chosen { + u-boot,spl-boot-order = &emmc, &sdmmc; + }; + + dmc: dmc { + u-boot,dm-pre-reloc; + compatible = "rockchip,rk3328-dmc"; + reg = <0x0 0xff400000 0x0 0x1000 + 0x0 0xff780000 0x0 0x3000 + 0x0 0xff100000 0x0 0x1000 + 0x0 0xff440000 0x0 0x1000 + 0x0 0xff720000 0x0 0x1000 + 0x0 0xff798000 0x0 0x1000>; + }; + + usb_host0_xhci: usb@ff600000 { + compatible = "rockchip,rk3328-xhci"; + reg = <0x0 0xff600000 0x0 0x100000>; + interrupts = ; + snps,dis-enblslpm-quirk; + snps,phyif-utmi-bits = <16>; + snps,dis-u2-freeclk-exists-quirk; + snps,dis-u2-susphy-quirk; + status = "disabled"; + }; +}; + +&cru { + u-boot,dm-pre-reloc; +}; + +&grf { + u-boot,dm-pre-reloc; +}; + +&uart2 { + u-boot,dm-pre-reloc; + clock-frequency = <24000000>; +}; + +&emmc { + u-boot,dm-pre-reloc; +}; + +&sdmmc { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/rk3328.dtsi b/arch/arm/dts/rk3328.dtsi index a080ae8..060c84e 100644 --- a/arch/arm/dts/rk3328.dtsi +++ b/arch/arm/dts/rk3328.dtsi @@ -186,7 +186,6 @@ }; grf: syscon@ff100000 { - u-boot,dm-pre-reloc; compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd"; reg = <0x0 0xff100000 0x0 0x1000>; @@ -232,7 +231,6 @@ interrupts = ; clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; clock-names = "baudclk", "apb_pclk"; - clock-frequency = <24000000>; reg-shift = <2>; reg-io-width = <4>; dmas = <&dmac 6>, <&dmac 7>; @@ -351,17 +349,6 @@ status = "disabled"; }; - dmc: dmc { - u-boot,dm-pre-reloc; - compatible = "rockchip,rk3328-dmc"; - reg = <0x0 0xff400000 0x0 0x1000 - 0x0 0xff780000 0x0 0x3000 - 0x0 0xff100000 0x0 0x1000 - 0x0 0xff440000 0x0 0x1000 - 0x0 0xff720000 0x0 0x1000 - 0x0 0xff798000 0x0 0x1000>; - }; - cru: clock-controller@ff440000 { compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon"; reg = <0x0 0xff440000 0x0 0x1000>; @@ -512,17 +499,6 @@ status = "disabled"; }; - usb_host0_xhci: usb@ff600000 { - compatible = "rockchip,rk3328-xhci"; - reg = <0x0 0xff600000 0x0 0x100000>; - interrupts = ; - snps,dis-enblslpm-quirk; - snps,phyif-utmi-bits = <16>; - snps,dis-u2-freeclk-exists-quirk; - snps,dis-u2-susphy-quirk; - status = "disabled"; - }; - gic: interrupt-controller@ffb70000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; -- cgit v1.1 From 08bbe44424ceb9b356882a0952c24fd28c76c889 Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Thu, 15 Aug 2019 11:13:28 +0800 Subject: rockchip: dts: rk3328-rock64: fix usb power supply According to rock64 schemetic, both VCC_HOST1_5V and VCC_HOST_5V are controlled by USB20_HOST_DRV(GPIO0A2), fix it so that we can get correct power supply for USB HOST ports. Signed-off-by: Kever Yang --- arch/arm/dts/rk3328-rock64.dts | 23 ++--------------------- 1 file changed, 2 insertions(+), 21 deletions(-) diff --git a/arch/arm/dts/rk3328-rock64.dts b/arch/arm/dts/rk3328-rock64.dts index 7bcc53f..a78eb4a 100644 --- a/arch/arm/dts/rk3328-rock64.dts +++ b/arch/arm/dts/rk3328-rock64.dts @@ -34,23 +34,10 @@ vcc_host_5v: vcc-host-5v-regulator { compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&usb30_host_drv>; - regulator-name = "vcc_host_5v"; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc_sys>; - }; - - vcc_host1_5v: vcc_otg_5v: vcc-host1-5v-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; + gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&usb20_host_drv>; - regulator-name = "vcc_host1_5v"; + regulator-name = "vcc_host_5v"; regulator-always-on; regulator-boot-on; vin-supply = <&vcc_sys>; @@ -244,12 +231,6 @@ rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; }; }; - - usb3 { - usb30_host_drv: usb30-host-drv { - rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; }; &sdmmc { -- cgit v1.1 From 4d2c572312ab9ed4ea2ee7ef1f7c384a0d8d05cf Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Mon, 19 Aug 2019 15:01:24 +0800 Subject: rockchip: Move config SYS_MALLOC_LEN to Kconfig Use Kconfig for option SYS_MALLOC_LEN and default to 0x2000000. Signed-off-by: Kever Yang --- Kconfig | 3 ++- include/configs/rk3036_common.h | 1 - include/configs/rk3128_common.h | 1 - include/configs/rk3188_common.h | 1 - include/configs/rk322x_common.h | 1 - include/configs/rk3288_common.h | 1 - include/configs/rk3328_common.h | 1 - include/configs/rk3368_common.h | 1 - include/configs/rk3399_common.h | 1 - include/configs/rv1108_common.h | 1 - 10 files changed, 2 insertions(+), 10 deletions(-) diff --git a/Kconfig b/Kconfig index d2eb744..d5538dd 100644 --- a/Kconfig +++ b/Kconfig @@ -156,7 +156,8 @@ config SYS_MALLOC_F_LEN config SYS_MALLOC_LEN hex "Define memory for Dynamic allocation" - depends on ARCH_ZYNQ || ARCH_VERSAL || ARCH_STM32MP + depends on ARCH_ZYNQ || ARCH_VERSAL || ARCH_STM32MP || ARCH_ROCKCHIP + default 0x2000000 if ARCH_ROCKCHIP help This defines memory to be allocated for Dynamic allocation TODO: Use for other architectures diff --git a/include/configs/rk3036_common.h b/include/configs/rk3036_common.h index 66331a1..7f148ef 100644 --- a/include/configs/rk3036_common.h +++ b/include/configs/rk3036_common.h @@ -8,7 +8,6 @@ #include #include "rockchip-common.h" -#define CONFIG_SYS_MALLOC_LEN (32 << 20) #define CONFIG_SYS_CBSIZE 1024 #define CONFIG_SKIP_LOWLEVEL_INIT diff --git a/include/configs/rk3128_common.h b/include/configs/rk3128_common.h index d12696d..be55fb7 100644 --- a/include/configs/rk3128_common.h +++ b/include/configs/rk3128_common.h @@ -10,7 +10,6 @@ #define CONFIG_SYS_MAXARGS 16 #define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_MALLOC_LEN (32 << 20) #define CONFIG_SYS_CBSIZE 1024 #define CONFIG_SKIP_LOWLEVEL_INIT diff --git a/include/configs/rk3188_common.h b/include/configs/rk3188_common.h index 44e8d0c..3bcc048 100644 --- a/include/configs/rk3188_common.h +++ b/include/configs/rk3188_common.h @@ -12,7 +12,6 @@ #include "rockchip-common.h" #define CONFIG_SKIP_LOWLEVEL_INIT_ONLY -#define CONFIG_SYS_MALLOC_LEN (32 << 20) #define CONFIG_SYS_CBSIZE 1024 #ifdef CONFIG_SPL_ROCKCHIP_BACK_TO_BROM diff --git a/include/configs/rk322x_common.h b/include/configs/rk322x_common.h index f2fb7e0..7e0c831 100644 --- a/include/configs/rk322x_common.h +++ b/include/configs/rk322x_common.h @@ -9,7 +9,6 @@ #include "rockchip-common.h" #define CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_SYS_MALLOC_LEN (32 << 20) #define CONFIG_SYS_CBSIZE 1024 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h index 84b474a..4a62da3 100644 --- a/include/configs/rk3288_common.h +++ b/include/configs/rk3288_common.h @@ -12,7 +12,6 @@ #define CONFIG_SYS_BOOTM_LEN (16 << 20) /* 16MB */ #define CONFIG_SKIP_LOWLEVEL_INIT_ONLY -#define CONFIG_SYS_MALLOC_LEN (32 << 20) #define CONFIG_SYS_CBSIZE 1024 #define CONFIG_ROCKCHIP_STIMER_BASE 0xff810020 diff --git a/include/configs/rk3328_common.h b/include/configs/rk3328_common.h index 6ed7525..f8b56ba 100644 --- a/include/configs/rk3328_common.h +++ b/include/configs/rk3328_common.h @@ -12,7 +12,6 @@ #define CONFIG_ROCKCHIP_STIMER_BASE 0xff1d0020 -#define CONFIG_SYS_MALLOC_LEN (32 << 20) #define CONFIG_SYS_CBSIZE 1024 #define CONFIG_SKIP_LOWLEVEL_INIT diff --git a/include/configs/rk3368_common.h b/include/configs/rk3368_common.h index 340413d..e4b2114 100644 --- a/include/configs/rk3368_common.h +++ b/include/configs/rk3368_common.h @@ -16,7 +16,6 @@ #define CONFIG_SYS_SDRAM_BASE 0 #define SDRAM_MAX_SIZE 0xff000000 #define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_MALLOC_LEN (32 << 20) #define CONFIG_SYS_CBSIZE 1024 #define CONFIG_SKIP_LOWLEVEL_INIT diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h index 12ad60d..a5e69b2 100644 --- a/include/configs/rk3399_common.h +++ b/include/configs/rk3399_common.h @@ -8,7 +8,6 @@ #include "rockchip-common.h" -#define CONFIG_SYS_MALLOC_LEN (32 << 20) #define CONFIG_SYS_CBSIZE 1024 #define CONFIG_SKIP_LOWLEVEL_INIT diff --git a/include/configs/rv1108_common.h b/include/configs/rv1108_common.h index 691aa51..758e85e 100644 --- a/include/configs/rv1108_common.h +++ b/include/configs/rv1108_common.h @@ -10,7 +10,6 @@ #define CONFIG_IRAM_BASE 0x10080000 -#define CONFIG_SYS_MALLOC_LEN (32 << 20) #define CONFIG_SYS_CBSIZE 1024 #define CONFIG_SKIP_LOWLEVEL_INIT -- cgit v1.1 From 8b221f5e0662a798d49ffc682f795936a01fbad5 Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Tue, 20 Aug 2019 11:47:00 +0800 Subject: rockchip: rk3328: defconfig: remove SPL raw image support RK3328 SPL only support FIT image for ATF bl31. Signed-off-by: Kever Yang --- configs/evb-rk3328_defconfig | 1 + configs/rock64-rk3328_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/configs/evb-rk3328_defconfig b/configs/evb-rk3328_defconfig index 2868f0f..3761077 100644 --- a/configs/evb-rk3328_defconfig +++ b/configs/evb-rk3328_defconfig @@ -20,6 +20,7 @@ CONFIG_SPL_LOAD_FIT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-evb.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_TPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_STACK_R=y CONFIG_TPL_DRIVERS_MISC_SUPPORT=y diff --git a/configs/rock64-rk3328_defconfig b/configs/rock64-rk3328_defconfig index e895859..3ab0af1 100644 --- a/configs/rock64-rk3328_defconfig +++ b/configs/rock64-rk3328_defconfig @@ -21,6 +21,7 @@ CONFIG_SPL_LOAD_FIT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-rock64.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_TPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_STACK_R=y CONFIG_SPL_ATF=y -- cgit v1.1 From 861e48e8fb27d60a7c13e5b3e540b4fdf976f8cf Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Tue, 20 Aug 2019 11:47:01 +0800 Subject: rockchip: rk3368: defconfig: remove SPL raw image support RK3368 SPL only support FIT image for ATF bl31. Signed-off-by: Kever Yang --- configs/evb-px5_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/evb-px5_defconfig b/configs/evb-px5_defconfig index 46a42a7..5a06b2a 100644 --- a/configs/evb-px5_defconfig +++ b/configs/evb-px5_defconfig @@ -29,6 +29,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3368-px5-evb.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_ARCH_EARLY_INIT_R=y CONFIG_SPL_BOOTROM_SUPPORT=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_TPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_STACK_R=y CONFIG_SPL_ATF=y -- cgit v1.1 From 58ec0aa3616f878f302201b4bc1448ee19726d61 Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Tue, 20 Aug 2019 11:47:02 +0800 Subject: rockchip: rk3399: defconfig: remove SPL raw image support RK3399 SPL only support FIT image for ATF bl31. Signed-off-by: Kever Yang --- configs/chromebook_bob_defconfig | 1 + configs/evb-rk3399_defconfig | 1 + configs/ficus-rk3399_defconfig | 1 + configs/firefly-rk3399_defconfig | 1 + configs/khadas-edge-captain-rk3399_defconfig | 1 + configs/khadas-edge-rk3399_defconfig | 1 + configs/khadas-edge-v-rk3399_defconfig | 1 + configs/nanopc-t4-rk3399_defconfig | 1 + configs/nanopi-m4-rk3399_defconfig | 1 + configs/nanopi-neo4-rk3399_defconfig | 1 + configs/orangepi-rk3399_defconfig | 1 + configs/roc-rk3399-pc_defconfig | 1 + configs/rock-pi-4-rk3399_defconfig | 1 + configs/rock960-rk3399_defconfig | 1 + configs/rockpro64-rk3399_defconfig | 1 + 15 files changed, 15 insertions(+) diff --git a/configs/chromebook_bob_defconfig b/configs/chromebook_bob_defconfig index d6fc7e3..5126098 100644 --- a/configs/chromebook_bob_defconfig +++ b/configs/chromebook_bob_defconfig @@ -18,6 +18,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-gru-bob.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_TEXT_BASE=0xff8c2000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 CONFIG_SPL_SPI_LOAD=y diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig index 14cca5b..a0d215a 100644 --- a/configs/evb-rk3399_defconfig +++ b/configs/evb-rk3399_defconfig @@ -11,6 +11,7 @@ CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-evb.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 CONFIG_TPL=y diff --git a/configs/ficus-rk3399_defconfig b/configs/ficus-rk3399_defconfig index c3d8656..8b3692c 100644 --- a/configs/ficus-rk3399_defconfig +++ b/configs/ficus-rk3399_defconfig @@ -11,6 +11,7 @@ CONFIG_DEBUG_UART=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_TEXT_BASE=0xff8c2000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 CONFIG_CMD_BOOTZ=y diff --git a/configs/firefly-rk3399_defconfig b/configs/firefly-rk3399_defconfig index 38ac8a3..d022631 100644 --- a/configs/firefly-rk3399_defconfig +++ b/configs/firefly-rk3399_defconfig @@ -11,6 +11,7 @@ CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-firefly.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 CONFIG_TPL=y diff --git a/configs/khadas-edge-captain-rk3399_defconfig b/configs/khadas-edge-captain-rk3399_defconfig index 11ec2da..acfd91d 100644 --- a/configs/khadas-edge-captain-rk3399_defconfig +++ b/configs/khadas-edge-captain-rk3399_defconfig @@ -11,6 +11,7 @@ CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-khadas-edge-captain.dtbi" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 CONFIG_TPL=y diff --git a/configs/khadas-edge-rk3399_defconfig b/configs/khadas-edge-rk3399_defconfig index c31360a..b71fd3a 100644 --- a/configs/khadas-edge-rk3399_defconfig +++ b/configs/khadas-edge-rk3399_defconfig @@ -11,6 +11,7 @@ CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-khadas-edge.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 CONFIG_TPL=y diff --git a/configs/khadas-edge-v-rk3399_defconfig b/configs/khadas-edge-v-rk3399_defconfig index 8c9e9fc..0a78987 100644 --- a/configs/khadas-edge-v-rk3399_defconfig +++ b/configs/khadas-edge-v-rk3399_defconfig @@ -11,6 +11,7 @@ CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-khadas-edge-v.dtbi" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 CONFIG_TPL=y diff --git a/configs/nanopc-t4-rk3399_defconfig b/configs/nanopc-t4-rk3399_defconfig index 8afa5e1..1d4c8f8 100644 --- a/configs/nanopc-t4-rk3399_defconfig +++ b/configs/nanopc-t4-rk3399_defconfig @@ -11,6 +11,7 @@ CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopc-t4.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 CONFIG_TPL=y diff --git a/configs/nanopi-m4-rk3399_defconfig b/configs/nanopi-m4-rk3399_defconfig index e708a4f..7375b75 100644 --- a/configs/nanopi-m4-rk3399_defconfig +++ b/configs/nanopi-m4-rk3399_defconfig @@ -11,6 +11,7 @@ CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-m4.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 CONFIG_TPL=y diff --git a/configs/nanopi-neo4-rk3399_defconfig b/configs/nanopi-neo4-rk3399_defconfig index 62cdddd..874ee5e 100644 --- a/configs/nanopi-neo4-rk3399_defconfig +++ b/configs/nanopi-neo4-rk3399_defconfig @@ -11,6 +11,7 @@ CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-neo4.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 CONFIG_TPL=y diff --git a/configs/orangepi-rk3399_defconfig b/configs/orangepi-rk3399_defconfig index b1afeae..7b02c59 100644 --- a/configs/orangepi-rk3399_defconfig +++ b/configs/orangepi-rk3399_defconfig @@ -11,6 +11,7 @@ CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-orangepi.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 CONFIG_TPL=y diff --git a/configs/roc-rk3399-pc_defconfig b/configs/roc-rk3399-pc_defconfig index 09e9b8a..26ea2e6 100644 --- a/configs/roc-rk3399-pc_defconfig +++ b/configs/roc-rk3399-pc_defconfig @@ -14,6 +14,7 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-roc-pc.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 CONFIG_CMD_BOOTZ=y diff --git a/configs/rock-pi-4-rk3399_defconfig b/configs/rock-pi-4-rk3399_defconfig index d9d576c..14d115b 100644 --- a/configs/rock-pi-4-rk3399_defconfig +++ b/configs/rock-pi-4-rk3399_defconfig @@ -11,6 +11,7 @@ CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock-pi-4.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 CONFIG_TPL=y diff --git a/configs/rock960-rk3399_defconfig b/configs/rock960-rk3399_defconfig index 7413e4b..abcc53f 100644 --- a/configs/rock960-rk3399_defconfig +++ b/configs/rock960-rk3399_defconfig @@ -12,6 +12,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock960.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_TEXT_BASE=0xff8c2000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 CONFIG_SYS_PROMPT="rock960 => " diff --git a/configs/rockpro64-rk3399_defconfig b/configs/rockpro64-rk3399_defconfig index 5bc6d5d..40ebad5 100644 --- a/configs/rockpro64-rk3399_defconfig +++ b/configs/rockpro64-rk3399_defconfig @@ -11,6 +11,7 @@ CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rockpro64.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 CONFIG_TPL=y -- cgit v1.1 From cb8c492f2016d137c6ed887f4f3eff5df98b865c Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Tue, 20 Aug 2019 18:01:44 +0800 Subject: rockchip: rk3288: remove fennec board support Since there is no one using this board, remove it. Signed-off-by: Kever Yang --- arch/arm/dts/Makefile | 1 - arch/arm/dts/rk3288-fennec-u-boot.dtsi | 54 ---- arch/arm/dts/rk3288-fennec.dts | 31 -- arch/arm/dts/rk3288-fennec.dtsi | 421 --------------------------- arch/arm/mach-rockchip/rk3288/Kconfig | 2 - board/rockchip/fennec_rk3288/Kconfig | 15 - board/rockchip/fennec_rk3288/MAINTAINERS | 6 - board/rockchip/fennec_rk3288/Makefile | 7 - board/rockchip/fennec_rk3288/fennec-rk3288.c | 5 - configs/fennec-rk3288_defconfig | 84 ------ doc/README.rockchip | 3 +- include/configs/fennec_rk3288.h | 14 - 12 files changed, 1 insertion(+), 642 deletions(-) delete mode 100644 arch/arm/dts/rk3288-fennec-u-boot.dtsi delete mode 100644 arch/arm/dts/rk3288-fennec.dts delete mode 100644 arch/arm/dts/rk3288-fennec.dtsi delete mode 100644 board/rockchip/fennec_rk3288/Kconfig delete mode 100644 board/rockchip/fennec_rk3288/MAINTAINERS delete mode 100644 board/rockchip/fennec_rk3288/Makefile delete mode 100644 board/rockchip/fennec_rk3288/fennec-rk3288.c delete mode 100644 configs/fennec-rk3288_defconfig delete mode 100644 include/configs/fennec_rk3288.h diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 05ff624..aac1b83 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -81,7 +81,6 @@ dtb-$(CONFIG_ROCKCHIP_RK322X) += \ dtb-$(CONFIG_ROCKCHIP_RK3288) += \ rk3288-evb.dtb \ - rk3288-fennec.dtb \ rk3288-firefly.dtb \ rk3288-miqi.dtb \ rk3288-phycore-rdk.dtb \ diff --git a/arch/arm/dts/rk3288-fennec-u-boot.dtsi b/arch/arm/dts/rk3288-fennec-u-boot.dtsi deleted file mode 100644 index 2efb309..0000000 --- a/arch/arm/dts/rk3288-fennec-u-boot.dtsi +++ /dev/null @@ -1,54 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2019 Rockchip Electronics Co., Ltd - */ - -#include "rk3288-u-boot.dtsi" - -&pinctrl { - u-boot,dm-pre-reloc; -}; - -&uart2 { - u-boot,dm-pre-reloc; -}; - -&sdmmc { - u-boot,dm-pre-reloc; -}; - -&emmc { - u-boot,dm-pre-reloc; -}; - -&gpio3 { - u-boot,dm-pre-reloc; -}; - -&gpio8 { - u-boot,dm-pre-reloc; -}; - -&pcfg_pull_none_drv_8ma { - u-boot,dm-spl; -}; - -&pcfg_pull_up_drv_8ma { - u-boot,dm-spl; -}; - -&sdmmc_bus4 { - u-boot,dm-spl; -}; - -&sdmmc_clk { - u-boot,dm-spl; -}; - -&sdmmc_cmd { - u-boot,dm-spl; -}; - -&sdmmc_pwr { - u-boot,dm-spl; -}; diff --git a/arch/arm/dts/rk3288-fennec.dts b/arch/arm/dts/rk3288-fennec.dts deleted file mode 100644 index e1d55e3..0000000 --- a/arch/arm/dts/rk3288-fennec.dts +++ /dev/null @@ -1,31 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR X11 -/* - * (C) Copyright 2016 Rockchip Electronics Co., Ltd - */ - -/dts-v1/; -#include "rk3288-fennec.dtsi" - -/ { - model = "Rockchip RK3288 Fennec Board"; - compatible = "rockchip,rk3288-fennec", "rockchip,rk3288"; - - chosen { - stdout-path = &uart2; - }; -}; - -&dmc { - rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d - 0x6 0x0 0x8 0x4 0x17 0x24 0xd 0x6 - 0x4 0x8 0x4 0x76 0x4 0x0 0x30 0x0 - 0x1 0x2 0x2 0x4 0x0 0x0 0xc0 0x4 - 0x8 0x1f4>; - rockchip,phy-timing = <0x48d7dd93 0x187008d8 0x121076 - 0x0 0xc3 0x6 0x2>; - rockchip,sdram-params = <0x20d266a4 0x5b6 2 533000000 6 9 0>; -}; - -&pwm1 { - status = "okay"; -}; diff --git a/arch/arm/dts/rk3288-fennec.dtsi b/arch/arm/dts/rk3288-fennec.dtsi deleted file mode 100644 index f61252c..0000000 --- a/arch/arm/dts/rk3288-fennec.dtsi +++ /dev/null @@ -1,421 +0,0 @@ -/* - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "rk3288.dtsi" - -/ { - memory { - reg = <0x0 0x80000000>; - device_type = "memory"; - }; - - ext_gmac: external-gmac-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <125000000>; - clock-output-names = "ext_gmac"; - }; - - vcc_sys: vsys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_sys"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; -}; - -&cpu0 { - cpu0-supply = <&vdd_cpu>; -}; - -&emmc { - bus-width = <8>; - cap-mmc-highspeed; - disable-wp; - non-removable; - num-slots = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>; - status = "okay"; -}; - -&sdmmc { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - card-detect-delay = <200>; - disable-wp; - num-slots = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; - status = "okay"; - vmmc-supply = <&vcc_sd>; - vqmmc-supply = <&vccio_sd>; -}; - -&gmac { - assigned-clocks = <&cru SCLK_MAC>; - assigned-clock-parents = <&ext_gmac>; - clock_in_out = "input"; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>, <&phy_rst>, <&phy_pmeb>, <&phy_int>; - phy-supply = <&vcc_lan>; - phy-mode = "rgmii"; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 1000000>; - snps,reset-gpio = <&gpio4 8 GPIO_ACTIVE_LOW>; - tx_delay = <0x30>; - rx_delay = <0x10>; - status = "okay"; -}; - -&gpu { - mali-supply = <&vdd_gpu>; - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - clock-frequency = <400000>; - - rk808: pmic@1b { - compatible = "rockchip,rk808"; - reg = <0x1b>; - interrupt-parent = <&gpio0>; - interrupts = <4 IRQ_TYPE_LEVEL_LOW>; - #clock-cells = <1>; - clock-output-names = "xin32k", "rk808-clkout2"; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int &global_pwroff>; - rockchip,system-power-controller; - wakeup-source; - - vcc1-supply = <&vcc_sys>; - vcc2-supply = <&vcc_sys>; - vcc3-supply = <&vcc_sys>; - vcc4-supply = <&vcc_sys>; - vcc6-supply = <&vcc_sys>; - vcc7-supply = <&vcc_sys>; - vcc8-supply = <&vcc_io>; - vcc9-supply = <&vcc_io>; - vcc10-supply = <&vcc_io>; - vcc11-supply = <&vcc_io>; - vcc12-supply = <&vcc_io>; - vddio-supply = <&vcc_io>; - - regulators { - vdd_cpu: DCDC_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1350000>; - regulator-name = "vdd_arm"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_gpu: DCDC_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1250000>; - regulator-name = "vdd_gpu"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vcc_ddr"; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_io: DCDC_REG4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc_io"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vccio_pmu: LDO_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vccio_pmu"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcca_33: LDO_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcca_33"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_10: LDO_REG3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-name = "vdd_10"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vcc_wl: LDO_REG4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc_wl"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vccio_sd: LDO_REG5 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vccio_sd"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vdd10_lcd: LDO_REG6 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-name = "vdd10_lcd"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vcc_18: LDO_REG7 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc_18"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc18_lcd: LDO_REG8 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc18_lcd"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc_sd: SWITCH_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vcc_sd"; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_lan: SWITCH_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vcc_lan"; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - }; - }; -}; - -&pinctrl { - pcfg_output_high: pcfg-output-high { - output-high; - }; - - pcfg_output_low: pcfg-output-low { - output-low; - }; - - pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma { - drive-strength = <8>; - }; - - pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma { - bias-pull-up; - drive-strength = <8>; - }; - - gmac { - phy_int: phy-int { - rockchip,pins = <0 9 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - phy_pmeb: phy-pmeb { - rockchip,pins = <0 8 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - phy_rst: phy-rst { - rockchip,pins = <4 8 RK_FUNC_GPIO &pcfg_output_high>; - }; - }; - - pmic { - pmic_int: pmic-int { - rockchip,pins = ; - }; - }; - - sdmmc { - sdmmc_bus4: sdmmc-bus4 { - rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up_drv_8ma>, - <6 17 RK_FUNC_1 &pcfg_pull_up_drv_8ma>, - <6 18 RK_FUNC_1 &pcfg_pull_up_drv_8ma>, - <6 19 RK_FUNC_1 &pcfg_pull_up_drv_8ma>; - }; - - sdmmc_clk: sdmmc-clk { - rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none_drv_8ma>; - }; - - sdmmc_cmd: sdmmc-cmd { - rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up_drv_8ma>; - }; - - sdmmc_pwr: sdmmc-pwr { - rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usbphy { - host_drv: host-drv { - rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&uart2 { - status = "okay"; -}; - -&usbphy { - pinctrl-names = "default"; - pinctrl-0 = <&host_drv>; - vbus_drv-gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host1 { - status = "okay"; -}; - -&usb_otg { - status = "okay"; -}; - -&usb_hsic { - status = "okay"; -}; - -&vopb { - status = "okay"; -}; - -&vopb_mmu { - status = "okay"; -}; - -&vopl { - status = "okay"; -}; - -&vopl_mmu { - status = "okay"; -}; - -&vpu { - status = "okay"; -}; diff --git a/arch/arm/mach-rockchip/rk3288/Kconfig b/arch/arm/mach-rockchip/rk3288/Kconfig index 87d0786..87e3d34 100644 --- a/arch/arm/mach-rockchip/rk3288/Kconfig +++ b/arch/arm/mach-rockchip/rk3288/Kconfig @@ -191,8 +191,6 @@ source "board/radxa/rock2/Kconfig" source "board/rockchip/evb_rk3288/Kconfig" -source "board/rockchip/fennec_rk3288/Kconfig" - source "board/rockchip/tinker_rk3288/Kconfig" endif diff --git a/board/rockchip/fennec_rk3288/Kconfig b/board/rockchip/fennec_rk3288/Kconfig deleted file mode 100644 index 1dcfcf0..0000000 --- a/board/rockchip/fennec_rk3288/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_FENNEC_RK3288 - -config SYS_BOARD - default "fennec_rk3288" - -config SYS_VENDOR - default "rockchip" - -config SYS_CONFIG_NAME - default "fennec_rk3288" - -config BOARD_SPECIFIC_OPTIONS # dummy - def_bool y - -endif diff --git a/board/rockchip/fennec_rk3288/MAINTAINERS b/board/rockchip/fennec_rk3288/MAINTAINERS deleted file mode 100644 index 78a389b..0000000 --- a/board/rockchip/fennec_rk3288/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -FENNEC-RK3288 -M: Lin Huang -S: Maintained -F: board/rockchip/fennec_rk3288 -F: include/configs/fennec_rk3288.h -F: configs/fennec-rk3288_defconfig diff --git a/board/rockchip/fennec_rk3288/Makefile b/board/rockchip/fennec_rk3288/Makefile deleted file mode 100644 index b287db6..0000000 --- a/board/rockchip/fennec_rk3288/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# -# (C) Copyright 2016 Rockchip Electronics Co., Ltd -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += fennec-rk3288.o diff --git a/board/rockchip/fennec_rk3288/fennec-rk3288.c b/board/rockchip/fennec_rk3288/fennec-rk3288.c deleted file mode 100644 index 779bc64..0000000 --- a/board/rockchip/fennec_rk3288/fennec-rk3288.c +++ /dev/null @@ -1,5 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2016 Rockchip Electronics Co., Ltd - */ - diff --git a/configs/fennec-rk3288_defconfig b/configs/fennec-rk3288_defconfig deleted file mode 100644 index c6d1ddb..0000000 --- a/configs/fennec-rk3288_defconfig +++ /dev/null @@ -1,84 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_ROCKCHIP=y -CONFIG_SYS_TEXT_BASE=0x00000000 -CONFIG_ROCKCHIP_RK3288=y -CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y -CONFIG_TARGET_FENNEC_RK3288=y -CONFIG_NR_DRAM_BANKS=1 -CONFIG_SPL_STACK_R_ADDR=0x80000 -CONFIG_DEBUG_UART_BASE=0xff690000 -CONFIG_DEBUG_UART_CLOCK=24000000 -CONFIG_DEBUG_UART=y -# CONFIG_ANDROID_BOOT_IMAGE is not set -CONFIG_USE_PREBOOT=y -CONFIG_SILENT_CONSOLE=y -CONFIG_CONSOLE_MUX=y -CONFIG_DEFAULT_FDT_FILE="rk3288-fennec.dtb" -# CONFIG_DISPLAY_CPUINFO is not set -CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_SPL_TEXT_BASE=0xff704000 -CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 -CONFIG_CMD_GPIO=y -CONFIG_CMD_GPT=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_SPI=y -CONFIG_CMD_USB=y -CONFIG_CMD_USB_MASS_STORAGE=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_CACHE=y -CONFIG_CMD_TIME=y -CONFIG_CMD_PMIC=y -CONFIG_CMD_REGULATOR=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set -CONFIG_SPL_PARTITION_UUIDS=y -CONFIG_SPL_OF_CONTROL=y -CONFIG_DEFAULT_DEVICE_TREE="rk3288-fennec" -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" -CONFIG_ENV_IS_IN_MMC=y -CONFIG_REGMAP=y -CONFIG_SPL_REGMAP=y -CONFIG_SYSCON=y -CONFIG_SPL_SYSCON=y -# CONFIG_SPL_SIMPLE_BUS is not set -CONFIG_CLK=y -CONFIG_SPL_CLK=y -CONFIG_FASTBOOT_FLASH=y -CONFIG_FASTBOOT_FLASH_MMC_DEV=0 -CONFIG_FASTBOOT_CMD_OEM_FORMAT=y -CONFIG_ROCKCHIP_GPIO=y -CONFIG_SYS_I2C_ROCKCHIP=y -CONFIG_MMC_DW=y -CONFIG_MMC_DW_ROCKCHIP=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_SPEED=20000000 -CONFIG_DM_ETH=y -CONFIG_ETH_DESIGNWARE=y -CONFIG_GMAC_ROCKCHIP=y -CONFIG_PINCTRL=y -CONFIG_SPL_PINCTRL=y -CONFIG_DM_PMIC=y -CONFIG_PMIC_RK8XX=y -CONFIG_DM_REGULATOR_FIXED=y -CONFIG_REGULATOR_RK8XX=y -CONFIG_PWM_ROCKCHIP=y -CONFIG_RAM=y -CONFIG_SPL_RAM=y -CONFIG_DEBUG_UART_SHIFT=2 -CONFIG_SYSRESET=y -CONFIG_USB=y -CONFIG_USB_DWC2=y -CONFIG_ROCKCHIP_USB2_PHY=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_MANUFACTURER="Rockchip" -CONFIG_USB_GADGET_VENDOR_NUM=0x2207 -CONFIG_USB_GADGET_PRODUCT_NUM=0x320a -CONFIG_USB_GADGET_DWC2_OTG=y -CONFIG_USB_HOST_ETHER=y -CONFIG_USB_ETHER_ASIX=y -CONFIG_USB_ETHER_SMSC95XX=y -CONFIG_CMD_DHRYSTONE=y -CONFIG_ERRNO_STR=y diff --git a/doc/README.rockchip b/doc/README.rockchip index 7d4dc1b..ab3361a 100644 --- a/doc/README.rockchip +++ b/doc/README.rockchip @@ -28,10 +28,9 @@ You will need: Building ======== -At present 12 RK3288 boards are supported: +At present 11 RK3288 boards are supported: - EVB RK3288 - use evb-rk3288 configuration - - Fennec RK3288 - use fennec-rk3288 configuration - Firefly RK3288 - use firefly-rk3288 configuration - Hisense Chromebook - use chromebook_jerry configuration - Asus C100P Chromebook - use chromebook_minnie configuration diff --git a/include/configs/fennec_rk3288.h b/include/configs/fennec_rk3288.h deleted file mode 100644 index ddd7012..0000000 --- a/include/configs/fennec_rk3288.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2016 Rockchip Electronics Co., Ltd - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define ROCKCHIP_DEVICE_SETTINGS -#include - -#define CONFIG_SYS_MMC_ENV_DEV 0 - -#endif -- cgit v1.1 From 04825384999f81c08e820fe380e95b6325352a6d Mon Sep 17 00:00:00 2001 From: Rohan Garg Date: Mon, 12 Aug 2019 17:04:34 +0200 Subject: rockchip: rk3399: derive ethaddr from cpuid Generate a MAC address based on the cpuid available in the efuse block: Use the first 6 byte of the cpuid's SHA256 hash and set the locally administered bits. Also ensure that the multicast bit is cleared. The MAC address is only generated and set if there is no ethaddr present in the saved environment. This is based off of Klaus Goger's work in 8adc9d Signed-off-by: Rohan Garg Reviewed-by: Kever Yang --- arch/arm/include/asm/arch-rockchip/misc.h | 13 ++++ arch/arm/mach-rockchip/Makefile | 4 ++ arch/arm/mach-rockchip/board.c | 23 ++++++ arch/arm/mach-rockchip/misc.c | 114 ++++++++++++++++++++++++++++++ 4 files changed, 154 insertions(+) create mode 100644 arch/arm/include/asm/arch-rockchip/misc.h create mode 100644 arch/arm/mach-rockchip/misc.c diff --git a/arch/arm/include/asm/arch-rockchip/misc.h b/arch/arm/include/asm/arch-rockchip/misc.h new file mode 100644 index 0000000..b6b03c9 --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/misc.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * RK3399: Architecture common definitions + * + * Copyright (C) 2019 Collabora Inc - https://www.collabora.com/ + * Rohan Garg + */ + +int rockchip_cpuid_from_efuse(const u32 cpuid_offset, + const u32 cpuid_length, + u8 *cpuid); +int rockchip_cpuid_set(const u8 *cpuid, const u32 cpuid_length); +int rockchip_setup_macaddr(void); diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile index aed379a..207f900 100644 --- a/arch/arm/mach-rockchip/Makefile +++ b/arch/arm/mach-rockchip/Makefile @@ -25,6 +25,10 @@ endif obj-$(CONFIG_$(SPL_TPL_)RAM) += sdram_common.o +ifdef CONFIG_MISC_INIT_R +obj-y += misc.o +endif + obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036/ obj-$(CONFIG_ROCKCHIP_RK3128) += rk3128/ ifndef CONFIG_TPL_BUILD diff --git a/arch/arm/mach-rockchip/board.c b/arch/arm/mach-rockchip/board.c index b2a88e7..8ca3463 100644 --- a/arch/arm/mach-rockchip/board.c +++ b/arch/arm/mach-rockchip/board.c @@ -11,6 +11,7 @@ #include #include #include +#include #include DECLARE_GLOBAL_DATA_PTR; @@ -102,3 +103,25 @@ int fastboot_set_reboot_flag(void) return 0; } #endif + +#ifdef CONFIG_MISC_INIT_R +__weak int misc_init_r(void) +{ + const u32 cpuid_offset = 0x7; + const u32 cpuid_length = 0x10; + u8 cpuid[cpuid_length]; + int ret; + + ret = rockchip_cpuid_from_efuse(cpuid_offset, cpuid_length, cpuid); + if (ret) + return ret; + + ret = rockchip_cpuid_set(cpuid, cpuid_length); + if (ret) + return ret; + + ret = rockchip_setup_macaddr(); + + return ret; +} +#endif diff --git a/arch/arm/mach-rockchip/misc.c b/arch/arm/mach-rockchip/misc.c new file mode 100644 index 0000000..fdb763c --- /dev/null +++ b/arch/arm/mach-rockchip/misc.c @@ -0,0 +1,114 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * RK3399: Architecture common definitions + * + * Copyright (C) 2019 Collabora Inc - https://www.collabora.com/ + * Rohan Garg + * + * Based on puma-rk3399.c: + * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH + */ + +#include +#include +#include +#include +#include +#include + +#include + +int rockchip_setup_macaddr(void) +{ +#if CONFIG_IS_ENABLED(CMD_NET) + int ret; + const char *cpuid = env_get("cpuid#"); + u8 hash[SHA256_SUM_LEN]; + int size = sizeof(hash); + u8 mac_addr[6]; + + /* Only generate a MAC address, if none is set in the environment */ + if (env_get("ethaddr")) + return -1; + + if (!cpuid) { + debug("%s: could not retrieve 'cpuid#'\n", __func__); + return -1; + } + + ret = hash_block("sha256", (void *)cpuid, strlen(cpuid), hash, &size); + if (ret) { + debug("%s: failed to calculate SHA256\n", __func__); + return -1; + } + + /* Copy 6 bytes of the hash to base the MAC address on */ + memcpy(mac_addr, hash, 6); + + /* Make this a valid MAC address and set it */ + mac_addr[0] &= 0xfe; /* clear multicast bit */ + mac_addr[0] |= 0x02; /* set local assignment bit (IEEE802) */ + eth_env_set_enetaddr("ethaddr", mac_addr); +#endif + return 0; +} + +int rockchip_cpuid_from_efuse(const u32 cpuid_offset, + const u32 cpuid_length, + u8 *cpuid) +{ +#if CONFIG_IS_ENABLED(ROCKCHIP_EFUSE) + struct udevice *dev; + int ret; + + /* retrieve the device */ + ret = uclass_get_device_by_driver(UCLASS_MISC, + DM_GET_DRIVER(rockchip_efuse), &dev); + if (ret) { + debug("%s: could not find efuse device\n", __func__); + return -1; + } + + /* read the cpu_id range from the efuses */ + ret = misc_read(dev, cpuid_offset, cpuid, sizeof(cpuid)); + if (ret) { + debug("%s: reading cpuid from the efuses failed\n", + __func__); + return -1; + } +#endif + return 0; +} + +int rockchip_cpuid_set(const u8 *cpuid, const u32 cpuid_length) +{ + u8 low[cpuid_length / 2], high[cpuid_length / 2]; + char cpuid_str[cpuid_length * 2 + 1]; + u64 serialno; + char serialno_str[17]; + int i; + + memset(cpuid_str, 0, sizeof(cpuid_str)); + for (i = 0; i < 16; i++) + sprintf(&cpuid_str[i * 2], "%02x", cpuid[i]); + + debug("cpuid: %s\n", cpuid_str); + + /* + * Mix the cpuid bytes using the same rules as in + * ${linux}/drivers/soc/rockchip/rockchip-cpuinfo.c + */ + for (i = 0; i < 8; i++) { + low[i] = cpuid[1 + (i << 1)]; + high[i] = cpuid[i << 1]; + } + + serialno = crc32_no_comp(0, low, 8); + serialno |= (u64)crc32_no_comp(serialno, high, 8) << 32; + snprintf(serialno_str, sizeof(serialno_str), "%016llx", serialno); + + env_set("cpuid#", cpuid_str); + env_set("serial#", serialno_str); + + return 0; +} -- cgit v1.1 From 015c3fbad9812776c13f9163ca3d1b3a0c51edf2 Mon Sep 17 00:00:00 2001 From: Rohan Garg Date: Mon, 12 Aug 2019 17:04:35 +0200 Subject: rockchip: rk3399: Enable CONFIG_MISC_INIT_R for the Rock PI 4 This enables us to set a static MAC address Signed-off-by: Rohan Garg Reviewed-by: Kever Yang --- configs/rock-pi-4-rk3399_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/rock-pi-4-rk3399_defconfig b/configs/rock-pi-4-rk3399_defconfig index 14d115b..91e60da 100644 --- a/configs/rock-pi-4-rk3399_defconfig +++ b/configs/rock-pi-4-rk3399_defconfig @@ -56,3 +56,4 @@ CONFIG_USB_ETHER_RTL8152=y CONFIG_USB_ETHER_SMSC95XX=y CONFIG_SPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y +CONFIG_MISC_INIT_R=y -- cgit v1.1 From fa177ff0208b74ea481202705eaddaaa29ba24fb Mon Sep 17 00:00:00 2001 From: Rohan Garg Date: Mon, 12 Aug 2019 17:04:36 +0200 Subject: board: puma: Use rockchip_* helpers to setup cpuid and macaddr We should use the shared helpers to setup the necessary parts Signed-off-by: Rohan Garg Reviewed-by: Kever Yang --- board/theobroma-systems/puma_rk3399/puma-rk3399.c | 108 ++++------------------ 1 file changed, 18 insertions(+), 90 deletions(-) diff --git a/board/theobroma-systems/puma_rk3399/puma-rk3399.c b/board/theobroma-systems/puma_rk3399/puma-rk3399.c index 4113a1c..47259b7 100644 --- a/board/theobroma-systems/puma_rk3399/puma-rk3399.c +++ b/board/theobroma-systems/puma_rk3399/puma-rk3399.c @@ -18,97 +18,10 @@ #include #include #include +#include #include #include -static void setup_macaddr(void) -{ -#if CONFIG_IS_ENABLED(CMD_NET) - int ret; - const char *cpuid = env_get("cpuid#"); - u8 hash[SHA256_SUM_LEN]; - int size = sizeof(hash); - u8 mac_addr[6]; - - /* Only generate a MAC address, if none is set in the environment */ - if (env_get("ethaddr")) - return; - - if (!cpuid) { - debug("%s: could not retrieve 'cpuid#'\n", __func__); - return; - } - - ret = hash_block("sha256", (void *)cpuid, strlen(cpuid), hash, &size); - if (ret) { - debug("%s: failed to calculate SHA256\n", __func__); - return; - } - - /* Copy 6 bytes of the hash to base the MAC address on */ - memcpy(mac_addr, hash, 6); - - /* Make this a valid MAC address and set it */ - mac_addr[0] &= 0xfe; /* clear multicast bit */ - mac_addr[0] |= 0x02; /* set local assignment bit (IEEE802) */ - eth_env_set_enetaddr("ethaddr", mac_addr); -#endif -} - -static void setup_serial(void) -{ -#if CONFIG_IS_ENABLED(ROCKCHIP_EFUSE) - const u32 cpuid_offset = 0x7; - const u32 cpuid_length = 0x10; - - struct udevice *dev; - int ret, i; - u8 cpuid[cpuid_length]; - u8 low[cpuid_length/2], high[cpuid_length/2]; - char cpuid_str[cpuid_length * 2 + 1]; - u64 serialno; - char serialno_str[17]; - - /* retrieve the device */ - ret = uclass_get_device_by_driver(UCLASS_MISC, - DM_GET_DRIVER(rockchip_efuse), &dev); - if (ret) { - debug("%s: could not find efuse device\n", __func__); - return; - } - - /* read the cpu_id range from the efuses */ - ret = misc_read(dev, cpuid_offset, &cpuid, sizeof(cpuid)); - if (ret) { - debug("%s: reading cpuid from the efuses failed\n", - __func__); - return; - } - - memset(cpuid_str, 0, sizeof(cpuid_str)); - for (i = 0; i < 16; i++) - sprintf(&cpuid_str[i * 2], "%02x", cpuid[i]); - - debug("cpuid: %s\n", cpuid_str); - - /* - * Mix the cpuid bytes using the same rules as in - * ${linux}/drivers/soc/rockchip/rockchip-cpuinfo.c - */ - for (i = 0; i < 8; i++) { - low[i] = cpuid[1 + (i << 1)]; - high[i] = cpuid[i << 1]; - } - - serialno = crc32_no_comp(0, low, 8); - serialno |= (u64)crc32_no_comp(serialno, high, 8) << 32; - snprintf(serialno_str, sizeof(serialno_str), "%016llx", serialno); - - env_set("cpuid#", cpuid_str); - env_set("serial#", serialno_str); -#endif -} - static void setup_iodomain(void) { const u32 GRF_IO_VSEL_GPIO4CD_SHIFT = 3; @@ -198,8 +111,23 @@ static int setup_boottargets(void) int misc_init_r(void) { - setup_serial(); - setup_macaddr(); + const u32 cpuid_offset = 0x7; + const u32 cpuid_length = 0x10; + u8 cpuid[cpuid_length]; + int ret; + + ret = rockchip_cpuid_from_efuse(cpuid_offset, cpuid_length, cpuid); + if (ret) + return ret; + + ret = rockchip_cpuid_set(cpuid, cpuid_length); + if (ret) + return ret; + + ret = rockchip_setup_macaddr(); + if (ret) + return ret; + setup_iodomain(); setup_boottargets(); -- cgit v1.1 From 20c568cae6e95c727bb97ba55a558916dc42baf4 Mon Sep 17 00:00:00 2001 From: Urja Rannikko Date: Thu, 11 Apr 2019 20:27:50 +0000 Subject: disk: efi: unify code for finding a valid gpt There were 3 copies of the same sequence, make it into a function. Signed-off-by: Urja Rannikko Reviewed-by: Kever Yang --- disk/part_efi.c | 73 +++++++++++++++++++++++++++------------------------------ 1 file changed, 34 insertions(+), 39 deletions(-) diff --git a/disk/part_efi.c b/disk/part_efi.c index 359b55a..3d93062 100644 --- a/disk/part_efi.c +++ b/disk/part_efi.c @@ -51,6 +51,8 @@ static int is_gpt_valid(struct blk_desc *dev_desc, u64 lba, static gpt_entry *alloc_read_gpt_entries(struct blk_desc *dev_desc, gpt_header *pgpt_head); static int is_pte_valid(gpt_entry * pte); +static int find_valid_gpt(struct blk_desc *dev_desc, gpt_header *gpt_head, + gpt_entry **pgpt_pte); static char *print_efiname(gpt_entry *pte) { @@ -192,19 +194,8 @@ int get_disk_guid(struct blk_desc * dev_desc, char *guid) unsigned char *guid_bin; /* This function validates AND fills in the GPT header and PTE */ - if (is_gpt_valid(dev_desc, GPT_PRIMARY_PARTITION_TABLE_LBA, - gpt_head, &gpt_pte) != 1) { - printf("%s: *** ERROR: Invalid GPT ***\n", __func__); - if (is_gpt_valid(dev_desc, dev_desc->lba - 1, - gpt_head, &gpt_pte) != 1) { - printf("%s: *** ERROR: Invalid Backup GPT ***\n", - __func__); - return -EINVAL; - } else { - printf("%s: *** Using Backup GPT ***\n", - __func__); - } - } + if (find_valid_gpt(dev_desc, gpt_head, &gpt_pte) != 1) + return -EINVAL; guid_bin = gpt_head->disk_guid.b; uuid_bin_to_str(guid_bin, guid, UUID_STR_FORMAT_GUID); @@ -223,19 +214,8 @@ void part_print_efi(struct blk_desc *dev_desc) unsigned char *uuid_bin; /* This function validates AND fills in the GPT header and PTE */ - if (is_gpt_valid(dev_desc, GPT_PRIMARY_PARTITION_TABLE_LBA, - gpt_head, &gpt_pte) != 1) { - printf("%s: *** ERROR: Invalid GPT ***\n", __func__); - if (is_gpt_valid(dev_desc, (dev_desc->lba - 1), - gpt_head, &gpt_pte) != 1) { - printf("%s: *** ERROR: Invalid Backup GPT ***\n", - __func__); - return; - } else { - printf("%s: *** Using Backup GPT ***\n", - __func__); - } - } + if (find_valid_gpt(dev_desc, gpt_head, &gpt_pte) != 1) + return; debug("%s: gpt-entry at %p\n", __func__, gpt_pte); @@ -284,19 +264,8 @@ int part_get_info_efi(struct blk_desc *dev_desc, int part, } /* This function validates AND fills in the GPT header and PTE */ - if (is_gpt_valid(dev_desc, GPT_PRIMARY_PARTITION_TABLE_LBA, - gpt_head, &gpt_pte) != 1) { - printf("%s: *** ERROR: Invalid GPT ***\n", __func__); - if (is_gpt_valid(dev_desc, (dev_desc->lba - 1), - gpt_head, &gpt_pte) != 1) { - printf("%s: *** ERROR: Invalid Backup GPT ***\n", - __func__); - return -1; - } else { - printf("%s: *** Using Backup GPT ***\n", - __func__); - } - } + if (find_valid_gpt(dev_desc, gpt_head, &gpt_pte) != 1) + return -1; if (part > le32_to_cpu(gpt_head->num_partition_entries) || !is_pte_valid(&gpt_pte[part - 1])) { @@ -997,6 +966,32 @@ static int is_gpt_valid(struct blk_desc *dev_desc, u64 lba, } /** + * find_valid_gpt() - finds a valid GPT header and PTEs + * + * gpt is a GPT header ptr, filled on return. + * ptes is a PTEs ptr, filled on return. + * + * Description: returns 1 if found a valid gpt, 0 on error. + * If valid, returns pointers to PTEs. + */ +static int find_valid_gpt(struct blk_desc *dev_desc, gpt_header *gpt_head, + gpt_entry **pgpt_pte) +{ + if (is_gpt_valid(dev_desc, GPT_PRIMARY_PARTITION_TABLE_LBA, + gpt_head, pgpt_pte) != 1) { + printf("%s: *** ERROR: Invalid GPT ***\n", __func__); + if (is_gpt_valid(dev_desc, (dev_desc->lba - 1), + gpt_head, pgpt_pte) != 1) { + printf("%s: *** ERROR: Invalid Backup GPT ***\n", + __func__); + return 0; + } + printf("%s: *** Using Backup GPT ***\n", __func__); + } + return 1; +} + +/** * alloc_read_gpt_entries(): reads partition entries from disk * @dev_desc * @gpt - GPT header -- cgit v1.1 From 0557d46b63cc1d871f3752ed771a9fc13d0c9786 Mon Sep 17 00:00:00 2001 From: Urja Rannikko Date: Thu, 11 Apr 2019 20:27:51 +0000 Subject: disk: efi: ignore 'IGNOREME' GPT header found on cros eMMCs Some ChromeOS devices (atleast veyron speedy) have the first 8MiB of the eMMC write protected and equipped with a dummy 'IGNOREME' GPT header - instead of spewing error messages about it, just silently try the backup GPT. Note: this does not touch the gpt cmd writing/verifying functions, those will still complain. Signed-off-by: Urja Rannikko Reviewed-by: Kever Yang --- disk/part_efi.c | 28 +++++++++++++++++++++------- include/part_efi.h | 2 ++ 2 files changed, 23 insertions(+), 7 deletions(-) diff --git a/disk/part_efi.c b/disk/part_efi.c index 3d93062..51fa4a7 100644 --- a/disk/part_efi.c +++ b/disk/part_efi.c @@ -908,7 +908,7 @@ static int is_pmbr_valid(legacy_mbr * mbr) * gpt is a GPT header ptr, filled on return. * ptes is a PTEs ptr, filled on return. * - * Description: returns 1 if valid, 0 on error. + * Description: returns 1 if valid, 0 on error, 2 if ignored header * If valid, returns pointers to PTEs. */ static int is_gpt_valid(struct blk_desc *dev_desc, u64 lba, @@ -934,6 +934,12 @@ static int is_gpt_valid(struct blk_desc *dev_desc, u64 lba, return 0; } + /* Invalid but nothing to yell about. */ + if (le64_to_cpu(pgpt_head->signature) == GPT_HEADER_CHROMEOS_IGNORE) { + debug("ChromeOS 'IGNOREME' GPT header found and ignored\n"); + return 2; + } + if (validate_gpt_header(pgpt_head, (lbaint_t)lba, dev_desc->lba)) return 0; @@ -977,16 +983,24 @@ static int is_gpt_valid(struct blk_desc *dev_desc, u64 lba, static int find_valid_gpt(struct blk_desc *dev_desc, gpt_header *gpt_head, gpt_entry **pgpt_pte) { - if (is_gpt_valid(dev_desc, GPT_PRIMARY_PARTITION_TABLE_LBA, - gpt_head, pgpt_pte) != 1) { - printf("%s: *** ERROR: Invalid GPT ***\n", __func__); - if (is_gpt_valid(dev_desc, (dev_desc->lba - 1), - gpt_head, pgpt_pte) != 1) { + int r; + + r = is_gpt_valid(dev_desc, GPT_PRIMARY_PARTITION_TABLE_LBA, gpt_head, + pgpt_pte); + + if (r != 1) { + if (r != 2) + printf("%s: *** ERROR: Invalid GPT ***\n", __func__); + + if (is_gpt_valid(dev_desc, (dev_desc->lba - 1), gpt_head, + pgpt_pte) != 1) { printf("%s: *** ERROR: Invalid Backup GPT ***\n", __func__); return 0; } - printf("%s: *** Using Backup GPT ***\n", __func__); + if (r != 2) + printf("%s: *** Using Backup GPT ***\n", + __func__); } return 1; } diff --git a/include/part_efi.h b/include/part_efi.h index 7170b61..eb5797a 100644 --- a/include/part_efi.h +++ b/include/part_efi.h @@ -25,6 +25,8 @@ #define EFI_PMBR_OSTYPE_EFI_GPT 0xEE #define GPT_HEADER_SIGNATURE_UBOOT 0x5452415020494645ULL +#define GPT_HEADER_CHROMEOS_IGNORE 0x454d45524f4e4749ULL // 'IGNOREME' + #define GPT_HEADER_REVISION_V1 0x00010000 #define GPT_PRIMARY_PARTITION_TABLE_LBA 1ULL #define GPT_ENTRY_NUMBERS CONFIG_EFI_PARTITION_ENTRIES_NUMBERS -- cgit v1.1 From cbd298b6ee78f3a1187798a30ecdca339df8c65d Mon Sep 17 00:00:00 2001 From: Max Kellermann Date: Tue, 4 Dec 2018 12:00:48 +0100 Subject: evb_rk3399: revert CONFIG_SYS_MMC_ENV_DEV to 0 This was changed to 1 in commit 0717dde057e, but a few months later, commit 5f9411af37b swapped the order of eMMC and SD card by assigning indexed aliases to `&sdhci` and `&sdmmc`. Signed-off-by: Max Kellermann Reviewed-by: Kever Yang (Add signature) Signed-off-by: Kever Yang --- include/configs/evb_rk3399.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/evb_rk3399.h b/include/configs/evb_rk3399.h index a99eeab..b9c4d68 100644 --- a/include/configs/evb_rk3399.h +++ b/include/configs/evb_rk3399.h @@ -8,7 +8,7 @@ #include -#define CONFIG_SYS_MMC_ENV_DEV 1 +#define CONFIG_SYS_MMC_ENV_DEV 0 #define SDRAM_BANK_SIZE (2UL << 30) -- cgit v1.1