From b3d97f8ce34011b8928919822eb17b98477f3d72 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 18 May 2023 00:02:39 +0200 Subject: ARM: stm32: Power cycle Buck3 in reset on DHSOM In case the DHSOM is in suspend state and either reset button is pushed or IWDG2 triggers a watchdog reset, then DRAM initialization could fail as follows: " RAM: DDR3L 32bits 2x4Gb 533MHz DDR invalid size : 0x4, expected 0x40000000 DRAM init failed: -22 ### ERROR ### Please RESET the board ### " Avoid this failure by not keeping any Buck regulators enabled during reset, let the SoC and DRAMs power cycle fully. Since the change which keeps Buck3 VDD enabled during reset is ST specific, move this addition to ST specific SPL board initialization so that it wouldn't affect the DHSOM . Signed-off-by: Marek Vasut Reviewed-by: Patrick Delaunay --- board/st/common/stpmic1.c | 10 +++------- board/st/common/stpmic1.h | 2 +- board/st/stm32mp1/spl.c | 13 +++++++++++-- 3 files changed, 15 insertions(+), 10 deletions(-) diff --git a/board/st/common/stpmic1.c b/board/st/common/stpmic1.c index d52dce4..969ad48 100644 --- a/board/st/common/stpmic1.c +++ b/board/st/common/stpmic1.c @@ -185,21 +185,17 @@ static int stmpic_buck1_set(struct udevice *dev, u32 voltage_mv) } /* early init of PMIC */ -void stpmic1_init(u32 voltage_mv) +struct udevice *stpmic1_init(u32 voltage_mv) { struct udevice *dev; if (uclass_get_device_by_driver(UCLASS_PMIC, DM_DRIVER_GET(pmic_stpmic1), &dev)) - return; + return NULL; /* update VDDCORE = BUCK1 */ if (voltage_mv) stmpic_buck1_set(dev, voltage_mv); - /* Keep vdd on during the reset cycle */ - pmic_clrsetbits(dev, - STPMIC1_BUCKS_MRST_CR, - STPMIC1_MRST_BUCK(STPMIC1_BUCK3), - STPMIC1_MRST_BUCK(STPMIC1_BUCK3)); + return dev; } diff --git a/board/st/common/stpmic1.h b/board/st/common/stpmic1.h index b17d6f1..7a7169d 100644 --- a/board/st/common/stpmic1.h +++ b/board/st/common/stpmic1.h @@ -3,4 +3,4 @@ * Copyright (C) 2020, STMicroelectronics - All Rights Reserved */ -void stpmic1_init(u32 voltage_mv); +struct udevice *stpmic1_init(u32 voltage_mv); diff --git a/board/st/stm32mp1/spl.c b/board/st/stm32mp1/spl.c index 747ec7e..8b4a529 100644 --- a/board/st/stm32mp1/spl.c +++ b/board/st/stm32mp1/spl.c @@ -5,6 +5,8 @@ #include #include +#include +#include #include #include "../common/stpmic1.h" @@ -19,8 +21,15 @@ void board_vddcore_init(u32 voltage_mv) int board_early_init_f(void) { - if (IS_ENABLED(CONFIG_PMIC_STPMIC1) && CONFIG_IS_ENABLED(POWER)) - stpmic1_init(opp_voltage_mv); + if (IS_ENABLED(CONFIG_PMIC_STPMIC1) && CONFIG_IS_ENABLED(POWER)) { + struct udevice *dev = stpmic1_init(opp_voltage_mv); + + /* Keep vdd on during the reset cycle */ + pmic_clrsetbits(dev, + STPMIC1_BUCKS_MRST_CR, + STPMIC1_MRST_BUCK(STPMIC1_BUCK3), + STPMIC1_MRST_BUCK(STPMIC1_BUCK3)); + } return 0; } -- cgit v1.1 From 141e232dbd981ab05e17660e63008ef170aea73d Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Fri, 23 Jun 2023 15:05:16 +0200 Subject: clk: stm32mp1: remove error for disabled clock in stm32mp1_clk_get_parent To disabled a clock in clock tree initialization for a mux of STM32MP15, the selected clock source index is set with the latest possible index for the number of bit used. Today this valid configuration cause a error in U-Boot messages, for example with CLK_ETH_DISABLED, when this clock is not needed for the used ETH PHY without crystal: no parents defined for clk id 123 This patch change the level of this message to avoid this trace for valid clock tree. Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard --- drivers/clk/stm32/clk-stm32mp1.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/clk/stm32/clk-stm32mp1.c b/drivers/clk/stm32/clk-stm32mp1.c index 4f4524f..6150287 100644 --- a/drivers/clk/stm32/clk-stm32mp1.c +++ b/drivers/clk/stm32/clk-stm32mp1.c @@ -881,7 +881,8 @@ static int stm32mp1_clk_get_parent(struct stm32mp1_clk_priv *priv, return sel[s].parent[p]; } - log_err("no parents defined for clk id %d\n", (u32)id); + /* clock is DISABLED when the clock src is not in clk_parent[] range */ + log_debug("no parents defined for clk id %d\n", (u32)id); return -EINVAL; } -- cgit v1.1 From fc7bd99f6d2d732d70bb2191f69955ea335577c6 Mon Sep 17 00:00:00 2001 From: Dario Binacchi Date: Mon, 3 Jul 2023 18:02:33 +0200 Subject: ARM: dts: stm32: fix display pinmux for stm32f746-disco As reported by the datasheet (DocID027590 Rev 4) for PG12: - AF9 -> LCD_B4 - AF14 -> LCD_B1 So replace AF14 with AF9 for PG12 in the dts. Fixes: fe63d3cfb77ef ("ARM: dts: stm32: Sync DT with v4.20 kernel for stm32f7") Signed-off-by: Dario Binacchi Reviewed-by: Patrice Chotard --- arch/arm/dts/stm32f746-disco-u-boot.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/dts/stm32f746-disco-u-boot.dtsi b/arch/arm/dts/stm32f746-disco-u-boot.dtsi index 19b5451..522cffb 100644 --- a/arch/arm/dts/stm32f746-disco-u-boot.dtsi +++ b/arch/arm/dts/stm32f746-disco-u-boot.dtsi @@ -169,7 +169,7 @@ ltdc_pins: ltdc@0 { pins { pinmux = , /* B0 */ - , /* B4 */ + , /* B4 */ , /* VSYNC */ , /* HSYNC */ , /* CLK */ -- cgit v1.1 From b58ab56d14f242850142a49e2a62a80389b3a11e Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 6 Jul 2023 23:32:27 +0200 Subject: ARM: stm32: Inhibit PDDS because CSTBYDIS is set The PWR_MPUCR CSTBYDIS bit is set, therefore the CA cores can never enter CStandby state and would always end up in CStop state. Clear the PDDS bit, which indicates the CA cores can enter CStandby state as it makes little sense to keep it set with CSTBYDIS also set. This does however fix a problem too. When both PWR_MPUCR and PWR_MCUCR PDDS bits are set, then the chip enters CStandby state even though the PWR_MCUCR CSTBYDIS is set. Clearing the PWR_MPUCR PDDS prevents that from happening. Signed-off-by: Marek Vasut Reviewed-by: Patrick Delaunay --- arch/arm/mach-stm32mp/psci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-stm32mp/psci.c b/arch/arm/mach-stm32mp/psci.c index 39b5200..8cdeb0a 100644 --- a/arch/arm/mach-stm32mp/psci.c +++ b/arch/arm/mach-stm32mp/psci.c @@ -729,7 +729,7 @@ void __secure psci_system_suspend(u32 __always_unused function_id, setbits_le32(STM32_RCC_BASE + RCC_MP_CIER, RCC_MP_CIFR_WKUPF); setbits_le32(STM32_PWR_BASE + PWR_MPUCR, - PWR_MPUCR_CSSF | PWR_MPUCR_CSTDBYDIS | PWR_MPUCR_PDDS); + PWR_MPUCR_CSSF | PWR_MPUCR_CSTDBYDIS); saved_mcudivr = readl(STM32_RCC_BASE + RCC_MCUDIVR); saved_pll3cr = readl(STM32_RCC_BASE + RCC_PLL3CR); -- cgit v1.1 From 61ad1a527a198a3c5ce4cdf25d74108bd038ebb4 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Mon, 10 Jul 2023 10:38:45 +0200 Subject: ARM: dts: stm32mp: alignment with v6.4 Device tree alignment with Linux kernel v6.4. Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard --- arch/arm/dts/stm32mp13-pinctrl.dtsi | 129 ++++++++++++++++++++++++++++++++++++ arch/arm/dts/stm32mp131.dtsi | 99 ++++++++++++++++++++++++++- arch/arm/dts/stm32mp135f-dk.dts | 42 +++++++++++- arch/arm/dts/stm32mp15-pinctrl.dtsi | 34 +++++----- arch/arm/dts/stm32mp151.dtsi | 4 +- arch/arm/dts/stm32mp157a-dk1.dts | 3 - arch/arm/dts/stm32mp157c-dk2.dts | 3 - arch/arm/dts/stm32mp157c-ed1.dts | 17 ++--- arch/arm/dts/stm32mp157c-ev1.dts | 9 ++- arch/arm/dts/stm32mp15xx-dkx.dtsi | 15 ++--- 10 files changed, 299 insertions(+), 56 deletions(-) diff --git a/arch/arm/dts/stm32mp13-pinctrl.dtsi b/arch/arm/dts/stm32mp13-pinctrl.dtsi index b2dce3a..27e0c38 100644 --- a/arch/arm/dts/stm32mp13-pinctrl.dtsi +++ b/arch/arm/dts/stm32mp13-pinctrl.dtsi @@ -258,4 +258,133 @@ bias-disable; }; }; + + uart4_idle_pins_a: uart4-idle-0 { + pins1 { + pinmux = ; /* UART4_TX */ + }; + pins2 { + pinmux = ; /* UART4_RX */ + bias-disable; + }; + }; + + uart4_sleep_pins_a: uart4-sleep-0 { + pins { + pinmux = , /* UART4_TX */ + ; /* UART4_RX */ + }; + }; + + uart8_pins_a: uart8-0 { + pins1 { + pinmux = ; /* UART8_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = ; /* UART8_RX */ + bias-pull-up; + }; + }; + + uart8_idle_pins_a: uart8-idle-0 { + pins1 { + pinmux = ; /* UART8_TX */ + }; + pins2 { + pinmux = ; /* UART8_RX */ + bias-pull-up; + }; + }; + + uart8_sleep_pins_a: uart8-sleep-0 { + pins { + pinmux = , /* UART8_TX */ + ; /* UART8_RX */ + }; + }; + + usart1_pins_a: usart1-0 { + pins1 { + pinmux = , /* USART1_TX */ + ; /* USART1_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = , /* USART1_RX */ + ; /* USART1_CTS_NSS */ + bias-pull-up; + }; + }; + + usart1_idle_pins_a: usart1-idle-0 { + pins1 { + pinmux = , /* USART1_TX */ + ; /* USART1_CTS_NSS */ + }; + pins2 { + pinmux = ; /* USART1_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins3 { + pinmux = ; /* USART1_RX */ + bias-pull-up; + }; + }; + + usart1_sleep_pins_a: usart1-sleep-0 { + pins { + pinmux = , /* USART1_TX */ + , /* USART1_RTS */ + , /* USART1_CTS_NSS */ + ; /* USART1_RX */ + }; + }; + + usart2_pins_a: usart2-0 { + pins1 { + pinmux = , /* USART2_TX */ + ; /* USART2_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = , /* USART2_RX */ + ; /* USART2_CTS_NSS */ + bias-disable; + }; + }; + + usart2_idle_pins_a: usart2-idle-0 { + pins1 { + pinmux = , /* USART2_TX */ + ; /* USART2_CTS_NSS */ + }; + pins2 { + pinmux = ; /* USART2_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins3 { + pinmux = ; /* USART2_RX */ + bias-disable; + }; + }; + + usart2_sleep_pins_a: usart2-sleep-0 { + pins { + pinmux = , /* USART2_TX */ + , /* USART2_RTS */ + , /* USART2_RX */ + ; /* USART2_CTS_NSS */ + }; + }; }; diff --git a/arch/arm/dts/stm32mp131.dtsi b/arch/arm/dts/stm32mp131.dtsi index d94ba25..d163c26 100644 --- a/arch/arm/dts/stm32mp131.dtsi +++ b/arch/arm/dts/stm32mp131.dtsi @@ -397,12 +397,42 @@ status = "disabled"; }; + usart3: serial@4000f000 { + compatible = "st,stm32h7-uart"; + reg = <0x4000f000 0x400>; + interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc USART3_K>; + resets = <&rcc USART3_R>; + wakeup-source; + dmas = <&dmamux1 45 0x400 0x5>, + <&dmamux1 46 0x400 0x1>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + uart4: serial@40010000 { compatible = "st,stm32h7-uart"; reg = <0x40010000 0x400>; - interrupts = ; + interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc UART4_K>; resets = <&rcc UART4_R>; + wakeup-source; + dmas = <&dmamux1 63 0x400 0x5>, + <&dmamux1 64 0x400 0x1>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart5: serial@40011000 { + compatible = "st,stm32h7-uart"; + reg = <0x40011000 0x400>; + interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc UART5_K>; + resets = <&rcc UART5_R>; + wakeup-source; + dmas = <&dmamux1 65 0x400 0x5>, + <&dmamux1 66 0x400 0x1>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -442,6 +472,32 @@ status = "disabled"; }; + uart7: serial@40018000 { + compatible = "st,stm32h7-uart"; + reg = <0x40018000 0x400>; + interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc UART7_K>; + resets = <&rcc UART7_R>; + wakeup-source; + dmas = <&dmamux1 79 0x400 0x5>, + <&dmamux1 80 0x400 0x1>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart8: serial@40019000 { + compatible = "st,stm32h7-uart"; + reg = <0x40019000 0x400>; + interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc UART8_K>; + resets = <&rcc UART8_R>; + wakeup-source; + dmas = <&dmamux1 81 0x400 0x5>, + <&dmamux1 82 0x400 0x1>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + timers1: timer@44000000 { #address-cells = <1>; #size-cells = <0>; @@ -524,6 +580,19 @@ }; }; + usart6: serial@44003000 { + compatible = "st,stm32h7-uart"; + reg = <0x44003000 0x400>; + interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc USART6_K>; + resets = <&rcc USART6_R>; + wakeup-source; + dmas = <&dmamux1 71 0x400 0x5>, + <&dmamux1 72 0x400 0x1>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + i2s1: audio-controller@44004000 { compatible = "st,stm32h7-i2s"; reg = <0x44004000 0x400>; @@ -748,6 +817,32 @@ status = "disabled"; }; + usart1: serial@4c000000 { + compatible = "st,stm32h7-uart"; + reg = <0x4c000000 0x400>; + interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc USART1_K>; + resets = <&rcc USART1_R>; + wakeup-source; + dmas = <&dmamux1 41 0x400 0x5>, + <&dmamux1 42 0x400 0x1>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + usart2: serial@4c001000 { + compatible = "st,stm32h7-uart"; + reg = <0x4c001000 0x400>; + interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc USART2_K>; + resets = <&rcc USART2_R>; + wakeup-source; + dmas = <&dmamux1 43 0x400 0x5>, + <&dmamux1 44 0x400 0x1>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + i2s4: audio-controller@4c002000 { compatible = "st,stm32h7-i2s"; reg = <0x4c002000 0x400>; @@ -1001,8 +1096,6 @@ reg = <0x50000000 0x1000>; #clock-cells = <1>; #reset-cells = <1>; - interrupts = ; - clock-names = "hse", "hsi", "csi", "lse", "lsi"; clocks = <&scmi_clk CK_SCMI_HSE>, <&scmi_clk CK_SCMI_HSI>, diff --git a/arch/arm/dts/stm32mp135f-dk.dts b/arch/arm/dts/stm32mp135f-dk.dts index c40686c..f0900ca 100644 --- a/arch/arm/dts/stm32mp135f-dk.dts +++ b/arch/arm/dts/stm32mp135f-dk.dts @@ -19,6 +19,13 @@ aliases { serial0 = &uart4; + serial1 = &usart1; + serial2 = &uart8; + serial3 = &usart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; }; memory@c0000000 { @@ -267,8 +274,41 @@ }; &uart4 { - pinctrl-names = "default"; + pinctrl-names = "default", "sleep", "idle"; pinctrl-0 = <&uart4_pins_a>; + pinctrl-1 = <&uart4_sleep_pins_a>; + pinctrl-2 = <&uart4_idle_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; +}; + +&uart8 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&uart8_pins_a>; + pinctrl-1 = <&uart8_sleep_pins_a>; + pinctrl-2 = <&uart8_idle_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; + status = "disabled"; +}; + +&usart1 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&usart1_pins_a>; + pinctrl-1 = <&usart1_sleep_pins_a>; + pinctrl-2 = <&usart1_idle_pins_a>; + uart-has-rtscts; + status = "disabled"; +}; + +/* Bluetooth */ +&usart2 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&usart2_pins_a>; + pinctrl-1 = <&usart2_sleep_pins_a>; + pinctrl-2 = <&usart2_idle_pins_a>; + uart-has-rtscts; status = "okay"; }; diff --git a/arch/arm/dts/stm32mp15-pinctrl.dtsi b/arch/arm/dts/stm32mp15-pinctrl.dtsi index a9d2bec..e86d989 100644 --- a/arch/arm/dts/stm32mp15-pinctrl.dtsi +++ b/arch/arm/dts/stm32mp15-pinctrl.dtsi @@ -1880,6 +1880,21 @@ }; }; + spi1_pins_b: spi1-1 { + pins1 { + pinmux = , /* SPI1_SCK */ + ; /* SPI1_MOSI */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + + pins2 { + pinmux = ; /* SPI1_MISO */ + bias-disable; + }; + }; + spi2_pins_a: spi2-0 { pins1 { pinmux = , /* SPI2_SCK */ @@ -2163,7 +2178,7 @@ ; /* USART2_RTS */ bias-disable; drive-push-pull; - slew-rate = <3>; + slew-rate = <0>; }; pins2 { pinmux = , /* USART2_RX */ @@ -2181,7 +2196,7 @@ pinmux = ; /* USART2_RTS */ bias-disable; drive-push-pull; - slew-rate = <3>; + slew-rate = <0>; }; pins3 { pinmux = ; /* USART2_RX */ @@ -2448,19 +2463,4 @@ bias-disable; }; }; - - spi1_pins_b: spi1-1 { - pins1 { - pinmux = , /* SPI1_SCK */ - ; /* SPI1_MOSI */ - bias-disable; - drive-push-pull; - slew-rate = <1>; - }; - - pins2 { - pinmux = ; /* SPI1_MISO */ - bias-disable; - }; - }; }; diff --git a/arch/arm/dts/stm32mp151.dtsi b/arch/arm/dts/stm32mp151.dtsi index b3baacb..21d11be 100644 --- a/arch/arm/dts/stm32mp151.dtsi +++ b/arch/arm/dts/stm32mp151.dtsi @@ -1148,8 +1148,8 @@ usbotg_hs: usb-otg@49000000 { compatible = "st,stm32mp15-hsotg", "snps,dwc2"; reg = <0x49000000 0x10000>; - clocks = <&rcc USBO_K>; - clock-names = "otg"; + clocks = <&rcc USBO_K>, <&usbphyc>; + clock-names = "otg", "utmi"; resets = <&rcc USBO_R>; reset-names = "dwc2"; interrupts = ; diff --git a/arch/arm/dts/stm32mp157a-dk1.dts b/arch/arm/dts/stm32mp157a-dk1.dts index 4c8be9c..0da3667 100644 --- a/arch/arm/dts/stm32mp157a-dk1.dts +++ b/arch/arm/dts/stm32mp157a-dk1.dts @@ -17,9 +17,6 @@ aliases { ethernet0 = ðernet0; - serial0 = &uart4; - serial1 = &usart3; - serial2 = &uart7; }; chosen { diff --git a/arch/arm/dts/stm32mp157c-dk2.dts b/arch/arm/dts/stm32mp157c-dk2.dts index 2bc92ef..ab13e34 100644 --- a/arch/arm/dts/stm32mp157c-dk2.dts +++ b/arch/arm/dts/stm32mp157c-dk2.dts @@ -18,9 +18,6 @@ aliases { ethernet0 = ðernet0; - serial0 = &uart4; - serial1 = &usart3; - serial2 = &uart7; serial3 = &usart2; }; diff --git a/arch/arm/dts/stm32mp157c-ed1.dts b/arch/arm/dts/stm32mp157c-ed1.dts index fe5c8f2..3541a17 100644 --- a/arch/arm/dts/stm32mp157c-ed1.dts +++ b/arch/arm/dts/stm32mp157c-ed1.dts @@ -16,6 +16,10 @@ model = "STMicroelectronics STM32MP157C eval daughter"; compatible = "st,stm32mp157c-ed1", "st,stm32mp157"; + aliases { + serial0 = &uart4; + }; + chosen { stdout-path = "serial0:115200n8"; }; @@ -65,15 +69,6 @@ reg = <0x38000000 0x10000>; no-map; }; - - gpu_reserved: gpu@e8000000 { - reg = <0xe8000000 0x8000000>; - no-map; - }; - }; - - aliases { - serial0 = &uart4; }; sd_switch: regulator-sd_switch { @@ -148,10 +143,6 @@ status = "okay"; }; -&gpu { - contiguous-area = <&gpu_reserved>; -}; - &hash1 { status = "okay"; }; diff --git a/arch/arm/dts/stm32mp157c-ev1.dts b/arch/arm/dts/stm32mp157c-ev1.dts index 542226c..ba8e9d9 100644 --- a/arch/arm/dts/stm32mp157c-ev1.dts +++ b/arch/arm/dts/stm32mp157c-ev1.dts @@ -14,16 +14,15 @@ model = "STMicroelectronics STM32MP157C eval daughter on eval mother"; compatible = "st,stm32mp157c-ev1", "st,stm32mp157c-ed1", "st,stm32mp157"; - chosen { - stdout-path = "serial0:115200n8"; - }; - aliases { - serial0 = &uart4; serial1 = &usart3; ethernet0 = ðernet0; }; + chosen { + stdout-path = "serial0:115200n8"; + }; + clocks { clk_ext_camera: clk-ext-camera { #clock-cells = <0>; diff --git a/arch/arm/dts/stm32mp15xx-dkx.dtsi b/arch/arm/dts/stm32mp15xx-dkx.dtsi index 49b3e76..f4de6c0 100644 --- a/arch/arm/dts/stm32mp15xx-dkx.dtsi +++ b/arch/arm/dts/stm32mp15xx-dkx.dtsi @@ -8,6 +8,12 @@ #include / { + aliases { + serial0 = &uart4; + serial1 = &usart3; + serial2 = &uart7; + }; + memory@c0000000 { device_type = "memory"; reg = <0xc0000000 0x20000000>; @@ -53,11 +59,6 @@ reg = <0x38000000 0x10000>; no-map; }; - - gpu_reserved: gpu@d4000000 { - reg = <0xd4000000 0x4000000>; - no-map; - }; }; led { @@ -159,10 +160,6 @@ }; }; -&gpu { - contiguous-area = <&gpu_reserved>; -}; - &hash1 { status = "okay"; }; -- cgit v1.1 From 284b08fb51b60255cbedcfe7aa7dcf319450d7e3 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Mon, 10 Jul 2023 13:30:59 +0200 Subject: board: stm32mp1: add splash screen with stmicroelectronics logo Display the STMicroelectronics logo with features VIDEO_LOGO and SPLASH_SCREEN on STMicroelectronics boards. With CONFIG_SYS_VENDOR = "st", the logo st.bmp is selected, loaded at the address indicated by splashimage and centered with "splashpos=m,m". Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard --- MAINTAINERS | 1 + configs/stm32mp15_basic_defconfig | 3 +++ configs/stm32mp15_defconfig | 3 +++ configs/stm32mp15_trusted_defconfig | 3 +++ include/configs/stm32mp15_st_common.h | 4 +++- tools/logos/st.bmp | Bin 0 -> 18244 bytes 6 files changed, 13 insertions(+), 1 deletion(-) create mode 100644 tools/logos/st.bmp diff --git a/MAINTAINERS b/MAINTAINERS index bf851cf..523c17e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -633,6 +633,7 @@ F: include/dt-bindings/clock/stm32mp* F: include/dt-bindings/pinctrl/stm32-pinfunc.h F: include/dt-bindings/reset/stm32mp* F: include/stm32_rcc.h +F: tools/logos/st.bmp F: tools/stm32image.c N: stm N: stm32 diff --git a/configs/stm32mp15_basic_defconfig b/configs/stm32mp15_basic_defconfig index 424ae5d..9ea5aaa 100644 --- a/configs/stm32mp15_basic_defconfig +++ b/configs/stm32mp15_basic_defconfig @@ -171,6 +171,7 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0483 CONFIG_USB_GADGET_PRODUCT_NUM=0x5720 CONFIG_USB_GADGET_DWC2_OTG=y CONFIG_VIDEO=y +CONFIG_VIDEO_LOGO=y CONFIG_BACKLIGHT_GPIO=y CONFIG_VIDEO_LCD_ORISETECH_OTM8009A=y CONFIG_VIDEO_LCD_RAYDIUM_RM68200=y @@ -178,6 +179,8 @@ CONFIG_VIDEO_STM32=y CONFIG_VIDEO_STM32_DSI=y CONFIG_VIDEO_STM32_MAX_XRES=1280 CONFIG_VIDEO_STM32_MAX_YRES=800 +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y CONFIG_BMP_16BPP=y CONFIG_BMP_24BPP=y CONFIG_BMP_32BPP=y diff --git a/configs/stm32mp15_defconfig b/configs/stm32mp15_defconfig index 2700b5c..4d0a81f 100644 --- a/configs/stm32mp15_defconfig +++ b/configs/stm32mp15_defconfig @@ -147,6 +147,7 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0483 CONFIG_USB_GADGET_PRODUCT_NUM=0x5720 CONFIG_USB_GADGET_DWC2_OTG=y CONFIG_VIDEO=y +CONFIG_VIDEO_LOGO=y CONFIG_BACKLIGHT_GPIO=y CONFIG_VIDEO_LCD_ORISETECH_OTM8009A=y CONFIG_VIDEO_LCD_RAYDIUM_RM68200=y @@ -154,6 +155,8 @@ CONFIG_VIDEO_STM32=y CONFIG_VIDEO_STM32_DSI=y CONFIG_VIDEO_STM32_MAX_XRES=1280 CONFIG_VIDEO_STM32_MAX_YRES=800 +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y CONFIG_BMP_16BPP=y CONFIG_BMP_24BPP=y CONFIG_BMP_32BPP=y diff --git a/configs/stm32mp15_trusted_defconfig b/configs/stm32mp15_trusted_defconfig index 5b94e0c..0a7d862 100644 --- a/configs/stm32mp15_trusted_defconfig +++ b/configs/stm32mp15_trusted_defconfig @@ -147,6 +147,7 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0483 CONFIG_USB_GADGET_PRODUCT_NUM=0x5720 CONFIG_USB_GADGET_DWC2_OTG=y CONFIG_VIDEO=y +CONFIG_VIDEO_LOGO=y CONFIG_BACKLIGHT_GPIO=y CONFIG_VIDEO_LCD_ORISETECH_OTM8009A=y CONFIG_VIDEO_LCD_RAYDIUM_RM68200=y @@ -154,6 +155,8 @@ CONFIG_VIDEO_STM32=y CONFIG_VIDEO_STM32_DSI=y CONFIG_VIDEO_STM32_MAX_XRES=1280 CONFIG_VIDEO_STM32_MAX_YRES=800 +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y CONFIG_BMP_16BPP=y CONFIG_BMP_24BPP=y CONFIG_BMP_32BPP=y diff --git a/include/configs/stm32mp15_st_common.h b/include/configs/stm32mp15_st_common.h index b45982a..60838cb 100644 --- a/include/configs/stm32mp15_st_common.h +++ b/include/configs/stm32mp15_st_common.h @@ -10,7 +10,9 @@ #define STM32MP_BOARD_EXTRA_ENV \ "usb_pgood_delay=2000\0" \ - "console=ttySTM0\0" + "console=ttySTM0\0" \ + "splashimage=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "splashpos=m,m\0" #include diff --git a/tools/logos/st.bmp b/tools/logos/st.bmp new file mode 100644 index 0000000..f59d3c5 Binary files /dev/null and b/tools/logos/st.bmp differ -- cgit v1.1 From c9678850bdef44bd7cab6238c56151b54d809047 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 27 Jul 2023 01:58:07 +0200 Subject: ARM: dts: stm32: Switch DWMAC RMII clock to MCO2 on DHCOM The DHCOM SoM has two options for supplying ETHRX clock to the DWMAC block and PHY. Either (1) ETHCK_K generates 50 MHz clock on ETH_CLK pad for the PHY and the same 50 MHz clock are fed back to ETHRX via internal eth_clk_fb clock connection OR (2) ETH_CLK is not used at all, MCO2 generates 50 MHz clock on MCO2 output pad for the PHY and the same MCO2 clock are fed back into ETHRX via ETH_RX_CLK input pad using external pad-to-pad connection. Option (1) has two downsides. ETHCK_K is supplied directly from either PLL3_Q or PLL4_P, hence the PLL output is limited to exactly 50 MHz and since the same PLL output is also used to supply SDMMC blocks, the performance of SD and eMMC access is affected. The second downside is that using this option, the EMI of the SoM is higher. Option (2) solves both of those problems, so implement it here. In this case, the PLL4_P is no longer limited and can be operated faster, at 100 MHz, which improves SDMMC performance (read performance is improved from ~41 MiB/s to ~57 MiB/s with dd if=/dev/mmcblk1 of=/dev/null bs=64M count=1). The EMI interference also decreases. Ported from Linux kernel commit 73ab99aad50cd ("ARM: dts: stm32: Switch DWMAC RMII clock to MCO2 on DHCOM") Signed-off-by: Marek Vasut Reviewed-by: Patrice Chotard --- arch/arm/dts/stm32mp15xx-dhcom-som.dtsi | 22 ++++++++++++++++++---- arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi | 14 ++++++++++++++ 2 files changed, 32 insertions(+), 4 deletions(-) diff --git a/arch/arm/dts/stm32mp15xx-dhcom-som.dtsi b/arch/arm/dts/stm32mp15xx-dhcom-som.dtsi index de76174..d3b85a8 100644 --- a/arch/arm/dts/stm32mp15xx-dhcom-som.dtsi +++ b/arch/arm/dts/stm32mp15xx-dhcom-som.dtsi @@ -118,13 +118,12 @@ ðernet0 { status = "okay"; - pinctrl-0 = <ðernet0_rmii_pins_a>; - pinctrl-1 = <ðernet0_rmii_sleep_pins_a>; + pinctrl-0 = <ðernet0_rmii_pins_c &mco2_pins_a>; + pinctrl-1 = <ðernet0_rmii_sleep_pins_c &mco2_sleep_pins_a>; pinctrl-names = "default", "sleep"; phy-mode = "rmii"; max-speed = <100>; phy-handle = <&phy0>; - st,eth-ref-clk-sel; mdio0 { #address-cells = <1>; @@ -136,7 +135,7 @@ /* LAN8710Ai */ compatible = "ethernet-phy-id0007.c0f0", "ethernet-phy-ieee802.3-c22"; - clocks = <&rcc ETHCK_K>; + clocks = <&rcc CK_MCO2>; reset-gpios = <&gpioh 3 GPIO_ACTIVE_LOW>; reset-assert-us = <500>; reset-deassert-us = <500>; @@ -450,6 +449,21 @@ }; }; +&rcc { + /* Connect MCO2 output to ETH_RX_CLK input via pad-pad connection */ + clocks = <&rcc CK_MCO2>; + clock-names = "ETH_RX_CLK/ETH_REF_CLK"; + + /* + * Set PLL4P output to 100 MHz to supply SDMMC with faster clock, + * set MCO2 output to 50 MHz to supply ETHRX clock with PLL4P/2, + * so that MCO2 behaves as a divider for the ETHRX clock here. + */ + assigned-clocks = <&rcc CK_MCO2>, <&rcc PLL4_P>; + assigned-clock-parents = <&rcc PLL4_P>; + assigned-clock-rates = <50000000>, <100000000>; +}; + &rng1 { status = "okay"; }; diff --git a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi index a808620..f12941b 100644 --- a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi +++ b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi @@ -153,6 +153,20 @@ }; &rcc { + /* + * Reinstate clock names from stm32mp151.dtsi, the MCO2 trick + * used in stm32mp15xx-dhcom-som.dtsi is not supported by the + * U-Boot clock framework. + */ + clock-names = "hse", "hsi", "csi", "lse", "lsi"; + clocks = <&clk_hse>, <&clk_hsi>, <&clk_csi>, + <&clk_lse>, <&clk_lsi>; + + /* The MCO2 is already configured correctly, remove those. */ + /delete-property/ assigned-clocks; + /delete-property/ assigned-clock-parents; + /delete-property/ assigned-clock-rates; + st,clksrc = < CLK_MPU_PLL1P CLK_AXI_PLL2P -- cgit v1.1 From 9e8cbea1a74516235820ccd50d513c961e43cb70 Mon Sep 17 00:00:00 2001 From: Valentin Caron Date: Fri, 4 Aug 2023 16:09:04 +0200 Subject: serial: stm32: extend TC timeout Waiting 150us TC bit couldn't be enough. If TFA lets 16 bits in USART fifo, we has to wait 16 times 87 us (time of 10 bits (1 byte in most use cases) at a baud rate of 115200). Fixes: b4dbc5d65a67 ("serial: stm32: Wait TC bit before performing initialization") Signed-off-by: Valentin Caron Signed-off-by: Patrice Chotard --- drivers/serial/serial_stm32.c | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/drivers/serial/serial_stm32.c b/drivers/serial/serial_stm32.c index 0085113..23d476f 100644 --- a/drivers/serial/serial_stm32.c +++ b/drivers/serial/serial_stm32.c @@ -22,6 +22,14 @@ #include "serial_stm32.h" #include +/* + * At 115200 bits/s + * 1 bit = 1 / 115200 = 8,68 us + * 8 bits = 69,444 us + * 10 bits are needed for worst case (8 bits + 1 start + 1 stop) = 86.806 us + */ +#define ONE_BYTE_B115200_US 87 + static void _stm32_serial_setbrg(fdt_addr_t base, struct stm32_uart_info *uart_info, u32 clock_rate, @@ -209,12 +217,10 @@ static int stm32_serial_probe(struct udevice *dev) * before uart initialization, wait for TC bit (Transmission Complete) * in case there is still chars from previous bootstage to transmit */ - ret = read_poll_timeout(readl, isr, isr & USART_ISR_TC, 10, 150, - plat->base + ISR_OFFSET(stm32f4)); - if (ret) { - clk_disable(&clk); - return ret; - } + ret = read_poll_timeout(readl, isr, isr & USART_ISR_TC, 50, + 16 * ONE_BYTE_B115200_US, plat->base + ISR_OFFSET(stm32f4)); + if (ret) + dev_dbg(dev, "FIFO not empty, some character can be lost (%d)\n", ret); ret = reset_get_by_index(dev, 0, &reset); if (!ret) { -- cgit v1.1