From 2b8dc36b4c515979da330a96d9fcc9bbbe5385fa Mon Sep 17 00:00:00 2001 From: Leo Yu-Chi Liang Date: Tue, 14 May 2024 17:50:11 +0800 Subject: andes: Unify naming policy for Andes related source Signed-off-by: Leo Yu-Chi Liang --- arch/riscv/Kconfig | 4 +- arch/riscv/cpu/andes/Kconfig | 17 ++ arch/riscv/cpu/andes/Makefile | 8 + arch/riscv/cpu/andes/cache.c | 129 +++++++++ arch/riscv/cpu/andes/cpu.c | 64 +++++ arch/riscv/cpu/andes/spl.c | 26 ++ arch/riscv/cpu/andesv5/Kconfig | 17 -- arch/riscv/cpu/andesv5/Makefile | 8 - arch/riscv/cpu/andesv5/cache.c | 129 --------- arch/riscv/cpu/andesv5/cpu.c | 64 ----- arch/riscv/cpu/andesv5/spl.c | 26 -- board/AndesTech/ae350/Kconfig | 44 ---- board/AndesTech/ae350/MAINTAINERS | 17 -- board/AndesTech/ae350/Makefile | 6 - board/AndesTech/ae350/ae350.c | 165 ------------ board/andestech/ae350/Kconfig | 44 ++++ board/andestech/ae350/MAINTAINERS | 17 ++ board/andestech/ae350/Makefile | 6 + board/andestech/ae350/ae350.c | 165 ++++++++++++ doc/board/AndesTech/adp-ag101p.rst | 40 --- doc/board/AndesTech/ae350.rst | 524 ------------------------------------- doc/board/AndesTech/index.rst | 10 - doc/board/andestech/adp-ag101p.rst | 40 +++ doc/board/andestech/ae350.rst | 524 +++++++++++++++++++++++++++++++++++++ doc/board/andestech/index.rst | 10 + doc/board/index.rst | 2 +- drivers/cache/Kconfig | 6 +- drivers/cache/Makefile | 2 +- drivers/cache/cache-andes-l2.c | 204 +++++++++++++++ drivers/cache/cache-v5l2.c | 204 --------------- 30 files changed, 1261 insertions(+), 1261 deletions(-) create mode 100644 arch/riscv/cpu/andes/Kconfig create mode 100644 arch/riscv/cpu/andes/Makefile create mode 100644 arch/riscv/cpu/andes/cache.c create mode 100644 arch/riscv/cpu/andes/cpu.c create mode 100644 arch/riscv/cpu/andes/spl.c delete mode 100644 arch/riscv/cpu/andesv5/Kconfig delete mode 100644 arch/riscv/cpu/andesv5/Makefile delete mode 100644 arch/riscv/cpu/andesv5/cache.c delete mode 100644 arch/riscv/cpu/andesv5/cpu.c delete mode 100644 arch/riscv/cpu/andesv5/spl.c delete mode 100644 board/AndesTech/ae350/Kconfig delete mode 100644 board/AndesTech/ae350/MAINTAINERS delete mode 100644 board/AndesTech/ae350/Makefile delete mode 100644 board/AndesTech/ae350/ae350.c create mode 100644 board/andestech/ae350/Kconfig create mode 100644 board/andestech/ae350/MAINTAINERS create mode 100644 board/andestech/ae350/Makefile create mode 100644 board/andestech/ae350/ae350.c delete mode 100644 doc/board/AndesTech/adp-ag101p.rst delete mode 100644 doc/board/AndesTech/ae350.rst delete mode 100644 doc/board/AndesTech/index.rst create mode 100644 doc/board/andestech/adp-ag101p.rst create mode 100644 doc/board/andestech/ae350.rst create mode 100644 doc/board/andestech/index.rst create mode 100644 drivers/cache/cache-andes-l2.c delete mode 100644 drivers/cache/cache-v5l2.c diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 7e20ef6..fa3b016 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -80,7 +80,7 @@ config SPL_ZERO_MEM_BEFORE_USE Sifive core devices that uses L2 cache to store SPL. # board-specific options below -source "board/AndesTech/ae350/Kconfig" +source "board/andestech/ae350/Kconfig" source "board/emulation/qemu-riscv/Kconfig" source "board/microchip/mpfs_icicle/Kconfig" source "board/openpiton/riscv64/Kconfig" @@ -93,7 +93,7 @@ source "board/thead/th1520_lpi4a/Kconfig" source "board/xilinx/mbv/Kconfig" # platform-specific options below -source "arch/riscv/cpu/andesv5/Kconfig" +source "arch/riscv/cpu/andes/Kconfig" source "arch/riscv/cpu/cv1800b/Kconfig" source "arch/riscv/cpu/fu540/Kconfig" source "arch/riscv/cpu/fu740/Kconfig" diff --git a/arch/riscv/cpu/andes/Kconfig b/arch/riscv/cpu/andes/Kconfig new file mode 100644 index 0000000..120fec5 --- /dev/null +++ b/arch/riscv/cpu/andes/Kconfig @@ -0,0 +1,17 @@ +config RISCV_ANDES + bool + select ARCH_EARLY_INIT_R + select SYS_CACHE_SHIFT_6 + imply CPU + imply CPU_RISCV + imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE) + imply ANDES_PLMT_TIMER + imply SPL_ANDES_PLMT_TIMER + imply ANDES_PLICSW if (RISCV_MMODE || SPL_RISCV_MMODE) + imply ANDES_L2_CACHE + imply SPL_CPU + imply SPL_OPENSBI + imply SPL_LOAD_FIT + help + Run U-Boot on AndeStar V5 platforms and use some specific features + which are provided by Andes Technology AndeStar V5 families. diff --git a/arch/riscv/cpu/andes/Makefile b/arch/riscv/cpu/andes/Makefile new file mode 100644 index 0000000..35a1a2f --- /dev/null +++ b/arch/riscv/cpu/andes/Makefile @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2017 Andes Technology Corporation +# Rick Chen, Andes Technology Corporation + +obj-y := cpu.o +obj-y += cache.o +obj-y += spl.o diff --git a/arch/riscv/cpu/andes/cache.c b/arch/riscv/cpu/andes/cache.c new file mode 100644 index 0000000..7d3df87 --- /dev/null +++ b/arch/riscv/cpu/andes/cache.c @@ -0,0 +1,129 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2023 Andes Technology Corporation + * Rick Chen, Andes Technology Corporation + */ + +#include +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_ANDES_L2_CACHE +void enable_caches(void) +{ + struct udevice *dev; + int ret; + + ret = uclass_get_device_by_driver(UCLASS_CACHE, + DM_DRIVER_GET(andes_l2_cache), + &dev); + if (ret) { + log_debug("Cannot enable Andes L2 cache\n"); + } else { + ret = cache_enable(dev); + if (ret) + log_debug("Failed to enable Andes L2 cache\n"); + } +} + +static void cache_ops(int (*ops)(struct udevice *dev)) +{ + struct udevice *dev = NULL; + + uclass_find_first_device(UCLASS_CACHE, &dev); + + if (dev) + ops(dev); +} +#endif + +void flush_dcache_all(void) +{ +#if CONFIG_IS_ENABLED(RISCV_MMODE) + csr_write(CSR_MCCTLCOMMAND, CCTL_L1D_WBINVAL_ALL); +#endif +} + +void flush_dcache_range(unsigned long start, unsigned long end) +{ + flush_dcache_all(); +} + +void invalidate_dcache_range(unsigned long start, unsigned long end) +{ + flush_dcache_all(); +} + +void icache_enable(void) +{ +#if CONFIG_IS_ENABLED(RISCV_MMODE) + asm volatile("csrsi %0, 0x1" :: "i"(CSR_MCACHE_CTL)); +#endif +} + +void icache_disable(void) +{ +#if CONFIG_IS_ENABLED(RISCV_MMODE) + asm volatile("csrci %0, 0x1" :: "i"(CSR_MCACHE_CTL)); +#endif +} + +void dcache_enable(void) +{ +#if CONFIG_IS_ENABLED(RISCV_MMODE) + asm volatile("csrsi %0, 0x2" :: "i"(CSR_MCACHE_CTL)); +#endif + +#ifdef CONFIG_ANDES_L2_CACHE + cache_ops(cache_enable); +#endif +} + +void dcache_disable(void) +{ +#if CONFIG_IS_ENABLED(RISCV_MMODE) + asm volatile("csrci %0, 0x2" :: "i"(CSR_MCACHE_CTL)); +#endif + +#ifdef CONFIG_ANDES_L2_CACHE + cache_ops(cache_disable); +#endif +} + +int icache_status(void) +{ + int ret = 0; + +#if CONFIG_IS_ENABLED(RISCV_MMODE) + asm volatile ( + "csrr t1, %1\n\t" + "andi %0, t1, 0x01\n\t" + : "=r" (ret) + : "i"(CSR_MCACHE_CTL) + : "memory" + ); +#endif + + return !!ret; +} + +int dcache_status(void) +{ + int ret = 0; + +#if CONFIG_IS_ENABLED(RISCV_MMODE) + asm volatile ( + "csrr t1, %1\n\t" + "andi %0, t1, 0x02\n\t" + : "=r" (ret) + : "i" (CSR_MCACHE_CTL) + : "memory" + ); +#endif + + return !!ret; +} diff --git a/arch/riscv/cpu/andes/cpu.c b/arch/riscv/cpu/andes/cpu.c new file mode 100644 index 0000000..d25ecba --- /dev/null +++ b/arch/riscv/cpu/andes/cpu.c @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2023 Andes Technology Corporation + * Rick Chen, Andes Technology Corporation + */ + +/* CPU specific code */ +#include +#include +#include +#include +#include + +/* + * cleanup_before_linux() is called just before we call linux + * it prepares the processor for linux + * + * we disable interrupt and caches. + */ +int cleanup_before_linux(void) +{ + disable_interrupts(); + + cache_flush(); + + return 0; +} + +void harts_early_init(void) +{ + /* Enable I/D-cache in SPL */ + if (CONFIG_IS_ENABLED(RISCV_MMODE)) { + unsigned long mcache_ctl_val = csr_read(CSR_MCACHE_CTL); + unsigned long mmisc_ctl_val = csr_read(CSR_MMISC_CTL); + + mcache_ctl_val |= (MCACHE_CTL_CCTL_SUEN | \ + MCACHE_CTL_IC_PREFETCH_EN | MCACHE_CTL_DC_PREFETCH_EN | \ + MCACHE_CTL_DC_WAROUND_EN | MCACHE_CTL_L2C_WAROUND_EN | \ + MCACHE_CTL_IC_ECCEN | MCACHE_CTL_DC_ECCEN | MCACHE_CTL_TLB_ECCEN); + + if (!CONFIG_IS_ENABLED(SYS_ICACHE_OFF)) + mcache_ctl_val |= MCACHE_CTL_IC_EN; + + if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) + mcache_ctl_val |= (MCACHE_CTL_DC_EN | MCACHE_CTL_DC_COHEN); + + csr_write(CSR_MCACHE_CTL, mcache_ctl_val); + + if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) { + /* + * Check mcache_ctl.DC_COHEN, we assume this platform does + * not support CM if the bit is hard-wired to 0. + */ + if (csr_read(CSR_MCACHE_CTL) & MCACHE_CTL_DC_COHEN) { + /* Wait for DC_COHSTA bit to be set */ + while (!(csr_read(CSR_MCACHE_CTL) & MCACHE_CTL_DC_COHSTA)); + } + } + + mmisc_ctl_val |= MMISC_CTL_NON_BLOCKING_EN; + + csr_write(CSR_MMISC_CTL, mmisc_ctl_val); + } +} diff --git a/arch/riscv/cpu/andes/spl.c b/arch/riscv/cpu/andes/spl.c new file mode 100644 index 0000000..a13dc40 --- /dev/null +++ b/arch/riscv/cpu/andes/spl.c @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2023 Andes Technology Corporation + * Rick Chen, Andes Technology Corporation + */ +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#if CONFIG_IS_ENABLED(RAM_SUPPORT) +struct legacy_img_hdr *spl_get_load_buffer(ssize_t offset, size_t size) +{ + return (void *)(CONFIG_SPL_LOAD_FIT_ADDRESS + offset); +} + +void *board_spl_fit_buffer_addr(ulong fit_size, int sectors, int bl_len) +{ + return spl_get_load_buffer(0, sectors * bl_len); +} +#endif diff --git a/arch/riscv/cpu/andesv5/Kconfig b/arch/riscv/cpu/andesv5/Kconfig deleted file mode 100644 index e3efb0d..0000000 --- a/arch/riscv/cpu/andesv5/Kconfig +++ /dev/null @@ -1,17 +0,0 @@ -config RISCV_NDS - bool - select ARCH_EARLY_INIT_R - select SYS_CACHE_SHIFT_6 - imply CPU - imply CPU_RISCV - imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE) - imply ANDES_PLMT_TIMER - imply SPL_ANDES_PLMT_TIMER - imply ANDES_PLICSW if (RISCV_MMODE || SPL_RISCV_MMODE) - imply V5L2_CACHE - imply SPL_CPU - imply SPL_OPENSBI - imply SPL_LOAD_FIT - help - Run U-Boot on AndeStar V5 platforms and use some specific features - which are provided by Andes Technology AndeStar V5 families. diff --git a/arch/riscv/cpu/andesv5/Makefile b/arch/riscv/cpu/andesv5/Makefile deleted file mode 100644 index 35a1a2f..0000000 --- a/arch/riscv/cpu/andesv5/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2017 Andes Technology Corporation -# Rick Chen, Andes Technology Corporation - -obj-y := cpu.o -obj-y += cache.o -obj-y += spl.o diff --git a/arch/riscv/cpu/andesv5/cache.c b/arch/riscv/cpu/andesv5/cache.c deleted file mode 100644 index 269bb27..0000000 --- a/arch/riscv/cpu/andesv5/cache.c +++ /dev/null @@ -1,129 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2023 Andes Technology Corporation - * Rick Chen, Andes Technology Corporation - */ - -#include -#include -#include -#include -#include -#include -#include - -#ifdef CONFIG_V5L2_CACHE -void enable_caches(void) -{ - struct udevice *dev; - int ret; - - ret = uclass_get_device_by_driver(UCLASS_CACHE, - DM_DRIVER_GET(v5l2_cache), - &dev); - if (ret) { - log_debug("Cannot enable v5l2 cache\n"); - } else { - ret = cache_enable(dev); - if (ret) - log_debug("v5l2 cache enable failed\n"); - } -} - -static void cache_ops(int (*ops)(struct udevice *dev)) -{ - struct udevice *dev = NULL; - - uclass_find_first_device(UCLASS_CACHE, &dev); - - if (dev) - ops(dev); -} -#endif - -void flush_dcache_all(void) -{ -#if CONFIG_IS_ENABLED(RISCV_MMODE) - csr_write(CSR_MCCTLCOMMAND, CCTL_L1D_WBINVAL_ALL); -#endif -} - -void flush_dcache_range(unsigned long start, unsigned long end) -{ - flush_dcache_all(); -} - -void invalidate_dcache_range(unsigned long start, unsigned long end) -{ - flush_dcache_all(); -} - -void icache_enable(void) -{ -#if CONFIG_IS_ENABLED(RISCV_MMODE) - asm volatile("csrsi %0, 0x1" :: "i"(CSR_MCACHE_CTL)); -#endif -} - -void icache_disable(void) -{ -#if CONFIG_IS_ENABLED(RISCV_MMODE) - asm volatile("csrci %0, 0x1" :: "i"(CSR_MCACHE_CTL)); -#endif -} - -void dcache_enable(void) -{ -#if CONFIG_IS_ENABLED(RISCV_MMODE) - asm volatile("csrsi %0, 0x2" :: "i"(CSR_MCACHE_CTL)); -#endif - -#ifdef CONFIG_V5L2_CACHE - cache_ops(cache_enable); -#endif -} - -void dcache_disable(void) -{ -#if CONFIG_IS_ENABLED(RISCV_MMODE) - asm volatile("csrci %0, 0x2" :: "i"(CSR_MCACHE_CTL)); -#endif - -#ifdef CONFIG_V5L2_CACHE - cache_ops(cache_disable); -#endif -} - -int icache_status(void) -{ - int ret = 0; - -#if CONFIG_IS_ENABLED(RISCV_MMODE) - asm volatile ( - "csrr t1, %1\n\t" - "andi %0, t1, 0x01\n\t" - : "=r" (ret) - : "i"(CSR_MCACHE_CTL) - : "memory" - ); -#endif - - return !!ret; -} - -int dcache_status(void) -{ - int ret = 0; - -#if CONFIG_IS_ENABLED(RISCV_MMODE) - asm volatile ( - "csrr t1, %1\n\t" - "andi %0, t1, 0x02\n\t" - : "=r" (ret) - : "i" (CSR_MCACHE_CTL) - : "memory" - ); -#endif - - return !!ret; -} diff --git a/arch/riscv/cpu/andesv5/cpu.c b/arch/riscv/cpu/andesv5/cpu.c deleted file mode 100644 index d25ecba..0000000 --- a/arch/riscv/cpu/andesv5/cpu.c +++ /dev/null @@ -1,64 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2023 Andes Technology Corporation - * Rick Chen, Andes Technology Corporation - */ - -/* CPU specific code */ -#include -#include -#include -#include -#include - -/* - * cleanup_before_linux() is called just before we call linux - * it prepares the processor for linux - * - * we disable interrupt and caches. - */ -int cleanup_before_linux(void) -{ - disable_interrupts(); - - cache_flush(); - - return 0; -} - -void harts_early_init(void) -{ - /* Enable I/D-cache in SPL */ - if (CONFIG_IS_ENABLED(RISCV_MMODE)) { - unsigned long mcache_ctl_val = csr_read(CSR_MCACHE_CTL); - unsigned long mmisc_ctl_val = csr_read(CSR_MMISC_CTL); - - mcache_ctl_val |= (MCACHE_CTL_CCTL_SUEN | \ - MCACHE_CTL_IC_PREFETCH_EN | MCACHE_CTL_DC_PREFETCH_EN | \ - MCACHE_CTL_DC_WAROUND_EN | MCACHE_CTL_L2C_WAROUND_EN | \ - MCACHE_CTL_IC_ECCEN | MCACHE_CTL_DC_ECCEN | MCACHE_CTL_TLB_ECCEN); - - if (!CONFIG_IS_ENABLED(SYS_ICACHE_OFF)) - mcache_ctl_val |= MCACHE_CTL_IC_EN; - - if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) - mcache_ctl_val |= (MCACHE_CTL_DC_EN | MCACHE_CTL_DC_COHEN); - - csr_write(CSR_MCACHE_CTL, mcache_ctl_val); - - if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) { - /* - * Check mcache_ctl.DC_COHEN, we assume this platform does - * not support CM if the bit is hard-wired to 0. - */ - if (csr_read(CSR_MCACHE_CTL) & MCACHE_CTL_DC_COHEN) { - /* Wait for DC_COHSTA bit to be set */ - while (!(csr_read(CSR_MCACHE_CTL) & MCACHE_CTL_DC_COHSTA)); - } - } - - mmisc_ctl_val |= MMISC_CTL_NON_BLOCKING_EN; - - csr_write(CSR_MMISC_CTL, mmisc_ctl_val); - } -} diff --git a/arch/riscv/cpu/andesv5/spl.c b/arch/riscv/cpu/andesv5/spl.c deleted file mode 100644 index a13dc40..0000000 --- a/arch/riscv/cpu/andesv5/spl.c +++ /dev/null @@ -1,26 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2023 Andes Technology Corporation - * Rick Chen, Andes Technology Corporation - */ -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -#if CONFIG_IS_ENABLED(RAM_SUPPORT) -struct legacy_img_hdr *spl_get_load_buffer(ssize_t offset, size_t size) -{ - return (void *)(CONFIG_SPL_LOAD_FIT_ADDRESS + offset); -} - -void *board_spl_fit_buffer_addr(ulong fit_size, int sectors, int bl_len) -{ - return spl_get_load_buffer(0, sectors * bl_len); -} -#endif diff --git a/board/AndesTech/ae350/Kconfig b/board/AndesTech/ae350/Kconfig deleted file mode 100644 index a85e7d6..0000000 --- a/board/AndesTech/ae350/Kconfig +++ /dev/null @@ -1,44 +0,0 @@ -if TARGET_ANDES_AE350 - -config SYS_CPU - default "andesv5" - -config SYS_BOARD - default "ae350" - -config SYS_VENDOR - default "AndesTech" - -config SYS_SOC - default "ae350" - -config SYS_CONFIG_NAME - default "ae350" - -config ENV_SIZE - default 0x2000 if ENV_IS_IN_SPI_FLASH - -config ENV_OFFSET - default 0x140000 if ENV_IS_IN_SPI_FLASH - -config SPL_TEXT_BASE - default 0x800000 - -config SPL_OPENSBI_LOAD_ADDR - default 0x00000000 - -config SYS_FDT_BASE - hex - default 0x800f0000 if OF_SEPARATE - -config BOARD_SPECIFIC_OPTIONS # dummy - def_bool y - select RISCV_NDS - select SUPPORT_SPL - select BINMAN if SPL - imply SMP - imply SPL_RAM_SUPPORT - imply SPL_RAM_DEVICE - imply OF_HAS_PRIOR_STAGE - -endif diff --git a/board/AndesTech/ae350/MAINTAINERS b/board/AndesTech/ae350/MAINTAINERS deleted file mode 100644 index a6bc90b..0000000 --- a/board/AndesTech/ae350/MAINTAINERS +++ /dev/null @@ -1,17 +0,0 @@ -AE350 BOARD -M: Rick Chen -S: Maintained -F: board/AndesTech/ae350/ -F: include/configs/ae350.h -F: configs/ae350_rv32_defconfig -F: configs/ae350_rv32_falcon_defconfig -F: configs/ae350_rv32_falcon_xip_defconfig -F: configs/ae350_rv32_spl_defconfig -F: configs/ae350_rv32_spl_xip_defconfig -F: configs/ae350_rv32_xip_defconfig -F: configs/ae350_rv64_defconfig -F: configs/ae350_rv64_falcon_defconfig -F: configs/ae350_rv64_falcon_xip_defconfig -F: configs/ae350_rv64_spl_defconfig -F: configs/ae350_rv64_spl_xip_defconfig -F: configs/ae350_rv64_xip_defconfig diff --git a/board/AndesTech/ae350/Makefile b/board/AndesTech/ae350/Makefile deleted file mode 100644 index 705ae43..0000000 --- a/board/AndesTech/ae350/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2017 Andes Technology Corporation. -# Rick Chen, Andes Technology Corporation - -obj-y := ae350.o diff --git a/board/AndesTech/ae350/ae350.c b/board/AndesTech/ae350/ae350.c deleted file mode 100644 index 62b93b4..0000000 --- a/board/AndesTech/ae350/ae350.c +++ /dev/null @@ -1,165 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2017 Andes Technology Corporation - * Rick Chen, Andes Technology Corporation - */ - -#include -#include -#include -#include -#include -#include -#if defined(CONFIG_FTMAC100) && !defined(CONFIG_DM_ETH) -#include -#endif -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -/* - * Miscellaneous platform dependent initializations - */ -#if IS_ENABLED(CONFIG_MISC_INIT_R) -int misc_init_r(void) -{ - long csr_marchid = 0; - const long mask_64 = 0x8000; - const long mask_cpu = 0xff; - char cpu_name[10] = {}; - -#if CONFIG_IS_ENABLED(RISCV_SMODE) - sbi_get_marchid(&csr_marchid); -#elif CONFIG_IS_ENABLED(RISCV_MMODE) - csr_marchid = csr_read(CSR_MARCHID); -#endif - if (mask_64 & csr_marchid) - snprintf(cpu_name, sizeof(cpu_name), "ax%lx", (mask_cpu & csr_marchid)); - else - snprintf(cpu_name, sizeof(cpu_name), "a%lx", (mask_cpu & csr_marchid)); - - return env_set("cpu", cpu_name); -} -#endif - -int board_init(void) -{ - gd->bd->bi_boot_params = PHYS_SDRAM_0 + 0x400; - - return 0; -} - -int dram_init(void) -{ - return fdtdec_setup_mem_size_base(); -} - -int dram_init_banksize(void) -{ - return fdtdec_setup_memory_banksize(); -} - -#if defined(CONFIG_FTMAC100) && !defined(CONFIG_DM_ETH) -int board_eth_init(struct bd_info *bd) -{ - return ftmac100_initialize(bd); -} -#endif - -ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info) -{ - return 0; -} - -#define ANDES_HW_DTB_ADDRESS 0xF2000000 -void *board_fdt_blob_setup(int *err) -{ - *err = 0; - - if (IS_ENABLED(CONFIG_OF_SEPARATE) || IS_ENABLED(CONFIG_OF_BOARD)) { - if (fdt_magic((uintptr_t)gd->arch.firmware_fdt_addr) == FDT_MAGIC) - return (void *)(ulong)gd->arch.firmware_fdt_addr; - } - - if (fdt_magic(CONFIG_SYS_FDT_BASE) == FDT_MAGIC) - return (void *)CONFIG_SYS_FDT_BASE; - return (void *)ANDES_HW_DTB_ADDRESS; - - *err = -EINVAL; - return NULL; -} - -#ifdef CONFIG_SPL_BOARD_INIT -void spl_board_init() -{ - /* enable v5l2 cache */ - if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) - enable_caches(); -} -#endif - -int smc_init(void) -{ - int node = -1; - const char *compat = "andestech,atfsmc020"; - void *blob = (void *)gd->fdt_blob; - fdt_addr_t addr; - struct ftsmc020_bank *regs; - - node = fdt_node_offset_by_compatible(blob, -1, compat); - if (node < 0) - return -FDT_ERR_NOTFOUND; - - addr = fdtdec_get_addr_size_auto_noparent(blob, node, - "reg", 0, NULL, false); - - if (addr == FDT_ADDR_T_NONE) - return -EINVAL; - - regs = (struct ftsmc020_bank *)(uintptr_t)addr; - regs->cr &= ~FTSMC020_BANK_WPROT; - - return 0; -} - -#ifdef CONFIG_BOARD_EARLY_INIT_F -int board_early_init_f(void) -{ - smc_init(); - - return 0; -} -#endif - -#ifdef CONFIG_SPL -void board_boot_order(u32 *spl_boot_list) -{ - u8 i; - u32 boot_devices[] = { -#ifdef CONFIG_SPL_RAM_SUPPORT - BOOT_DEVICE_RAM, -#endif -#ifdef CONFIG_SPL_MMC - BOOT_DEVICE_MMC1, -#endif - }; - - for (i = 0; i < ARRAY_SIZE(boot_devices); i++) - spl_boot_list[i] = boot_devices[i]; -} -#endif - -#ifdef CONFIG_SPL_LOAD_FIT -int board_fit_config_name_match(const char *name) -{ - /* boot using first FIT config */ - return 0; -} -#endif diff --git a/board/andestech/ae350/Kconfig b/board/andestech/ae350/Kconfig new file mode 100644 index 0000000..096564b --- /dev/null +++ b/board/andestech/ae350/Kconfig @@ -0,0 +1,44 @@ +if TARGET_ANDES_AE350 + +config SYS_CPU + default "andes" + +config SYS_BOARD + default "ae350" + +config SYS_VENDOR + default "andestech" + +config SYS_SOC + default "ae350" + +config SYS_CONFIG_NAME + default "ae350" + +config ENV_SIZE + default 0x2000 if ENV_IS_IN_SPI_FLASH + +config ENV_OFFSET + default 0x140000 if ENV_IS_IN_SPI_FLASH + +config SPL_TEXT_BASE + default 0x800000 + +config SPL_OPENSBI_LOAD_ADDR + default 0x00000000 + +config SYS_FDT_BASE + hex + default 0x800f0000 if OF_SEPARATE + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select RISCV_ANDES + select SUPPORT_SPL + select BINMAN if SPL + imply SMP + imply SPL_RAM_SUPPORT + imply SPL_RAM_DEVICE + imply OF_HAS_PRIOR_STAGE + +endif diff --git a/board/andestech/ae350/MAINTAINERS b/board/andestech/ae350/MAINTAINERS new file mode 100644 index 0000000..31e34e6 --- /dev/null +++ b/board/andestech/ae350/MAINTAINERS @@ -0,0 +1,17 @@ +AE350 BOARD +M: Rick Chen +S: Maintained +F: board/andestech/ae350/ +F: include/configs/ae350.h +F: configs/ae350_rv32_defconfig +F: configs/ae350_rv32_falcon_defconfig +F: configs/ae350_rv32_falcon_xip_defconfig +F: configs/ae350_rv32_spl_defconfig +F: configs/ae350_rv32_spl_xip_defconfig +F: configs/ae350_rv32_xip_defconfig +F: configs/ae350_rv64_defconfig +F: configs/ae350_rv64_falcon_defconfig +F: configs/ae350_rv64_falcon_xip_defconfig +F: configs/ae350_rv64_spl_defconfig +F: configs/ae350_rv64_spl_xip_defconfig +F: configs/ae350_rv64_xip_defconfig diff --git a/board/andestech/ae350/Makefile b/board/andestech/ae350/Makefile new file mode 100644 index 0000000..705ae43 --- /dev/null +++ b/board/andestech/ae350/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2017 Andes Technology Corporation. +# Rick Chen, Andes Technology Corporation + +obj-y := ae350.o diff --git a/board/andestech/ae350/ae350.c b/board/andestech/ae350/ae350.c new file mode 100644 index 0000000..5ae5bae --- /dev/null +++ b/board/andestech/ae350/ae350.c @@ -0,0 +1,165 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2017 Andes Technology Corporation + * Rick Chen, Andes Technology Corporation + */ + +#include +#include +#include +#include +#include +#include +#if defined(CONFIG_FTMAC100) && !defined(CONFIG_DM_ETH) +#include +#endif +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Miscellaneous platform dependent initializations + */ +#if IS_ENABLED(CONFIG_MISC_INIT_R) +int misc_init_r(void) +{ + long csr_marchid = 0; + const long mask_64 = 0x8000; + const long mask_cpu = 0xff; + char cpu_name[10] = {}; + +#if CONFIG_IS_ENABLED(RISCV_SMODE) + sbi_get_marchid(&csr_marchid); +#elif CONFIG_IS_ENABLED(RISCV_MMODE) + csr_marchid = csr_read(CSR_MARCHID); +#endif + if (mask_64 & csr_marchid) + snprintf(cpu_name, sizeof(cpu_name), "ax%lx", (mask_cpu & csr_marchid)); + else + snprintf(cpu_name, sizeof(cpu_name), "a%lx", (mask_cpu & csr_marchid)); + + return env_set("cpu", cpu_name); +} +#endif + +int board_init(void) +{ + gd->bd->bi_boot_params = PHYS_SDRAM_0 + 0x400; + + return 0; +} + +int dram_init(void) +{ + return fdtdec_setup_mem_size_base(); +} + +int dram_init_banksize(void) +{ + return fdtdec_setup_memory_banksize(); +} + +#if defined(CONFIG_FTMAC100) && !defined(CONFIG_DM_ETH) +int board_eth_init(struct bd_info *bd) +{ + return ftmac100_initialize(bd); +} +#endif + +ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info) +{ + return 0; +} + +#define ANDES_HW_DTB_ADDRESS 0xF2000000 +void *board_fdt_blob_setup(int *err) +{ + *err = 0; + + if (IS_ENABLED(CONFIG_OF_SEPARATE) || IS_ENABLED(CONFIG_OF_BOARD)) { + if (fdt_magic((uintptr_t)gd->arch.firmware_fdt_addr) == FDT_MAGIC) + return (void *)(ulong)gd->arch.firmware_fdt_addr; + } + + if (fdt_magic(CONFIG_SYS_FDT_BASE) == FDT_MAGIC) + return (void *)CONFIG_SYS_FDT_BASE; + return (void *)ANDES_HW_DTB_ADDRESS; + + *err = -EINVAL; + return NULL; +} + +#ifdef CONFIG_SPL_BOARD_INIT +void spl_board_init() +{ + /* enable andes-l2 cache */ + if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) + enable_caches(); +} +#endif + +int smc_init(void) +{ + int node = -1; + const char *compat = "andestech,atfsmc020"; + void *blob = (void *)gd->fdt_blob; + fdt_addr_t addr; + struct ftsmc020_bank *regs; + + node = fdt_node_offset_by_compatible(blob, -1, compat); + if (node < 0) + return -FDT_ERR_NOTFOUND; + + addr = fdtdec_get_addr_size_auto_noparent(blob, node, + "reg", 0, NULL, false); + + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + regs = (struct ftsmc020_bank *)(uintptr_t)addr; + regs->cr &= ~FTSMC020_BANK_WPROT; + + return 0; +} + +#ifdef CONFIG_BOARD_EARLY_INIT_F +int board_early_init_f(void) +{ + smc_init(); + + return 0; +} +#endif + +#ifdef CONFIG_SPL +void board_boot_order(u32 *spl_boot_list) +{ + u8 i; + u32 boot_devices[] = { +#ifdef CONFIG_SPL_RAM_SUPPORT + BOOT_DEVICE_RAM, +#endif +#ifdef CONFIG_SPL_MMC + BOOT_DEVICE_MMC1, +#endif + }; + + for (i = 0; i < ARRAY_SIZE(boot_devices); i++) + spl_boot_list[i] = boot_devices[i]; +} +#endif + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + /* boot using first FIT config */ + return 0; +} +#endif diff --git a/doc/board/AndesTech/adp-ag101p.rst b/doc/board/AndesTech/adp-ag101p.rst deleted file mode 100644 index f867eea..0000000 --- a/doc/board/AndesTech/adp-ag101p.rst +++ /dev/null @@ -1,40 +0,0 @@ -.. SPDX-License-Identifier: GPL-2.0+ - -ADP-AG101P -========== - -ADP-AG101P is the SoC with AG101 hardcore CPU. - -AG101P SoC ----------- - -AG101P is the mainline SoC produced by Andes Technology using N1213 CPU core -with FPU and DDR contoller support. -AG101P has integrated both AHB and APB bus and many periphals for application -and product development. - - -Configurations --------------- - -CONFIG_MEM_REMAP: - Doing memory remap is essential for preparing some non-OS or RTOS - applications. - -CONFIG_SKIP_LOWLEVEL_INIT: - If you want to boot this system from SPI ROM and bypass e-bios (the - other boot loader on ROM). You should enable CONFIG_SKIP_LOWLEVEL_INIT - when running menuconfig or similar. - -Build and boot steps --------------------- - -Build: - -1. Prepare the toolchains and make sure the $PATH to toolchains is correct. -2. Use `make adp-ag101p_defconfig` in u-boot root to build the image. - -Burn U-Boot to SPI ROM ----------------------- - -This section will be added later. diff --git a/doc/board/AndesTech/ae350.rst b/doc/board/AndesTech/ae350.rst deleted file mode 100644 index 99622fd..0000000 --- a/doc/board/AndesTech/ae350.rst +++ /dev/null @@ -1,524 +0,0 @@ -.. SPDX-License-Identifier: GPL-2.0+ - -AE350 -===== - -AE350 is the mainline SoC produced by Andes Technology using AndesV5 CPU core -based on RISC-V architecture. - -AE350 has integrated both AHB and APB bus and many periphals for application -and product development. - -AndesV5 is Andes CPU IP family that adopts RISC-V architecture. - -AndesV5 family includes 25, 27, 45 series. - -25-Series Features ------------------- - -CPU Core - - 5-stage in-order execution pipeline - - Hardware Multiplier - - radix-2/radix-4/radix-16/radix-256/fast - - Hardware Divider - - Optional branch prediction - - Machine mode and optional user mode - - Optional performance monitoring - -ISA - - RV64I base integer instructions - - RVC for 16-bit compressed instructions - - RVM for multiplication and division instructions - -Memory subsystem - - I & D local memory - - Size: 4KB to 16MB - - Memory subsyetem soft-error protection - - Protection scheme: parity-checking or error-checking-and-correction (ECC) - - Automatic hardware error correction - -Bus - - Interface Protocol - - Synchronous AHB (32-bit/64-bit data-width), or - - Synchronous AXI4 (64-bit data-width) - -Power management - - Wait for interrupt (WFI) mode - -Debug - - Configurable number of breakpoints: 2/4/8 - - External Debug Module - - AHB slave port - - External JTAG debug transport module - -Platform Level Interrupt Controller (PLIC) - - AHB slave port - - Configurable number of interrupts: 1-1023 - - Configurable number of interrupt priorities: 3/7/15/63/127/255 - - Configurable number of targets: 1-16 - - Preempted interrupt priority stack - -Build and boot steps --------------------- - -Build: - -1. Prepare the toolchains and make sure the $PATH to toolchains is correct. -2. Use `make ae350_rv[32|64]_defconfig` in u-boot root to build the image for - 32 or 64 bit. - -Verification: - -1. startup -2. relocation -3. timer driver -4. uart driver -5. mac driver -6. mmc driver -7. spi driver - -Steps ------ - -1. Ping a server by mac driver -2. Scan sd card and copy u-boot image which is booted from flash to ram by sd driver -3. Burn this u-boot image to spi rom by spi driver -4. Re-boot u-boot from spi flash with power off and power on - -Messages of U-Boot boot on AE350 board --------------------------------------- - -.. code-block:: none - - U-Boot 2018.01-rc2-00033-g824f89a (Dec 21 2017 - 16:51:26 +0800) - - DRAM: 1 GiB - MMC: mmc@f0e00000: 0 - SF: Detected mx25u1635e with page size 256 Bytes, erase size 4 KiB, total 2 MiB - In: serial@f0300000 - Out: serial@f0300000 - Err: serial@f0300000 - Net: - Warning: mac@e0100000 (eth0) using random MAC address - be:dd:d7:e4:e8:10 - eth0: mac@e0100000 - - RISC-V # version - U-Boot 2018.01-rc2-00033-gb265b91-dirty (Dec 22 2017 - 13:54:21 +0800) - - riscv32-unknown-linux-gnu-gcc (GCC) 7.2.0 - GNU ld (GNU Binutils) 2.29 - - RISC-V # setenv ipaddr 10.0.4.200 ; - RISC-V # setenv serverip 10.0.4.97 ; - RISC-V # ping 10.0.4.97 ; - Using mac@e0100000 device - host 10.0.4.97 is alive - - RISC-V # mmc rescan - RISC-V # fatls mmc 0:1 - 318907 u-boot-ae350-64.bin - 1252 hello_world_ae350_32.bin - 328787 u-boot-ae350-32.bin - - 3 file(s), 0 dir(s) - - RISC-V # sf probe 0:0 50000000 0 - SF: Detected mx25u1635e with page size 256 Bytes, erase size 4 KiB, total 2 MiB - - RISC-V # sf test 0x100000 0x1000 - SPI flash test: - 0 erase: 36 ticks, 111 KiB/s 0.888 Mbps - 1 check: 29 ticks, 137 KiB/s 1.096 Mbps - 2 write: 40 ticks, 100 KiB/s 0.800 Mbps - 3 read: 20 ticks, 200 KiB/s 1.600 Mbps - Test passed - 0 erase: 36 ticks, 111 KiB/s 0.888 Mbps - 1 check: 29 ticks, 137 KiB/s 1.096 Mbps - 2 write: 40 ticks, 100 KiB/s 0.800 Mbps - 3 read: 20 ticks, 200 KiB/s 1.600 Mbps - - RISC-V # fatload mmc 0:1 0x600000 u-boot-ae350-32.bin - reading u-boot-ae350-32.bin - 328787 bytes read in 324 ms (990.2 KiB/s) - - RISC-V # sf erase 0x0 0x51000 - SF: 331776 bytes @ 0x0 Erased: OK - - RISC-V # sf write 0x600000 0x0 0x50453 - device 0 offset 0x0, size 0x50453 - SF: 328787 bytes @ 0x0 Written: OK - - RISC-V # crc32 0x600000 0x50453 - crc32 for 00600000 ... 00650452 ==> 692dc44a - - RISC-V # crc32 0x80000000 0x50453 - crc32 for 80000000 ... 80050452 ==> 692dc44a - RISC-V # - - *** power-off and power-on, this U-Boot is booted from spi flash *** - - U-Boot 2018.01-rc2-00032-gf67dd47-dirty (Dec 21 2017 - 13:56:03 +0800) - - DRAM: 1 GiB - MMC: mmc@f0e00000: 0 - SF: Detected mx25u1635e with page size 256 Bytes, erase size 4 KiB, total 2 MiB - In: serial@f0300000 - Out: serial@f0300000 - Err: serial@f0300000 - Net: - Warning: mac@e0100000 (eth0) using random MAC address - ee:4c:58:29:32:f5 - eth0: mac@e0100000 - RISC-V # - - -Boot bbl and riscv-linux via U-Boot on QEMU -------------------------------------------- - -1. Build riscv-linux -2. Build bbl and riscv-linux with --with-payload -3. Prepare ae350.dtb -4. Creating OS-kernel images - -.. code-block:: none - - ./mkimage -A riscv -O linux -T kernel -C none -a 0x0000 -e 0x0000 -d bbl.bin bootmImage-bbl.bin - Image Name: - Created: Tue Mar 13 10:06:42 2018 - Image Type: RISC-V Linux Kernel Image (uncompressed) - Data Size: 17901204 Bytes = 17481.64 KiB = 17.07 MiB - Load Address: 00000000 - Entry Point: 00000000 - -5. Copy bootmImage-bbl.bin and ae350.dtb to qemu sd card image -6. Message of booting riscv-linux from bbl via u-boot on qemu - -.. code-block:: none - - U-Boot 2018.03-rc4-00031-g2631273 (Mar 13 2018 - 15:02:55 +0800) - - DRAM: 1 GiB - main-loop: WARNING: I/O thread spun for 1000 iterations - MMC: mmc@f0e00000: 0 - Loading Environment from SPI Flash... *** Warning - spi_flash_probe_bus_cs() failed, using default environment - - Failed (-22) - In: serial@f0300000 - Out: serial@f0300000 - Err: serial@f0300000 - Net: - Warning: mac@e0100000 (eth0) using random MAC address - 02:00:00:00:00:00 - eth0: mac@e0100000 - RISC-V # mmc rescan - RISC-V # mmc part - - Partition Map for MMC device 0 -- Partition Type: DOS - - Part Start Sector Num Sectors UUID Type - RISC-V # fatls mmc 0:0 - 17901268 bootmImage-bbl.bin - 1954 ae2xx.dtb - - 2 file(s), 0 dir(s) - - RISC-V # fatload mmc 0:0 0x00600000 bootmImage-bbl.bin - 17901268 bytes read in 4642 ms (3.7 MiB/s) - RISC-V # fatload mmc 0:0 0x2000000 ae350.dtb - 1954 bytes read in 1 ms (1.9 MiB/s) - RISC-V # setenv bootm_size 0x2000000 - RISC-V # setenv fdt_high 0x1f00000 - RISC-V # bootm 0x00600000 - 0x2000000 - ## Booting kernel from Legacy Image at 00600000 ... - Image Name: - Image Type: RISC-V Linux Kernel Image (uncompressed) - Data Size: 17901204 Bytes = 17.1 MiB - Load Address: 00000000 - Entry Point: 00000000 - Verifying Checksum ... OK - ## Flattened Device Tree blob at 02000000 - Booting using the fdt blob at 0x2000000 - Loading Kernel Image ... OK - Loading Device Tree to 0000000001efc000, end 0000000001eff7a1 ... OK - [ 0.000000] OF: fdt: Ignoring memory range 0x0 - 0x200000 - [ 0.000000] Linux version 4.14.0-00046-gf3e439f-dirty (rick@atcsqa06) (gcc version 7.1.1 20170509 (GCC)) #1 Tue Jan 9 16:34:25 CST 2018 - [ 0.000000] bootconsole [early0] enabled - [ 0.000000] Initial ramdisk at: 0xffffffe000016a98 (12267008 bytes) - [ 0.000000] Zone ranges: - [ 0.000000] DMA [mem 0x0000000000200000-0x000000007fffffff] - [ 0.000000] Normal empty - [ 0.000000] Movable zone start for each node - [ 0.000000] Early memory node ranges - [ 0.000000] node 0: [mem 0x0000000000200000-0x000000007fffffff] - [ 0.000000] Initmem setup node 0 [mem 0x0000000000200000-0x000000007fffffff] - [ 0.000000] elf_hwcap is 0x112d - [ 0.000000] random: fast init done - [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 516615 - [ 0.000000] Kernel command line: console=ttyS0,38400n8 earlyprintk=uart8250-32bit,0xf0300000 debug loglevel=7 - [ 0.000000] PID hash table entries: 4096 (order: 3, 32768 bytes) - [ 0.000000] Dentry cache hash table entries: 262144 (order: 9, 2097152 bytes) - [ 0.000000] Inode-cache hash table entries: 131072 (order: 8, 1048576 bytes) - [ 0.000000] Sorting __ex_table... - [ 0.000000] Memory: 2047832K/2095104K available (1856K kernel code, 204K rwdata, 532K rodata, 12076K init, 756K bss, 47272K reserved, 0K cma-reserved) - [ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1 - [ 0.000000] NR_IRQS: 0, nr_irqs: 0, preallocated irqs: 0 - [ 0.000000] riscv,cpu_intc,0: 64 local interrupts mapped - [ 0.000000] riscv,plic0,e4000000: mapped 31 interrupts to 1/2 handlers - [ 0.000000] clocksource: riscv_clocksource: mask: 0xffffffffffffffff max_cycles: 0x24e6a1710, max_idle_ns: 440795202120 ns - [ 0.000000] Calibrating delay loop (skipped), value calculated using timer frequency.. 20.00 BogoMIPS (lpj=40000) - [ 0.000000] pid_max: default: 32768 minimum: 301 - [ 0.004000] Mount-cache hash table entries: 4096 (order: 3, 32768 bytes) - [ 0.004000] Mountpoint-cache hash table entries: 4096 (order: 3, 32768 bytes) - [ 0.056000] devtmpfs: initialized - [ 0.060000] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns - [ 0.064000] futex hash table entries: 256 (order: 0, 6144 bytes) - [ 0.068000] NET: Registered protocol family 16 - [ 0.080000] vgaarb: loaded - [ 0.084000] clocksource: Switched to clocksource riscv_clocksource - [ 0.088000] NET: Registered protocol family 2 - [ 0.092000] TCP established hash table entries: 16384 (order: 5, 131072 bytes) - [ 0.096000] TCP bind hash table entries: 16384 (order: 5, 131072 bytes) - [ 0.096000] TCP: Hash tables configured (established 16384 bind 16384) - [ 0.100000] UDP hash table entries: 1024 (order: 3, 32768 bytes) - [ 0.100000] UDP-Lite hash table entries: 1024 (order: 3, 32768 bytes) - [ 0.104000] NET: Registered protocol family 1 - [ 0.616000] Unpacking initramfs... - [ 1.220000] workingset: timestamp_bits=62 max_order=19 bucket_order=0 - [ 1.244000] io scheduler noop registered - [ 1.244000] io scheduler cfq registered (default) - [ 1.244000] io scheduler mq-deadline registered - [ 1.248000] io scheduler kyber registered - [ 1.360000] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled - [ 1.368000] console [ttyS0] disabled - [ 1.372000] f0300000.serial: ttyS0 at MMIO 0xf0300020 (irq = 10, base_baud = 1228800) is a 16550A - [ 1.392000] console [ttyS0] enabled - [ 1.392000] ftmac100: Loading version 0.2 ... - [ 1.396000] ftmac100 e0100000.mac eth0: irq 8, mapped at ffffffd002005000 - [ 1.400000] ftmac100 e0100000.mac eth0: generated random MAC address 6e:ac:c3:92:36:c0 - [ 1.404000] IR NEC protocol handler initialized - [ 1.404000] IR RC5(x/sz) protocol handler initialized - [ 1.404000] IR RC6 protocol handler initialized - [ 1.404000] IR JVC protocol handler initialized - [ 1.408000] IR Sony protocol handler initialized - [ 1.408000] IR SANYO protocol handler initialized - [ 1.408000] IR Sharp protocol handler initialized - [ 1.408000] IR MCE Keyboard/mouse protocol handler initialized - [ 1.412000] IR XMP protocol handler initialized - [ 1.456000] ftsdc010 f0e00000.mmc: mmc0 - using hw SDIO IRQ - [ 1.464000] bootconsole [early0] uses init memory and must be disabled even before the real one is ready - [ 1.464000] bootconsole [early0] disabled - [ 1.508000] Freeing unused kernel memory: 12076K - [ 1.512000] This architecture does not have kernel memory protection. - [ 1.520000] mmc0: new SD card at address 4567 - [ 1.524000] mmcblk0: mmc0:4567 QEMU! 20.0 MiB - [ 1.844000] mmcblk0: - Wed Dec 1 10:00:00 CST 2010 - / # - - -Running U-Boot SPL ------------------- -The U-Boot SPL will boot in M mode and load the FIT image which include -OpenSBI and U-Boot proper images. After loading progress, it will jump -to OpenSBI first and then U-Boot proper which will run in S mode. - - -How to build U-Boot SPL ------------------------ -Before building U-Boot SPL, OpenSBI must be build first. OpenSBI can be -cloned and build for AE350 as below: - -.. code-block:: none - - git clone https://github.com/riscv/opensbi.git - cd opensbi - make PLATFORM=andes/ae350 - -Copy OpenSBI FW_DYNAMIC image (build/platform/andes/ae350/firmware/fw_dynamic.bin) -into U-Boot root directory - - -How to build U-Boot SPL booting from RAM ----------------------------------------- -With ae350_rv[32|64]_spl_defconfigs: - -U-Boot SPL will be loaded by gdb or FSBL and runs in RAM in machine mode -and then load FIT image from RAM device on AE350. - - -How to build U-Boot SPL booting from ROM ----------------------------------------- -With ae350_rv[32|64]_spl_xip_defconfigs: - -U-Boot SPL can be burned into SPI flash and run in flash in machine mode -and then load FIT image from SPI flash or MMC device on AE350. - - -Messages of U-Boot SPL boots Kernel on AE350 board --------------------------------------------------- - -.. code-block:: none - - U-Boot SPL 2020.01-rc1-00292-g67a3313-dirty (Nov 14 2019 - 11:26:21 +0800) - Trying to boot from RAM - - OpenSBI v0.5-1-gdd8ef28 (Nov 14 2019 11:08:39) - ____ _____ ____ _____ - / __ \ / ____| _ \_ _| - | | | |_ __ ___ _ __ | (___ | |_) || | - | | | | '_ \ / _ \ '_ \ \___ \| _ < | | - | |__| | |_) | __/ | | |____) | |_) || |_ - \____/| .__/ \___|_| |_|_____/|____/_____| - | | - |_| - - Platform Name : Andes AE350 - Platform HART Features : RV64ACIMSUX - Platform Max HARTs : 4 - Current Hart : 0 - Firmware Base : 0x0 - Firmware Size : 84 KB - Runtime SBI Version : 0.2 - - PMP0: 0x0000000000000000-0x000000000001ffff (A) - PMP1: 0x0000000000000000-0x00000001ffffffff (A,R,W,X) - - - U-Boot 2020.01-rc1-00292-g67a3313-dirty (Nov 14 2019 - 11:26:21 +0800) - - DRAM: 1 GiB - Flash: 64 MiB - MMC: mmc@f0e00000: 0 - Loading Environment from SPI Flash... SF: Detected mx25u1635e with page size 256 Bytes, erase size 4 KiB, total 2 MiB - OK - In: serial@f0300000 - Out: serial@f0300000 - Err: serial@f0300000 - Net: no alias for ethernet0 - - Warning: mac@e0100000 (eth0) using random MAC address - a2:ae:93:7b:cc:8f - eth0: mac@e0100000 - Hit any key to stop autoboot: 0 - 6455 bytes read in 31 ms (203.1 KiB/s) - 20421684 bytes read in 8647 ms (2.3 MiB/s) - ## Booting kernel from Legacy Image at 00600000 ... - Image Name: - Image Type: RISC-V Linux Kernel Image (uncompressed) - Data Size: 20421620 Bytes = 19.5 MiB - Load Address: 00200000 - Entry Point: 00200000 - Verifying Checksum ... OK - ## Flattened Device Tree blob at 20000000 - Booting using the fdt blob at 0x20000000 - Loading Kernel Image - Loading Device Tree to 000000001effb000, end 000000001efff936 ... OK - - Starting kernel ... - - OF: fdt: Ignoring memory range 0x0 - 0x200000 - Linux version 4.17.0-00253-g49136e10bcb2 (sqa@atcsqa07) (gcc version 7.3.0 (2019-04-06_nds64le-linux-glibc-v5_experimental)) #1 SMP PREEMPT Sat Apr 6 23:41:49 CST 2019 - bootconsole [early0] enabled - Initial ramdisk at: 0x (ptrval) (13665712 bytes) - Zone ranges: - DMA32 [mem 0x0000000000200000-0x000000003fffffff] - Normal empty - Movable zone start for each node - Early memory node ranges - node 0: [mem 0x0000000000200000-0x000000003fffffff] - Initmem setup node 0 [mem 0x0000000000200000-0x000000003fffffff] - software IO TLB [mem 0x3b1f8000-0x3f1f8000] (64MB) mapped at [ (ptrval)- (ptrval)] - elf_platform is rv64i2p0m2p0a2p0c2p0xv5-0p0 - compatible privileged spec version 1.10 - percpu: Embedded 16 pages/cpu @ (ptrval) s28184 r8192 d29160 u65536 - Built 1 zonelists, mobility grouping on. Total pages: 258055 - Kernel command line: console=ttyS0,38400n8 debug loglevel=7 - log_buf_len individual max cpu contribution: 4096 bytes - log_buf_len total cpu_extra contributions: 12288 bytes - log_buf_len min size: 16384 bytes - log_buf_len: 32768 bytes - early log buf free: 14608(89%) - Dentry cache hash table entries: 131072 (order: 8, 1048576 bytes) - Inode-cache hash table entries: 65536 (order: 7, 524288 bytes) - Sorting __ex_table... - Memory: 944428K/1046528K available (3979K kernel code, 246K rwdata, 1490K rodata, 13523K init, 688K bss, 102100K reserved, 0K cma-reserved) - SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1 - Preemptible hierarchical RCU implementation. - Tasks RCU enabled. - NR_IRQS: 72, nr_irqs: 72, preallocated irqs: 0 - riscv,cpu_intc,0: 64 local interrupts mapped - riscv,cpu_intc,1: 64 local interrupts mapped - riscv,cpu_intc,2: 64 local interrupts mapped - riscv,cpu_intc,3: 64 local interrupts mapped - riscv,plic0,e4000000: mapped 71 interrupts to 8/8 handlers - clocksource: riscv_clocksource: mask: 0xffffffffffffffff max_cycles: 0x1bacf917bf, max_idle_ns: 881590412290 ns - sched_clock: 64 bits at 60MHz, resolution 16ns, wraps every 4398046511098ns - Console: colour dummy device 40x30 - Calibrating delay loop (skipped), value calculated using timer frequency.. 120.00 BogoMIPS (lpj=600000) - pid_max: default: 32768 minimum: 301 - Mount-cache hash table entries: 2048 (order: 2, 16384 bytes) - Mountpoint-cache hash table entries: 2048 (order: 2, 16384 bytes) - Hierarchical SRCU implementation. - smp: Bringing up secondary CPUs ... - CPU0: online - CPU2: online - CPU3: online - smp: Brought up 1 node, 4 CPUs - devtmpfs: initialized - random: get_random_u32 called from bucket_table_alloc+0x198/0x1d8 with crng_init=0 - clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns - futex hash table entries: 1024 (order: 4, 65536 bytes) - NET: Registered protocol family 16 - Advanced Linux Sound Architecture Driver Initialized. - clocksource: Switched to clocksource riscv_clocksource - NET: Registered protocol family 2 - tcp_listen_portaddr_hash hash table entries: 512 (order: 1, 8192 bytes) - TCP established hash table entries: 8192 (order: 4, 65536 bytes) - TCP bind hash table entries: 8192 (order: 5, 131072 bytes) - TCP: Hash tables configured (established 8192 bind 8192) - UDP hash table entries: 512 (order: 2, 16384 bytes) - UDP-Lite hash table entries: 512 (order: 2, 16384 bytes) - NET: Registered protocol family 1 - RPC: Registered named UNIX socket transport module. - RPC: Registered udp transport module. - RPC: Registered tcp transport module. - RPC: Registered tcp NFSv4.1 backchannel transport module. - Unpacking initramfs... - workingset: timestamp_bits=62 max_order=18 bucket_order=0 - NFS: Registering the id_resolver key type - Key type id_resolver registered - Key type id_legacy registered - nfs4filelayout_init: NFSv4 File Layout Driver Registering... - io scheduler noop registered - io scheduler cfq registered (default) - io scheduler mq-deadline registered - io scheduler kyber registered - Console: switching to colour frame buffer device 40x30 - Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled - console [ttyS0] disabled - f0300000.serial: ttyS0 at MMIO 0xf0300020 (irq = 20, base_baud = 1228800) is a 16550A - console [ttyS0] enabled - console [ttyS0] enabled - bootconsole [early0] disabled - bootconsole [early0] disabled - loop: module loaded - tun: Universal TUN/TAP device driver, 1.6 - ftmac100: Loading version 0.2 ... - ftmac100 e0100000.mac eth0: irq 21, mapped at (ptrval) - ftmac100 e0100000.mac eth0: generated random MAC address 4e:fd:bd:f3:04:fc - ftsdc010 f0e00000.mmc: mmc0 - using hw SDIO IRQ - mmc0: new SDHC card at address d555 - ftssp010 card registered! - mmcblk0: mmc0:d555 SD04G 3.79 GiB - NET: Registered protocol family 10 - mmcblk0: p1 - Segment Routing with IPv6 - sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver - NET: Registered protocol family 17 - NET: Registered protocol family 15 - ALSA device list: - #0: ftssp_ac97 controller - Freeing unused kernel memory: 13520K - This architecture does not have kernel memory protection. - Sysinit starting - Sat Apr 6 23:33:53 CST 2019 - nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering... - - ~ # diff --git a/doc/board/AndesTech/index.rst b/doc/board/AndesTech/index.rst deleted file mode 100644 index cacc579..0000000 --- a/doc/board/AndesTech/index.rst +++ /dev/null @@ -1,10 +0,0 @@ -.. SPDX-License-Identifier: GPL-2.0+ - -Andes Tech -========== - -.. toctree:: - :maxdepth: 2 - - adp-ag101p - ae350 diff --git a/doc/board/andestech/adp-ag101p.rst b/doc/board/andestech/adp-ag101p.rst new file mode 100644 index 0000000..f867eea --- /dev/null +++ b/doc/board/andestech/adp-ag101p.rst @@ -0,0 +1,40 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +ADP-AG101P +========== + +ADP-AG101P is the SoC with AG101 hardcore CPU. + +AG101P SoC +---------- + +AG101P is the mainline SoC produced by Andes Technology using N1213 CPU core +with FPU and DDR contoller support. +AG101P has integrated both AHB and APB bus and many periphals for application +and product development. + + +Configurations +-------------- + +CONFIG_MEM_REMAP: + Doing memory remap is essential for preparing some non-OS or RTOS + applications. + +CONFIG_SKIP_LOWLEVEL_INIT: + If you want to boot this system from SPI ROM and bypass e-bios (the + other boot loader on ROM). You should enable CONFIG_SKIP_LOWLEVEL_INIT + when running menuconfig or similar. + +Build and boot steps +-------------------- + +Build: + +1. Prepare the toolchains and make sure the $PATH to toolchains is correct. +2. Use `make adp-ag101p_defconfig` in u-boot root to build the image. + +Burn U-Boot to SPI ROM +---------------------- + +This section will be added later. diff --git a/doc/board/andestech/ae350.rst b/doc/board/andestech/ae350.rst new file mode 100644 index 0000000..99622fd --- /dev/null +++ b/doc/board/andestech/ae350.rst @@ -0,0 +1,524 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +AE350 +===== + +AE350 is the mainline SoC produced by Andes Technology using AndesV5 CPU core +based on RISC-V architecture. + +AE350 has integrated both AHB and APB bus and many periphals for application +and product development. + +AndesV5 is Andes CPU IP family that adopts RISC-V architecture. + +AndesV5 family includes 25, 27, 45 series. + +25-Series Features +------------------ + +CPU Core + - 5-stage in-order execution pipeline + - Hardware Multiplier + - radix-2/radix-4/radix-16/radix-256/fast + - Hardware Divider + - Optional branch prediction + - Machine mode and optional user mode + - Optional performance monitoring + +ISA + - RV64I base integer instructions + - RVC for 16-bit compressed instructions + - RVM for multiplication and division instructions + +Memory subsystem + - I & D local memory + - Size: 4KB to 16MB + - Memory subsyetem soft-error protection + - Protection scheme: parity-checking or error-checking-and-correction (ECC) + - Automatic hardware error correction + +Bus + - Interface Protocol + - Synchronous AHB (32-bit/64-bit data-width), or + - Synchronous AXI4 (64-bit data-width) + +Power management + - Wait for interrupt (WFI) mode + +Debug + - Configurable number of breakpoints: 2/4/8 + - External Debug Module + - AHB slave port + - External JTAG debug transport module + +Platform Level Interrupt Controller (PLIC) + - AHB slave port + - Configurable number of interrupts: 1-1023 + - Configurable number of interrupt priorities: 3/7/15/63/127/255 + - Configurable number of targets: 1-16 + - Preempted interrupt priority stack + +Build and boot steps +-------------------- + +Build: + +1. Prepare the toolchains and make sure the $PATH to toolchains is correct. +2. Use `make ae350_rv[32|64]_defconfig` in u-boot root to build the image for + 32 or 64 bit. + +Verification: + +1. startup +2. relocation +3. timer driver +4. uart driver +5. mac driver +6. mmc driver +7. spi driver + +Steps +----- + +1. Ping a server by mac driver +2. Scan sd card and copy u-boot image which is booted from flash to ram by sd driver +3. Burn this u-boot image to spi rom by spi driver +4. Re-boot u-boot from spi flash with power off and power on + +Messages of U-Boot boot on AE350 board +-------------------------------------- + +.. code-block:: none + + U-Boot 2018.01-rc2-00033-g824f89a (Dec 21 2017 - 16:51:26 +0800) + + DRAM: 1 GiB + MMC: mmc@f0e00000: 0 + SF: Detected mx25u1635e with page size 256 Bytes, erase size 4 KiB, total 2 MiB + In: serial@f0300000 + Out: serial@f0300000 + Err: serial@f0300000 + Net: + Warning: mac@e0100000 (eth0) using random MAC address - be:dd:d7:e4:e8:10 + eth0: mac@e0100000 + + RISC-V # version + U-Boot 2018.01-rc2-00033-gb265b91-dirty (Dec 22 2017 - 13:54:21 +0800) + + riscv32-unknown-linux-gnu-gcc (GCC) 7.2.0 + GNU ld (GNU Binutils) 2.29 + + RISC-V # setenv ipaddr 10.0.4.200 ; + RISC-V # setenv serverip 10.0.4.97 ; + RISC-V # ping 10.0.4.97 ; + Using mac@e0100000 device + host 10.0.4.97 is alive + + RISC-V # mmc rescan + RISC-V # fatls mmc 0:1 + 318907 u-boot-ae350-64.bin + 1252 hello_world_ae350_32.bin + 328787 u-boot-ae350-32.bin + + 3 file(s), 0 dir(s) + + RISC-V # sf probe 0:0 50000000 0 + SF: Detected mx25u1635e with page size 256 Bytes, erase size 4 KiB, total 2 MiB + + RISC-V # sf test 0x100000 0x1000 + SPI flash test: + 0 erase: 36 ticks, 111 KiB/s 0.888 Mbps + 1 check: 29 ticks, 137 KiB/s 1.096 Mbps + 2 write: 40 ticks, 100 KiB/s 0.800 Mbps + 3 read: 20 ticks, 200 KiB/s 1.600 Mbps + Test passed + 0 erase: 36 ticks, 111 KiB/s 0.888 Mbps + 1 check: 29 ticks, 137 KiB/s 1.096 Mbps + 2 write: 40 ticks, 100 KiB/s 0.800 Mbps + 3 read: 20 ticks, 200 KiB/s 1.600 Mbps + + RISC-V # fatload mmc 0:1 0x600000 u-boot-ae350-32.bin + reading u-boot-ae350-32.bin + 328787 bytes read in 324 ms (990.2 KiB/s) + + RISC-V # sf erase 0x0 0x51000 + SF: 331776 bytes @ 0x0 Erased: OK + + RISC-V # sf write 0x600000 0x0 0x50453 + device 0 offset 0x0, size 0x50453 + SF: 328787 bytes @ 0x0 Written: OK + + RISC-V # crc32 0x600000 0x50453 + crc32 for 00600000 ... 00650452 ==> 692dc44a + + RISC-V # crc32 0x80000000 0x50453 + crc32 for 80000000 ... 80050452 ==> 692dc44a + RISC-V # + + *** power-off and power-on, this U-Boot is booted from spi flash *** + + U-Boot 2018.01-rc2-00032-gf67dd47-dirty (Dec 21 2017 - 13:56:03 +0800) + + DRAM: 1 GiB + MMC: mmc@f0e00000: 0 + SF: Detected mx25u1635e with page size 256 Bytes, erase size 4 KiB, total 2 MiB + In: serial@f0300000 + Out: serial@f0300000 + Err: serial@f0300000 + Net: + Warning: mac@e0100000 (eth0) using random MAC address - ee:4c:58:29:32:f5 + eth0: mac@e0100000 + RISC-V # + + +Boot bbl and riscv-linux via U-Boot on QEMU +------------------------------------------- + +1. Build riscv-linux +2. Build bbl and riscv-linux with --with-payload +3. Prepare ae350.dtb +4. Creating OS-kernel images + +.. code-block:: none + + ./mkimage -A riscv -O linux -T kernel -C none -a 0x0000 -e 0x0000 -d bbl.bin bootmImage-bbl.bin + Image Name: + Created: Tue Mar 13 10:06:42 2018 + Image Type: RISC-V Linux Kernel Image (uncompressed) + Data Size: 17901204 Bytes = 17481.64 KiB = 17.07 MiB + Load Address: 00000000 + Entry Point: 00000000 + +5. Copy bootmImage-bbl.bin and ae350.dtb to qemu sd card image +6. Message of booting riscv-linux from bbl via u-boot on qemu + +.. code-block:: none + + U-Boot 2018.03-rc4-00031-g2631273 (Mar 13 2018 - 15:02:55 +0800) + + DRAM: 1 GiB + main-loop: WARNING: I/O thread spun for 1000 iterations + MMC: mmc@f0e00000: 0 + Loading Environment from SPI Flash... *** Warning - spi_flash_probe_bus_cs() failed, using default environment + + Failed (-22) + In: serial@f0300000 + Out: serial@f0300000 + Err: serial@f0300000 + Net: + Warning: mac@e0100000 (eth0) using random MAC address - 02:00:00:00:00:00 + eth0: mac@e0100000 + RISC-V # mmc rescan + RISC-V # mmc part + + Partition Map for MMC device 0 -- Partition Type: DOS + + Part Start Sector Num Sectors UUID Type + RISC-V # fatls mmc 0:0 + 17901268 bootmImage-bbl.bin + 1954 ae2xx.dtb + + 2 file(s), 0 dir(s) + + RISC-V # fatload mmc 0:0 0x00600000 bootmImage-bbl.bin + 17901268 bytes read in 4642 ms (3.7 MiB/s) + RISC-V # fatload mmc 0:0 0x2000000 ae350.dtb + 1954 bytes read in 1 ms (1.9 MiB/s) + RISC-V # setenv bootm_size 0x2000000 + RISC-V # setenv fdt_high 0x1f00000 + RISC-V # bootm 0x00600000 - 0x2000000 + ## Booting kernel from Legacy Image at 00600000 ... + Image Name: + Image Type: RISC-V Linux Kernel Image (uncompressed) + Data Size: 17901204 Bytes = 17.1 MiB + Load Address: 00000000 + Entry Point: 00000000 + Verifying Checksum ... OK + ## Flattened Device Tree blob at 02000000 + Booting using the fdt blob at 0x2000000 + Loading Kernel Image ... OK + Loading Device Tree to 0000000001efc000, end 0000000001eff7a1 ... OK + [ 0.000000] OF: fdt: Ignoring memory range 0x0 - 0x200000 + [ 0.000000] Linux version 4.14.0-00046-gf3e439f-dirty (rick@atcsqa06) (gcc version 7.1.1 20170509 (GCC)) #1 Tue Jan 9 16:34:25 CST 2018 + [ 0.000000] bootconsole [early0] enabled + [ 0.000000] Initial ramdisk at: 0xffffffe000016a98 (12267008 bytes) + [ 0.000000] Zone ranges: + [ 0.000000] DMA [mem 0x0000000000200000-0x000000007fffffff] + [ 0.000000] Normal empty + [ 0.000000] Movable zone start for each node + [ 0.000000] Early memory node ranges + [ 0.000000] node 0: [mem 0x0000000000200000-0x000000007fffffff] + [ 0.000000] Initmem setup node 0 [mem 0x0000000000200000-0x000000007fffffff] + [ 0.000000] elf_hwcap is 0x112d + [ 0.000000] random: fast init done + [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 516615 + [ 0.000000] Kernel command line: console=ttyS0,38400n8 earlyprintk=uart8250-32bit,0xf0300000 debug loglevel=7 + [ 0.000000] PID hash table entries: 4096 (order: 3, 32768 bytes) + [ 0.000000] Dentry cache hash table entries: 262144 (order: 9, 2097152 bytes) + [ 0.000000] Inode-cache hash table entries: 131072 (order: 8, 1048576 bytes) + [ 0.000000] Sorting __ex_table... + [ 0.000000] Memory: 2047832K/2095104K available (1856K kernel code, 204K rwdata, 532K rodata, 12076K init, 756K bss, 47272K reserved, 0K cma-reserved) + [ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1 + [ 0.000000] NR_IRQS: 0, nr_irqs: 0, preallocated irqs: 0 + [ 0.000000] riscv,cpu_intc,0: 64 local interrupts mapped + [ 0.000000] riscv,plic0,e4000000: mapped 31 interrupts to 1/2 handlers + [ 0.000000] clocksource: riscv_clocksource: mask: 0xffffffffffffffff max_cycles: 0x24e6a1710, max_idle_ns: 440795202120 ns + [ 0.000000] Calibrating delay loop (skipped), value calculated using timer frequency.. 20.00 BogoMIPS (lpj=40000) + [ 0.000000] pid_max: default: 32768 minimum: 301 + [ 0.004000] Mount-cache hash table entries: 4096 (order: 3, 32768 bytes) + [ 0.004000] Mountpoint-cache hash table entries: 4096 (order: 3, 32768 bytes) + [ 0.056000] devtmpfs: initialized + [ 0.060000] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns + [ 0.064000] futex hash table entries: 256 (order: 0, 6144 bytes) + [ 0.068000] NET: Registered protocol family 16 + [ 0.080000] vgaarb: loaded + [ 0.084000] clocksource: Switched to clocksource riscv_clocksource + [ 0.088000] NET: Registered protocol family 2 + [ 0.092000] TCP established hash table entries: 16384 (order: 5, 131072 bytes) + [ 0.096000] TCP bind hash table entries: 16384 (order: 5, 131072 bytes) + [ 0.096000] TCP: Hash tables configured (established 16384 bind 16384) + [ 0.100000] UDP hash table entries: 1024 (order: 3, 32768 bytes) + [ 0.100000] UDP-Lite hash table entries: 1024 (order: 3, 32768 bytes) + [ 0.104000] NET: Registered protocol family 1 + [ 0.616000] Unpacking initramfs... + [ 1.220000] workingset: timestamp_bits=62 max_order=19 bucket_order=0 + [ 1.244000] io scheduler noop registered + [ 1.244000] io scheduler cfq registered (default) + [ 1.244000] io scheduler mq-deadline registered + [ 1.248000] io scheduler kyber registered + [ 1.360000] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled + [ 1.368000] console [ttyS0] disabled + [ 1.372000] f0300000.serial: ttyS0 at MMIO 0xf0300020 (irq = 10, base_baud = 1228800) is a 16550A + [ 1.392000] console [ttyS0] enabled + [ 1.392000] ftmac100: Loading version 0.2 ... + [ 1.396000] ftmac100 e0100000.mac eth0: irq 8, mapped at ffffffd002005000 + [ 1.400000] ftmac100 e0100000.mac eth0: generated random MAC address 6e:ac:c3:92:36:c0 + [ 1.404000] IR NEC protocol handler initialized + [ 1.404000] IR RC5(x/sz) protocol handler initialized + [ 1.404000] IR RC6 protocol handler initialized + [ 1.404000] IR JVC protocol handler initialized + [ 1.408000] IR Sony protocol handler initialized + [ 1.408000] IR SANYO protocol handler initialized + [ 1.408000] IR Sharp protocol handler initialized + [ 1.408000] IR MCE Keyboard/mouse protocol handler initialized + [ 1.412000] IR XMP protocol handler initialized + [ 1.456000] ftsdc010 f0e00000.mmc: mmc0 - using hw SDIO IRQ + [ 1.464000] bootconsole [early0] uses init memory and must be disabled even before the real one is ready + [ 1.464000] bootconsole [early0] disabled + [ 1.508000] Freeing unused kernel memory: 12076K + [ 1.512000] This architecture does not have kernel memory protection. + [ 1.520000] mmc0: new SD card at address 4567 + [ 1.524000] mmcblk0: mmc0:4567 QEMU! 20.0 MiB + [ 1.844000] mmcblk0: + Wed Dec 1 10:00:00 CST 2010 + / # + + +Running U-Boot SPL +------------------ +The U-Boot SPL will boot in M mode and load the FIT image which include +OpenSBI and U-Boot proper images. After loading progress, it will jump +to OpenSBI first and then U-Boot proper which will run in S mode. + + +How to build U-Boot SPL +----------------------- +Before building U-Boot SPL, OpenSBI must be build first. OpenSBI can be +cloned and build for AE350 as below: + +.. code-block:: none + + git clone https://github.com/riscv/opensbi.git + cd opensbi + make PLATFORM=andes/ae350 + +Copy OpenSBI FW_DYNAMIC image (build/platform/andes/ae350/firmware/fw_dynamic.bin) +into U-Boot root directory + + +How to build U-Boot SPL booting from RAM +---------------------------------------- +With ae350_rv[32|64]_spl_defconfigs: + +U-Boot SPL will be loaded by gdb or FSBL and runs in RAM in machine mode +and then load FIT image from RAM device on AE350. + + +How to build U-Boot SPL booting from ROM +---------------------------------------- +With ae350_rv[32|64]_spl_xip_defconfigs: + +U-Boot SPL can be burned into SPI flash and run in flash in machine mode +and then load FIT image from SPI flash or MMC device on AE350. + + +Messages of U-Boot SPL boots Kernel on AE350 board +-------------------------------------------------- + +.. code-block:: none + + U-Boot SPL 2020.01-rc1-00292-g67a3313-dirty (Nov 14 2019 - 11:26:21 +0800) + Trying to boot from RAM + + OpenSBI v0.5-1-gdd8ef28 (Nov 14 2019 11:08:39) + ____ _____ ____ _____ + / __ \ / ____| _ \_ _| + | | | |_ __ ___ _ __ | (___ | |_) || | + | | | | '_ \ / _ \ '_ \ \___ \| _ < | | + | |__| | |_) | __/ | | |____) | |_) || |_ + \____/| .__/ \___|_| |_|_____/|____/_____| + | | + |_| + + Platform Name : Andes AE350 + Platform HART Features : RV64ACIMSUX + Platform Max HARTs : 4 + Current Hart : 0 + Firmware Base : 0x0 + Firmware Size : 84 KB + Runtime SBI Version : 0.2 + + PMP0: 0x0000000000000000-0x000000000001ffff (A) + PMP1: 0x0000000000000000-0x00000001ffffffff (A,R,W,X) + + + U-Boot 2020.01-rc1-00292-g67a3313-dirty (Nov 14 2019 - 11:26:21 +0800) + + DRAM: 1 GiB + Flash: 64 MiB + MMC: mmc@f0e00000: 0 + Loading Environment from SPI Flash... SF: Detected mx25u1635e with page size 256 Bytes, erase size 4 KiB, total 2 MiB + OK + In: serial@f0300000 + Out: serial@f0300000 + Err: serial@f0300000 + Net: no alias for ethernet0 + + Warning: mac@e0100000 (eth0) using random MAC address - a2:ae:93:7b:cc:8f + eth0: mac@e0100000 + Hit any key to stop autoboot: 0 + 6455 bytes read in 31 ms (203.1 KiB/s) + 20421684 bytes read in 8647 ms (2.3 MiB/s) + ## Booting kernel from Legacy Image at 00600000 ... + Image Name: + Image Type: RISC-V Linux Kernel Image (uncompressed) + Data Size: 20421620 Bytes = 19.5 MiB + Load Address: 00200000 + Entry Point: 00200000 + Verifying Checksum ... OK + ## Flattened Device Tree blob at 20000000 + Booting using the fdt blob at 0x20000000 + Loading Kernel Image + Loading Device Tree to 000000001effb000, end 000000001efff936 ... OK + + Starting kernel ... + + OF: fdt: Ignoring memory range 0x0 - 0x200000 + Linux version 4.17.0-00253-g49136e10bcb2 (sqa@atcsqa07) (gcc version 7.3.0 (2019-04-06_nds64le-linux-glibc-v5_experimental)) #1 SMP PREEMPT Sat Apr 6 23:41:49 CST 2019 + bootconsole [early0] enabled + Initial ramdisk at: 0x (ptrval) (13665712 bytes) + Zone ranges: + DMA32 [mem 0x0000000000200000-0x000000003fffffff] + Normal empty + Movable zone start for each node + Early memory node ranges + node 0: [mem 0x0000000000200000-0x000000003fffffff] + Initmem setup node 0 [mem 0x0000000000200000-0x000000003fffffff] + software IO TLB [mem 0x3b1f8000-0x3f1f8000] (64MB) mapped at [ (ptrval)- (ptrval)] + elf_platform is rv64i2p0m2p0a2p0c2p0xv5-0p0 + compatible privileged spec version 1.10 + percpu: Embedded 16 pages/cpu @ (ptrval) s28184 r8192 d29160 u65536 + Built 1 zonelists, mobility grouping on. Total pages: 258055 + Kernel command line: console=ttyS0,38400n8 debug loglevel=7 + log_buf_len individual max cpu contribution: 4096 bytes + log_buf_len total cpu_extra contributions: 12288 bytes + log_buf_len min size: 16384 bytes + log_buf_len: 32768 bytes + early log buf free: 14608(89%) + Dentry cache hash table entries: 131072 (order: 8, 1048576 bytes) + Inode-cache hash table entries: 65536 (order: 7, 524288 bytes) + Sorting __ex_table... + Memory: 944428K/1046528K available (3979K kernel code, 246K rwdata, 1490K rodata, 13523K init, 688K bss, 102100K reserved, 0K cma-reserved) + SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1 + Preemptible hierarchical RCU implementation. + Tasks RCU enabled. + NR_IRQS: 72, nr_irqs: 72, preallocated irqs: 0 + riscv,cpu_intc,0: 64 local interrupts mapped + riscv,cpu_intc,1: 64 local interrupts mapped + riscv,cpu_intc,2: 64 local interrupts mapped + riscv,cpu_intc,3: 64 local interrupts mapped + riscv,plic0,e4000000: mapped 71 interrupts to 8/8 handlers + clocksource: riscv_clocksource: mask: 0xffffffffffffffff max_cycles: 0x1bacf917bf, max_idle_ns: 881590412290 ns + sched_clock: 64 bits at 60MHz, resolution 16ns, wraps every 4398046511098ns + Console: colour dummy device 40x30 + Calibrating delay loop (skipped), value calculated using timer frequency.. 120.00 BogoMIPS (lpj=600000) + pid_max: default: 32768 minimum: 301 + Mount-cache hash table entries: 2048 (order: 2, 16384 bytes) + Mountpoint-cache hash table entries: 2048 (order: 2, 16384 bytes) + Hierarchical SRCU implementation. + smp: Bringing up secondary CPUs ... + CPU0: online + CPU2: online + CPU3: online + smp: Brought up 1 node, 4 CPUs + devtmpfs: initialized + random: get_random_u32 called from bucket_table_alloc+0x198/0x1d8 with crng_init=0 + clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns + futex hash table entries: 1024 (order: 4, 65536 bytes) + NET: Registered protocol family 16 + Advanced Linux Sound Architecture Driver Initialized. + clocksource: Switched to clocksource riscv_clocksource + NET: Registered protocol family 2 + tcp_listen_portaddr_hash hash table entries: 512 (order: 1, 8192 bytes) + TCP established hash table entries: 8192 (order: 4, 65536 bytes) + TCP bind hash table entries: 8192 (order: 5, 131072 bytes) + TCP: Hash tables configured (established 8192 bind 8192) + UDP hash table entries: 512 (order: 2, 16384 bytes) + UDP-Lite hash table entries: 512 (order: 2, 16384 bytes) + NET: Registered protocol family 1 + RPC: Registered named UNIX socket transport module. + RPC: Registered udp transport module. + RPC: Registered tcp transport module. + RPC: Registered tcp NFSv4.1 backchannel transport module. + Unpacking initramfs... + workingset: timestamp_bits=62 max_order=18 bucket_order=0 + NFS: Registering the id_resolver key type + Key type id_resolver registered + Key type id_legacy registered + nfs4filelayout_init: NFSv4 File Layout Driver Registering... + io scheduler noop registered + io scheduler cfq registered (default) + io scheduler mq-deadline registered + io scheduler kyber registered + Console: switching to colour frame buffer device 40x30 + Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled + console [ttyS0] disabled + f0300000.serial: ttyS0 at MMIO 0xf0300020 (irq = 20, base_baud = 1228800) is a 16550A + console [ttyS0] enabled + console [ttyS0] enabled + bootconsole [early0] disabled + bootconsole [early0] disabled + loop: module loaded + tun: Universal TUN/TAP device driver, 1.6 + ftmac100: Loading version 0.2 ... + ftmac100 e0100000.mac eth0: irq 21, mapped at (ptrval) + ftmac100 e0100000.mac eth0: generated random MAC address 4e:fd:bd:f3:04:fc + ftsdc010 f0e00000.mmc: mmc0 - using hw SDIO IRQ + mmc0: new SDHC card at address d555 + ftssp010 card registered! + mmcblk0: mmc0:d555 SD04G 3.79 GiB + NET: Registered protocol family 10 + mmcblk0: p1 + Segment Routing with IPv6 + sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver + NET: Registered protocol family 17 + NET: Registered protocol family 15 + ALSA device list: + #0: ftssp_ac97 controller + Freeing unused kernel memory: 13520K + This architecture does not have kernel memory protection. + Sysinit starting + Sat Apr 6 23:33:53 CST 2019 + nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering... + + ~ # diff --git a/doc/board/andestech/index.rst b/doc/board/andestech/index.rst new file mode 100644 index 0000000..cacc579 --- /dev/null +++ b/doc/board/andestech/index.rst @@ -0,0 +1,10 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Andes Tech +========== + +.. toctree:: + :maxdepth: 2 + + adp-ag101p + ae350 diff --git a/doc/board/index.rst b/doc/board/index.rst index 428faa8..2340eeb 100644 --- a/doc/board/index.rst +++ b/doc/board/index.rst @@ -8,7 +8,7 @@ Board-specific doc actions/index advantech/index - AndesTech/index + andestech/index allwinner/index amlogic/index anbernic/index diff --git a/drivers/cache/Kconfig b/drivers/cache/Kconfig index 26c2d80..4f35865 100644 --- a/drivers/cache/Kconfig +++ b/drivers/cache/Kconfig @@ -22,11 +22,11 @@ config L2X0_CACHE ARMv7(32-bit) devices. The driver configures the cache settings found in the device tree. -config V5L2_CACHE - bool "Andes V5L2 cache driver" +config ANDES_L2_CACHE + bool "Andes L2 cache driver" select CACHE help - Support Andes V5L2 cache controller in AE350 platform. + Support Andes L2 cache controller in AE350 platform. It will configure tag and data ram timing control from the device tree and enable L2 cache. diff --git a/drivers/cache/Makefile b/drivers/cache/Makefile index 78e673d..e1b71e0 100644 --- a/drivers/cache/Makefile +++ b/drivers/cache/Makefile @@ -3,6 +3,6 @@ obj-$(CONFIG_$(SPL_TPL_)CACHE) += cache-uclass.o obj-$(CONFIG_SANDBOX) += sandbox_cache.o obj-$(CONFIG_L2X0_CACHE) += cache-l2x0.o obj-$(CONFIG_NCORE_CACHE) += cache-ncore.o -obj-$(CONFIG_V5L2_CACHE) += cache-v5l2.o +obj-$(CONFIG_ANDES_L2_CACHE) += cache-andes-l2.o obj-$(CONFIG_SIFIVE_CCACHE) += cache-sifive-ccache.o obj-$(CONFIG_SIFIVE_PL2) += cache-sifive-pl2.o diff --git a/drivers/cache/cache-andes-l2.c b/drivers/cache/cache-andes-l2.c new file mode 100644 index 0000000..7de8f16 --- /dev/null +++ b/drivers/cache/cache-andes-l2.c @@ -0,0 +1,204 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 Andes Technology Corporation + * Rick Chen, Andes Technology Corporation + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +struct l2cache { + volatile u64 configure; + volatile u64 control; + volatile u64 hpm0; + volatile u64 hpm1; + volatile u64 hpm2; + volatile u64 hpm3; + volatile u64 error_status; + volatile u64 ecc_error; + volatile u64 cctl_command0; + volatile u64 cctl_access_line0; + volatile u64 cctl_command1; + volatile u64 cctl_access_line1; + volatile u64 cctl_command2; + volatile u64 cctl_access_line2; + volatile u64 cctl_command3; + volatile u64 cctl_access_line4; + volatile u64 cctl_status; +}; + +/* Configuration register */ +#define MEM_MAP_OFF 20 +#define MEM_MAP_MSK BIT(MEM_MAP_OFF) +/* offset of v0 memory map (Gen1) */ +static u32 cmd_stride = 0x10; +static u32 status_stride = 0x0; +static u32 status_bit_offset = 0x4; + +/* Control Register */ +#define L2_ENABLE 0x1 +/* prefetch */ +#define IPREPETCH_OFF 3 +#define DPREPETCH_OFF 5 +#define IPREPETCH_MSK (3 << IPREPETCH_OFF) +#define DPREPETCH_MSK (3 << DPREPETCH_OFF) +/* tag ram */ +#define TRAMOCTL_OFF 8 +#define TRAMICTL_OFF 10 +#define TRAMOCTL_MSK (3 << TRAMOCTL_OFF) +#define TRAMICTL_MSK BIT(TRAMICTL_OFF) +/* data ram */ +#define DRAMOCTL_OFF 11 +#define DRAMICTL_OFF 13 +#define DRAMOCTL_MSK (3 << DRAMOCTL_OFF) +#define DRAMICTL_MSK BIT(DRAMICTL_OFF) + +/* CCTL Command Register */ +#define CCTL_CMD_REG(base, hart) ((ulong)(base) + 0x40 + (hart) * (cmd_stride)) +#define L2_WBINVAL_ALL 0x12 + +/* CCTL Status Register */ +#define CCTL_STATUS_REG(base, hart) ((ulong)(base) + 0x80 + (hart) * (status_stride)) +#define CCTL_STATUS_MSK(hart) (0xf << ((hart) * (status_bit_offset))) +#define CCTL_STATUS_IDLE(hart) (0 << ((hart) * (status_bit_offset))) +#define CCTL_STATUS_PROCESS(hart) (1 << ((hart) * (status_bit_offset))) +#define CCTL_STATUS_ILLEGAL(hart) (2 << ((hart) * (status_bit_offset))) + +DECLARE_GLOBAL_DATA_PTR; + +struct andes_l2_plat { + struct l2cache *regs; + u32 iprefetch; + u32 dprefetch; + u32 tram_ctl[2]; + u32 dram_ctl[2]; +}; + +static int andes_l2_enable(struct udevice *dev) +{ + struct andes_l2_plat *plat = dev_get_plat(dev); + volatile struct l2cache *regs = plat->regs; + + if (regs) + setbits_le32(®s->control, L2_ENABLE); + + return 0; +} + +static int andes_l2_disable(struct udevice *dev) +{ + struct andes_l2_plat *plat = dev_get_plat(dev); + volatile struct l2cache *regs = plat->regs; + u8 hart = gd->arch.boot_hart; + void __iomem *cctlcmd = (void __iomem *)CCTL_CMD_REG(regs, hart); + + if ((regs) && (readl(®s->control) & L2_ENABLE)) { + writel(L2_WBINVAL_ALL, cctlcmd); + + while ((readl(®s->cctl_status) & CCTL_STATUS_MSK(hart))) { + if ((readl(®s->cctl_status) & CCTL_STATUS_ILLEGAL(hart))) { + printf("L2 flush illegal! hanging..."); + hang(); + } + } + clrbits_le32(®s->control, L2_ENABLE); + } + + return 0; +} + +static int andes_l2_of_to_plat(struct udevice *dev) +{ + struct andes_l2_plat *plat = dev_get_plat(dev); + struct l2cache *regs; + + regs = dev_read_addr_ptr(dev); + plat->regs = regs; + + plat->iprefetch = -EINVAL; + plat->dprefetch = -EINVAL; + plat->tram_ctl[0] = -EINVAL; + plat->dram_ctl[0] = -EINVAL; + + /* Instruction and data fetch prefetch depth */ + dev_read_u32(dev, "andes,inst-prefetch", &plat->iprefetch); + dev_read_u32(dev, "andes,data-prefetch", &plat->dprefetch); + + /* Set tag RAM and data RAM setup and output cycle */ + dev_read_u32_array(dev, "andes,tag-ram-ctl", plat->tram_ctl, 2); + dev_read_u32_array(dev, "andes,data-ram-ctl", plat->dram_ctl, 2); + + return 0; +} + +static int andes_l2_probe(struct udevice *dev) +{ + struct andes_l2_plat *plat = dev_get_plat(dev); + struct l2cache *regs = plat->regs; + u32 cfg_val, ctl_val; + + cfg_val = readl(®s->configure); + ctl_val = readl(®s->control); + + /* If true, v1 memory map (Gen2) */ + if (cfg_val & MEM_MAP_MSK) { + cmd_stride = 0x1000; + status_stride = 0x1000; + status_bit_offset = 0x0; + } + + ctl_val |= L2_ENABLE; + + if (plat->iprefetch != -EINVAL) { + ctl_val &= ~(IPREPETCH_MSK); + ctl_val |= (plat->iprefetch << IPREPETCH_OFF); + } + + if (plat->dprefetch != -EINVAL) { + ctl_val &= ~(DPREPETCH_MSK); + ctl_val |= (plat->dprefetch << DPREPETCH_OFF); + } + + if (plat->tram_ctl[0] != -EINVAL) { + ctl_val &= ~(TRAMOCTL_MSK | TRAMICTL_MSK); + ctl_val |= plat->tram_ctl[0] << TRAMOCTL_OFF; + ctl_val |= plat->tram_ctl[1] << TRAMICTL_OFF; + } + + if (plat->dram_ctl[0] != -EINVAL) { + ctl_val &= ~(DRAMOCTL_MSK | DRAMICTL_MSK); + ctl_val |= plat->dram_ctl[0] << DRAMOCTL_OFF; + ctl_val |= plat->dram_ctl[1] << DRAMICTL_OFF; + } + + writel(ctl_val, ®s->control); + + return 0; +} + +static const struct udevice_id andes_l2_cache_ids[] = { + { .compatible = "cache" }, + {} +}; + +static const struct cache_ops andes_l2_cache_ops = { + .enable = andes_l2_enable, + .disable = andes_l2_disable, +}; + +U_BOOT_DRIVER(andes_l2_cache) = { + .name = "andes_l2_cache", + .id = UCLASS_CACHE, + .of_match = andes_l2_cache_ids, + .of_to_plat = andes_l2_of_to_plat, + .probe = andes_l2_probe, + .plat_auto = sizeof(struct andes_l2_plat), + .ops = &andes_l2_cache_ops, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/cache/cache-v5l2.c b/drivers/cache/cache-v5l2.c deleted file mode 100644 index f0b8ecc..0000000 --- a/drivers/cache/cache-v5l2.c +++ /dev/null @@ -1,204 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2019 Andes Technology Corporation - * Rick Chen, Andes Technology Corporation - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -struct l2cache { - volatile u64 configure; - volatile u64 control; - volatile u64 hpm0; - volatile u64 hpm1; - volatile u64 hpm2; - volatile u64 hpm3; - volatile u64 error_status; - volatile u64 ecc_error; - volatile u64 cctl_command0; - volatile u64 cctl_access_line0; - volatile u64 cctl_command1; - volatile u64 cctl_access_line1; - volatile u64 cctl_command2; - volatile u64 cctl_access_line2; - volatile u64 cctl_command3; - volatile u64 cctl_access_line4; - volatile u64 cctl_status; -}; - -/* Configuration register */ -#define MEM_MAP_OFF 20 -#define MEM_MAP_MSK BIT(MEM_MAP_OFF) -/* offset of v0 memory map (Gen1) */ -static u32 cmd_stride = 0x10; -static u32 status_stride = 0x0; -static u32 status_bit_offset = 0x4; - -/* Control Register */ -#define L2_ENABLE 0x1 -/* prefetch */ -#define IPREPETCH_OFF 3 -#define DPREPETCH_OFF 5 -#define IPREPETCH_MSK (3 << IPREPETCH_OFF) -#define DPREPETCH_MSK (3 << DPREPETCH_OFF) -/* tag ram */ -#define TRAMOCTL_OFF 8 -#define TRAMICTL_OFF 10 -#define TRAMOCTL_MSK (3 << TRAMOCTL_OFF) -#define TRAMICTL_MSK BIT(TRAMICTL_OFF) -/* data ram */ -#define DRAMOCTL_OFF 11 -#define DRAMICTL_OFF 13 -#define DRAMOCTL_MSK (3 << DRAMOCTL_OFF) -#define DRAMICTL_MSK BIT(DRAMICTL_OFF) - -/* CCTL Command Register */ -#define CCTL_CMD_REG(base, hart) ((ulong)(base) + 0x40 + (hart) * (cmd_stride)) -#define L2_WBINVAL_ALL 0x12 - -/* CCTL Status Register */ -#define CCTL_STATUS_REG(base, hart) ((ulong)(base) + 0x80 + (hart) * (status_stride)) -#define CCTL_STATUS_MSK(hart) (0xf << ((hart) * (status_bit_offset))) -#define CCTL_STATUS_IDLE(hart) (0 << ((hart) * (status_bit_offset))) -#define CCTL_STATUS_PROCESS(hart) (1 << ((hart) * (status_bit_offset))) -#define CCTL_STATUS_ILLEGAL(hart) (2 << ((hart) * (status_bit_offset))) - -DECLARE_GLOBAL_DATA_PTR; - -struct v5l2_plat { - struct l2cache *regs; - u32 iprefetch; - u32 dprefetch; - u32 tram_ctl[2]; - u32 dram_ctl[2]; -}; - -static int v5l2_enable(struct udevice *dev) -{ - struct v5l2_plat *plat = dev_get_plat(dev); - volatile struct l2cache *regs = plat->regs; - - if (regs) - setbits_le32(®s->control, L2_ENABLE); - - return 0; -} - -static int v5l2_disable(struct udevice *dev) -{ - struct v5l2_plat *plat = dev_get_plat(dev); - volatile struct l2cache *regs = plat->regs; - u8 hart = gd->arch.boot_hart; - void __iomem *cctlcmd = (void __iomem *)CCTL_CMD_REG(regs, hart); - - if ((regs) && (readl(®s->control) & L2_ENABLE)) { - writel(L2_WBINVAL_ALL, cctlcmd); - - while ((readl(®s->cctl_status) & CCTL_STATUS_MSK(hart))) { - if ((readl(®s->cctl_status) & CCTL_STATUS_ILLEGAL(hart))) { - printf("L2 flush illegal! hanging..."); - hang(); - } - } - clrbits_le32(®s->control, L2_ENABLE); - } - - return 0; -} - -static int v5l2_of_to_plat(struct udevice *dev) -{ - struct v5l2_plat *plat = dev_get_plat(dev); - struct l2cache *regs; - - regs = dev_read_addr_ptr(dev); - plat->regs = regs; - - plat->iprefetch = -EINVAL; - plat->dprefetch = -EINVAL; - plat->tram_ctl[0] = -EINVAL; - plat->dram_ctl[0] = -EINVAL; - - /* Instruction and data fetch prefetch depth */ - dev_read_u32(dev, "andes,inst-prefetch", &plat->iprefetch); - dev_read_u32(dev, "andes,data-prefetch", &plat->dprefetch); - - /* Set tag RAM and data RAM setup and output cycle */ - dev_read_u32_array(dev, "andes,tag-ram-ctl", plat->tram_ctl, 2); - dev_read_u32_array(dev, "andes,data-ram-ctl", plat->dram_ctl, 2); - - return 0; -} - -static int v5l2_probe(struct udevice *dev) -{ - struct v5l2_plat *plat = dev_get_plat(dev); - struct l2cache *regs = plat->regs; - u32 cfg_val, ctl_val; - - cfg_val = readl(®s->configure); - ctl_val = readl(®s->control); - - /* If true, v1 memory map (Gen2) */ - if (cfg_val & MEM_MAP_MSK) { - cmd_stride = 0x1000; - status_stride = 0x1000; - status_bit_offset = 0x0; - } - - ctl_val |= L2_ENABLE; - - if (plat->iprefetch != -EINVAL) { - ctl_val &= ~(IPREPETCH_MSK); - ctl_val |= (plat->iprefetch << IPREPETCH_OFF); - } - - if (plat->dprefetch != -EINVAL) { - ctl_val &= ~(DPREPETCH_MSK); - ctl_val |= (plat->dprefetch << DPREPETCH_OFF); - } - - if (plat->tram_ctl[0] != -EINVAL) { - ctl_val &= ~(TRAMOCTL_MSK | TRAMICTL_MSK); - ctl_val |= plat->tram_ctl[0] << TRAMOCTL_OFF; - ctl_val |= plat->tram_ctl[1] << TRAMICTL_OFF; - } - - if (plat->dram_ctl[0] != -EINVAL) { - ctl_val &= ~(DRAMOCTL_MSK | DRAMICTL_MSK); - ctl_val |= plat->dram_ctl[0] << DRAMOCTL_OFF; - ctl_val |= plat->dram_ctl[1] << DRAMICTL_OFF; - } - - writel(ctl_val, ®s->control); - - return 0; -} - -static const struct udevice_id v5l2_cache_ids[] = { - { .compatible = "cache" }, - {} -}; - -static const struct cache_ops v5l2_cache_ops = { - .enable = v5l2_enable, - .disable = v5l2_disable, -}; - -U_BOOT_DRIVER(v5l2_cache) = { - .name = "v5l2_cache", - .id = UCLASS_CACHE, - .of_match = v5l2_cache_ids, - .of_to_plat = v5l2_of_to_plat, - .probe = v5l2_probe, - .plat_auto = sizeof(struct v5l2_plat), - .ops = &v5l2_cache_ops, - .flags = DM_FLAG_PRE_RELOC, -}; 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