From fac7fc43cfc63a778f8385917cf86fae7a1eb446 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Fri, 4 Mar 2022 16:30:09 +0000 Subject: vexpress64: Kconfig: move board definitions out of arch/arm At the moment we define three "VExpress64" boards in arch/arm/Kconfig, plus have a second Kconfig file in board/armltd/Kconfig. One of those three boards is actually bogus (TARGET_VEXPRESS64_AEMV8A), that stanza looks like being forgotten in a previous cleanup. To remove the clutter from the generic Kconfig file, just define some ARCH_VEXPRESS64 symbol there, enable some common options, and do the board/model specific configuration in the board/armltd Kconfig file. That allows to streamline and fine tune the configuration later, and to also pull a lot of "non user choices" out of the defconfigs. Signed-off-by: Andre Przywara --- arch/arm/Kconfig | 28 +++------------------------- board/armltd/vexpress64/Kconfig | 20 +++++++++++++++++++- configs/vexpress_aemv8a_juno_defconfig | 3 ++- configs/vexpress_aemv8a_semi_defconfig | 4 +--- 4 files changed, 25 insertions(+), 30 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index b5ca14f..8f70d5d 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1250,34 +1250,12 @@ config ARCH_TEGRA imply DISTRO_DEFAULTS imply FAT_WRITE -config TARGET_VEXPRESS64_AEMV8A - bool "Support vexpress_aemv8a" +config ARCH_VEXPRESS64 + bool "Support ARMv8 Arm Ltd. VExpress based boards and models" select ARM64 - select GPIO_EXTRA_HEADER - select PL01X_SERIAL - -config TARGET_VEXPRESS64_BASE_FVP - bool "Support Versatile Express ARMv8a FVP BASE model" - select ARM64 - select GPIO_EXTRA_HEADER - select PL01X_SERIAL - select SEMIHOSTING - -config TARGET_VEXPRESS64_JUNO - bool "Support Versatile Express Juno Development Platform" - select ARM64 - select GPIO_EXTRA_HEADER - select PL01X_SERIAL select DM - select OF_CONTROL - select CLK select DM_SERIAL - select ARM_PSCI_FW - select PSCI_RESET - select DM_ETH - select BLK - select USB - imply OF_HAS_PRIOR_STAGE + select PL01X_SERIAL config TARGET_TOTAL_COMPUTE bool "Support Total Compute Platform" diff --git a/board/armltd/vexpress64/Kconfig b/board/armltd/vexpress64/Kconfig index 4aab3f0..55fe011 100644 --- a/board/armltd/vexpress64/Kconfig +++ b/board/armltd/vexpress64/Kconfig @@ -1,4 +1,4 @@ -if TARGET_VEXPRESS64_BASE_FVP || TARGET_VEXPRESS64_JUNO +if ARCH_VEXPRESS64 config SYS_BOARD default "vexpress64" @@ -9,6 +9,24 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "vexpress_aemv8" +choice + prompt "VExpress64 board variant" + +config TARGET_VEXPRESS64_BASE_FVP + bool "Support Versatile Express ARMv8a FVP BASE model" + select SEMIHOSTING + +config TARGET_VEXPRESS64_JUNO + bool "Support Versatile Express Juno Development Platform" + select DM_ETH + select USB + select OF_CONTROL + select CLK + select BLK + imply OF_HAS_PRIOR_STAGE + +endchoice + config JUNO_DTB_PART string "NOR flash partition holding DTB" default "board.dtb" diff --git a/configs/vexpress_aemv8a_juno_defconfig b/configs/vexpress_aemv8a_juno_defconfig index 76a851c..1f8f101 100644 --- a/configs/vexpress_aemv8a_juno_defconfig +++ b/configs/vexpress_aemv8a_juno_defconfig @@ -1,5 +1,5 @@ CONFIG_ARM=y -CONFIG_TARGET_VEXPRESS64_JUNO=y +CONFIG_ARCH_VEXPRESS64=y CONFIG_SYS_TEXT_BASE=0xe0000000 CONFIG_SYS_MALLOC_LEN=0x810000 CONFIG_SYS_MALLOC_F_LEN=0x2000 @@ -8,6 +8,7 @@ CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_DEFAULT_DEVICE_TREE="juno-r2" CONFIG_IDENT_STRING=" vexpress_aemv8a" +CONFIG_TARGET_VEXPRESS64_JUNO=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0xff000000 CONFIG_DISTRO_DEFAULTS=y diff --git a/configs/vexpress_aemv8a_semi_defconfig b/configs/vexpress_aemv8a_semi_defconfig index b36a33a..959b3b3 100644 --- a/configs/vexpress_aemv8a_semi_defconfig +++ b/configs/vexpress_aemv8a_semi_defconfig @@ -1,6 +1,6 @@ CONFIG_ARM=y # CONFIG_ARM64_CRC32 is not set -CONFIG_TARGET_VEXPRESS64_BASE_FVP=y +CONFIG_ARCH_VEXPRESS64=y CONFIG_SYS_TEXT_BASE=0x88000000 CONFIG_SYS_MALLOC_LEN=0x840000 CONFIG_SYS_MALLOC_F_LEN=0x2000 @@ -39,7 +39,6 @@ CONFIG_CMD_UBI=y # CONFIG_EFI_PARTITION is not set CONFIG_ENV_IS_IN_FLASH=y CONFIG_ENV_ADDR=0xFFC0000 -CONFIG_DM=y # CONFIG_MMC is not set CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y @@ -47,5 +46,4 @@ CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y -CONFIG_DM_SERIAL=y CONFIG_OF_LIBFDT=y -- cgit v1.1 From 71fa41ebfc3f247f5f2654045713242830fde471 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Fri, 4 Mar 2022 16:30:10 +0000 Subject: arm: dts: Add Arm FVP Fastmodel RevC .dts files from Linux The Arm Fixed Virtual Platform (FVP) is a software model for an artificial ARM platform, it is available for free on the Arm website[1]. Add the devicetree files for the latest RevC version, as we will need them to enable OF_CONTROL for the vexpress_aemv8a_semi board. This is a verbatim copy of the respective files from Linux v5.17-rc6, which is unchanged from the v5.16 release. [1] https://developer.arm.com/tools-and-software/simulation-models/fast-models Signed-off-by: Andre Przywara --- arch/arm/dts/fvp-base-revc.dts | 246 ++++++++++++++++++++++++++++ arch/arm/dts/rtsm_ve-motherboard-rs2.dtsi | 27 ++++ arch/arm/dts/rtsm_ve-motherboard.dtsi | 258 ++++++++++++++++++++++++++++++ 3 files changed, 531 insertions(+) create mode 100644 arch/arm/dts/fvp-base-revc.dts create mode 100644 arch/arm/dts/rtsm_ve-motherboard-rs2.dtsi create mode 100644 arch/arm/dts/rtsm_ve-motherboard.dtsi diff --git a/arch/arm/dts/fvp-base-revc.dts b/arch/arm/dts/fvp-base-revc.dts new file mode 100644 index 0000000..269b649 --- /dev/null +++ b/arch/arm/dts/fvp-base-revc.dts @@ -0,0 +1,246 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * ARM Ltd. Fast Models + * + * Architecture Envelope Model (AEM) ARMv8-A + * ARMAEMv8AMPCT + * + * FVP Base RevC + */ + +/dts-v1/; + +#include + +/memreserve/ 0x80000000 0x00010000; + +#include "rtsm_ve-motherboard.dtsi" +#include "rtsm_ve-motherboard-rs2.dtsi" + +/ { + model = "FVP Base RevC"; + compatible = "arm,fvp-base-revc", "arm,vexpress"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + chosen { }; + + aliases { + serial0 = &v2m_serial0; + serial1 = &v2m_serial1; + serial2 = &v2m_serial2; + serial3 = &v2m_serial3; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x000>; + enable-method = "psci"; + }; + cpu1: cpu@100 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x100>; + enable-method = "psci"; + }; + cpu2: cpu@200 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x200>; + enable-method = "psci"; + }; + cpu3: cpu@300 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x300>; + enable-method = "psci"; + }; + cpu4: cpu@10000 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x10000>; + enable-method = "psci"; + }; + cpu5: cpu@10100 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x10100>; + enable-method = "psci"; + }; + cpu6: cpu@10200 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x10200>; + enable-method = "psci"; + }; + cpu7: cpu@10300 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x10300>; + enable-method = "psci"; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x00000000 0x80000000 0 0x80000000>, + <0x00000008 0x80000000 0 0x80000000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* Chipselect 2,00000000 is physically at 0x18000000 */ + vram: vram@18000000 { + /* 8 MB of designated video RAM */ + compatible = "shared-dma-pool"; + reg = <0x00000000 0x18000000 0 0x00800000>; + no-map; + }; + }; + + gic: interrupt-controller@2f000000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + interrupt-controller; + reg = <0x0 0x2f000000 0 0x10000>, // GICD + <0x0 0x2f100000 0 0x200000>, // GICR + <0x0 0x2c000000 0 0x2000>, // GICC + <0x0 0x2c010000 0 0x2000>, // GICH + <0x0 0x2c02f000 0 0x2000>; // GICV + interrupts = ; + + its: msi-controller@2f020000 { + #msi-cells = <1>; + compatible = "arm,gic-v3-its"; + reg = <0x0 0x2f020000 0x0 0x20000>; // GITS + msi-controller; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = ; + }; + + spe-pmu { + compatible = "arm,statistical-profiling-extension-v1"; + interrupts = ; + }; + + pci: pci@40000000 { + #address-cells = <0x3>; + #size-cells = <0x2>; + #interrupt-cells = <0x1>; + compatible = "pci-host-ecam-generic"; + device_type = "pci"; + bus-range = <0x0 0x1>; + reg = <0x0 0x40000000 0x0 0x10000000>; + ranges = <0x2000000 0x0 0x50000000 0x0 0x50000000 0x0 0x10000000>; + interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gic 0 0 GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gic 0 0 GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gic 0 0 GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + msi-map = <0x0 &its 0x0 0x10000>; + iommu-map = <0x0 &smmu 0x0 0x10000>; + + dma-coherent; + }; + + smmu: iommu@2b400000 { + compatible = "arm,smmu-v3"; + reg = <0x0 0x2b400000 0x0 0x100000>; + interrupts = , + , + , + ; + interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; + dma-coherent; + #iommu-cells = <1>; + msi-parent = <&its 0x10000>; + }; + + panel { + compatible = "arm,rtsm-display", "panel-dpi"; + port { + panel_in: endpoint { + remote-endpoint = <&clcd_pads>; + }; + }; + }; + + bus@8000000 { + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 63>; + interrupt-map = <0 0 0 &gic 0 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <0 0 1 &gic 0 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + <0 0 2 &gic 0 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <0 0 3 &gic 0 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <0 0 4 &gic 0 0 GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, + <0 0 5 &gic 0 0 GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, + <0 0 6 &gic 0 0 GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, + <0 0 7 &gic 0 0 GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <0 0 8 &gic 0 0 GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <0 0 9 &gic 0 0 GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <0 0 10 &gic 0 0 GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, + <0 0 11 &gic 0 0 GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, + <0 0 12 &gic 0 0 GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, + <0 0 13 &gic 0 0 GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, + <0 0 14 &gic 0 0 GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, + <0 0 15 &gic 0 0 GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, + <0 0 16 &gic 0 0 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, + <0 0 17 &gic 0 0 GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, + <0 0 18 &gic 0 0 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, + <0 0 19 &gic 0 0 GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, + <0 0 20 &gic 0 0 GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, + <0 0 21 &gic 0 0 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, + <0 0 22 &gic 0 0 GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, + <0 0 23 &gic 0 0 GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, + <0 0 24 &gic 0 0 GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, + <0 0 25 &gic 0 0 GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, + <0 0 26 &gic 0 0 GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, + <0 0 27 &gic 0 0 GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, + <0 0 28 &gic 0 0 GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, + <0 0 29 &gic 0 0 GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, + <0 0 30 &gic 0 0 GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, + <0 0 31 &gic 0 0 GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, + <0 0 32 &gic 0 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, + <0 0 33 &gic 0 0 GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, + <0 0 34 &gic 0 0 GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, + <0 0 35 &gic 0 0 GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, + <0 0 36 &gic 0 0 GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, + <0 0 37 &gic 0 0 GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, + <0 0 38 &gic 0 0 GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, + <0 0 39 &gic 0 0 GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, + <0 0 40 &gic 0 0 GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, + <0 0 41 &gic 0 0 GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, + <0 0 42 &gic 0 0 GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, + <0 0 43 &gic 0 0 GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, + <0 0 44 &gic 0 0 GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; + }; +}; diff --git a/arch/arm/dts/rtsm_ve-motherboard-rs2.dtsi b/arch/arm/dts/rtsm_ve-motherboard-rs2.dtsi new file mode 100644 index 0000000..33182d9 --- /dev/null +++ b/arch/arm/dts/rtsm_ve-motherboard-rs2.dtsi @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * ARM Ltd. Fast Models + * + * "rs2" extension for the v2m motherboard + */ +/ { + bus@8000000 { + motherboard-bus@8000000 { + arm,v2m-memory-map = "rs2"; + + iofpga-bus@300000000 { + virtio-p9@140000 { + compatible = "virtio,mmio"; + reg = <0x140000 0x200>; + interrupts = <43>; + }; + + virtio-net@150000 { + compatible = "virtio,mmio"; + reg = <0x150000 0x200>; + interrupts = <44>; + }; + }; + }; + }; +}; diff --git a/arch/arm/dts/rtsm_ve-motherboard.dtsi b/arch/arm/dts/rtsm_ve-motherboard.dtsi new file mode 100644 index 0000000..5f6cab6 --- /dev/null +++ b/arch/arm/dts/rtsm_ve-motherboard.dtsi @@ -0,0 +1,258 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * ARM Ltd. Fast Models + * + * Versatile Express (VE) system model + * Motherboard component + * + * VEMotherBoard.lisa + */ +/ { + v2m_clk24mhz: clk24mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "v2m:clk24mhz"; + }; + + v2m_refclk1mhz: refclk1mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1000000>; + clock-output-names = "v2m:refclk1mhz"; + }; + + v2m_refclk32khz: refclk32khz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "v2m:refclk32khz"; + }; + + v2m_fixed_3v3: v2m-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + mcc { + compatible = "arm,vexpress,config-bus"; + arm,vexpress,config-bridge = <&v2m_sysreg>; + + v2m_oscclk1: oscclk1 { + /* CLCD clock */ + compatible = "arm,vexpress-osc"; + arm,vexpress-sysreg,func = <1 1>; + freq-range = <23750000 63500000>; + #clock-cells = <0>; + clock-output-names = "v2m:oscclk1"; + }; + + reset { + compatible = "arm,vexpress-reset"; + arm,vexpress-sysreg,func = <5 0>; + }; + + muxfpga { + compatible = "arm,vexpress-muxfpga"; + arm,vexpress-sysreg,func = <7 0>; + }; + + shutdown { + compatible = "arm,vexpress-shutdown"; + arm,vexpress-sysreg,func = <8 0>; + }; + + reboot { + compatible = "arm,vexpress-reboot"; + arm,vexpress-sysreg,func = <9 0>; + }; + + dvimode { + compatible = "arm,vexpress-dvimode"; + arm,vexpress-sysreg,func = <11 0>; + }; + }; + + bus@8000000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0x8000000 0 0x8000000 0x18000000>; + + motherboard-bus@8000000 { + compatible = "arm,vexpress,v2m-p1", "simple-bus"; + #address-cells = <2>; /* SMB chipselect number and offset */ + #size-cells = <1>; + ranges = <0 0 0 0x08000000 0x04000000>, + <1 0 0 0x14000000 0x04000000>, + <2 0 0 0x18000000 0x04000000>, + <3 0 0 0x1c000000 0x04000000>, + <4 0 0 0x0c000000 0x04000000>, + <5 0 0 0x10000000 0x04000000>; + + flash@0 { + compatible = "arm,vexpress-flash", "cfi-flash"; + reg = <0 0x00000000 0x04000000>, + <4 0x00000000 0x04000000>; + bank-width = <4>; + }; + + ethernet@202000000 { + compatible = "smsc,lan91c111"; + reg = <2 0x02000000 0x10000>; + interrupts = <15>; + }; + + iofpga-bus@300000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 3 0 0x200000>; + + v2m_sysreg: sysreg@10000 { + compatible = "arm,vexpress-sysreg"; + reg = <0x010000 0x1000>; + gpio-controller; + #gpio-cells = <2>; + }; + + v2m_sysctl: sysctl@20000 { + compatible = "arm,sp810", "arm,primecell"; + reg = <0x020000 0x1000>; + clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&v2m_clk24mhz>; + clock-names = "refclk", "timclk", "apb_pclk"; + #clock-cells = <1>; + clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3"; + assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>; + assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>; + }; + + aaci@40000 { + compatible = "arm,pl041", "arm,primecell"; + reg = <0x040000 0x1000>; + interrupts = <11>; + clocks = <&v2m_clk24mhz>; + clock-names = "apb_pclk"; + }; + + mmc@50000 { + compatible = "arm,pl180", "arm,primecell"; + reg = <0x050000 0x1000>; + interrupts = <9>, <10>; + cd-gpios = <&v2m_sysreg 0 0>; + wp-gpios = <&v2m_sysreg 1 0>; + max-frequency = <12000000>; + vmmc-supply = <&v2m_fixed_3v3>; + clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; + clock-names = "mclk", "apb_pclk"; + }; + + kmi@60000 { + compatible = "arm,pl050", "arm,primecell"; + reg = <0x060000 0x1000>; + interrupts = <12>; + clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; + clock-names = "KMIREFCLK", "apb_pclk"; + }; + + kmi@70000 { + compatible = "arm,pl050", "arm,primecell"; + reg = <0x070000 0x1000>; + interrupts = <13>; + clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; + clock-names = "KMIREFCLK", "apb_pclk"; + }; + + v2m_serial0: serial@90000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x090000 0x1000>; + interrupts = <5>; + clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; + clock-names = "uartclk", "apb_pclk"; + }; + + v2m_serial1: serial@a0000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0a0000 0x1000>; + interrupts = <6>; + clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; + clock-names = "uartclk", "apb_pclk"; + }; + + v2m_serial2: serial@b0000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0b0000 0x1000>; + interrupts = <7>; + clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; + clock-names = "uartclk", "apb_pclk"; + }; + + v2m_serial3: serial@c0000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0c0000 0x1000>; + interrupts = <8>; + clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; + clock-names = "uartclk", "apb_pclk"; + }; + + watchdog@f0000 { + compatible = "arm,sp805", "arm,primecell"; + reg = <0x0f0000 0x1000>; + interrupts = <0>; + clocks = <&v2m_refclk32khz>, <&v2m_clk24mhz>; + clock-names = "wdog_clk", "apb_pclk"; + }; + + v2m_timer01: timer@110000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x110000 0x1000>; + interrupts = <2>; + clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_clk24mhz>; + clock-names = "timclken1", "timclken2", "apb_pclk"; + }; + + v2m_timer23: timer@120000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x120000 0x1000>; + interrupts = <3>; + clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&v2m_clk24mhz>; + clock-names = "timclken1", "timclken2", "apb_pclk"; + }; + + virtio-block@130000 { + compatible = "virtio,mmio"; + reg = <0x130000 0x200>; + interrupts = <42>; + }; + + rtc@170000 { + compatible = "arm,pl031", "arm,primecell"; + reg = <0x170000 0x1000>; + interrupts = <4>; + clocks = <&v2m_clk24mhz>; + clock-names = "apb_pclk"; + }; + + clcd@1f0000 { + compatible = "arm,pl111", "arm,primecell"; + reg = <0x1f0000 0x1000>; + interrupt-names = "combined"; + interrupts = <14>; + clocks = <&v2m_oscclk1>, <&v2m_clk24mhz>; + clock-names = "clcdclk", "apb_pclk"; + memory-region = <&vram>; + + port { + clcd_pads: endpoint { + remote-endpoint = <&panel_in>; + arm,pl11x,tft-r0g0b0-pads = <0 8 16>; + }; + }; + }; + }; + }; + }; +}; -- cgit v1.1 From c0fce929564f996f6f21418827c48519eb79d1b6 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Fri, 4 Mar 2022 16:30:11 +0000 Subject: vexpress64: fvp: enable OF_CONTROL The FVP base model is relying on a DT for Linux operation, so there is no reason we would need to rely on hardcoded information for U-Boot. Letting U-Boot use a DT will open up the usage of actual peripherals, beyond the support for semihosting only. Enable OF_CONTROL in the Kconfig, and use the latest dts files from Linux. Depending on whether we use the boot-wrapper or TF-A, there is already a DTB provided or not, respectively. To cover the boot-wrapper, we add an arm64 Linux kernel header, which allows the boot-wrapper to treat U-Boot like a Linux kernel. U-Boot will find the pointer to the DTB in x0, and will use it. Even though TF-A carries a DT, at the moment this is not made available to non-secure world, so to not break users, we use the U-Boot provided DTB copy in that case. For some reason TF-A puts some DT like structure at the address x0 is pointing at, but that is very small and doesn't carry any hardware information. Make the code to ignore those small DTBs. Signed-off-by: Andre Przywara --- arch/arm/Kconfig | 2 ++ arch/arm/dts/Makefile | 1 + board/armltd/vexpress64/Kconfig | 8 ++++++-- board/armltd/vexpress64/vexpress64.c | 8 +++++++- configs/vexpress_aemv8a_semi_defconfig | 2 +- 5 files changed, 17 insertions(+), 4 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 8f70d5d..0691292 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1256,6 +1256,8 @@ config ARCH_VEXPRESS64 select DM select DM_SERIAL select PL01X_SERIAL + select OF_CONTROL + select CLK config TARGET_TOTAL_COMPUTE bool "Support Total Compute Platform" diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index beaaf15..fe726d4 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1185,6 +1185,7 @@ dtb-$(CONFIG_TARGET_MX53PPD) += imx53-ppd.dtb # TODO(Linus Walleij ): Should us a single vexpress # Kconfig option to build all of these. See examples above. dtb-$(CONFIG_TARGET_VEXPRESS_CA9X4) += vexpress-v2p-ca9.dtb +dtb-$(CONFIG_TARGET_VEXPRESS64_BASE_FVP) += fvp-base-revc.dtb dtb-$(CONFIG_TARGET_VEXPRESS64_JUNO) += juno-r2.dtb dtb-$(CONFIG_TARGET_TOTAL_COMPUTE) += total_compute.dtb diff --git a/board/armltd/vexpress64/Kconfig b/board/armltd/vexpress64/Kconfig index 55fe011..3412644 100644 --- a/board/armltd/vexpress64/Kconfig +++ b/board/armltd/vexpress64/Kconfig @@ -15,13 +15,14 @@ choice config TARGET_VEXPRESS64_BASE_FVP bool "Support Versatile Express ARMv8a FVP BASE model" select SEMIHOSTING + select LINUX_KERNEL_IMAGE_HEADER + select POSITION_INDEPENDENT + select OF_BOARD config TARGET_VEXPRESS64_JUNO bool "Support Versatile Express Juno Development Platform" select DM_ETH select USB - select OF_CONTROL - select CLK select BLK imply OF_HAS_PRIOR_STAGE @@ -34,4 +35,7 @@ config JUNO_DTB_PART The ARM partition name in the NOR flash memory holding the device tree blob to configure U-Boot. +config LNX_KRNL_IMG_TEXT_OFFSET_BASE + default SYS_TEXT_BASE + endif diff --git a/board/armltd/vexpress64/vexpress64.c b/board/armltd/vexpress64/vexpress64.c index 5e22e89..7d5e551 100644 --- a/board/armltd/vexpress64/vexpress64.c +++ b/board/armltd/vexpress64/vexpress64.c @@ -168,11 +168,17 @@ void *board_fdt_blob_setup(int *err) } #endif - if (fdt_magic(prior_stage_fdt_address) == FDT_MAGIC) { + if (fdt_magic(prior_stage_fdt_address) == FDT_MAGIC && + fdt_totalsize(prior_stage_fdt_address) > 0x100) { *err = 0; return (void *)prior_stage_fdt_address; } + if (fdt_magic(gd->fdt_blob) == FDT_MAGIC) { + *err = 0; + return (void *)gd->fdt_blob; + } + *err = -ENXIO; return NULL; } diff --git a/configs/vexpress_aemv8a_semi_defconfig b/configs/vexpress_aemv8a_semi_defconfig index 959b3b3..dd06a1c 100644 --- a/configs/vexpress_aemv8a_semi_defconfig +++ b/configs/vexpress_aemv8a_semi_defconfig @@ -7,6 +7,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SIZE=0x40000 CONFIG_ENV_SECT_SIZE=0x40000 +CONFIG_DEFAULT_DEVICE_TREE="fvp-base-revc" CONFIG_IDENT_STRING=" vexpress_aemv8a" CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0xff000000 @@ -46,4 +47,3 @@ CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y -CONFIG_OF_LIBFDT=y -- cgit v1.1 From e09ec8e340260ace3d49d634fc869b7a9eb09186 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Fri, 4 Mar 2022 16:30:12 +0000 Subject: vexpress64: config header: unify environment definition The definition of the standard environment variables (kernel_addr_r and friends) has been improved lately for the FVP model, but the Juno board is still using some custom scheme. Since we need to extend this to a third board soon, let's unify the definition: - Define the Juno addresses in the same generic way we do for the FVP model, and move the actual variable setting out of the board #ifdef's. - Add the missing addresses for a PXE file and a boot script. - Cleanup some stale comments on the way. As the FVP model doesn't have support for distro_boot quite yet, add a dummy definition for now, to be replaced with the real thing later. Signed-off-by: Andre Przywara --- include/configs/vexpress_aemv8.h | 83 ++++++++++++++++++++++------------------ 1 file changed, 45 insertions(+), 38 deletions(-) diff --git a/include/configs/vexpress_aemv8.h b/include/configs/vexpress_aemv8.h index b956bd9..f8731aa 100644 --- a/include/configs/vexpress_aemv8.h +++ b/include/configs/vexpress_aemv8.h @@ -99,8 +99,6 @@ #define CONFIG_PL011_CLOCK 24000000 #endif -/* Miscellaneous configurable options */ - /* Physical Memory Map */ #define PHYS_SDRAM_1 (V2M_BASE) /* SDRAM Bank #1 */ /* Top 16MB reserved for secure world use */ @@ -116,11 +114,7 @@ #define PHYS_SDRAM_2_SIZE 0x80000000 #endif -/* Enable memtest */ - -/* Initial environment variables */ -#ifdef CONFIG_TARGET_VEXPRESS64_JUNO -/* Copy the kernel and FDT to DRAM memory and boot */ +/* Copy the kernel, initrd and FDT from NOR flash to DRAM memory and boot. */ #define BOOTENV_DEV_AFS(devtypeu, devtypel, instance) \ "bootcmd_afs=" \ "afs load ${kernel_name} ${kernel_addr_r} ;"\ @@ -143,6 +137,10 @@ "booti ${kernel_addr_r} ${ramdisk_param} ${fdt_addr_r}\0" #define BOOTENV_DEV_NAME_AFS(devtypeu, devtypel, instance) "afs " +/* Boot sources for distro boot and load addresses, per board */ + +#ifdef CONFIG_TARGET_VEXPRESS64_JUNO /* Arm Juno board */ + #define BOOT_TARGET_DEVICES(func) \ func(USB, usb, 0) \ func(SATA, sata, 0) \ @@ -153,40 +151,49 @@ #include -/* - * Defines where the kernel and FDT exist in NOR flash and where it will - * be copied into DRAM - */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "kernel_name=norkern\0" \ - "kernel_alt_name=Image\0" \ - "kernel_addr_r=0x80080000\0" \ - "ramdisk_name=ramdisk.img\0" \ - "ramdisk_addr_r=0x88000000\0" \ - "fdtfile=board.dtb\0" \ - "fdt_alt_name=juno\0" \ - "fdt_addr_r=0x80000000\0" \ - BOOTENV - -#elif CONFIG_TARGET_VEXPRESS64_BASE_FVP - -#define VEXPRESS_KERNEL_ADDR 0x80080000 -#define VEXPRESS_FDT_ADDR 0x8fc00000 -#define VEXPRESS_BOOT_ADDR 0x8fd00000 -#define VEXPRESS_RAMDISK_ADDR 0x8fe00000 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "kernel_name=Image\0" \ - "kernel_addr_r=" __stringify(VEXPRESS_KERNEL_ADDR) "\0" \ - "ramdisk_name=ramdisk.img\0" \ - "ramdisk_addr_r=" __stringify(VEXPRESS_RAMDISK_ADDR) "\0" \ - "fdtfile=devtree.dtb\0" \ - "fdt_addr_r=" __stringify(VEXPRESS_FDT_ADDR) "\0" \ - "boot_name=boot.img\0" \ - "boot_addr_r=" __stringify(VEXPRESS_BOOT_ADDR) "\0" +#define VEXPRESS_KERNEL_ADDR 0x80080000 +#define VEXPRESS_PXEFILE_ADDR 0x8fb00000 +#define VEXPRESS_FDT_ADDR 0x8fc00000 +#define VEXPRESS_SCRIPT_ADDR 0x8fd00000 +#define VEXPRESS_RAMDISK_ADDR 0x8fe00000 + +#define EXTRA_ENV_NAMES \ + "kernel_name=norkern\0" \ + "kernel_alt_name=Image\0" \ + "ramdisk_name=ramdisk.img\0" \ + "fdtfile=board.dtb\0" \ + "fdt_alt_name=juno\0" + +#elif CONFIG_TARGET_VEXPRESS64_BASE_FVP /* ARMv8-A base model */ + +#define VEXPRESS_KERNEL_ADDR 0x80080000 +#define VEXPRESS_PXEFILE_ADDR 0x8fa00000 +#define VEXPRESS_SCRIPT_ADDR 0x8fb00000 +#define VEXPRESS_FDT_ADDR 0x8fc00000 +#define VEXPRESS_BOOT_ADDR 0x8fd00000 +#define VEXPRESS_RAMDISK_ADDR 0x8fe00000 + +#define EXTRA_ENV_NAMES \ + "kernel_name=Image\0" \ + "ramdisk_name=ramdisk.img\0" \ + "fdtfile=devtree.dtb\0" \ + "boot_name=boot.img\0" \ + "boot_addr_r=" __stringify(VEXPRESS_BOOT_ADDR) "\0" + +#define BOOTENV #endif +/* Default load addresses and names for the different payloads. */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "kernel_addr_r=" __stringify(VEXPRESS_KERNEL_ADDR) "\0" \ + "ramdisk_addr_r=" __stringify(VEXPRESS_RAMDISK_ADDR) "\0" \ + "pxefile_addr_r=" __stringify(VEXPRESS_PXEFILE_ADDR) "\0" \ + "fdt_addr_r=" __stringify(VEXPRESS_FDT_ADDR) "\0" \ + "scriptaddr=" __stringify(VEXPRESS_SCRIPT_ADDR) "\0" \ + EXTRA_ENV_NAMES \ + BOOTENV + /* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ #define CONFIG_SYS_MAXARGS 64 /* max command args */ -- cgit v1.1 From 5865038257d1a38dd71f8107e4510f3c0c0dd584 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Fri, 4 Mar 2022 16:30:13 +0000 Subject: vexpress64: move hardware setting from defconfig to Kconfig The defconfigs for the Arm Juno board and the FVP model are quite large, setting a lot of platform-fixed variables like SYS_TEXT_BASE. As those values are not really a user choice, let's provide default values for them in our Kconfig file, so a lot of cruft can be removed from the defconfig files. This also moves the driver selection out of there, since this is again not something a user should really decide on. Instead we allow users to enable or disable subsystems, and select the appropriate drivers based on that in the Kconfig file. Signed-off-by: Andre Przywara --- arch/arm/Kconfig | 4 ++++ board/armltd/vexpress64/Kconfig | 41 +++++++++++++++++++++++++++++++--- configs/vexpress_aemv8a_juno_defconfig | 21 ++--------------- configs/vexpress_aemv8a_semi_defconfig | 10 --------- 4 files changed, 44 insertions(+), 32 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 0691292..7e613c7 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1258,6 +1258,10 @@ config ARCH_VEXPRESS64 select PL01X_SERIAL select OF_CONTROL select CLK + select BLK + select MTD_NOR_FLASH if MTD + select FLASH_CFI_DRIVER if MTD + select ENV_IS_IN_FLASH if MTD config TARGET_TOTAL_COMPUTE bool "Support Total Compute Platform" diff --git a/board/armltd/vexpress64/Kconfig b/board/armltd/vexpress64/Kconfig index 3412644..512bbbe 100644 --- a/board/armltd/vexpress64/Kconfig +++ b/board/armltd/vexpress64/Kconfig @@ -15,15 +15,24 @@ choice config TARGET_VEXPRESS64_BASE_FVP bool "Support Versatile Express ARMv8a FVP BASE model" select SEMIHOSTING + select VIRTIO_BLK if VIRTIO_MMIO + select VIRTIO_NET if VIRTIO_MMIO + select DM_ETH if VIRTIO_NET select LINUX_KERNEL_IMAGE_HEADER select POSITION_INDEPENDENT select OF_BOARD config TARGET_VEXPRESS64_JUNO bool "Support Versatile Express Juno Development Platform" - select DM_ETH - select USB - select BLK + select PCIE_ECAM_GENERIC if PCI + select SATA_SIL + select SMC911X if DM_ETH + select SMC911X_32_BIT if SMC911X + select CMD_USB if USB + select USB_EHCI_HCD if USB + select USB_EHCI_GENERIC if USB + select USB_OHCI_HCD if USB + select USB_OHCI_GENERIC if USB imply OF_HAS_PRIOR_STAGE endchoice @@ -38,4 +47,30 @@ config JUNO_DTB_PART config LNX_KRNL_IMG_TEXT_OFFSET_BASE default SYS_TEXT_BASE +config SYS_TEXT_BASE + default 0x88000000 if TARGET_VEXPRESS64_BASE_FVP + default 0xe0000000 if TARGET_VEXPRESS64_JUNO + +config SYS_MALLOC_LEN + default 0x810000 if TARGET_VEXPRESS64_JUNO + default 0x840000 if TARGET_VEXPRESS64_BASE_FVP + +config SYS_MALLOC_F_LEN + default 0x2000 + +config SYS_LOAD_ADDR + default 0x90000000 + +config ENV_ADDR + default 0x0BFC0000 if TARGET_VEXPRESS64_JUNO + default 0x0FFC0000 if TARGET_VEXPRESS64_BASE_FVP + +config ENV_SIZE + default 0x10000 if TARGET_VEXPRESS64_JUNO + default 0x40000 + +config ENV_SECT_SIZE + default 0x10000 if TARGET_VEXPRESS64_JUNO + default 0x40000 + endif diff --git a/configs/vexpress_aemv8a_juno_defconfig b/configs/vexpress_aemv8a_juno_defconfig index 1f8f101..a5d7247 100644 --- a/configs/vexpress_aemv8a_juno_defconfig +++ b/configs/vexpress_aemv8a_juno_defconfig @@ -1,11 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_VEXPRESS64=y -CONFIG_SYS_TEXT_BASE=0xe0000000 -CONFIG_SYS_MALLOC_LEN=0x810000 -CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_NR_DRAM_BANKS=2 -CONFIG_ENV_SIZE=0x10000 -CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_DEFAULT_DEVICE_TREE="juno-r2" CONFIG_IDENT_STRING=" vexpress_aemv8a" CONFIG_TARGET_VEXPRESS64_JUNO=y @@ -13,7 +8,6 @@ CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0xff000000 CONFIG_DISTRO_DEFAULTS=y CONFIG_REMAKE_ELF=y -CONFIG_SYS_LOAD_ADDR=0x90000000 CONFIG_BOOTDELAY=1 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyAMA0,115200n8 root=/dev/sda2 rw rootwait earlycon=pl011,0x7ff80000 debug user_debug=31 androidboot.hardware=juno loglevel=9" @@ -28,7 +22,6 @@ CONFIG_CMD_ARMFLASH=y # CONFIG_CMD_LOADS is not set CONFIG_CMD_PCI=y CONFIG_CMD_SATA=y -CONFIG_CMD_USB=y # CONFIG_CMD_ITEST is not set # CONFIG_CMD_SETEXPR is not set CONFIG_BOOTP_BOOTFILESIZE=y @@ -36,21 +29,11 @@ CONFIG_BOOTP_BOOTFILESIZE=y CONFIG_CMD_CACHE=y # CONFIG_CMD_SLEEP is not set CONFIG_CMD_UBI=y -CONFIG_ENV_IS_IN_FLASH=y -CONFIG_ENV_ADDR=0xBFC0000 -CONFIG_SATA_SIL=y # CONFIG_MMC is not set CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y -CONFIG_SMC911X=y -CONFIG_SMC911X_32_BIT=y +CONFIG_DM_ETH=y CONFIG_PCI=y -CONFIG_PCIE_ECAM_GENERIC=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_EHCI_GENERIC=y -CONFIG_USB_OHCI_HCD=y -CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB=y diff --git a/configs/vexpress_aemv8a_semi_defconfig b/configs/vexpress_aemv8a_semi_defconfig index dd06a1c..b47aba2 100644 --- a/configs/vexpress_aemv8a_semi_defconfig +++ b/configs/vexpress_aemv8a_semi_defconfig @@ -1,19 +1,13 @@ CONFIG_ARM=y # CONFIG_ARM64_CRC32 is not set CONFIG_ARCH_VEXPRESS64=y -CONFIG_SYS_TEXT_BASE=0x88000000 -CONFIG_SYS_MALLOC_LEN=0x840000 -CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_NR_DRAM_BANKS=2 -CONFIG_ENV_SIZE=0x40000 -CONFIG_ENV_SECT_SIZE=0x40000 CONFIG_DEFAULT_DEVICE_TREE="fvp-base-revc" CONFIG_IDENT_STRING=" vexpress_aemv8a" CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0xff000000 CONFIG_DISTRO_DEFAULTS=y CONFIG_REMAKE_ELF=y -CONFIG_SYS_LOAD_ADDR=0x90000000 CONFIG_ANDROID_BOOT_IMAGE=y CONFIG_BOOTDELAY=1 CONFIG_USE_BOOTARGS=y @@ -38,12 +32,8 @@ CONFIG_CMD_CACHE=y CONFIG_CMD_UBI=y # CONFIG_ISO_PARTITION is not set # CONFIG_EFI_PARTITION is not set -CONFIG_ENV_IS_IN_FLASH=y -CONFIG_ENV_ADDR=0xFFC0000 # CONFIG_MMC is not set CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y -- cgit v1.1 From 8a0a8ff52c1681a3cde8568cb6e252b9a98fdf06 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Fri, 4 Mar 2022 16:30:14 +0000 Subject: vexpress64: fvp: add distro_boot support So far the FVP model just supports booting through semihosting, so by loading files from the host the model is running on. This allows for quick booting of new kernels (or replacing DTBs), but prevents more featureful boots like using UEFI. Enable the distro_boot feature, and provide a list of possible boot sources that U-Boot should check: - For backwards compatibility we start with semihosting, which gets its commands migrated from CONFIG_BOOTCOMMAND into the distro_boot infrastructure. This is also slightly tweaked to fail graceful in case the required files could not be found. - Next we try to use a user provided script, that could be easily placed into memory using the model command line. - Since we gained virtio support with the enablement of OF_CONTROL, let's check virtio block devices next. This is where UEFI boot can be easily used, for instance by providing a distro installer .iso file through virtio-blk. - Networking is now provided by virtio as well, so enable the default PXE and DHCP boot flows, mostly because we can. Signed-off-by: Andre Przywara --- arch/arm/Kconfig | 1 + configs/vexpress_aemv8a_juno_defconfig | 1 - configs/vexpress_aemv8a_semi_defconfig | 5 +-- include/configs/vexpress_aemv8.h | 57 +++++++++++++++++++++++++++++++--- 4 files changed, 55 insertions(+), 9 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 7e613c7..1f2b849 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1262,6 +1262,7 @@ config ARCH_VEXPRESS64 select MTD_NOR_FLASH if MTD select FLASH_CFI_DRIVER if MTD select ENV_IS_IN_FLASH if MTD + imply DISTRO_DEFAULTS config TARGET_TOTAL_COMPUTE bool "Support Total Compute Platform" diff --git a/configs/vexpress_aemv8a_juno_defconfig b/configs/vexpress_aemv8a_juno_defconfig index a5d7247..6afeac2 100644 --- a/configs/vexpress_aemv8a_juno_defconfig +++ b/configs/vexpress_aemv8a_juno_defconfig @@ -6,7 +6,6 @@ CONFIG_IDENT_STRING=" vexpress_aemv8a" CONFIG_TARGET_VEXPRESS64_JUNO=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0xff000000 -CONFIG_DISTRO_DEFAULTS=y CONFIG_REMAKE_ELF=y CONFIG_BOOTDELAY=1 CONFIG_USE_BOOTARGS=y diff --git a/configs/vexpress_aemv8a_semi_defconfig b/configs/vexpress_aemv8a_semi_defconfig index b47aba2..0834c6f 100644 --- a/configs/vexpress_aemv8a_semi_defconfig +++ b/configs/vexpress_aemv8a_semi_defconfig @@ -6,13 +6,11 @@ CONFIG_DEFAULT_DEVICE_TREE="fvp-base-revc" CONFIG_IDENT_STRING=" vexpress_aemv8a" CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0xff000000 -CONFIG_DISTRO_DEFAULTS=y CONFIG_REMAKE_ELF=y CONFIG_ANDROID_BOOT_IMAGE=y CONFIG_BOOTDELAY=1 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyAMA0 earlycon=pl011,0x1c090000 debug user_debug=31 loglevel=9" -CONFIG_BOOTCOMMAND="if smhload ${boot_name} ${boot_addr_r}; then setenv bootargs; abootimg addr ${boot_addr_r}; abootimg get dtb --index=0 fdt_addr_r; bootm ${boot_addr_r} ${boot_addr_r} ${fdt_addr_r}; else; setenv fdt_high 0xffffffffffffffff; setenv initrd_high 0xffffffffffffffff; smhload ${kernel_name} ${kernel_addr_r}; smhload ${fdtfile} ${fdt_addr_r}; smhload ${ramdisk_name} ${ramdisk_addr_r} ramdisk_end; fdt addr ${fdt_addr_r}; fdt resize; fdt chosen ${ramdisk_addr_r} ${ramdisk_end}; booti $kernel_addr_r - $fdt_addr_r; fi" # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SYS_PROMPT="VExpress64# " @@ -30,10 +28,9 @@ CONFIG_BOOTP_BOOTFILESIZE=y CONFIG_CMD_CACHE=y # CONFIG_CMD_SLEEP is not set CONFIG_CMD_UBI=y -# CONFIG_ISO_PARTITION is not set -# CONFIG_EFI_PARTITION is not set # CONFIG_MMC is not set CONFIG_MTD=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y +CONFIG_VIRTIO_MMIO=y diff --git a/include/configs/vexpress_aemv8.h b/include/configs/vexpress_aemv8.h index f8731aa..74060c6 100644 --- a/include/configs/vexpress_aemv8.h +++ b/include/configs/vexpress_aemv8.h @@ -137,6 +137,50 @@ "booti ${kernel_addr_r} ${ramdisk_param} ${fdt_addr_r}\0" #define BOOTENV_DEV_NAME_AFS(devtypeu, devtypel, instance) "afs " +/* Boot by executing a U-Boot script pre-loaded into DRAM. */ +#define BOOTENV_DEV_MEM(devtypeu, devtypel, instance) \ + "bootcmd_mem= " \ + "source ${scriptaddr}; " \ + "if test $? -eq 1; then " \ + " env import -t ${scriptaddr}; " \ + " if test -n $uenvcmd; then " \ + " echo Running uenvcmd ...; " \ + " run uenvcmd; " \ + " fi; " \ + "fi\0" +#define BOOTENV_DEV_NAME_MEM(devtypeu, devtypel, instance) "mem " + +#ifdef CONFIG_CMD_VIRTIO +#define FUNC_VIRTIO(func) func(VIRTIO, virtio, 0) +#else +#define FUNC_VIRTIO(func) +#endif + +/* + * Boot by loading an Android image, or kernel, initrd and FDT through + * semihosting into DRAM. + */ +#define BOOTENV_DEV_SMH(devtypeu, devtypel, instance) \ + "bootcmd_smh= " \ + "if smhload ${boot_name} ${boot_addr_r}; then" \ + " setenv bootargs;" \ + " abootimg addr ${boot_addr_r};" \ + " abootimg get dtb --index=0 fdt_addr_r;" \ + " bootm ${boot_addr_r} ${boot_addr_r} ${fdt_addr_r};" \ + "else" \ + " if smhload ${kernel_name} ${kernel_addr_r}; then" \ + " setenv fdt_high 0xffffffffffffffff;" \ + " setenv initrd_high 0xffffffffffffffff;" \ + " smhload ${fdtfile} ${fdt_addr_r};" \ + " smhload ${ramdisk_name} ${ramdisk_addr_r} ramdisk_end;" \ + " fdt addr ${fdt_addr_r};" \ + " fdt resize;" \ + " fdt chosen ${ramdisk_addr_r} ${ramdisk_end};" \ + " booti $kernel_addr_r - $fdt_addr_r;" \ + " fi;" \ + "fi\0" +#define BOOTENV_DEV_NAME_SMH(devtypeu, devtypel, instance) "smh " + /* Boot sources for distro boot and load addresses, per board */ #ifdef CONFIG_TARGET_VEXPRESS64_JUNO /* Arm Juno board */ @@ -149,8 +193,6 @@ func(DHCP, dhcp, na) \ func(AFS, afs, na) -#include - #define VEXPRESS_KERNEL_ADDR 0x80080000 #define VEXPRESS_PXEFILE_ADDR 0x8fb00000 #define VEXPRESS_FDT_ADDR 0x8fc00000 @@ -166,6 +208,13 @@ #elif CONFIG_TARGET_VEXPRESS64_BASE_FVP /* ARMv8-A base model */ +#define BOOT_TARGET_DEVICES(func) \ + func(SMH, smh, na) \ + func(MEM, mem, na) \ + FUNC_VIRTIO(func) \ + func(PXE, pxe, na) \ + func(DHCP, dhcp, na) + #define VEXPRESS_KERNEL_ADDR 0x80080000 #define VEXPRESS_PXEFILE_ADDR 0x8fa00000 #define VEXPRESS_SCRIPT_ADDR 0x8fb00000 @@ -180,10 +229,10 @@ "boot_name=boot.img\0" \ "boot_addr_r=" __stringify(VEXPRESS_BOOT_ADDR) "\0" -#define BOOTENV - #endif +#include + /* Default load addresses and names for the different payloads. */ #define CONFIG_EXTRA_ENV_SETTINGS \ "kernel_addr_r=" __stringify(VEXPRESS_KERNEL_ADDR) "\0" \ -- cgit v1.1 From 168e815d258c410e191107bceecc426557474be2 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Fri, 4 Mar 2022 16:30:15 +0000 Subject: vexpress64: defconfigs: allow default commands Right now the defconfig the Arm VExpress64 boards disables quite some standard commands, for apparently no good reasons (as image size is hardly a concern here). Remove the lines explicitly disabling those features, leaving it to the U-Boot default settings to set them. Signed-off-by: Andre Przywara --- configs/vexpress_aemv8a_juno_defconfig | 8 -------- configs/vexpress_aemv8a_semi_defconfig | 9 --------- 2 files changed, 17 deletions(-) diff --git a/configs/vexpress_aemv8a_juno_defconfig b/configs/vexpress_aemv8a_juno_defconfig index 6afeac2..374fa32 100644 --- a/configs/vexpress_aemv8a_juno_defconfig +++ b/configs/vexpress_aemv8a_juno_defconfig @@ -13,20 +13,12 @@ CONFIG_BOOTARGS="console=ttyAMA0,115200n8 root=/dev/sda2 rw rootwait earlycon=pl # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SYS_PROMPT="VExpress64# " -# CONFIG_CMD_CONSOLE is not set -# CONFIG_CMD_XIMG is not set -# CONFIG_CMD_EDITENV is not set CONFIG_CMD_MEMTEST=y CONFIG_CMD_ARMFLASH=y -# CONFIG_CMD_LOADS is not set CONFIG_CMD_PCI=y CONFIG_CMD_SATA=y -# CONFIG_CMD_ITEST is not set -# CONFIG_CMD_SETEXPR is not set CONFIG_BOOTP_BOOTFILESIZE=y -# CONFIG_CMD_NFS is not set CONFIG_CMD_CACHE=y -# CONFIG_CMD_SLEEP is not set CONFIG_CMD_UBI=y # CONFIG_MMC is not set CONFIG_MTD=y diff --git a/configs/vexpress_aemv8a_semi_defconfig b/configs/vexpress_aemv8a_semi_defconfig index 0834c6f..eca6176 100644 --- a/configs/vexpress_aemv8a_semi_defconfig +++ b/configs/vexpress_aemv8a_semi_defconfig @@ -12,21 +12,12 @@ CONFIG_BOOTDELAY=1 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyAMA0 earlycon=pl011,0x1c090000 debug user_debug=31 loglevel=9" # CONFIG_DISPLAY_CPUINFO is not set -# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SYS_PROMPT="VExpress64# " -# CONFIG_CMD_CONSOLE is not set CONFIG_CMD_ABOOTIMG=y -# CONFIG_CMD_XIMG is not set -# CONFIG_CMD_EDITENV is not set CONFIG_CMD_MEMTEST=y CONFIG_CMD_ARMFLASH=y -# CONFIG_CMD_LOADS is not set -# CONFIG_CMD_ITEST is not set -# CONFIG_CMD_SETEXPR is not set CONFIG_BOOTP_BOOTFILESIZE=y -# CONFIG_CMD_NFS is not set CONFIG_CMD_CACHE=y -# CONFIG_CMD_SLEEP is not set CONFIG_CMD_UBI=y # CONFIG_MMC is not set CONFIG_MTD=y -- cgit v1.1 From 30cacb8123459328c46c25f65196bb4885dcdb05 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Fri, 4 Mar 2022 16:30:16 +0000 Subject: vexpress64: generalise page table generation In preparation for the ARMv8-R64 FVP support, which has DRAM mapped at 0x0, generalise the page table generation, by using symbolic names for the address ranges instead of fixed numbers. We already define the base of the DRAM and MMIO regions, so just use those symbols in the page table description. Rename V2M_BASE to the more speaking V2M_DRAM_BASE on the way. On the VExpress memory map, the address space right after 4GB is of no particular interest to software, as the whole of DRAM is mapped at 32GB instead. The first 2 GB alias to the lower 2GB of DRAM mapped below 4GB, so we skip this part and map some more of the high DRAM, should anyone need it. Signed-off-by: Andre Przywara --- board/armltd/vexpress64/vexpress64.c | 24 ++++++++++++++++++------ include/configs/vexpress_aemv8.h | 4 ++-- 2 files changed, 20 insertions(+), 8 deletions(-) diff --git a/board/armltd/vexpress64/vexpress64.c b/board/armltd/vexpress64/vexpress64.c index 7d5e551..c3ad1fc 100644 --- a/board/armltd/vexpress64/vexpress64.c +++ b/board/armltd/vexpress64/vexpress64.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include "pcie.h" #include @@ -38,16 +39,27 @@ U_BOOT_DRVINFO(vexpress_serials) = { static struct mm_region vexpress64_mem_map[] = { { - .virt = 0x0UL, - .phys = 0x0UL, - .size = 0x80000000UL, + .virt = V2M_PA_BASE, + .phys = V2M_PA_BASE, + .size = SZ_2G, .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, { - .virt = 0x80000000UL, - .phys = 0x80000000UL, - .size = 0xff80000000UL, + .virt = V2M_DRAM_BASE, + .phys = V2M_DRAM_BASE, + .size = SZ_2G, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + /* + * DRAM beyond 2 GiB is located high. Let's map just some + * of it, although U-Boot won't realistically use it, and + * the actual available amount might be smaller on the model. + */ + .virt = 0x880000000UL, /* 32 + 2 GiB */ + .phys = 0x880000000UL, + .size = 6UL * SZ_1G, .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE }, { diff --git a/include/configs/vexpress_aemv8.h b/include/configs/vexpress_aemv8.h index 74060c6..e0f9bbe 100644 --- a/include/configs/vexpress_aemv8.h +++ b/include/configs/vexpress_aemv8.h @@ -20,7 +20,7 @@ #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ /* CS register bases for the original memory map. */ -#define V2M_BASE 0x80000000 +#define V2M_DRAM_BASE 0x80000000 #define V2M_PA_BASE 0x00000000 #define V2M_PA_CS0 (V2M_PA_BASE + 0x00000000) @@ -100,7 +100,7 @@ #endif /* Physical Memory Map */ -#define PHYS_SDRAM_1 (V2M_BASE) /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1 (V2M_DRAM_BASE) /* SDRAM Bank #1 */ /* Top 16MB reserved for secure world use */ #define DRAM_SEC_SIZE 0x01000000 #define PHYS_SDRAM_1_SIZE 0x80000000 - DRAM_SEC_SIZE -- cgit v1.1 From 1a1143a45457161e90ea4cd5f3b0561d924ed8fe Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Fri, 4 Mar 2022 16:30:17 +0000 Subject: vexpress64: pick DRAM size from DT So far the DRAM size for both the Juno and the FVP model were hardcoded in our config header file. For the Juno this is fine, as all models have 8 GiB of DRAM, but the DRAM size can be configured on the model command line. Drop the fixed DRAM size setup, instead look up the size in the device tree, that we now have for every board. This allows a user to inject a DT with the proper size, and be able to use the full amount of DRAM. Signed-off-by: Andre Przywara --- board/armltd/vexpress64/vexpress64.c | 12 ++---------- 1 file changed, 2 insertions(+), 10 deletions(-) diff --git a/board/armltd/vexpress64/vexpress64.c b/board/armltd/vexpress64/vexpress64.c index c3ad1fc..709ebf3 100644 --- a/board/armltd/vexpress64/vexpress64.c +++ b/board/armltd/vexpress64/vexpress64.c @@ -88,20 +88,12 @@ int board_init(void) int dram_init(void) { - gd->ram_size = PHYS_SDRAM_1_SIZE; - return 0; + return fdtdec_setup_mem_size_base(); } int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; -#ifdef PHYS_SDRAM_2 - gd->bd->bi_dram[1].start = PHYS_SDRAM_2; - gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; -#endif - - return 0; + return fdtdec_setup_memory_banksize(); } /* Assigned in lowlevel_init.S -- cgit v1.1 From 8d78a6b67467145f7e02295ca5d4944251dbc645 Mon Sep 17 00:00:00 2001 From: Peter Hoyes Date: Fri, 4 Mar 2022 16:30:18 +0000 Subject: vexpress64: Add ARMv8R-64 board variant The ARMv8-R64 architecture introduces optional VMSA (paging based MMU) support in the EL1/0 translation regime, which makes that part mostly compatible to ARMv8-A. Add a new board variant to describe the "BASE-R64" FVP model, which inherits a lot from the existing v8-A FVP support. One major difference is that the memory map in "inverted": DRAM starts at 0x0, MMIO is at 2GB [1]. * Create new TARGET_VEXPRESS64_BASER_FVP target, sharing most of the exising configuration. * Implement inverted memory map in vexpress_aemv8.h * Create vexpress_aemv8r defconfig * Provide an MMU memory map for the BASER_FVP * Update vexpress64 documentation At the moment the boot-wrapper is the only supported secure firmware. As there is no official DT for the board yet, we rely on it being supplied by the boot-wrapper into U-Boot, so use OF_HAS_PRIOR_STAGE, and go with a dummy DT for now. [1] https://developer.arm.com/documentation/100964/1114/Base-Platform/Base---memory/BaseR-Platform-memory-map Signed-off-by: Peter Hoyes [Andre: rebase and add Linux kernel header] Signed-off-by: Andre Przywara [trini: Add MAINTAINERS entry for Peter] --- arch/arm/dts/Makefile | 1 + arch/arm/dts/arm_fvp.dts | 11 +++++++++++ board/armltd/vexpress64/Kconfig | 22 +++++++++++++++++----- board/armltd/vexpress64/MAINTAINERS | 5 +++++ configs/vexpress_aemv8r_defconfig | 14 ++++++++++++++ doc/arch/arm64.rst | 3 ++- doc/board/armltd/vexpress64.rst | 1 + include/configs/vexpress_aemv8.h | 23 +++++++++++++++++++++++ 8 files changed, 74 insertions(+), 6 deletions(-) create mode 100644 arch/arm/dts/arm_fvp.dts create mode 100644 configs/vexpress_aemv8r_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index fe726d4..99dc7bc 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1186,6 +1186,7 @@ dtb-$(CONFIG_TARGET_MX53PPD) += imx53-ppd.dtb # Kconfig option to build all of these. See examples above. dtb-$(CONFIG_TARGET_VEXPRESS_CA9X4) += vexpress-v2p-ca9.dtb dtb-$(CONFIG_TARGET_VEXPRESS64_BASE_FVP) += fvp-base-revc.dtb +dtb-$(CONFIG_TARGET_VEXPRESS64_BASER_FVP) += arm_fvp.dtb dtb-$(CONFIG_TARGET_VEXPRESS64_JUNO) += juno-r2.dtb dtb-$(CONFIG_TARGET_TOTAL_COMPUTE) += total_compute.dtb diff --git a/arch/arm/dts/arm_fvp.dts b/arch/arm/dts/arm_fvp.dts new file mode 100644 index 0000000..3a4ad5d --- /dev/null +++ b/arch/arm/dts/arm_fvp.dts @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Empty device tree for the Arm Ltd FVP platform model + + * Copyright 2022 Arm Ltd. + */ + +/dts-v1/; + +/ { +}; diff --git a/board/armltd/vexpress64/Kconfig b/board/armltd/vexpress64/Kconfig index 512bbbe..a0314c6 100644 --- a/board/armltd/vexpress64/Kconfig +++ b/board/armltd/vexpress64/Kconfig @@ -9,19 +9,28 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "vexpress_aemv8" -choice - prompt "VExpress64 board variant" - -config TARGET_VEXPRESS64_BASE_FVP - bool "Support Versatile Express ARMv8a FVP BASE model" +config VEXPRESS64_BASE_MODEL + bool select SEMIHOSTING select VIRTIO_BLK if VIRTIO_MMIO select VIRTIO_NET if VIRTIO_MMIO select DM_ETH if VIRTIO_NET select LINUX_KERNEL_IMAGE_HEADER select POSITION_INDEPENDENT + +choice + prompt "VExpress64 board variant" + +config TARGET_VEXPRESS64_BASE_FVP + bool "Support Versatile Express ARMv8a FVP BASE model" + select VEXPRESS64_BASE_MODEL select OF_BOARD +config TARGET_VEXPRESS64_BASER_FVP + bool "Support Versatile Express ARMv8r64 FVP BASE model" + select VEXPRESS64_BASE_MODEL + imply OF_HAS_PRIOR_STAGE + config TARGET_VEXPRESS64_JUNO bool "Support Versatile Express Juno Development Platform" select PCIE_ECAM_GENERIC if PCI @@ -50,6 +59,7 @@ config LNX_KRNL_IMG_TEXT_OFFSET_BASE config SYS_TEXT_BASE default 0x88000000 if TARGET_VEXPRESS64_BASE_FVP default 0xe0000000 if TARGET_VEXPRESS64_JUNO + default 0x00001000 if TARGET_VEXPRESS64_BASER_FVP config SYS_MALLOC_LEN default 0x810000 if TARGET_VEXPRESS64_JUNO @@ -59,11 +69,13 @@ config SYS_MALLOC_F_LEN default 0x2000 config SYS_LOAD_ADDR + default 0x10000000 if TARGET_VEXPRESS64_BASER_FVP default 0x90000000 config ENV_ADDR default 0x0BFC0000 if TARGET_VEXPRESS64_JUNO default 0x0FFC0000 if TARGET_VEXPRESS64_BASE_FVP + default 0x8FFC0000 if TARGET_VEXPRESS64_BASER_FVP config ENV_SIZE default 0x10000 if TARGET_VEXPRESS64_JUNO diff --git a/board/armltd/vexpress64/MAINTAINERS b/board/armltd/vexpress64/MAINTAINERS index 0ba044d..b3ecc9b 100644 --- a/board/armltd/vexpress64/MAINTAINERS +++ b/board/armltd/vexpress64/MAINTAINERS @@ -14,3 +14,8 @@ JUNO DEVELOPMENT PLATFORM BOARD M: Linus Walleij S: Maintained F: configs/vexpress_aemv8a_juno_defconfig + +VEXPRESS64 ARMV8R-64 +M: Peter Hoyes +S: Maintained +F: configs/vexpress_aemv8r_defconfig diff --git a/configs/vexpress_aemv8r_defconfig b/configs/vexpress_aemv8r_defconfig new file mode 100644 index 0000000..612797e --- /dev/null +++ b/configs/vexpress_aemv8r_defconfig @@ -0,0 +1,14 @@ +CONFIG_ARM=y +CONFIG_ARCH_VEXPRESS64=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_DEFAULT_DEVICE_TREE="arm_fvp" +CONFIG_IDENT_STRING=" vexpress_aemv8r64" +CONFIG_TARGET_VEXPRESS64_BASER_FVP=y +CONFIG_REMAKE_ELF=y +CONFIG_BOOTDELAY=3 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyAMA0 earlycon=pl011,0x9c090000 rootfstype=ext4 root=/dev/vda2 rw rootwait" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_SYS_PROMPT="VExpress64# " +# CONFIG_MMC is not set +CONFIG_VIRTIO_MMIO=y diff --git a/doc/arch/arm64.rst b/doc/arch/arm64.rst index 80498f6..7c07135 100644 --- a/doc/arch/arm64.rst +++ b/doc/arch/arm64.rst @@ -18,7 +18,8 @@ Notes classical firmware (like initial hardware setup, CPU errata workarounds or SMP bringup). U-Boot can be entered in EL2 when its main purpose is that of a boot loader. It can drop to lower exception levels before - entering the OS. + entering the OS. For ARMv8-R it is recommened to enter at S-EL1, as for this + architecture there is no S-EL3. 2. U-Boot for arm64 is compiled with AArch64-gcc. AArch64-gcc use rela relocation format, a tool(tools/relocate-rela) by Scott Wood diff --git a/doc/board/armltd/vexpress64.rst b/doc/board/armltd/vexpress64.rst index d87b1c3..a7f771d 100644 --- a/doc/board/armltd/vexpress64.rst +++ b/doc/board/armltd/vexpress64.rst @@ -6,6 +6,7 @@ Arm Versatile Express The vexpress_* board configuration supports the following platforms: * FVP_Base_RevC-2xAEMvA + * FVP_BaseR_AEMv8R * Juno development board Fixed Virtual Platforms diff --git a/include/configs/vexpress_aemv8.h b/include/configs/vexpress_aemv8.h index e0f9bbe..efffea9 100644 --- a/include/configs/vexpress_aemv8.h +++ b/include/configs/vexpress_aemv8.h @@ -20,8 +20,13 @@ #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ /* CS register bases for the original memory map. */ +#ifdef CONFIG_TARGET_VEXPRESS64_BASER_FVP +#define V2M_DRAM_BASE 0x00000000 +#define V2M_PA_BASE 0x80000000 +#else #define V2M_DRAM_BASE 0x80000000 #define V2M_PA_BASE 0x00000000 +#endif #define V2M_PA_CS0 (V2M_PA_BASE + 0x00000000) #define V2M_PA_CS1 (V2M_PA_BASE + 0x14000000) @@ -229,6 +234,24 @@ "boot_name=boot.img\0" \ "boot_addr_r=" __stringify(VEXPRESS_BOOT_ADDR) "\0" +#elif CONFIG_TARGET_VEXPRESS64_BASER_FVP /* ARMv8-R base model */ + +#define BOOT_TARGET_DEVICES(func) \ + func(MEM, mem, na) \ + FUNC_VIRTIO(func) \ + func(PXE, pxe, na) \ + func(DHCP, dhcp, na) + +#define VEXPRESS_KERNEL_ADDR 0x00200000 +#define VEXPRESS_PXEFILE_ADDR 0x0fb00000 +#define VEXPRESS_FDT_ADDR 0x0fc00000 +#define VEXPRESS_SCRIPT_ADDR 0x0fd00000 +#define VEXPRESS_RAMDISK_ADDR 0x0fe00000 + +#define EXTRA_ENV_NAMES \ + "kernel_name=Image\0" \ + "ramdisk_name=ramdisk.img\0" \ + "fdtfile=board.dtb\0" #endif #include -- cgit v1.1 From d0ed9b10810f17c5b5cb2ee962c6d4df29a65a9c Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Tue, 22 Mar 2022 16:59:09 -0400 Subject: doc: Convert semihosting readme to rST This converts the semihosting readme to rST. I have tried to make only cosmetic changes, but I did fix up the first link (which was broken). Signed-off-by: Sean Anderson --- doc/README.semihosting | 38 -------------------------------------- doc/usage/index.rst | 1 + doc/usage/semihosting.rst | 43 +++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 44 insertions(+), 38 deletions(-) delete mode 100644 doc/README.semihosting create mode 100644 doc/usage/semihosting.rst diff --git a/doc/README.semihosting b/doc/README.semihosting deleted file mode 100644 index f382d01..0000000 --- a/doc/README.semihosting +++ /dev/null @@ -1,38 +0,0 @@ -SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2014 Broadcom Corporation. - */ - -Semihosting is ARM's way of having a real or virtual target communicate -with a host or host debugger for basic operations such as file I/O, -console I/O, etc. Please see -http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0471c/Bgbjjgij.html for more information. - -For developing on armv8 virtual fastmodel platforms, semihosting is a -valuable tool since it allows access to image/configuration files before -eMMC or other NV media are available. - -There are two main ARM virtual Fixed Virtual Platform (FVP) models, -Versatile Express (VE) FVP and BASE FVP (See -http://www.arm.com/products/tools/models/fast-models/foundation-model.php) -The initial vexpress64 u-boot board created here runs on the VE virtual -platform using the license-free Foundation_v8 simulator. Fortunately, -the Foundation_v8 simulator also supports the BASE_FVP model which -companies can purchase licenses for and contain much more functionality. -So we can, in u-boot, run either model by either using the VE FVP (default), -or turning on CONFIG_BASE_FVP for the more full featured model. - -Rather than create a new armv8 board similar to armltd/vexpress64, add -semihosting calls to the existing one, enabled with CONFIG_SEMIHOSTING -and CONFIG_BASE_FVP both set. Also reuse the existing board config file -vexpress_aemv8.h but differentiate the two models by the presence or -absence of CONFIG_BASE_FVP. This change is tested and works on both the -Foundation and Base fastmodel simulators. - -The semihosting code adds a command: - - smhload
[env var] - -That will load an image from the host filesystem into RAM at the specified -address and optionally store the load end address in the specified -environment variable. diff --git a/doc/usage/index.rst b/doc/usage/index.rst index 5b42579..3e52053 100644 --- a/doc/usage/index.rst +++ b/doc/usage/index.rst @@ -11,6 +11,7 @@ Use U-Boot netconsole partitions cmdline + semihosting Shell commands -------------- diff --git a/doc/usage/semihosting.rst b/doc/usage/semihosting.rst new file mode 100644 index 0000000..ed16e4d --- /dev/null +++ b/doc/usage/semihosting.rst @@ -0,0 +1,43 @@ +.. SPDX-License-Identifier: GPL-2.0+ +.. Copyright 2014 Broadcom Corporation. + +Semihosting +=========== + +Semihosting is ARM's way of having a real or virtual target communicate +with a host or host debugger for basic operations such as file I/O, +console I/O, etc. Please see `Arm's semihosting documentation +`_ for more +information. + +For developing on armv8 virtual fastmodel platforms, semihosting is a +valuable tool since it allows access to image/configuration files before +eMMC or other NV media are available. + +There are two main ARM virtual Fixed Virtual Platform (FVP) models, +`Versatile Express (VE) FVP and BASE FVP +`_. +The initial vexpress64 u-boot board created here runs on the VE virtual +platform using the license-free Foundation_v8 simulator. Fortunately, +the Foundation_v8 simulator also supports the BASE_FVP model which +companies can purchase licenses for and contain much more functionality. +So we can, in U-Boot, run either model by either using the VE FVP (default), +or turning on ``CONFIG_BASE_FVP`` for the more full featured model. + +Rather than create a new armv8 board similar to ``armltd/vexpress64``, add +semihosting calls to the existing one, enabled with ``CONFIG_SEMIHOSTING`` +and ``CONFIG_BASE_FVP`` both set. Also reuse the existing board config file +vexpress_aemv8.h but differentiate the two models by the presence or +absence of ``CONFIG_BASE_FVP``. This change is tested and works on both the +Foundation and Base fastmodel simulators. + +Loading files +------------- + +The semihosting code adds a "hostfs":: + + smhload
[env var] + +That will load an image from the host filesystem into RAM at the specified +address and optionally store the load end address in the specified +environment variable. -- cgit v1.1 From 71230cdaa9597d410f1e8aca62ea5a0daeebc0ac Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Tue, 22 Mar 2022 16:59:10 -0400 Subject: nxp: ls1046ardb: Convert README to rST This converts the readme for this board to rST. I have tried not to change any semantics from the original (though I did convert MB to M). Signed-off-by: Sean Anderson --- board/freescale/ls1046ardb/MAINTAINERS | 1 + board/freescale/ls1046ardb/README | 76 ------------------------- doc/board/nxp/index.rst | 1 + doc/board/nxp/ls1046ardb.rst | 100 +++++++++++++++++++++++++++++++++ 4 files changed, 102 insertions(+), 76 deletions(-) delete mode 100644 board/freescale/ls1046ardb/README create mode 100644 doc/board/nxp/ls1046ardb.rst diff --git a/board/freescale/ls1046ardb/MAINTAINERS b/board/freescale/ls1046ardb/MAINTAINERS index efdea22..3c8cfe7 100644 --- a/board/freescale/ls1046ardb/MAINTAINERS +++ b/board/freescale/ls1046ardb/MAINTAINERS @@ -14,3 +14,4 @@ F: configs/ls1046ardb_tfa_SECURE_BOOT_defconfig F: configs/ls1046ardb_SECURE_BOOT_defconfig F: configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig F: configs/ls1046ardb_qspi_SECURE_BOOT_defconfig +F: doc/board/nxp/ls1046ardb.rst diff --git a/board/freescale/ls1046ardb/README b/board/freescale/ls1046ardb/README deleted file mode 100644 index 90c44f4..0000000 --- a/board/freescale/ls1046ardb/README +++ /dev/null @@ -1,76 +0,0 @@ -Overview --------- -The LS1046A Reference Design Board (RDB) is a high-performance computing, -evaluation, and development platform that supports the QorIQ LS1046A -LayerScape Architecture processor. The LS1046ARDB provides SW development -platform for the Freescale LS1046A processor series, with a complete -debugging environment. The LS1046A RDB is lead-free and RoHS-compliant. - -LS1046A SoC Overview --------------------- -Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1046A -SoC overview. - - LS1046ARDB board Overview - ----------------------- - - SERDES1 Connections, 4 lanes supporting: - - Lane0: 10GBase-R with x1 RJ45 connector - - Lane1: 10GBase-R Cage - - Lane2: SGMII.5 - - Lane3: SGMII.6 - - SERDES2 Connections, 4 lanes supporting: - - Lane0: PCIe1 with miniPCIe slot - - Lane1: PCIe2 with PCIe x2 slot - - Lane2: PCIe3 with PCIe x4 slot - - Lane3: SATA - - DDR Controller - - 8GB 64bits DDR4 SDRAM. Support rates of up to 2133MT/s - -IFC/Local Bus - - One 512 MB NAND flash with ECC support - - CPLD connection - - USB 3.0 - - one Type A port, one Micro-AB port - - SDHC: connects directly to a full SD/MMC slot - - DSPI: 64 MB high-speed flash Memory for boot code and storage (up to 108MHz) - - 4 I2C controllers - - UART - - Two 4-pin serial ports at up to 115.2 Kbit/s - - Two DB9 D-Type connectors supporting one Serial port each - - ARM JTAG support - -Memory map from core's view ----------------------------- -Start Address End Address Description Size -0x00_0000_0000 - 0x00_000F_FFFF Secure Boot ROM 1MB -0x00_0100_0000 - 0x00_0FFF_FFFF CCSRBAR 240MB -0x00_1000_0000 - 0x00_1000_FFFF OCRAM0 64KB -0x00_1001_0000 - 0x00_1001_FFFF OCRAM1 64KB -0x00_2000_0000 - 0x00_20FF_FFFF DCSR 16MB -0x00_7E80_0000 - 0x00_7E80_FFFF IFC - NAND Flash 64KB -0x00_7FB0_0000 - 0x00_7FB0_0FFF IFC - CPLD 4KB -0x00_8000_0000 - 0x00_FFFF_FFFF DRAM1 2GB -0x05_0000_0000 - 0x05_07FF_FFFF QMAN S/W Portal 128M -0x05_0800_0000 - 0x05_0FFF_FFFF BMAN S/W Portal 128M -0x08_8000_0000 - 0x09_FFFF_FFFF DRAM2 6GB -0x40_0000_0000 - 0x47_FFFF_FFFF PCI Express1 32G -0x48_0000_0000 - 0x4F_FFFF_FFFF PCI Express2 32G -0x50_0000_0000 - 0x57_FFFF_FFFF PCI Express3 32G - -QSPI flash map: -Start Address End Address Description Size -0x00_4000_0000 - 0x00_400F_FFFF RCW + PBI 1MB -0x00_4010_0000 - 0x00_402F_FFFF U-Boot 2MB -0x00_4030_0000 - 0x00_403F_FFFF U-Boot Env 1MB -0x00_4040_0000 - 0x00_405F_FFFF PPA 2MB -0x00_4060_0000 - 0x00_408F_FFFF Secure boot header - + bootscript 3MB -0x00_4090_0000 - 0x00_4093_FFFF FMan ucode 256KB -0x00_4094_0000 - 0x00_4097_FFFF QE/uQE firmware 256KB -0x00_4098_0000 - 0x00_40FF_FFFF Reserved 6MB -0x00_4100_0000 - 0x00_43FF_FFFF FIT Image 48MB - -Booting Options ---------------- -a) QSPI boot -b) SD boot -c) eMMC boot diff --git a/doc/board/nxp/index.rst b/doc/board/nxp/index.rst index 6395628..4514b89 100644 --- a/doc/board/nxp/index.rst +++ b/doc/board/nxp/index.rst @@ -13,6 +13,7 @@ NXP Semiconductors imx8qxp_mek imxrt1020-evk imxrt1050-evk + ls1046ardb mx6sabreauto mx6sabresd mx6ul_14x14_evk diff --git a/doc/board/nxp/ls1046ardb.rst b/doc/board/nxp/ls1046ardb.rst new file mode 100644 index 0000000..4bfeaa9 --- /dev/null +++ b/doc/board/nxp/ls1046ardb.rst @@ -0,0 +1,100 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +LS1046ARDB +========== + +The LS1046A Reference Design Board (RDB) is a high-performance computing, +evaluation, and development platform that supports the QorIQ LS1046A +LayerScape Architecture processor. The LS1046ARDB provides SW development +platform for the Freescale LS1046A processor series, with a complete +debugging environment. The LS1046A RDB is lead-free and RoHS-compliant. + +LS1046A SoC Overview +-------------------- +Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1046A +SoC overview. + +LS1046ARDB board Overview +------------------------- +- SERDES1 Connections, 4 lanes supporting: + + - Lane0: 10GBase-R with x1 RJ45 connector + - Lane1: 10GBase-R Cage + - Lane2: SGMII.5 + - Lane3: SGMII.6 + +- SERDES2 Connections, 4 lanes supporting: + + - Lane0: PCIe1 with miniPCIe slot + - Lane1: PCIe2 with PCIe x2 slot + - Lane2: PCIe3 with PCIe x4 slot + - Lane3: SATA + +- DDR Controller + + - 8GB 64bits DDR4 SDRAM. Support rates of up to 2133MT/s + +- IFC/Local Bus + + - One 512 MB NAND flash with ECC support + - CPLD connection + +- USB 3.0 + + - one Type A port, one Micro-AB port + +- SDHC: connects directly to a full SD/MMC slot +- DSPI: 64 MB high-speed flash Memory for boot code and storage (up to 108MHz) +- 4 I2C controllers +- UART + + - Two 4-pin serial ports at up to 115.2 Kbit/s + - Two DB9 D-Type connectors supporting one Serial port each + +- ARM JTAG support + +Memory map from core's view +---------------------------- + +================== ================== ================ ===== +Start Address End Address Description Size +================== ================== ================ ===== +``0x00_0000_0000`` ``0x00_000F_FFFF`` Secure Boot ROM 1M +``0x00_0100_0000`` ``0x00_0FFF_FFFF`` CCSRBAR 240M +``0x00_1000_0000`` ``0x00_1000_FFFF`` OCRAM0 64K +``0x00_1001_0000`` ``0x00_1001_FFFF`` OCRAM1 64K +``0x00_2000_0000`` ``0x00_20FF_FFFF`` DCSR 16M +``0x00_7E80_0000`` ``0x00_7E80_FFFF`` IFC - NAND Flash 64K +``0x00_7FB0_0000`` ``0x00_7FB0_0FFF`` IFC - CPLD 4K +``0x00_8000_0000`` ``0x00_FFFF_FFFF`` DRAM1 2G +``0x05_0000_0000`` ``0x05_07FF_FFFF`` QMAN S/W Portal 128M +``0x05_0800_0000`` ``0x05_0FFF_FFFF`` BMAN S/W Portal 128M +``0x08_8000_0000`` ``0x09_FFFF_FFFF`` DRAM2 6G +``0x40_0000_0000`` ``0x47_FFFF_FFFF`` PCI Express1 32G +``0x48_0000_0000`` ``0x4F_FFFF_FFFF`` PCI Express2 32G +``0x50_0000_0000`` ``0x57_FFFF_FFFF`` PCI Express3 32G +================== ================== ================ ===== + +QSPI flash map +-------------- + +================== ================== ================== ===== +Start Address End Address Description Size +================== ================== ================== ===== +``0x00_4000_0000`` ``0x00_400F_FFFF`` RCW + PBI 1M +``0x00_4010_0000`` ``0x00_402F_FFFF`` U-Boot 2M +``0x00_4030_0000`` ``0x00_403F_FFFF`` U-Boot Env 1M +``0x00_4040_0000`` ``0x00_405F_FFFF`` PPA 2M +``0x00_4060_0000`` ``0x00_408F_FFFF`` Secure boot header 3M + + bootscript +``0x00_4090_0000`` ``0x00_4093_FFFF`` FMan ucode 256K +``0x00_4094_0000`` ``0x00_4097_FFFF`` QE/uQE firmware 256K +``0x00_4098_0000`` ``0x00_40FF_FFFF`` Reserved 6M +``0x00_4100_0000`` ``0x00_43FF_FFFF`` FIT Image 48M +================== ================== ================== ===== + +Booting Options +--------------- +- QSPI boot +- SD boot +- eMMC boot -- cgit v1.1 From b5ec417b56bfbd6685247f58a26592052ab0f42e Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Tue, 22 Mar 2022 16:59:11 -0400 Subject: doc: ls1046ardb: Expand boot mode section This adds some additional info about booting from different sources, including the correct switch positions. Signed-off-by: Sean Anderson --- doc/board/nxp/ls1046ardb.rst | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) diff --git a/doc/board/nxp/ls1046ardb.rst b/doc/board/nxp/ls1046ardb.rst index 4bfeaa9..c73516c 100644 --- a/doc/board/nxp/ls1046ardb.rst +++ b/doc/board/nxp/ls1046ardb.rst @@ -95,6 +95,17 @@ Start Address End Address Description Size Booting Options --------------- -- QSPI boot -- SD boot -- eMMC boot + +NB: The reference manual documents the RCW source with the *least-significant +bit first*. + +QSPI boot +^^^^^^^^^ + +This is the default. ``{ SW5[0:8], SW4[0] }`` should be ``0010_0010_0``. + +SD boot and eMMC boot +^^^^^^^^^^^^^^^^^^^^^ + +``{ SW5[0:8], SW4[0] }`` should be ``0010_0000_0``. eMMC is selected only if +there is no SD card in the slot. -- cgit v1.1 From e5e982c69bc6c90c62e5c080d1746bf6cdcc56c8 Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Tue, 22 Mar 2022 16:59:12 -0400 Subject: doc: ls1046ardb: Document debug uart This adds some instructions for enabling the debug uart, including the correct address and clock rate. Signed-off-by: Sean Anderson --- doc/board/nxp/ls1046ardb.rst | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/doc/board/nxp/ls1046ardb.rst b/doc/board/nxp/ls1046ardb.rst index c73516c..e4499a1 100644 --- a/doc/board/nxp/ls1046ardb.rst +++ b/doc/board/nxp/ls1046ardb.rst @@ -109,3 +109,12 @@ SD boot and eMMC boot ``{ SW5[0:8], SW4[0] }`` should be ``0010_0000_0``. eMMC is selected only if there is no SD card in the slot. + +Debug UART +---------- + +To enable the debug UART, enable the following config options:: + + CONFIG_DEBUG_UART_NS16550=y + CONFIG_DEBUG_UART_BASE=0x21c0500 + CONFIG_DEBUG_UART_CLOCK=300000000 -- cgit v1.1 From c8f4cc9590c480f962451344a4c795b1503c1359 Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Tue, 22 Mar 2022 16:59:13 -0400 Subject: arm: smh: Add semihosting entry to MAINTAINERS These files are spread all over the tree, so just use a regex. Orphaned for now, since this is more of a "one-off" series. Though I'll be happy to review patches. Signed-off-by: Sean Anderson --- MAINTAINERS | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 74d5263..d36e649 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1173,6 +1173,11 @@ F: arch/sandbox/ F: doc/arch/sandbox.rst F: include/dt-bindings/*/sandbox*.h +SEMIHOSTING +R: Sean Anderson +S: Orphaned +N: semihosting + SETEXPR M: Roland Gaudig S: Maintained -- cgit v1.1 From b10f724807312a996100c7c4b779d320ed40d573 Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Tue, 22 Mar 2022 16:59:14 -0400 Subject: arm: smh: Export semihosting functions This exports semihosting functions for use in other files. The header is in include/ and not arm/include/asm because I anticipate that RISC-V may want to add their own implementation at some point. smh_len_fd has been renamed to smh_flen to more closely match the semihosting spec. Signed-off-by: Sean Anderson --- arch/arm/lib/semihosting.c | 11 ++++++----- include/semihosting.h | 14 ++++++++++++++ 2 files changed, 20 insertions(+), 5 deletions(-) create mode 100644 include/semihosting.h diff --git a/arch/arm/lib/semihosting.c b/arch/arm/lib/semihosting.c index 9fd8245..c38892f 100644 --- a/arch/arm/lib/semihosting.c +++ b/arch/arm/lib/semihosting.c @@ -15,6 +15,7 @@ #include #include #include +#include #define SYSOPEN 0x01 #define SYSCLOSE 0x02 @@ -45,7 +46,7 @@ static noinline long smh_trap(unsigned int sysnum, void *addr) * Open a file on the host. Mode is "r" or "rb" currently. Returns a file * descriptor or -1 on error. */ -static long smh_open(const char *fname, char *modestr) +long smh_open(const char *fname, char *modestr) { long fd; unsigned long mode; @@ -84,7 +85,7 @@ static long smh_open(const char *fname, char *modestr) /* * Read 'len' bytes of file into 'memp'. Returns 0 on success, else failure */ -static long smh_read(long fd, void *memp, size_t len) +long smh_read(long fd, void *memp, size_t len) { long ret; struct smh_read_s { @@ -118,7 +119,7 @@ static long smh_read(long fd, void *memp, size_t len) /* * Close the file using the file descriptor */ -static long smh_close(long fd) +long smh_close(long fd) { long ret; @@ -134,7 +135,7 @@ static long smh_close(long fd) /* * Get the file length from the file descriptor */ -static long smh_len_fd(long fd) +long smh_flen(long fd) { long ret; @@ -158,7 +159,7 @@ static int smh_load_file(const char * const name, ulong load_addr, if (fd == -1) return -1; - len = smh_len_fd(fd); + len = smh_flen(fd); if (len < 0) { smh_close(fd); return -1; diff --git a/include/semihosting.h b/include/semihosting.h new file mode 100644 index 0000000..3843863 --- /dev/null +++ b/include/semihosting.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2022 Sean Anderson + */ + +#ifndef _SEMIHOSTING_H +#define _SEMIHOSTING_H + +long smh_open(const char *fname, char *modestr); +long smh_read(long fd, void *memp, size_t len); +long smh_close(long fd); +long smh_flen(long fd); + +#endif /* _SEMIHOSTING_H */ -- cgit v1.1 From eff77c3a24ff6623f3767816ca54b8124f0e69a7 Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Tue, 22 Mar 2022 16:59:15 -0400 Subject: arm: smh: Use numeric modes for smh_open There's no point in using string constants for smh_open if we are just going to have to parse them. Instead, use numeric modes. The user needs to be a bit careful with these, since they are much closer semantically to string modes used by fopen(3) than the numeric modes used with open(2). Signed-off-by: Sean Anderson --- arch/arm/lib/semihosting.c | 21 +++------------------ include/semihosting.h | 25 ++++++++++++++++++++++++- 2 files changed, 27 insertions(+), 19 deletions(-) diff --git a/arch/arm/lib/semihosting.c b/arch/arm/lib/semihosting.c index c38892f..b983cc3 100644 --- a/arch/arm/lib/semihosting.c +++ b/arch/arm/lib/semihosting.c @@ -22,9 +22,6 @@ #define SYSREAD 0x06 #define SYSFLEN 0x0C -#define MODE_READ 0x0 -#define MODE_READBIN 0x1 - /* * Call the handler */ @@ -46,28 +43,16 @@ static noinline long smh_trap(unsigned int sysnum, void *addr) * Open a file on the host. Mode is "r" or "rb" currently. Returns a file * descriptor or -1 on error. */ -long smh_open(const char *fname, char *modestr) +long smh_open(const char *fname, enum smh_open_mode mode) { long fd; - unsigned long mode; struct smh_open_s { const char *fname; unsigned long mode; size_t len; } open; - debug("%s: file \'%s\', mode \'%s\'\n", __func__, fname, modestr); - - /* Check the file mode */ - if (!(strcmp(modestr, "r"))) { - mode = MODE_READ; - } else if (!(strcmp(modestr, "rb"))) { - mode = MODE_READBIN; - } else { - printf("%s: ERROR mode \'%s\' not supported\n", __func__, - modestr); - return -1; - } + debug("%s: file \'%s\', mode \'%u\'\n", __func__, fname, mode); open.fname = fname; open.len = strlen(fname); @@ -155,7 +140,7 @@ static int smh_load_file(const char * const name, ulong load_addr, long len; long ret; - fd = smh_open(name, "rb"); + fd = smh_open(name, MODE_READ | MODE_BINARY); if (fd == -1) return -1; diff --git a/include/semihosting.h b/include/semihosting.h index 3843863..cf54819 100644 --- a/include/semihosting.h +++ b/include/semihosting.h @@ -6,7 +6,30 @@ #ifndef _SEMIHOSTING_H #define _SEMIHOSTING_H -long smh_open(const char *fname, char *modestr); +/** + * enum smh_open_mode - Numeric file modes for use with smh_open() + * MODE_READ: 'r' + * MODE_BINARY: 'b' + * MODE_PLUS: '+' + * MODE_WRITE: 'w' + * MODE_APPEND: 'a' + * + * These modes represent the mode string used by fopen(3) in a form which can + * be passed to smh_open(). These do NOT correspond directly to %O_RDONLY, + * %O_CREAT, etc; see fopen(3) for details. In particular, @MODE_PLUS + * effectively results in adding %O_RDWR, and @MODE_WRITE will add %O_TRUNC. + * For compatibility, @MODE_BINARY should be added when opening non-text files + * (such as images). + */ +enum smh_open_mode { + MODE_READ = 0x0, + MODE_BINARY = 0x1, + MODE_PLUS = 0x2, + MODE_WRITE = 0x4, + MODE_APPEND = 0x8, +}; + +long smh_open(const char *fname, enum smh_open_mode mode); long smh_read(long fd, void *memp, size_t len); long smh_close(long fd); long smh_flen(long fd); -- cgit v1.1 From 80e62ccfa630b8a5dda479c8d9dc5f8872acb370 Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Tue, 22 Mar 2022 16:59:16 -0400 Subject: arm: smh: Return errno on error Instead of printing in what are now library functions, try to return a numeric error code. This also adjust some functions (such as read) to behave more similarly to read(2). For example, we now return the number of bytes read instead of failing immediately on a short read. Signed-off-by: Sean Anderson --- arch/arm/lib/semihosting.c | 67 +++++++++++++++++++++++++--------------------- 1 file changed, 36 insertions(+), 31 deletions(-) diff --git a/arch/arm/lib/semihosting.c b/arch/arm/lib/semihosting.c index b983cc3..1686457 100644 --- a/arch/arm/lib/semihosting.c +++ b/arch/arm/lib/semihosting.c @@ -21,6 +21,7 @@ #define SYSCLOSE 0x02 #define SYSREAD 0x06 #define SYSFLEN 0x0C +#define SYSERRNO 0x13 /* * Call the handler @@ -39,10 +40,24 @@ static noinline long smh_trap(unsigned int sysnum, void *addr) return result; } -/* - * Open a file on the host. Mode is "r" or "rb" currently. Returns a file - * descriptor or -1 on error. +/** + * smh_errno() - Read the host's errno + * + * This gets the value of the host's errno and negates it. The host's errno may + * or may not be set, so only call this function if a previous semihosting call + * has failed. + * + * Return: a negative error value */ +static int smh_errno(void) +{ + long ret = smh_trap(SYSERRNO, NULL); + + if (ret > 0 && ret < INT_MAX) + return -ret; + return -EIO; +} + long smh_open(const char *fname, enum smh_open_mode mode) { long fd; @@ -61,9 +76,7 @@ long smh_open(const char *fname, enum smh_open_mode mode) /* Open the file on the host */ fd = smh_trap(SYSOPEN, &open); if (fd == -1) - printf("%s: ERROR fd %ld for file \'%s\'\n", __func__, fd, - fname); - + return smh_errno(); return fd; } @@ -86,19 +99,9 @@ long smh_read(long fd, void *memp, size_t len) read.len = len; ret = smh_trap(SYSREAD, &read); - if (ret < 0) { - /* - * The ARM handler allows for returning partial lengths, - * but in practice this never happens so rather than create - * hard to maintain partial read loops and such, just fail - * with an error message. - */ - printf("%s: ERROR ret %ld, fd %ld, len %zu memp %p\n", - __func__, ret, fd, len, memp); - return -1; - } - - return 0; + if (ret < 0) + return smh_errno(); + return len - ret; } /* @@ -112,9 +115,8 @@ long smh_close(long fd) ret = smh_trap(SYSCLOSE, &fd); if (ret == -1) - printf("%s: ERROR fd %ld\n", __func__, fd); - - return ret; + return smh_errno(); + return 0; } /* @@ -128,8 +130,7 @@ long smh_flen(long fd) ret = smh_trap(SYSFLEN, &fd); if (ret == -1) - printf("%s: ERROR ret %ld, fd %ld\n", __func__, ret, fd); - + return smh_errno(); return ret; } @@ -141,28 +142,32 @@ static int smh_load_file(const char * const name, ulong load_addr, long ret; fd = smh_open(name, MODE_READ | MODE_BINARY); - if (fd == -1) - return -1; + if (fd < 0) + return fd; len = smh_flen(fd); if (len < 0) { smh_close(fd); - return -1; + return len; } ret = smh_read(fd, (void *)load_addr, len); smh_close(fd); - if (ret == 0) { + if (ret == len) { *end_addr = load_addr + len - 1; printf("loaded file %s from %08lX to %08lX, %08lX bytes\n", name, load_addr, *end_addr, len); - } else { - printf("read failed\n"); - return 0; + } else if (ret >= 0) { + ret = -EAGAIN; + } + + if (ret < 0) { + printf("read failed: %ld\n", ret); + return ret; } return 0; -- cgit v1.1 From 79f6ad6a7b9c30bacb135b91a268fd9767bca79d Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Tue, 22 Mar 2022 16:59:17 -0400 Subject: arm: smh: Document functions in header This adds some documentation for semihosting functions in the header. Signed-off-by: Sean Anderson --- arch/arm/lib/semihosting.c | 9 --------- include/semihosting.h | 32 ++++++++++++++++++++++++++++++++ 2 files changed, 32 insertions(+), 9 deletions(-) diff --git a/arch/arm/lib/semihosting.c b/arch/arm/lib/semihosting.c index 1686457..2943f7b 100644 --- a/arch/arm/lib/semihosting.c +++ b/arch/arm/lib/semihosting.c @@ -80,9 +80,6 @@ long smh_open(const char *fname, enum smh_open_mode mode) return fd; } -/* - * Read 'len' bytes of file into 'memp'. Returns 0 on success, else failure - */ long smh_read(long fd, void *memp, size_t len) { long ret; @@ -104,9 +101,6 @@ long smh_read(long fd, void *memp, size_t len) return len - ret; } -/* - * Close the file using the file descriptor - */ long smh_close(long fd) { long ret; @@ -119,9 +113,6 @@ long smh_close(long fd) return 0; } -/* - * Get the file length from the file descriptor - */ long smh_flen(long fd) { long ret; diff --git a/include/semihosting.h b/include/semihosting.h index cf54819..d8337b6 100644 --- a/include/semihosting.h +++ b/include/semihosting.h @@ -29,9 +29,41 @@ enum smh_open_mode { MODE_APPEND = 0x8, }; +/** + * smh_open() - Open a file on the host + * @fname: The name of the file to open + * @mode: The mode to use when opening the file + * + * Return: Either a file descriptor or a negative error on failure + */ long smh_open(const char *fname, enum smh_open_mode mode); + +/** + * smh_read() - Read data from a file + * @fd: A file descriptor returned from smh_open() + * @memp: Pointer to a buffer of memory of at least @len bytes + * @len: The number of bytes to read + * + * Return: + * * The number of bytes read on success, with 0 indicating %EOF + * * A negative error on failure + */ long smh_read(long fd, void *memp, size_t len); + +/** + * smh_close() - Close an open file + * @fd: A file descriptor returned from smh_open() + * + * Return: 0 on success or negative error on failure + */ long smh_close(long fd); + +/** + * smh_flen() - Get the length of a file + * @fd: A file descriptor returned from smh_open() + * + * Return: The length of the file, in bytes, or a negative error on failure + */ long smh_flen(long fd); #endif /* _SEMIHOSTING_H */ -- cgit v1.1 From 12a05b3bcd85ff4aa930e7a1fb8795d5a6bfdf81 Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Tue, 22 Mar 2022 16:59:18 -0400 Subject: arm: smh: Add some file manipulation commands In order to add filesystem support, we will need to be able to seek and write files. Add the appropriate helper functions. Signed-off-by: Sean Anderson --- arch/arm/lib/semihosting.c | 67 ++++++++++++++++++++++++++++++++++++++-------- include/semihosting.h | 20 ++++++++++++++ 2 files changed, 76 insertions(+), 11 deletions(-) diff --git a/arch/arm/lib/semihosting.c b/arch/arm/lib/semihosting.c index 2943f7b..d08003c 100644 --- a/arch/arm/lib/semihosting.c +++ b/arch/arm/lib/semihosting.c @@ -1,15 +1,13 @@ // SPDX-License-Identifier: GPL-2.0+ /* + * Copyright (C) 2022 Sean Anderson * Copyright 2014 Broadcom Corporation */ /* - * Minimal semihosting implementation for reading files into memory. If more - * features like writing files or console output are required they can be - * added later. This code has been tested on arm64/aarch64 fastmodel only. - * An untested placeholder exists for armv7 architectures, but since they - * are commonly available in silicon now, fastmodel usage makes less sense - * for them. + * This code has been tested on arm64/aarch64 fastmodel only. An untested + * placeholder exists for armv7 architectures, but since they are commonly + * available in silicon now, fastmodel usage makes less sense for them. */ #include #include @@ -19,7 +17,9 @@ #define SYSOPEN 0x01 #define SYSCLOSE 0x02 +#define SYSWRITE 0x05 #define SYSREAD 0x06 +#define SYSSEEK 0x0A #define SYSFLEN 0x0C #define SYSERRNO 0x13 @@ -80,14 +80,22 @@ long smh_open(const char *fname, enum smh_open_mode mode) return fd; } +/** + * struct smg_rdwr_s - Arguments for read and write + * @fd: A file descriptor returned from smh_open() + * @memp: Pointer to a buffer of memory of at least @len bytes + * @len: The number of bytes to read or write + */ +struct smh_rdwr_s { + long fd; + void *memp; + size_t len; +}; + long smh_read(long fd, void *memp, size_t len) { long ret; - struct smh_read_s { - long fd; - void *memp; - size_t len; - } read; + struct smh_rdwr_s read; debug("%s: fd %ld, memp %p, len %zu\n", __func__, fd, memp, len); @@ -101,6 +109,24 @@ long smh_read(long fd, void *memp, size_t len) return len - ret; } +long smh_write(long fd, const void *memp, size_t len, ulong *written) +{ + long ret; + struct smh_rdwr_s write; + + debug("%s: fd %ld, memp %p, len %zu\n", __func__, fd, memp, len); + + write.fd = fd; + write.memp = (void *)memp; + write.len = len; + + ret = smh_trap(SYSWRITE, &write); + *written = len - ret; + if (ret) + return smh_errno(); + return 0; +} + long smh_close(long fd) { long ret; @@ -125,6 +151,25 @@ long smh_flen(long fd) return ret; } +long smh_seek(long fd, long pos) +{ + long ret; + struct smh_seek_s { + long fd; + long pos; + } seek; + + debug("%s: fd %ld pos %ld\n", __func__, fd, pos); + + seek.fd = fd; + seek.pos = pos; + + ret = smh_trap(SYSSEEK, &seek); + if (ret) + return smh_errno(); + return 0; +} + static int smh_load_file(const char * const name, ulong load_addr, ulong *end_addr) { diff --git a/include/semihosting.h b/include/semihosting.h index d8337b6..b53c650 100644 --- a/include/semihosting.h +++ b/include/semihosting.h @@ -51,6 +51,17 @@ long smh_open(const char *fname, enum smh_open_mode mode); long smh_read(long fd, void *memp, size_t len); /** + * smh_write() - Write data to a file + * @fd: A file descriptor returned from smh_open() + * @memp: Pointer to a buffer of memory of at least @len bytes + * @len: The number of bytes to read + * @written: Pointer which will be updated with the actual bytes written + * + * Return: 0 on success or negative error on failure + */ +long smh_write(long fd, const void *memp, size_t len, ulong *written); + +/** * smh_close() - Close an open file * @fd: A file descriptor returned from smh_open() * @@ -66,4 +77,13 @@ long smh_close(long fd); */ long smh_flen(long fd); +/** + * smh_seek() - Seek to a position in a file + * @fd: A file descriptor returned from smh_open() + * @pos: The offset (in bytes) to seek to + * + * Return: 0 on success or negative error on failure + */ +long smh_seek(long fd, long pos); + #endif /* _SEMIHOSTING_H */ -- cgit v1.1 From 8e1c9fe243a31a0b0a40a80cc20fc3c06246d675 Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Tue, 22 Mar 2022 16:59:19 -0400 Subject: spl: Add semihosting boot method This adds a boot method for loading the next stage from the host. It is mostly modeled off of spl_load_image_ext. I am not really sure why/how spl_load_image_fat uses three different methods to load the image, but the simple case seems to work OK for now. To control the presence of this boot method, we add a config symbol. While we're at it, we update the original semihosting config symbol. I think semihosting has some advantages of other forms of JTAG boot. Common other ways to boot from JTAG include: - Implementing DDR initialization through JTAG (typically with dozens of lines of TCL) and then loading U-Boot. The DDR initialization typically uses hard-coded register writes, and is not easily adapted to different boards. BOOT_DEVICE_SMH allows booting with SPL, leveraging U-Boot's existing DDR initialization code. This is the method used by NXP's CodeWarrior IDE on Layerscape processors (see AN12270). - Loading a bootloader into SDRAM, waiting for it to initialize DDR, and then loading U-Boot. This is tricky, because the debugger must stop the boot after the bootloader has completed its work. Trying to load U-Boot too early can cause failure to boot. This is the method used by Xilinx with its Zynq(MP) processors. - Loading SPL with BOOT_DEVICE_RAM and breaking before SPL loads the image to load U-Boot at the appropriate place. This can be a bit tricky, because the load address is dependent on the header size. An elf with symbols must also be used in order to stop at the appropriate point. BOOT_DEVICE_SMH can be viewed as an extension of this process, where SPL automatically stops and tells the host where to place the image. Signed-off-by: Sean Anderson --- arch/arm/Kconfig | 26 +++++++++++++--- arch/arm/include/asm/spl.h | 1 + arch/arm/lib/Makefile | 2 +- common/spl/Makefile | 1 + common/spl/spl_semihosting.c | 71 ++++++++++++++++++++++++++++++++++++++++++++ 5 files changed, 96 insertions(+), 5 deletions(-) create mode 100644 common/spl/spl_semihosting.c diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 1f2b849..b2e2873 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -403,11 +403,29 @@ config ARM_SMCCC firmware (for example, PSCI) according to SMCCC. config SEMIHOSTING - bool "support boot from semihosting" + bool "Support ARM semihosting" help - In emulated environments, semihosting is a way for - the hosted environment to call out to the emulator to - retrieve files from the host machine. + Semihosting is a method for a target to communicate with a host + debugger. It uses special instructions which the debugger will trap + on and interpret. This allows U-Boot to read/write files, print to + the console, and execute arbitrary commands on the host system. + + Enabling this option will add support for reading and writing files + on the host system. If you don't have a debugger attached then trying + to do this will likely cause U-Boot to hang. Say 'n' if you are unsure. + +config SPL_SEMIHOSTING + bool "Support ARM semihosting in SPL" + depends on SPL + help + Semihosting is a method for a target to communicate with a host + debugger. It uses special instructions which the debugger will trap + on and interpret. This allows U-Boot to read/write files, print to + the console, and execute arbitrary commands on the host system. + + Enabling this option will add support for reading and writing files + on the host system. If you don't have a debugger attached then trying + to do this will likely cause U-Boot to hang. Say 'n' if you are unsure. config SYS_THUMB_BUILD bool "Build U-Boot using the Thumb instruction set" diff --git a/arch/arm/include/asm/spl.h b/arch/arm/include/asm/spl.h index e568af2..b5790bd 100644 --- a/arch/arm/include/asm/spl.h +++ b/arch/arm/include/asm/spl.h @@ -30,6 +30,7 @@ enum { BOOT_DEVICE_DFU, BOOT_DEVICE_XIP, BOOT_DEVICE_BOOTROM, + BOOT_DEVICE_SMH, BOOT_DEVICE_NONE }; #endif diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile index c48e1f6..594fc12 100644 --- a/arch/arm/lib/Makefile +++ b/arch/arm/lib/Makefile @@ -46,7 +46,7 @@ else obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMSET) += memset.o obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMCPY) += memcpy.o endif -obj-$(CONFIG_SEMIHOSTING) += semihosting.o +obj-$(CONFIG_$(SPL_TPL_)SEMIHOSTING) += semihosting.o obj-y += bdinfo.o obj-y += sections.o diff --git a/common/spl/Makefile b/common/spl/Makefile index db8fd36..e71e7be 100644 --- a/common/spl/Makefile +++ b/common/spl/Makefile @@ -28,6 +28,7 @@ obj-$(CONFIG_$(SPL_TPL_)USB_STORAGE) += spl_usb.o obj-$(CONFIG_$(SPL_TPL_)FS_FAT) += spl_fat.o obj-$(CONFIG_$(SPL_TPL_)FS_EXT4) += spl_ext.o obj-$(CONFIG_$(SPL_TPL_)SATA) += spl_sata.o +obj-$(CONFIG_$(SPL_TPL_)SEMIHOSTING) += spl_semihosting.o obj-$(CONFIG_$(SPL_TPL_)DFU) += spl_dfu.o obj-$(CONFIG_$(SPL_TPL_)SPI_LOAD) += spl_spi.o obj-$(CONFIG_$(SPL_TPL_)RAM_SUPPORT) += spl_ram.o diff --git a/common/spl/spl_semihosting.c b/common/spl/spl_semihosting.c new file mode 100644 index 0000000..df6aeb2 --- /dev/null +++ b/common/spl/spl_semihosting.c @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2022 Sean Anderson + */ + +#include +#include +#include +#include +#include + +static int smh_read_full(long fd, void *memp, size_t len) +{ + long read; + + read = smh_read(fd, memp, len); + if (read < 0) + return read; + if (read != len) + return -EIO; + return 0; +} + +static int spl_smh_load_image(struct spl_image_info *spl_image, + struct spl_boot_device *bootdev) +{ + const char *filename = CONFIG_SPL_FS_LOAD_PAYLOAD_NAME; + int ret; + long fd, len; + struct image_header *header = + spl_get_load_buffer(-sizeof(*header), sizeof(*header)); + + fd = smh_open(filename, MODE_READ | MODE_BINARY); + if (fd < 0) { + log_debug("could not open %s: %ld\n", filename, fd); + return fd; + } + + ret = smh_flen(fd); + if (ret < 0) { + log_debug("could not get length of image: %d\n", ret); + goto out; + } + len = ret; + + ret = smh_read_full(fd, header, sizeof(struct image_header)); + if (ret) { + log_debug("could not read image header: %d\n", ret); + goto out; + } + + ret = spl_parse_image_header(spl_image, bootdev, header); + if (ret) { + log_debug("failed to parse image header: %d\n", ret); + goto out; + } + + ret = smh_seek(fd, 0); + if (ret) { + log_debug("could not seek to start of image: %d\n", ret); + goto out; + } + + ret = smh_read_full(fd, (void *)spl_image->load_addr, len); + if (ret) + log_debug("could not read %s: %d\n", filename, ret); +out: + smh_close(fd); + return ret; +} +SPL_LOAD_IMAGE_METHOD("SEMIHOSTING", 0, BOOT_DEVICE_SMH, spl_smh_load_image); -- cgit v1.1 From f676b45151c33986501e5f8f9bcc64f4a9511089 Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Tue, 22 Mar 2022 16:59:20 -0400 Subject: fs: Add semihosting filesystem This adds a filesystem which is backed by the host's filesystem. It is modeled off of sandboxfs, which has very similar aims. Semihosting doesn't support listing directories (except with SYS_SYSTEM), so neither do we. it's possible to optimize a bit for the common case of reading a whole file by omitting a call to smh_seek, but this is left as a future optimization. Signed-off-by: Sean Anderson --- disk/part.c | 4 +- fs/Makefile | 1 + fs/fs.c | 20 +++++++++ fs/semihostingfs.c | 115 ++++++++++++++++++++++++++++++++++++++++++++++++ include/fs.h | 1 + include/semihostingfs.h | 21 +++++++++ 6 files changed, 160 insertions(+), 2 deletions(-) create mode 100644 fs/semihostingfs.c create mode 100644 include/semihostingfs.h diff --git a/disk/part.c b/disk/part.c index 49e39a2..b95405b 100644 --- a/disk/part.c +++ b/disk/part.c @@ -455,7 +455,7 @@ int blk_get_device_part_str(const char *ifname, const char *dev_part_str, int part; struct disk_partition tmpinfo; -#ifdef CONFIG_SANDBOX +#if IS_ENABLED(CONFIG_SANDBOX) || IS_ENABLED(CONFIG_SEMIHOSTING) /* * Special-case a pseudo block device "hostfs", to allow access to the * host's own filesystem. @@ -467,7 +467,7 @@ int blk_get_device_part_str(const char *ifname, const char *dev_part_str, info->blksz = 0; info->bootable = 0; strcpy((char *)info->type, BOOT_PART_TYPE); - strcpy((char *)info->name, "Sandbox host"); + strcpy((char *)info->name, "Host filesystem"); #if CONFIG_IS_ENABLED(PARTITION_UUIDS) info->uuid[0] = 0; #endif diff --git a/fs/Makefile b/fs/Makefile index f05a21c..4bed2ff 100644 --- a/fs/Makefile +++ b/fs/Makefile @@ -21,6 +21,7 @@ obj-$(CONFIG_FS_FAT) += fat/ obj-$(CONFIG_FS_JFFS2) += jffs2/ obj-$(CONFIG_CMD_REISER) += reiserfs/ obj-$(CONFIG_SANDBOX) += sandbox/ +obj-$(CONFIG_SEMIHOSTING) += semihostingfs.o obj-$(CONFIG_CMD_UBIFS) += ubifs/ obj-$(CONFIG_YAFFS2) += yaffs2/ obj-$(CONFIG_CMD_ZFS) += zfs/ diff --git a/fs/fs.c b/fs/fs.c index 99dac0f..c3a2ed9 100644 --- a/fs/fs.c +++ b/fs/fs.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -247,6 +248,25 @@ static struct fstype_info fstypes[] = { .ln = fs_ln_unsupported, }, #endif +#ifdef CONFIG_SEMIHOSTING + { + .fstype = FS_TYPE_SEMIHOSTING, + .name = "semihosting", + .null_dev_desc_ok = true, + .probe = smh_fs_set_blk_dev, + .close = fs_close_unsupported, + .ls = fs_ls_unsupported, + .exists = fs_exists_unsupported, + .size = smh_fs_size, + .read = smh_fs_read, + .write = smh_fs_write, + .uuid = fs_uuid_unsupported, + .opendir = fs_opendir_unsupported, + .unlink = fs_unlink_unsupported, + .mkdir = fs_mkdir_unsupported, + .ln = fs_ln_unsupported, + }, +#endif #ifdef CONFIG_CMD_UBIFS { .fstype = FS_TYPE_UBIFS, diff --git a/fs/semihostingfs.c b/fs/semihostingfs.c new file mode 100644 index 0000000..96eb334 --- /dev/null +++ b/fs/semihostingfs.c @@ -0,0 +1,115 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2022, Sean Anderson + * Copyright (c) 2012, Google Inc. + */ + +#include +#include +#include +#include +#include +#include + +int smh_fs_set_blk_dev(struct blk_desc *rbdd, struct disk_partition *info) +{ + /* + * Only accept a NULL struct blk_desc for the semihosting, which is when + * hostfs interface is used + */ + return !!rbdd; +} + +static int smh_fs_read_at(const char *filename, loff_t pos, void *buffer, + loff_t maxsize, loff_t *actread) +{ + long fd, size, ret; + + fd = smh_open(filename, MODE_READ | MODE_BINARY); + if (fd < 0) + return fd; + ret = smh_seek(fd, pos); + if (ret < 0) { + smh_close(fd); + return ret; + } + if (!maxsize) { + size = smh_flen(fd); + if (ret < 0) { + smh_close(fd); + return size; + } + + maxsize = size; + } + + size = smh_read(fd, buffer, maxsize); + smh_close(fd); + if (size < 0) + return size; + + *actread = size; + return 0; +} + +static int smh_fs_write_at(const char *filename, loff_t pos, void *buffer, + loff_t towrite, loff_t *actwrite) +{ + long fd, size, ret; + + fd = smh_open(filename, MODE_READ | MODE_BINARY | MODE_PLUS); + if (fd < 0) + return fd; + ret = smh_seek(fd, pos); + if (ret < 0) { + smh_close(fd); + return ret; + } + + ret = smh_write(fd, buffer, towrite, &size); + smh_close(fd); + *actwrite = size; + return ret; +} + +int smh_fs_size(const char *filename, loff_t *result) +{ + long fd, size; + + fd = smh_open(filename, MODE_READ | MODE_BINARY); + if (fd < 0) + return fd; + + size = smh_flen(fd); + smh_close(fd); + + if (size < 0) + return size; + + *result = size; + return 0; +} + +int smh_fs_read(const char *filename, void *buf, loff_t offset, loff_t len, + loff_t *actread) +{ + int ret; + + ret = smh_fs_read_at(filename, offset, buf, len, actread); + if (ret) + printf("** Unable to read file %s **\n", filename); + + return ret; +} + +int smh_fs_write(const char *filename, void *buf, loff_t offset, + loff_t len, loff_t *actwrite) +{ + int ret; + + ret = smh_fs_write_at(filename, offset, buf, len, actwrite); + if (ret) + printf("** Unable to write file %s **\n", filename); + + return ret; +} diff --git a/include/fs.h b/include/fs.h index b607b00..e2beba3 100644 --- a/include/fs.h +++ b/include/fs.h @@ -18,6 +18,7 @@ struct cmd_tbl; #define FS_TYPE_BTRFS 5 #define FS_TYPE_SQUASHFS 6 #define FS_TYPE_EROFS 7 +#define FS_TYPE_SEMIHOSTING 8 struct blk_desc; diff --git a/include/semihostingfs.h b/include/semihostingfs.h new file mode 100644 index 0000000..25ebdbb --- /dev/null +++ b/include/semihostingfs.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2022, Sean Anderson + * Copyright (c) 2012, Google Inc. + */ + +#ifndef __SEMIHOSTING_FS__ +#define __SEMIHOSTING_FS__ + +struct blk_desc; +struct disk_partition; + +int smh_fs_set_blk_dev(struct blk_desc *rbdd, struct disk_partition *info); +void smh_fs_close(void); +int smh_fs_size(const char *filename, loff_t *size); +int smh_fs_read(const char *filename, void *buf, loff_t offset, loff_t len, + loff_t *actread); +int smh_fs_write(const char *filename, void *buf, loff_t offset, + loff_t len, loff_t *actwrite); + +#endif -- cgit v1.1 From dbf6f7c95240bd5fc7f5bbc2b36e275248279f53 Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Tue, 22 Mar 2022 16:59:21 -0400 Subject: cmd: fdt: Use start/size for chosen instead of start/end Most U-Boot command deal with start/size instead of start/end. Convert the "fdt chosen" command to use these semantics as well. The only user of this subcommand is vexpress, so convert the smhload command to use this as well. We don't bother renaming the variable in vexpress64's bootcommand, since it will be rewritten in the next commit. Signed-off-by: Sean Anderson --- arch/arm/lib/semihosting.c | 16 ++++++++-------- cmd/fdt.c | 6 +++--- 2 files changed, 11 insertions(+), 11 deletions(-) diff --git a/arch/arm/lib/semihosting.c b/arch/arm/lib/semihosting.c index d08003c..45cd566 100644 --- a/arch/arm/lib/semihosting.c +++ b/arch/arm/lib/semihosting.c @@ -171,7 +171,7 @@ long smh_seek(long fd, long pos) } static int smh_load_file(const char * const name, ulong load_addr, - ulong *end_addr) + ulong *size) { long fd; long len; @@ -191,11 +191,11 @@ static int smh_load_file(const char * const name, ulong load_addr, smh_close(fd); if (ret == len) { - *end_addr = load_addr + len - 1; + *size = len; printf("loaded file %s from %08lX to %08lX, %08lX bytes\n", name, load_addr, - *end_addr, + load_addr + len - 1, len); } else if (ret >= 0) { ret = -EAGAIN; @@ -214,22 +214,22 @@ static int do_smhload(struct cmd_tbl *cmdtp, int flag, int argc, { if (argc == 3 || argc == 4) { ulong load_addr; - ulong end_addr = 0; + ulong size = 0; int ret; - char end_str[64]; + char size_str[64]; load_addr = hextoul(argv[2], NULL); if (!load_addr) return -1; - ret = smh_load_file(argv[1], load_addr, &end_addr); + ret = smh_load_file(argv[1], load_addr, &size); if (ret < 0) return CMD_RET_FAILURE; /* Optionally save returned end to the environment */ if (argc == 4) { - sprintf(end_str, "0x%08lx", end_addr); - env_set(argv[3], end_str); + sprintf(size_str, "0x%08lx", size); + env_set(argv[3], size_str); } } else { return CMD_RET_USAGE; diff --git a/cmd/fdt.c b/cmd/fdt.c index 2a207bf..7d7cae8 100644 --- a/cmd/fdt.c +++ b/cmd/fdt.c @@ -638,7 +638,7 @@ static int do_fdt(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) if (argc == 4) { initrd_start = hextoul(argv[2], NULL); - initrd_end = hextoul(argv[3], NULL); + initrd_end = initrd_start + hextoul(argv[3], NULL) - 1; } fdt_chosen(working_fdt); @@ -1083,8 +1083,8 @@ static char fdt_help_text[] = "fdt rsvmem print - Show current mem reserves\n" "fdt rsvmem add - Add a mem reserve\n" "fdt rsvmem delete - Delete a mem reserves\n" - "fdt chosen [ ] - Add/update the /chosen branch in the tree\n" - " / - initrd start/end addr\n" + "fdt chosen [ ] - Add/update the /chosen branch in the tree\n" + " / - initrd start addr/size\n" #if defined(CONFIG_FIT_SIGNATURE) "fdt checksign [] - check FIT signature\n" " - addr of key blob\n" -- cgit v1.1 From dcc4f9623e27b92a1e0b97326631b0d5841c49cb Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Tue, 22 Mar 2022 16:59:22 -0400 Subject: arm: smh: Remove smhload command This command's functionality is now completely implemented by the standard fs load command. Convert the vexpress64 boot command (which is the only user) and remove the implementation. Signed-off-by: Sean Anderson --- arch/arm/lib/semihosting.c | 76 ---------------------------------------- include/configs/vexpress_aemv8.h | 10 +++--- 2 files changed, 5 insertions(+), 81 deletions(-) diff --git a/arch/arm/lib/semihosting.c b/arch/arm/lib/semihosting.c index 45cd566..57ab252 100644 --- a/arch/arm/lib/semihosting.c +++ b/arch/arm/lib/semihosting.c @@ -10,8 +10,6 @@ * available in silicon now, fastmodel usage makes less sense for them. */ #include -#include -#include #include #include @@ -169,77 +167,3 @@ long smh_seek(long fd, long pos) return smh_errno(); return 0; } - -static int smh_load_file(const char * const name, ulong load_addr, - ulong *size) -{ - long fd; - long len; - long ret; - - fd = smh_open(name, MODE_READ | MODE_BINARY); - if (fd < 0) - return fd; - - len = smh_flen(fd); - if (len < 0) { - smh_close(fd); - return len; - } - - ret = smh_read(fd, (void *)load_addr, len); - smh_close(fd); - - if (ret == len) { - *size = len; - printf("loaded file %s from %08lX to %08lX, %08lX bytes\n", - name, - load_addr, - load_addr + len - 1, - len); - } else if (ret >= 0) { - ret = -EAGAIN; - } - - if (ret < 0) { - printf("read failed: %ld\n", ret); - return ret; - } - - return 0; -} - -static int do_smhload(struct cmd_tbl *cmdtp, int flag, int argc, - char *const argv[]) -{ - if (argc == 3 || argc == 4) { - ulong load_addr; - ulong size = 0; - int ret; - char size_str[64]; - - load_addr = hextoul(argv[2], NULL); - if (!load_addr) - return -1; - - ret = smh_load_file(argv[1], load_addr, &size); - if (ret < 0) - return CMD_RET_FAILURE; - - /* Optionally save returned end to the environment */ - if (argc == 4) { - sprintf(size_str, "0x%08lx", size); - env_set(argv[3], size_str); - } - } else { - return CMD_RET_USAGE; - } - return 0; -} - -U_BOOT_CMD(smhload, 4, 0, do_smhload, "load a file using semihosting", - " 0x
[end var]\n" - " - load a semihosted file to the address specified\n" - " if the optional [end var] is specified, the end\n" - " address of the file will be stored in this environment\n" - " variable.\n"); diff --git a/include/configs/vexpress_aemv8.h b/include/configs/vexpress_aemv8.h index efffea9..4f0ff23 100644 --- a/include/configs/vexpress_aemv8.h +++ b/include/configs/vexpress_aemv8.h @@ -167,20 +167,20 @@ */ #define BOOTENV_DEV_SMH(devtypeu, devtypel, instance) \ "bootcmd_smh= " \ - "if smhload ${boot_name} ${boot_addr_r}; then" \ + "if load hostfs - ${boot_addr_r} ${boot_name}; then" \ " setenv bootargs;" \ " abootimg addr ${boot_addr_r};" \ " abootimg get dtb --index=0 fdt_addr_r;" \ " bootm ${boot_addr_r} ${boot_addr_r} ${fdt_addr_r};" \ "else" \ - " if smhload ${kernel_name} ${kernel_addr_r}; then" \ + " if load hostfs - ${kernel_addr_r} ${kernel_name}; then" \ " setenv fdt_high 0xffffffffffffffff;" \ " setenv initrd_high 0xffffffffffffffff;" \ - " smhload ${fdtfile} ${fdt_addr_r};" \ - " smhload ${ramdisk_name} ${ramdisk_addr_r} ramdisk_end;" \ + " load hostfs - ${fdt_addr_r} ${fdtfile};" \ + " load hostfs - ${ramdisk_addr_r} ${ramdisk_name};" \ " fdt addr ${fdt_addr_r};" \ " fdt resize;" \ - " fdt chosen ${ramdisk_addr_r} ${ramdisk_end};" \ + " fdt chosen ${ramdisk_addr_r} ${filesize};" \ " booti $kernel_addr_r - $fdt_addr_r;" \ " fi;" \ "fi\0" -- cgit v1.1 From 3ea744e87359f95251ae7ec3c7a92f8b3293593b Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Tue, 22 Mar 2022 16:59:23 -0400 Subject: arm: smh: Add some functions for working with the host console This adds three wrappers around the semihosting commands for reading and writing to the host console. We use the more standard getc/putc/puts names instead of readc/writec/write0 for familiarity. Signed-off-by: Sean Anderson --- arch/arm/lib/semihosting.c | 18 ++++++++++++++++++ include/semihosting.h | 19 +++++++++++++++++++ 2 files changed, 37 insertions(+) diff --git a/arch/arm/lib/semihosting.c b/arch/arm/lib/semihosting.c index 57ab252..7595dbc 100644 --- a/arch/arm/lib/semihosting.c +++ b/arch/arm/lib/semihosting.c @@ -15,8 +15,11 @@ #define SYSOPEN 0x01 #define SYSCLOSE 0x02 +#define SYSWRITEC 0x03 +#define SYSWRITE0 0x04 #define SYSWRITE 0x05 #define SYSREAD 0x06 +#define SYSREADC 0x07 #define SYSSEEK 0x0A #define SYSFLEN 0x0C #define SYSERRNO 0x13 @@ -167,3 +170,18 @@ long smh_seek(long fd, long pos) return smh_errno(); return 0; } + +int smh_getc(void) +{ + return smh_trap(SYSREADC, NULL); +} + +void smh_putc(char ch) +{ + smh_trap(SYSWRITEC, &ch); +} + +void smh_puts(const char *s) +{ + smh_trap(SYSWRITE0, (char *)s); +} diff --git a/include/semihosting.h b/include/semihosting.h index b53c650..6f3c297 100644 --- a/include/semihosting.h +++ b/include/semihosting.h @@ -86,4 +86,23 @@ long smh_flen(long fd); */ long smh_seek(long fd, long pos); +/** + * smh_getc() - Read a character from stdin + * + * Return: The character read, or a negative error on failure + */ +int smh_getc(void); + +/** + * smh_putc() - Print a character on stdout + * @ch: The character to print + */ +void smh_putc(char ch); + +/** + * smh_write0() - Print a nul-terminated string on stdout + * @s: The string to print + */ +void smh_puts(const char *s); + #endif /* _SEMIHOSTING_H */ -- cgit v1.1 From 74d11d37e2d33c616748d5572fd5718944826d17 Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Tue, 22 Mar 2022 16:59:24 -0400 Subject: serial: Add semihosting driver This adds a serial driver which uses semihosting calls to read and write to the host's console. For convenience, if CONFIG_DM_SERIAL is enabled, we will instantiate a serial driver. This allows users to enable this driver (which has no physical device) without modifying their device trees or board files. We also implement a non-DM driver for SPL, or for much faster output in U-Boot proper. There are three ways to print to the console: Method Baud ================== ===== smh_putc in a loop 170 smh_puts 1600 smh_write with :tt 20000 ================== ===== These speeds were measured using a 175 character message with a J-Link adapter. For reference, U-Boot typically prints around 2700 characters during boot on this board. There are two major factors affecting the speed of these functions. First, each breakpoint incurs a delay. Second, each debugger memory transaction incurs a delay. smh_putc has a breakpoint and memory transaction for every character. smh_puts has one breakpoint, but still has to use a transaction for every character. This is because we don't know the length up front, so OpenOCD has to check if each character is nul. smh_write has only one breakpoint and one memory transfer. DM serial drivers can only implement a putc interface, so we are stuck with the slowest API. Non-DM drivers can implement puts, which is vastly more efficient. When the driver starts up, we try to open :tt. Since this is an extension, this may fail. If it does, we fall back to smh_puts. We don't check :semihosting-features, since there are nonconforming implementations (OpenOCD) which don't implement it (but *do* implement :tt). Some semihosting implementations (QEMU) don't handle READC properly. To work around this, we try to use open/read (much like for stdin) if possible. There is no non-blocking I/O available, so we don't implement pending. This will cause __serial_tstc to always return true. If CONFIG_SERIAL_RX_BUFFER is enabled, _serial_tstc will try and read characters forever. To avoid this, we depend on this config being disabled. Signed-off-by: Sean Anderson Reviewed-by: Simon Glass --- drivers/serial/Kconfig | 22 ++++++ drivers/serial/Makefile | 1 + drivers/serial/serial.c | 2 + drivers/serial/serial_semihosting.c | 147 ++++++++++++++++++++++++++++++++++++ include/serial.h | 1 + 5 files changed, 173 insertions(+) create mode 100644 drivers/serial/serial_semihosting.c diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 610f806..a07fab2 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -399,6 +399,15 @@ config DEBUG_UART_SANDBOX start up driver model. The driver will be available until the real driver model serial is running. +config DEBUG_UART_SEMIHOSTING + bool "semihosting" + depends on SEMIHOSTING_SERIAL + help + Select this to enable the debug UART using the semihosting driver. + This provides basic serial output from the console without needing to + start up driver model. The driver will be available until the real + driver model serial is running. + config DEBUG_UART_SIFIVE bool "SiFive UART" depends on SIFIVE_SERIAL @@ -782,6 +791,19 @@ config SCIF_CONSOLE on systems with RCar or SH SoCs, say Y to this option. If unsure, say N. +config SEMIHOSTING_SERIAL + bool "Semihosting UART support" + depends on SEMIHOSTING && !SERIAL_RX_BUFFER + help + Select this to enable a serial UART using semihosting. Special halt + instructions will be issued which an external debugger (such as a + JTAG emulator) may interpret. The debugger will display U-Boot's + console output on the host system. + + Enable this option only if you are using a debugger which supports + semihosting. If you are not using a debugger, this driver will halt + the boot. + config UNIPHIER_SERIAL bool "Support for UniPhier on-chip UART" depends on ARCH_UNIPHIER diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 52e70aa..b68b5e7 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -52,6 +52,7 @@ endif obj-$(CONFIG_XILINX_UARTLITE) += serial_xuartlite.o obj-$(CONFIG_SANDBOX_SERIAL) += sandbox.o obj-$(CONFIG_SCIF_CONSOLE) += serial_sh.o +obj-$(CONFIG_SEMIHOSTING_SERIAL) += serial_semihosting.o obj-$(CONFIG_ZYNQ_SERIAL) += serial_zynq.o obj-$(CONFIG_FSL_LPUART) += serial_lpuart.o obj-$(CONFIG_FSL_LINFLEXUART) += serial_linflexuart.o diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c index ebbd219..6cdbb89 100644 --- a/drivers/serial/serial.c +++ b/drivers/serial/serial.c @@ -126,6 +126,7 @@ serial_initfunc(mxc_serial_initialize); serial_initfunc(ns16550_serial_initialize); serial_initfunc(pl01x_serial_initialize); serial_initfunc(pxa_serial_initialize); +serial_initfunc(smh_serial_initialize); serial_initfunc(sh_serial_initialize); serial_initfunc(mtk_serial_initialize); @@ -180,6 +181,7 @@ int serial_initialize(void) ns16550_serial_initialize(); pl01x_serial_initialize(); pxa_serial_initialize(); + smh_serial_initialize(); sh_serial_initialize(); mtk_serial_initialize(); diff --git a/drivers/serial/serial_semihosting.c b/drivers/serial/serial_semihosting.c new file mode 100644 index 0000000..7c7c5d9 --- /dev/null +++ b/drivers/serial/serial_semihosting.c @@ -0,0 +1,147 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2022 Sean Anderson + */ + +#include +#include +#include +#include + +/** + * struct smh_serial_priv - Semihosting serial private data + * @infd: stdin file descriptor (or error) + */ +struct smh_serial_priv { + int infd; + int outfd; +}; + +#if CONFIG_IS_ENABLED(DM_SERIAL) +static int smh_serial_getc(struct udevice *dev) +{ + char ch = 0; + struct smh_serial_priv *priv = dev_get_priv(dev); + + if (priv->infd < 0) + return smh_getc(); + + smh_read(priv->infd, &ch, sizeof(ch)); + return ch; +} + +static int smh_serial_putc(struct udevice *dev, const char ch) +{ + smh_putc(ch); + return 0; +} + +static const struct dm_serial_ops smh_serial_ops = { + .putc = smh_serial_putc, + .getc = smh_serial_getc, +}; + +static int smh_serial_probe(struct udevice *dev) +{ + struct smh_serial_priv *priv = dev_get_priv(dev); + + priv->infd = smh_open(":tt", MODE_READ); + return 0; +} + +U_BOOT_DRIVER(smh_serial) = { + .name = "serial_semihosting", + .id = UCLASS_SERIAL, + .probe = smh_serial_probe, + .priv_auto = sizeof(struct smh_serial_priv), + .ops = &smh_serial_ops, + .flags = DM_FLAG_PRE_RELOC, +}; + +U_BOOT_DRVINFO(smh_serial) = { + .name = "serial_semihosting", +}; +#else /* DM_SERIAL */ +static int infd = -ENODEV; +static int outfd = -ENODEV; + +static int smh_serial_start(void) +{ + infd = smh_open(":tt", MODE_READ); + outfd = smh_open(":tt", MODE_WRITE); + return 0; +} + +static int smh_serial_stop(void) +{ + if (outfd >= 0) + smh_close(outfd); + return 0; +} + +static void smh_serial_setbrg(void) +{ +} + +static int smh_serial_getc(void) +{ + char ch = 0; + + if (infd < 0) + return smh_getc(); + + smh_read(infd, &ch, sizeof(ch)); + return ch; +} + +static int smh_serial_tstc(void) +{ + return 1; +} + +static void smh_serial_puts(const char *s) +{ + ulong unused; + + if (outfd < 0) + smh_puts(s); + else + smh_write(outfd, s, strlen(s), &unused); +} + +struct serial_device serial_smh_device = { + .name = "serial_smh", + .start = smh_serial_start, + .stop = smh_serial_stop, + .setbrg = smh_serial_setbrg, + .getc = smh_serial_getc, + .tstc = smh_serial_tstc, + .putc = smh_putc, + .puts = smh_serial_puts, +}; + +void smh_serial_initialize(void) +{ + serial_register(&serial_smh_device); +} + +__weak struct serial_device *default_serial_console(void) +{ + return &serial_smh_device; +} +#endif + +#ifdef CONFIG_DEBUG_UART_SEMIHOSTING +#include + +static inline void _debug_uart_init(void) +{ +} + +static inline void _debug_uart_putc(int c) +{ + smh_putc(c); +} + +DEBUG_UART_FUNCS +#endif diff --git a/include/serial.h b/include/serial.h index 19a8c0c..2681d26 100644 --- a/include/serial.h +++ b/include/serial.h @@ -23,6 +23,7 @@ struct serial_device { void default_serial_puts(const char *s); extern struct serial_device serial_smc_device; +extern struct serial_device serial_smh_device; extern struct serial_device serial_scc_device; extern struct serial_device *default_serial_console(void); -- cgit v1.1 From eeb54e81ca9226aa2a664af7d1e5bc2e44d790e3 Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Tue, 22 Mar 2022 16:59:25 -0400 Subject: doc: smh: Update semihosting documentation This documents how to use semihosting, the new semihosting features, and how to migrate from smhload. Signed-off-by: Sean Anderson --- doc/usage/semihosting.rst | 71 ++++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 67 insertions(+), 4 deletions(-) diff --git a/doc/usage/semihosting.rst b/doc/usage/semihosting.rst index ed16e4d..1d79398 100644 --- a/doc/usage/semihosting.rst +++ b/doc/usage/semihosting.rst @@ -10,6 +10,12 @@ console I/O, etc. Please see `Arm's semihosting documentation `_ for more information. +Platform Support +---------------- + +Versatile Express +^^^^^^^^^^^^^^^^^ + For developing on armv8 virtual fastmodel platforms, semihosting is a valuable tool since it allows access to image/configuration files before eMMC or other NV media are available. @@ -31,13 +37,70 @@ vexpress_aemv8.h but differentiate the two models by the presence or absence of ``CONFIG_BASE_FVP``. This change is tested and works on both the Foundation and Base fastmodel simulators. +QEMU +^^^^ + +Another ARM emulator which supports semihosting is `QEMU +`_. To enable semihosting, enable +``CONFIG_SERIAL_PROBE_ALL`` when configuring U-Boot, and use +``-semihosting`` when invoking QEMU. Adding ``-nographic`` can also be +helpful. When using a semihosted serial console, QEMU will block waiting +for input. This will cause the GUI to become unresponsive. To mitigate +this, try adding ``-nographic``. For more information about building and +running QEMU, refer to the :doc:`board documentation +<../board/emulation/qemu-arm>`. + +OpenOCD +^^^^^^^ + +Any ARM platform can use semihosting with an attached debugger. One such +debugger with good support for a variety of boards and JTAG adapters is +`OpenOCD `_. Semihosting is not enabled by default, +so you will need to enable it:: + + $ openocd -f -c init -c halt -c \ + 'arm semihosting enable' -c resume + +Note that enabling semihosting can only be done after attaching to the +board with ``init``, and must be done while the CPU is halted. + Loading files ------------- -The semihosting code adds a "hostfs":: +The semihosting code adds a "semihosting filesystem":: - smhload
[env var] + load hostfs -
That will load an image from the host filesystem into RAM at the specified -address and optionally store the load end address in the specified -environment variable. +address. If you are using U-Boot SPL, you can also use ``BOOT_DEVICE_SMH`` +which will load ``CONFIG_SPL_FS_LOAD_PAYLOAD_NAME``. + +Host console +------------ + +U-Boot can use the host's console instead of a physical serial device by +enabling ``CONFIG_SERIAL_SEMIHOSTING``. If you don't have +``CONFIG_DM_SERIAL`` enabled, make sure you disable any other serial +drivers. + +Migrating from ``smhload`` +-------------------------- + +If you were using the ``smhload`` command, you can migrate commands like:: + + smhload
[] + +to a generic load command like:: + + load hostfs -
+ +The ``load`` command will set the ``filesize`` variable with the size of +the file. The ``fdt chosen`` command has been updated to take a size +instead of an end address. If you were adding the initramfs to your device +tree like:: + + fdt chosen
+ +you can now run:: + + fdt chosen
$filesize -- cgit v1.1 From 93c3d329707e0d8dc98e5f86938bbedbe15b5349 Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Tue, 22 Mar 2022 17:16:05 -0400 Subject: ls1046ardb: Add support for JTAG boot This adds support for booting entirely from JTAG while using a hard-coded RCW. With these steps, it is not necessary to program a "good" RCW using CodeWarrior. The method here can be performed with any JTAG adapter supported by OpenOCD, including the on-board CMSIS-DAP (albeit very slowly). These steps require LS1046A support in OpenOCD, which was added in [1]. [1] https://sourceforge.net/p/openocd/code/ci/5b70c1f679755677c925b4e6dd2c3d8be4715717/ Signed-off-by: Sean Anderson [trini: Add reference to doc/board/nxp/ls1046ardb.rst] --- arch/arm/cpu/armv8/fsl-layerscape/spl.c | 2 + board/freescale/ls1046ardb/ls1046ardb.c | 10 +++++ doc/board/nxp/ls1046ardb.rst | 73 +++++++++++++++++++++++++++++++++ doc/usage/semihosting.rst | 3 +- include/configs/ls1046ardb.h | 2 + 5 files changed, 89 insertions(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/spl.c b/arch/arm/cpu/armv8/fsl-layerscape/spl.c index 564cc27..1a7dde3 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/spl.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/spl.c @@ -27,6 +27,8 @@ DECLARE_GLOBAL_DATA_PTR; u32 spl_boot_device(void) { + if (IS_ENABLED(CONFIG_SPL_SEMIHOSTING)) + return BOOT_DEVICE_SMH; #ifdef CONFIG_SPL_MMC return BOOT_DEVICE_MMC1; #endif diff --git a/board/freescale/ls1046ardb/ls1046ardb.c b/board/freescale/ls1046ardb/ls1046ardb.c index d0abfe8..9af7cf7 100644 --- a/board/freescale/ls1046ardb/ls1046ardb.c +++ b/board/freescale/ls1046ardb/ls1046ardb.c @@ -7,6 +7,8 @@ #include #include #include +#include +#include #include #include #include @@ -27,6 +29,14 @@ DECLARE_GLOBAL_DATA_PTR; +struct serial_device *default_serial_console(void) +{ +#if IS_ENABLED(CONFIG_SEMIHOSTING_SERIAL) + return &serial_smh_device; +#endif + return &eserial1_device; +} + int board_early_init_f(void) { fsl_lsch2_early_init_f(); diff --git a/doc/board/nxp/ls1046ardb.rst b/doc/board/nxp/ls1046ardb.rst index e4499a1..35465d0 100644 --- a/doc/board/nxp/ls1046ardb.rst +++ b/doc/board/nxp/ls1046ardb.rst @@ -110,6 +110,79 @@ SD boot and eMMC boot ``{ SW5[0:8], SW4[0] }`` should be ``0010_0000_0``. eMMC is selected only if there is no SD card in the slot. +.. _ls1046ardb_jtag: + +JTAG boot +^^^^^^^^^ + +To recover a bricked board, or to perform initial programming, the ls1046 +supports using two hard-coded Reset Configuration Words (RCWs). Unfortunately, +this configuration disables most functionality, including the uarts and ethernet. +However, the SD/MMC and flash controllers are still functional. To get around +the lack of a serial console, we will use ARM semihosting instead. When +enabled, OpenOCD will interpret certain instructions as calls to the host +operating system. This allows U-Boot to use the console, read/write files, or +run arbitrary commands (!). + +When configuring U-Boot, ensure that ``CONFIG_SEMIHOSTING``, +``CONFIG_SPL_SEMIHOSTING``, and ``CONFIG_SEMIHOSTING_SERIAL`` are enabled. +``{ SW5[0:8], SW4[0] }`` should be ``0100_1111_0``. Additionally, ``SW4[7]`` +should be set to ``0``. Connect to the "console" USB connector on the front of +the enclosure. + +Create a new file called ``u-boot.tcl`` (or whatever you choose) with the +following contents:: + + # Load the configuration for the LS1046ARDB + source [find board/nxp_rdb-ls1046a.cfg] + # Initialize the scan chain + init + # Stop the processor + halt + # Enable semihosting + arm semihosting enable + # Load U-Boot SPL + load_image spl/u-boot-spl 0 elf + # Start executing SPL at the beginning of OCRAM + resume 0x10000000 + +Then, launch openocd like:: + + openocd -f u-boot.tcl + +You should see the U-boot SPL banner followed by the banner for U-Boot proper +in the output of openocd. The CMSIS-DAP adapter is slow, so this can take a +long time. If you don't see it, something has gone wrong. After a while, you +should see the prompt. You can load an image using semihosting by running:: + + => load hostfs - $loadaddr + +Note that openocd's terminal is "cooked," so commands will only be sent to +U-Boot when you press enter, and all commands will be echoed twice. +Additionally, openocd will block when waiting for input, ignoring gdb, JTAG +events, and Ctrl-Cs. To make openocd process these events, just hit enter. + +Using an external JTAG adapter +"""""""""""""""""""""""""""""" + +The CMSIS-DAP adapter can be rather slow. To speed up booting, use an external +JTAG adapter. The following examples assume you are using a J-Link, though any +adapter supported by OpenOCD will do. Ensure that ``SW4[7]`` is ``1``. Attach +your jtag adapter to J22. Modify ``u-boot.tcl`` and replace the first two lines +with the following:: + + # Load the J-Link configuration (or whatever your adapter is) + source [find interface/jlink.cfg] + # Use JTAG, since the J-Link also supports SWD + transport select jtag + # The reset pin resets the whole CPU + reset_config srst_only + # Load the LS1046A config + source [find target/ls1046a.cfg] + +You can proceed as normal through the rest of the steps above. I got a speedup +of around 100x by using a J-Link. + Debug UART ---------- diff --git a/doc/usage/semihosting.rst b/doc/usage/semihosting.rst index 1d79398..6a280b4 100644 --- a/doc/usage/semihosting.rst +++ b/doc/usage/semihosting.rst @@ -62,7 +62,8 @@ so you will need to enable it:: 'arm semihosting enable' -c resume Note that enabling semihosting can only be done after attaching to the -board with ``init``, and must be done while the CPU is halted. +board with ``init``, and must be done while the CPU is halted. For a more +extended example, refer to the :ref:`LS1046ARDB docs `. Loading files ------------- diff --git a/include/configs/ls1046ardb.h b/include/configs/ls1046ardb.h index 04c3ad0..df699bc 100644 --- a/include/configs/ls1046ardb.h +++ b/include/configs/ls1046ardb.h @@ -140,6 +140,8 @@ #endif #endif +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" + #include #endif /* __LS1046ARDB_H__ */ -- cgit v1.1 From e97ac4780d69c719b81086bba615c8568afd14a1 Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Tue, 22 Mar 2022 17:17:35 -0400 Subject: arm64: Save esr in pt_regs To avoid passing around an extra register everywhere, save esr in pt_regs like the rest. For proper alignment we need to have a second (unused) register. All the printfs have to be adjusted, since it's now an unsigned long and not an int. Signed-off-by: Sean Anderson --- arch/arm/cpu/armv8/exceptions.S | 6 ++++-- arch/arm/include/asm/proc-armv/ptrace.h | 2 ++ arch/arm/include/asm/u-boot-arm.h | 7 +------ arch/arm/lib/interrupts_64.c | 33 +++++++++++++++++---------------- arch/arm/mach-imx/imx8m/soc.c | 4 ++-- 5 files changed, 26 insertions(+), 26 deletions(-) diff --git a/arch/arm/cpu/armv8/exceptions.S b/arch/arm/cpu/armv8/exceptions.S index a15af72..001913f 100644 --- a/arch/arm/cpu/armv8/exceptions.S +++ b/arch/arm/cpu/armv8/exceptions.S @@ -84,7 +84,8 @@ _save_el_regs: 1: mrs x1, esr_el1 mrs x2, elr_el1 0: - stp x2, x0, [sp, #-16]! + stp x1, x0, [sp, #-16]! + stp xzr, x2, [sp, #-16]! mov x0, sp ret @@ -98,7 +99,7 @@ _save_el_regs: * This is the first part of the shared routine called into from all entries. */ exception_exit: - ldp x2, x0, [sp],#16 + ldp xzr, x2, [sp],#16 switch_el x11, 3f, 2f, 1f 3: msr elr_el3, x2 b _restore_regs @@ -118,6 +119,7 @@ exception_exit: * This is the second part of the shared routine called into from all entries. */ _restore_regs: + ldp xzr, x0, [sp],#16 ldp x1, x2, [sp],#16 ldp x3, x4, [sp],#16 ldp x5, x6, [sp],#16 diff --git a/arch/arm/include/asm/proc-armv/ptrace.h b/arch/arm/include/asm/proc-armv/ptrace.h index e37ad8f..bebcaf6 100644 --- a/arch/arm/include/asm/proc-armv/ptrace.h +++ b/arch/arm/include/asm/proc-armv/ptrace.h @@ -21,7 +21,9 @@ * on the stack during an exception. */ struct pt_regs { + unsigned long unused; unsigned long elr; + unsigned long esr; unsigned long regs[31]; }; diff --git a/arch/arm/include/asm/u-boot-arm.h b/arch/arm/include/asm/u-boot-arm.h index 0b93cc4..aef0487 100644 --- a/arch/arm/include/asm/u-boot-arm.h +++ b/arch/arm/include/asm/u-boot-arm.h @@ -46,13 +46,8 @@ void do_software_interrupt(struct pt_regs *pt_regs); void do_prefetch_abort(struct pt_regs *pt_regs); void do_data_abort(struct pt_regs *pt_regs); void do_not_used(struct pt_regs *pt_regs); -#ifdef CONFIG_ARM64 -void do_fiq(struct pt_regs *pt_regs, unsigned int esr); -void do_irq(struct pt_regs *pt_regs, unsigned int esr); -#else void do_fiq(struct pt_regs *pt_regs); -void do_irq(struct pt_regs *pt_regswq); -#endif +void do_irq(struct pt_regs *pt_regs); void reset_misc(void); diff --git a/arch/arm/lib/interrupts_64.c b/arch/arm/lib/interrupts_64.c index c653e67..049beec 100644 --- a/arch/arm/lib/interrupts_64.c +++ b/arch/arm/lib/interrupts_64.c @@ -66,10 +66,11 @@ void show_regs(struct pt_regs *regs) /* * do_bad_sync handles the impossible case in the Synchronous Abort vector. */ -void do_bad_sync(struct pt_regs *pt_regs, unsigned int esr) +void do_bad_sync(struct pt_regs *pt_regs) { efi_restore_gd(); - printf("Bad mode in \"Synchronous Abort\" handler, esr 0x%08x\n", esr); + printf("Bad mode in \"Synchronous Abort\" handler, esr 0x%08lx\n", + pt_regs->esr); show_regs(pt_regs); show_efi_loaded_images(pt_regs); panic("Resetting CPU ...\n"); @@ -78,10 +79,10 @@ void do_bad_sync(struct pt_regs *pt_regs, unsigned int esr) /* * do_bad_irq handles the impossible case in the Irq vector. */ -void do_bad_irq(struct pt_regs *pt_regs, unsigned int esr) +void do_bad_irq(struct pt_regs *pt_regs) { efi_restore_gd(); - printf("Bad mode in \"Irq\" handler, esr 0x%08x\n", esr); + printf("Bad mode in \"Irq\" handler, esr 0x%08lx\n", pt_regs->esr); show_regs(pt_regs); show_efi_loaded_images(pt_regs); panic("Resetting CPU ...\n"); @@ -90,10 +91,10 @@ void do_bad_irq(struct pt_regs *pt_regs, unsigned int esr) /* * do_bad_fiq handles the impossible case in the Fiq vector. */ -void do_bad_fiq(struct pt_regs *pt_regs, unsigned int esr) +void do_bad_fiq(struct pt_regs *pt_regs) { efi_restore_gd(); - printf("Bad mode in \"Fiq\" handler, esr 0x%08x\n", esr); + printf("Bad mode in \"Fiq\" handler, esr 0x%08lx\n", pt_regs->esr); show_regs(pt_regs); show_efi_loaded_images(pt_regs); panic("Resetting CPU ...\n"); @@ -102,10 +103,10 @@ void do_bad_fiq(struct pt_regs *pt_regs, unsigned int esr) /* * do_bad_error handles the impossible case in the Error vector. */ -void do_bad_error(struct pt_regs *pt_regs, unsigned int esr) +void do_bad_error(struct pt_regs *pt_regs) { efi_restore_gd(); - printf("Bad mode in \"Error\" handler, esr 0x%08x\n", esr); + printf("Bad mode in \"Error\" handler, esr 0x%08lx\n", pt_regs->esr); show_regs(pt_regs); show_efi_loaded_images(pt_regs); panic("Resetting CPU ...\n"); @@ -114,10 +115,10 @@ void do_bad_error(struct pt_regs *pt_regs, unsigned int esr) /* * do_sync handles the Synchronous Abort exception. */ -void do_sync(struct pt_regs *pt_regs, unsigned int esr) +void do_sync(struct pt_regs *pt_regs) { efi_restore_gd(); - printf("\"Synchronous Abort\" handler, esr 0x%08x\n", esr); + printf("\"Synchronous Abort\" handler, esr 0x%08lx\n", pt_regs->esr); show_regs(pt_regs); show_efi_loaded_images(pt_regs); panic("Resetting CPU ...\n"); @@ -126,10 +127,10 @@ void do_sync(struct pt_regs *pt_regs, unsigned int esr) /* * do_irq handles the Irq exception. */ -void do_irq(struct pt_regs *pt_regs, unsigned int esr) +void do_irq(struct pt_regs *pt_regs) { efi_restore_gd(); - printf("\"Irq\" handler, esr 0x%08x\n", esr); + printf("\"Irq\" handler, esr 0x%08lx\n", pt_regs->esr); show_regs(pt_regs); show_efi_loaded_images(pt_regs); panic("Resetting CPU ...\n"); @@ -138,10 +139,10 @@ void do_irq(struct pt_regs *pt_regs, unsigned int esr) /* * do_fiq handles the Fiq exception. */ -void do_fiq(struct pt_regs *pt_regs, unsigned int esr) +void do_fiq(struct pt_regs *pt_regs) { efi_restore_gd(); - printf("\"Fiq\" handler, esr 0x%08x\n", esr); + printf("\"Fiq\" handler, esr 0x%08lx\n", pt_regs->esr); show_regs(pt_regs); show_efi_loaded_images(pt_regs); panic("Resetting CPU ...\n"); @@ -153,10 +154,10 @@ void do_fiq(struct pt_regs *pt_regs, unsigned int esr) * it is defined with weak attribute and can be redefined * in processor specific code. */ -void __weak do_error(struct pt_regs *pt_regs, unsigned int esr) +void __weak do_error(struct pt_regs *pt_regs) { efi_restore_gd(); - printf("\"Error\" handler, esr 0x%08x\n", esr); + printf("\"Error\" handler, esr 0x%08lx\n", pt_regs->esr); show_regs(pt_regs); show_efi_loaded_images(pt_regs); panic("Resetting CPU ...\n"); diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c index 838f0a3..7397b99 100644 --- a/arch/arm/mach-imx/imx8m/soc.c +++ b/arch/arm/mach-imx/imx8m/soc.c @@ -1295,7 +1295,7 @@ void imx_tmu_arch_init(void *reg_base) #if defined(CONFIG_IMX8MQ) || defined(CONFIG_IMX8MM) || defined(CONFIG_IMX8MN) bool serror_need_skip = true; -void do_error(struct pt_regs *pt_regs, unsigned int esr) +void do_error(struct pt_regs *pt_regs) { /* * If stack is still in ROM reserved OCRAM not switch to SPL, @@ -1320,7 +1320,7 @@ void do_error(struct pt_regs *pt_regs, unsigned int esr) } efi_restore_gd(); - printf("\"Error\" handler, esr 0x%08x\n", esr); + printf("\"Error\" handler, esr 0x%08lx\n", pt_regs->esr); show_regs(pt_regs); panic("Resetting CPU ...\n"); } -- cgit v1.1 From e75d791c5083cd7d25c36677825b2a01ce708b7d Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Tue, 22 Mar 2022 16:59:28 -0400 Subject: arm64: Save spsr in pt_regs This register holds "pstate" which includes (among other things) the instruction mode the CPU was in when the exception was taken. This is necessary to correctly interpret instructions at elr. Signed-off-by: Sean Anderson --- arch/arm/cpu/armv8/exceptions.S | 5 ++++- arch/arm/include/asm/proc-armv/ptrace.h | 2 +- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm/cpu/armv8/exceptions.S b/arch/arm/cpu/armv8/exceptions.S index 001913f..504d566 100644 --- a/arch/arm/cpu/armv8/exceptions.S +++ b/arch/arm/cpu/armv8/exceptions.S @@ -77,15 +77,18 @@ _save_el_regs: switch_el x11, 3f, 2f, 1f 3: mrs x1, esr_el3 mrs x2, elr_el3 + mrs x3, spsr_el3 b 0f 2: mrs x1, esr_el2 mrs x2, elr_el2 + mrs x3, spsr_el2 b 0f 1: mrs x1, esr_el1 mrs x2, elr_el1 + mrs x3, spsr_el1 0: stp x1, x0, [sp, #-16]! - stp xzr, x2, [sp, #-16]! + stp x3, x2, [sp, #-16]! mov x0, sp ret diff --git a/arch/arm/include/asm/proc-armv/ptrace.h b/arch/arm/include/asm/proc-armv/ptrace.h index bebcaf6..3b8fe7a 100644 --- a/arch/arm/include/asm/proc-armv/ptrace.h +++ b/arch/arm/include/asm/proc-armv/ptrace.h @@ -21,7 +21,7 @@ * on the stack during an exception. */ struct pt_regs { - unsigned long unused; + unsigned long spsr; unsigned long elr; unsigned long esr; unsigned long regs[31]; -- cgit v1.1 From 6d16157426b63361d6390b3ab4b304bbe101c825 Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Tue, 22 Mar 2022 17:18:37 -0400 Subject: arm64: Import some ESR and SPSR defines from Linux This imports some defines for esr and spsr from Linux v5.16. I have modified the includes and fixed some indentation nits but otherwise it is the same. There are a lot more defines than we need, but it doesn't hurt. Signed-off-by: Sean Anderson --- arch/arm/include/asm/esr.h | 343 ++++++++++++++++++++++++++++++++ arch/arm/include/asm/proc-armv/ptrace.h | 73 +++++++ 2 files changed, 416 insertions(+) create mode 100644 arch/arm/include/asm/esr.h diff --git a/arch/arm/include/asm/esr.h b/arch/arm/include/asm/esr.h new file mode 100644 index 0000000..f19e4e7 --- /dev/null +++ b/arch/arm/include/asm/esr.h @@ -0,0 +1,343 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2013 - ARM Ltd + * Author: Marc Zyngier + */ + +#ifndef __ASM_ESR_H +#define __ASM_ESR_H + +#include +#include + +#define ESR_ELx_EC_UNKNOWN (0x00) +#define ESR_ELx_EC_WFx (0x01) +/* Unallocated EC: 0x02 */ +#define ESR_ELx_EC_CP15_32 (0x03) +#define ESR_ELx_EC_CP15_64 (0x04) +#define ESR_ELx_EC_CP14_MR (0x05) +#define ESR_ELx_EC_CP14_LS (0x06) +#define ESR_ELx_EC_FP_ASIMD (0x07) +#define ESR_ELx_EC_CP10_ID (0x08) /* EL2 only */ +#define ESR_ELx_EC_PAC (0x09) /* EL2 and above */ +/* Unallocated EC: 0x0A - 0x0B */ +#define ESR_ELx_EC_CP14_64 (0x0C) +#define ESR_ELx_EC_BTI (0x0D) +#define ESR_ELx_EC_ILL (0x0E) +/* Unallocated EC: 0x0F - 0x10 */ +#define ESR_ELx_EC_SVC32 (0x11) +#define ESR_ELx_EC_HVC32 (0x12) /* EL2 only */ +#define ESR_ELx_EC_SMC32 (0x13) /* EL2 and above */ +/* Unallocated EC: 0x14 */ +#define ESR_ELx_EC_SVC64 (0x15) +#define ESR_ELx_EC_HVC64 (0x16) /* EL2 and above */ +#define ESR_ELx_EC_SMC64 (0x17) /* EL2 and above */ +#define ESR_ELx_EC_SYS64 (0x18) +#define ESR_ELx_EC_SVE (0x19) +#define ESR_ELx_EC_ERET (0x1a) /* EL2 only */ +/* Unallocated EC: 0x1B */ +#define ESR_ELx_EC_FPAC (0x1C) /* EL1 and above */ +/* Unallocated EC: 0x1D - 0x1E */ +#define ESR_ELx_EC_IMP_DEF (0x1f) /* EL3 only */ +#define ESR_ELx_EC_IABT_LOW (0x20) +#define ESR_ELx_EC_IABT_CUR (0x21) +#define ESR_ELx_EC_PC_ALIGN (0x22) +/* Unallocated EC: 0x23 */ +#define ESR_ELx_EC_DABT_LOW (0x24) +#define ESR_ELx_EC_DABT_CUR (0x25) +#define ESR_ELx_EC_SP_ALIGN (0x26) +/* Unallocated EC: 0x27 */ +#define ESR_ELx_EC_FP_EXC32 (0x28) +/* Unallocated EC: 0x29 - 0x2B */ +#define ESR_ELx_EC_FP_EXC64 (0x2C) +/* Unallocated EC: 0x2D - 0x2E */ +#define ESR_ELx_EC_SERROR (0x2F) +#define ESR_ELx_EC_BREAKPT_LOW (0x30) +#define ESR_ELx_EC_BREAKPT_CUR (0x31) +#define ESR_ELx_EC_SOFTSTP_LOW (0x32) +#define ESR_ELx_EC_SOFTSTP_CUR (0x33) +#define ESR_ELx_EC_WATCHPT_LOW (0x34) +#define ESR_ELx_EC_WATCHPT_CUR (0x35) +/* Unallocated EC: 0x36 - 0x37 */ +#define ESR_ELx_EC_BKPT32 (0x38) +/* Unallocated EC: 0x39 */ +#define ESR_ELx_EC_VECTOR32 (0x3A) /* EL2 only */ +/* Unallocated EC: 0x3B */ +#define ESR_ELx_EC_BRK64 (0x3C) +/* Unallocated EC: 0x3D - 0x3F */ +#define ESR_ELx_EC_MAX (0x3F) + +#define ESR_ELx_EC_SHIFT (26) +#define ESR_ELx_EC_WIDTH (6) +#define ESR_ELx_EC_MASK (UL(0x3F) << ESR_ELx_EC_SHIFT) +#define ESR_ELx_EC(esr) (((esr) & ESR_ELx_EC_MASK) >> ESR_ELx_EC_SHIFT) + +#define ESR_ELx_IL_SHIFT (25) +#define ESR_ELx_IL (UL(1) << ESR_ELx_IL_SHIFT) +#define ESR_ELx_ISS_MASK (ESR_ELx_IL - 1) + +/* ISS field definitions shared by different classes */ +#define ESR_ELx_WNR_SHIFT (6) +#define ESR_ELx_WNR (UL(1) << ESR_ELx_WNR_SHIFT) + +/* Asynchronous Error Type */ +#define ESR_ELx_IDS_SHIFT (24) +#define ESR_ELx_IDS (UL(1) << ESR_ELx_IDS_SHIFT) +#define ESR_ELx_AET_SHIFT (10) +#define ESR_ELx_AET (UL(0x7) << ESR_ELx_AET_SHIFT) + +#define ESR_ELx_AET_UC (UL(0) << ESR_ELx_AET_SHIFT) +#define ESR_ELx_AET_UEU (UL(1) << ESR_ELx_AET_SHIFT) +#define ESR_ELx_AET_UEO (UL(2) << ESR_ELx_AET_SHIFT) +#define ESR_ELx_AET_UER (UL(3) << ESR_ELx_AET_SHIFT) +#define ESR_ELx_AET_CE (UL(6) << ESR_ELx_AET_SHIFT) + +/* Shared ISS field definitions for Data/Instruction aborts */ +#define ESR_ELx_SET_SHIFT (11) +#define ESR_ELx_SET_MASK (UL(3) << ESR_ELx_SET_SHIFT) +#define ESR_ELx_FnV_SHIFT (10) +#define ESR_ELx_FnV (UL(1) << ESR_ELx_FnV_SHIFT) +#define ESR_ELx_EA_SHIFT (9) +#define ESR_ELx_EA (UL(1) << ESR_ELx_EA_SHIFT) +#define ESR_ELx_S1PTW_SHIFT (7) +#define ESR_ELx_S1PTW (UL(1) << ESR_ELx_S1PTW_SHIFT) + +/* Shared ISS fault status code(IFSC/DFSC) for Data/Instruction aborts */ +#define ESR_ELx_FSC (0x3F) +#define ESR_ELx_FSC_TYPE (0x3C) +#define ESR_ELx_FSC_LEVEL (0x03) +#define ESR_ELx_FSC_EXTABT (0x10) +#define ESR_ELx_FSC_MTE (0x11) +#define ESR_ELx_FSC_SERROR (0x11) +#define ESR_ELx_FSC_ACCESS (0x08) +#define ESR_ELx_FSC_FAULT (0x04) +#define ESR_ELx_FSC_PERM (0x0C) + +/* ISS field definitions for Data Aborts */ +#define ESR_ELx_ISV_SHIFT (24) +#define ESR_ELx_ISV (UL(1) << ESR_ELx_ISV_SHIFT) +#define ESR_ELx_SAS_SHIFT (22) +#define ESR_ELx_SAS (UL(3) << ESR_ELx_SAS_SHIFT) +#define ESR_ELx_SSE_SHIFT (21) +#define ESR_ELx_SSE (UL(1) << ESR_ELx_SSE_SHIFT) +#define ESR_ELx_SRT_SHIFT (16) +#define ESR_ELx_SRT_MASK (UL(0x1F) << ESR_ELx_SRT_SHIFT) +#define ESR_ELx_SF_SHIFT (15) +#define ESR_ELx_SF (UL(1) << ESR_ELx_SF_SHIFT) +#define ESR_ELx_AR_SHIFT (14) +#define ESR_ELx_AR (UL(1) << ESR_ELx_AR_SHIFT) +#define ESR_ELx_CM_SHIFT (8) +#define ESR_ELx_CM (UL(1) << ESR_ELx_CM_SHIFT) + +/* ISS field definitions for exceptions taken in to Hyp */ +#define ESR_ELx_CV (UL(1) << 24) +#define ESR_ELx_COND_SHIFT (20) +#define ESR_ELx_COND_MASK (UL(0xF) << ESR_ELx_COND_SHIFT) +#define ESR_ELx_WFx_ISS_TI (UL(1) << 0) +#define ESR_ELx_WFx_ISS_WFI (UL(0) << 0) +#define ESR_ELx_WFx_ISS_WFE (UL(1) << 0) +#define ESR_ELx_xVC_IMM_MASK ((1UL << 16) - 1) + +#define DISR_EL1_IDS (UL(1) << 24) +/* + * DISR_EL1 and ESR_ELx share the bottom 13 bits, but the RES0 bits may mean + * different things in the future... + */ +#define DISR_EL1_ESR_MASK (ESR_ELx_AET | ESR_ELx_EA | ESR_ELx_FSC) + +/* ESR value templates for specific events */ +#define ESR_ELx_WFx_MASK (ESR_ELx_EC_MASK | ESR_ELx_WFx_ISS_TI) +#define ESR_ELx_WFx_WFI_VAL ((ESR_ELx_EC_WFx << ESR_ELx_EC_SHIFT) | \ + ESR_ELx_WFx_ISS_WFI) + +/* BRK instruction trap from AArch64 state */ +#define ESR_ELx_BRK64_ISS_COMMENT_MASK 0xffff + +/* ISS field definitions for System instruction traps */ +#define ESR_ELx_SYS64_ISS_RES0_SHIFT 22 +#define ESR_ELx_SYS64_ISS_RES0_MASK (UL(0x7) << ESR_ELx_SYS64_ISS_RES0_SHIFT) +#define ESR_ELx_SYS64_ISS_DIR_MASK 0x1 +#define ESR_ELx_SYS64_ISS_DIR_READ 0x1 +#define ESR_ELx_SYS64_ISS_DIR_WRITE 0x0 + +#define ESR_ELx_SYS64_ISS_RT_SHIFT 5 +#define ESR_ELx_SYS64_ISS_RT_MASK (UL(0x1f) << ESR_ELx_SYS64_ISS_RT_SHIFT) +#define ESR_ELx_SYS64_ISS_CRM_SHIFT 1 +#define ESR_ELx_SYS64_ISS_CRM_MASK (UL(0xf) << ESR_ELx_SYS64_ISS_CRM_SHIFT) +#define ESR_ELx_SYS64_ISS_CRN_SHIFT 10 +#define ESR_ELx_SYS64_ISS_CRN_MASK (UL(0xf) << ESR_ELx_SYS64_ISS_CRN_SHIFT) +#define ESR_ELx_SYS64_ISS_OP1_SHIFT 14 +#define ESR_ELx_SYS64_ISS_OP1_MASK (UL(0x7) << ESR_ELx_SYS64_ISS_OP1_SHIFT) +#define ESR_ELx_SYS64_ISS_OP2_SHIFT 17 +#define ESR_ELx_SYS64_ISS_OP2_MASK (UL(0x7) << ESR_ELx_SYS64_ISS_OP2_SHIFT) +#define ESR_ELx_SYS64_ISS_OP0_SHIFT 20 +#define ESR_ELx_SYS64_ISS_OP0_MASK (UL(0x3) << ESR_ELx_SYS64_ISS_OP0_SHIFT) +#define ESR_ELx_SYS64_ISS_SYS_MASK (ESR_ELx_SYS64_ISS_OP0_MASK | \ + ESR_ELx_SYS64_ISS_OP1_MASK | \ + ESR_ELx_SYS64_ISS_OP2_MASK | \ + ESR_ELx_SYS64_ISS_CRN_MASK | \ + ESR_ELx_SYS64_ISS_CRM_MASK) +#define ESR_ELx_SYS64_ISS_SYS_VAL(op0, op1, op2, crn, crm) \ + (((op0) << ESR_ELx_SYS64_ISS_OP0_SHIFT) | \ + ((op1) << ESR_ELx_SYS64_ISS_OP1_SHIFT) | \ + ((op2) << ESR_ELx_SYS64_ISS_OP2_SHIFT) | \ + ((crn) << ESR_ELx_SYS64_ISS_CRN_SHIFT) | \ + ((crm) << ESR_ELx_SYS64_ISS_CRM_SHIFT)) + +#define ESR_ELx_SYS64_ISS_SYS_OP_MASK (ESR_ELx_SYS64_ISS_SYS_MASK | \ + ESR_ELx_SYS64_ISS_DIR_MASK) +#define ESR_ELx_SYS64_ISS_RT(esr) \ + (((esr) & ESR_ELx_SYS64_ISS_RT_MASK) >> ESR_ELx_SYS64_ISS_RT_SHIFT) +/* + * User space cache operations have the following sysreg encoding + * in System instructions. + * op0=1, op1=3, op2=1, crn=7, crm={ 5, 10, 11, 12, 13, 14 }, WRITE (L=0) + */ +#define ESR_ELx_SYS64_ISS_CRM_DC_CIVAC 14 +#define ESR_ELx_SYS64_ISS_CRM_DC_CVADP 13 +#define ESR_ELx_SYS64_ISS_CRM_DC_CVAP 12 +#define ESR_ELx_SYS64_ISS_CRM_DC_CVAU 11 +#define ESR_ELx_SYS64_ISS_CRM_DC_CVAC 10 +#define ESR_ELx_SYS64_ISS_CRM_IC_IVAU 5 + +#define ESR_ELx_SYS64_ISS_EL0_CACHE_OP_MASK (ESR_ELx_SYS64_ISS_OP0_MASK | \ + ESR_ELx_SYS64_ISS_OP1_MASK | \ + ESR_ELx_SYS64_ISS_OP2_MASK | \ + ESR_ELx_SYS64_ISS_CRN_MASK | \ + ESR_ELx_SYS64_ISS_DIR_MASK) +#define ESR_ELx_SYS64_ISS_EL0_CACHE_OP_VAL \ + (ESR_ELx_SYS64_ISS_SYS_VAL(1, 3, 1, 7, 0) | \ + ESR_ELx_SYS64_ISS_DIR_WRITE) +/* + * User space MRS operations which are supported for emulation + * have the following sysreg encoding in System instructions. + * op0 = 3, op1= 0, crn = 0, {crm = 0, 4-7}, READ (L = 1) + */ +#define ESR_ELx_SYS64_ISS_SYS_MRS_OP_MASK (ESR_ELx_SYS64_ISS_OP0_MASK | \ + ESR_ELx_SYS64_ISS_OP1_MASK | \ + ESR_ELx_SYS64_ISS_CRN_MASK | \ + ESR_ELx_SYS64_ISS_DIR_MASK) +#define ESR_ELx_SYS64_ISS_SYS_MRS_OP_VAL \ + (ESR_ELx_SYS64_ISS_SYS_VAL(3, 0, 0, 0, 0) | \ + ESR_ELx_SYS64_ISS_DIR_READ) + +#define ESR_ELx_SYS64_ISS_SYS_CTR ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 1, 0, 0) +#define ESR_ELx_SYS64_ISS_SYS_CTR_READ (ESR_ELx_SYS64_ISS_SYS_CTR | \ + ESR_ELx_SYS64_ISS_DIR_READ) + +#define ESR_ELx_SYS64_ISS_SYS_CNTVCT (ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 2, 14, 0) | \ + ESR_ELx_SYS64_ISS_DIR_READ) + +#define ESR_ELx_SYS64_ISS_SYS_CNTVCTSS (ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 6, 14, 0) | \ + ESR_ELx_SYS64_ISS_DIR_READ) + +#define ESR_ELx_SYS64_ISS_SYS_CNTFRQ (ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 0, 14, 0) | \ + ESR_ELx_SYS64_ISS_DIR_READ) + +#define esr_sys64_to_sysreg(e) \ + sys_reg((((e) & ESR_ELx_SYS64_ISS_OP0_MASK) >> \ + ESR_ELx_SYS64_ISS_OP0_SHIFT), \ + (((e) & ESR_ELx_SYS64_ISS_OP1_MASK) >> \ + ESR_ELx_SYS64_ISS_OP1_SHIFT), \ + (((e) & ESR_ELx_SYS64_ISS_CRN_MASK) >> \ + ESR_ELx_SYS64_ISS_CRN_SHIFT), \ + (((e) & ESR_ELx_SYS64_ISS_CRM_MASK) >> \ + ESR_ELx_SYS64_ISS_CRM_SHIFT), \ + (((e) & ESR_ELx_SYS64_ISS_OP2_MASK) >> \ + ESR_ELx_SYS64_ISS_OP2_SHIFT)) + +#define esr_cp15_to_sysreg(e) \ + sys_reg(3, \ + (((e) & ESR_ELx_SYS64_ISS_OP1_MASK) >> \ + ESR_ELx_SYS64_ISS_OP1_SHIFT), \ + (((e) & ESR_ELx_SYS64_ISS_CRN_MASK) >> \ + ESR_ELx_SYS64_ISS_CRN_SHIFT), \ + (((e) & ESR_ELx_SYS64_ISS_CRM_MASK) >> \ + ESR_ELx_SYS64_ISS_CRM_SHIFT), \ + (((e) & ESR_ELx_SYS64_ISS_OP2_MASK) >> \ + ESR_ELx_SYS64_ISS_OP2_SHIFT)) + +/* + * ISS field definitions for floating-point exception traps + * (FP_EXC_32/FP_EXC_64). + * + * (The FPEXC_* constants are used instead for common bits.) + */ + +#define ESR_ELx_FP_EXC_TFV (UL(1) << 23) + +/* + * ISS field definitions for CP15 accesses + */ +#define ESR_ELx_CP15_32_ISS_DIR_MASK 0x1 +#define ESR_ELx_CP15_32_ISS_DIR_READ 0x1 +#define ESR_ELx_CP15_32_ISS_DIR_WRITE 0x0 + +#define ESR_ELx_CP15_32_ISS_RT_SHIFT 5 +#define ESR_ELx_CP15_32_ISS_RT_MASK (UL(0x1f) << ESR_ELx_CP15_32_ISS_RT_SHIFT) +#define ESR_ELx_CP15_32_ISS_CRM_SHIFT 1 +#define ESR_ELx_CP15_32_ISS_CRM_MASK (UL(0xf) << ESR_ELx_CP15_32_ISS_CRM_SHIFT) +#define ESR_ELx_CP15_32_ISS_CRN_SHIFT 10 +#define ESR_ELx_CP15_32_ISS_CRN_MASK (UL(0xf) << ESR_ELx_CP15_32_ISS_CRN_SHIFT) +#define ESR_ELx_CP15_32_ISS_OP1_SHIFT 14 +#define ESR_ELx_CP15_32_ISS_OP1_MASK (UL(0x7) << ESR_ELx_CP15_32_ISS_OP1_SHIFT) +#define ESR_ELx_CP15_32_ISS_OP2_SHIFT 17 +#define ESR_ELx_CP15_32_ISS_OP2_MASK (UL(0x7) << ESR_ELx_CP15_32_ISS_OP2_SHIFT) + +#define ESR_ELx_CP15_32_ISS_SYS_MASK (ESR_ELx_CP15_32_ISS_OP1_MASK | \ + ESR_ELx_CP15_32_ISS_OP2_MASK | \ + ESR_ELx_CP15_32_ISS_CRN_MASK | \ + ESR_ELx_CP15_32_ISS_CRM_MASK | \ + ESR_ELx_CP15_32_ISS_DIR_MASK) +#define ESR_ELx_CP15_32_ISS_SYS_VAL(op1, op2, crn, crm) \ + (((op1) << ESR_ELx_CP15_32_ISS_OP1_SHIFT) | \ + ((op2) << ESR_ELx_CP15_32_ISS_OP2_SHIFT) | \ + ((crn) << ESR_ELx_CP15_32_ISS_CRN_SHIFT) | \ + ((crm) << ESR_ELx_CP15_32_ISS_CRM_SHIFT)) + +#define ESR_ELx_CP15_64_ISS_DIR_MASK 0x1 +#define ESR_ELx_CP15_64_ISS_DIR_READ 0x1 +#define ESR_ELx_CP15_64_ISS_DIR_WRITE 0x0 + +#define ESR_ELx_CP15_64_ISS_RT_SHIFT 5 +#define ESR_ELx_CP15_64_ISS_RT_MASK (UL(0x1f) << ESR_ELx_CP15_64_ISS_RT_SHIFT) + +#define ESR_ELx_CP15_64_ISS_RT2_SHIFT 10 +#define ESR_ELx_CP15_64_ISS_RT2_MASK (UL(0x1f) << ESR_ELx_CP15_64_ISS_RT2_SHIFT) + +#define ESR_ELx_CP15_64_ISS_OP1_SHIFT 16 +#define ESR_ELx_CP15_64_ISS_OP1_MASK (UL(0xf) << ESR_ELx_CP15_64_ISS_OP1_SHIFT) +#define ESR_ELx_CP15_64_ISS_CRM_SHIFT 1 +#define ESR_ELx_CP15_64_ISS_CRM_MASK (UL(0xf) << ESR_ELx_CP15_64_ISS_CRM_SHIFT) + +#define ESR_ELx_CP15_64_ISS_SYS_VAL(op1, crm) \ + (((op1) << ESR_ELx_CP15_64_ISS_OP1_SHIFT) | \ + ((crm) << ESR_ELx_CP15_64_ISS_CRM_SHIFT)) + +#define ESR_ELx_CP15_64_ISS_SYS_MASK (ESR_ELx_CP15_64_ISS_OP1_MASK | \ + ESR_ELx_CP15_64_ISS_CRM_MASK | \ + ESR_ELx_CP15_64_ISS_DIR_MASK) + +#define ESR_ELx_CP15_64_ISS_SYS_CNTVCT (ESR_ELx_CP15_64_ISS_SYS_VAL(1, 14) | \ + ESR_ELx_CP15_64_ISS_DIR_READ) + +#define ESR_ELx_CP15_64_ISS_SYS_CNTVCTSS (ESR_ELx_CP15_64_ISS_SYS_VAL(9, 14) | \ + ESR_ELx_CP15_64_ISS_DIR_READ) + +#define ESR_ELx_CP15_32_ISS_SYS_CNTFRQ (ESR_ELx_CP15_32_ISS_SYS_VAL(0, 0, 14, 0) |\ + ESR_ELx_CP15_32_ISS_DIR_READ) + +#ifndef __ASSEMBLY__ +#include + +static inline bool esr_is_data_abort(u32 esr) +{ + const u32 ec = ESR_ELx_EC(esr); + + return ec == ESR_ELx_EC_DABT_LOW || ec == ESR_ELx_EC_DABT_CUR; +} + +const char *esr_get_class_string(u32 esr); +#endif /* __ASSEMBLY */ + +#endif /* __ASM_ESR_H */ diff --git a/arch/arm/include/asm/proc-armv/ptrace.h b/arch/arm/include/asm/proc-armv/ptrace.h index 3b8fe7a..2db60d5 100644 --- a/arch/arm/include/asm/proc-armv/ptrace.h +++ b/arch/arm/include/asm/proc-armv/ptrace.h @@ -14,6 +14,79 @@ #define PCMASK 0 +/* + * PSR bits + */ +#define PSR_MODE_EL0t 0x00000000 +#define PSR_MODE_EL1t 0x00000004 +#define PSR_MODE_EL1h 0x00000005 +#define PSR_MODE_EL2t 0x00000008 +#define PSR_MODE_EL2h 0x00000009 +#define PSR_MODE_EL3t 0x0000000c +#define PSR_MODE_EL3h 0x0000000d +#define PSR_MODE_MASK 0x0000000f + +/* AArch32 CPSR bits */ +#define PSR_MODE32_BIT 0x00000010 + +/* AArch64 SPSR bits */ +#define PSR_F_BIT 0x00000040 +#define PSR_I_BIT 0x00000080 +#define PSR_A_BIT 0x00000100 +#define PSR_D_BIT 0x00000200 +#define PSR_BTYPE_MASK 0x00000c00 +#define PSR_SSBS_BIT 0x00001000 +#define PSR_PAN_BIT 0x00400000 +#define PSR_UAO_BIT 0x00800000 +#define PSR_DIT_BIT 0x01000000 +#define PSR_TCO_BIT 0x02000000 +#define PSR_V_BIT 0x10000000 +#define PSR_C_BIT 0x20000000 +#define PSR_Z_BIT 0x40000000 +#define PSR_N_BIT 0x80000000 + +#define PSR_BTYPE_SHIFT 10 + +/* + * Groups of PSR bits + */ +#define PSR_f 0xff000000 /* Flags */ +#define PSR_s 0x00ff0000 /* Status */ +#define PSR_x 0x0000ff00 /* Extension */ +#define PSR_c 0x000000ff /* Control */ + +/* Convenience names for the values of PSTATE.BTYPE */ +#define PSR_BTYPE_NONE (0b00 << PSR_BTYPE_SHIFT) +#define PSR_BTYPE_JC (0b01 << PSR_BTYPE_SHIFT) +#define PSR_BTYPE_C (0b10 << PSR_BTYPE_SHIFT) +#define PSR_BTYPE_J (0b11 << PSR_BTYPE_SHIFT) + +/* SPSR_ELx bits for exceptions taken from AArch32 */ +#define PSR_AA32_MODE_MASK 0x0000001f +#define PSR_AA32_MODE_USR 0x00000010 +#define PSR_AA32_MODE_FIQ 0x00000011 +#define PSR_AA32_MODE_IRQ 0x00000012 +#define PSR_AA32_MODE_SVC 0x00000013 +#define PSR_AA32_MODE_ABT 0x00000017 +#define PSR_AA32_MODE_HYP 0x0000001a +#define PSR_AA32_MODE_UND 0x0000001b +#define PSR_AA32_MODE_SYS 0x0000001f +#define PSR_AA32_T_BIT 0x00000020 +#define PSR_AA32_F_BIT 0x00000040 +#define PSR_AA32_I_BIT 0x00000080 +#define PSR_AA32_A_BIT 0x00000100 +#define PSR_AA32_E_BIT 0x00000200 +#define PSR_AA32_PAN_BIT 0x00400000 +#define PSR_AA32_SSBS_BIT 0x00800000 +#define PSR_AA32_DIT_BIT 0x01000000 +#define PSR_AA32_Q_BIT 0x08000000 +#define PSR_AA32_V_BIT 0x10000000 +#define PSR_AA32_C_BIT 0x20000000 +#define PSR_AA32_Z_BIT 0x40000000 +#define PSR_AA32_N_BIT 0x80000000 +#define PSR_AA32_IT_MASK 0x0600fc00 /* If-Then execution state mask */ +#define PSR_AA32_GE_MASK 0x000f0000 + #ifndef __ASSEMBLY__ /* -- cgit v1.1 From 385d69d76b4216c10083f908005983d0c62e159c Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Tue, 22 Mar 2022 16:59:30 -0400 Subject: arm: smh: Add option to detect semihosting These functions are intended to support detecting semihosting and falling back gracefully to alternative implementations. The test starts by making semihosting call. SYS_ERRNO is chosen because it should not mutate any state. If this semihosting call results in an exception (rather than being caught by the debugger), then the exception handler should call disable_semihosting() and resume execution after the call. Ideally, this would just be part of semihosting by default, and not a separate config. However, to reduce space ARM SPL doesn't include exception vectors by default. This means we can't detect if a semihosting call failed unless we enable them. To avoid forcing them to be enabled, we use a separate config option. It might also be possible to try and detect whether a debugger has enabled (by reading HDE from DSCR), but I wasn't able to figure out a way to do this from all ELs. This patch just introduces the generic code to handle detection. The next patch will implement it for arm64 (but not arm32). Signed-off-by: Sean Anderson --- arch/arm/Kconfig | 21 +++++++++++++++++++++ arch/arm/lib/semihosting.c | 21 +++++++++++++++++++++ include/semihosting.h | 30 ++++++++++++++++++++++++++++++ 3 files changed, 72 insertions(+) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index b2e2873..f277929 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -414,6 +414,16 @@ config SEMIHOSTING on the host system. If you don't have a debugger attached then trying to do this will likely cause U-Boot to hang. Say 'n' if you are unsure. +config SEMIHOSTING_FALLBACK + bool "Recover gracefully when semihosting fails" + depends on SEMIHOSTING && ARM64 + default y + help + Normally, if U-Boot makes a semihosting call and no debugger is + attached, then it will panic due to a synchronous abort + exception. This config adds an exception handler which will allow + U-Boot to recover. Say 'y' if unsure. + config SPL_SEMIHOSTING bool "Support ARM semihosting in SPL" depends on SPL @@ -427,6 +437,17 @@ config SPL_SEMIHOSTING on the host system. If you don't have a debugger attached then trying to do this will likely cause U-Boot to hang. Say 'n' if you are unsure. +config SPL_SEMIHOSTING_FALLBACK + bool "Recover gracefully when semihosting fails in SPL" + depends on SPL_SEMIHOSTING && ARM64 + select ARMV8_SPL_EXCEPTION_VECTORS + default y + help + Normally, if U-Boot makes a semihosting call and no debugger is + attached, then it will panic due to a synchronous abort + exception. This config adds an exception handler which will allow + U-Boot to recover. Say 'y' if unsure. + config SYS_THUMB_BUILD bool "Build U-Boot using the Thumb instruction set" depends on !ARM64 diff --git a/arch/arm/lib/semihosting.c b/arch/arm/lib/semihosting.c index 7595dbc..dbea2b0 100644 --- a/arch/arm/lib/semihosting.c +++ b/arch/arm/lib/semihosting.c @@ -20,6 +20,7 @@ #define SYSWRITE 0x05 #define SYSREAD 0x06 #define SYSREADC 0x07 +#define SYSISERROR 0x08 #define SYSSEEK 0x0A #define SYSFLEN 0x0C #define SYSERRNO 0x13 @@ -41,6 +42,26 @@ static noinline long smh_trap(unsigned int sysnum, void *addr) return result; } +#if CONFIG_IS_ENABLED(SEMIHOSTING_FALLBACK) +static bool _semihosting_enabled = true; +static bool try_semihosting = true; + +bool semihosting_enabled(void) +{ + if (try_semihosting) { + smh_trap(SYSERRNO, NULL); + try_semihosting = false; + } + + return _semihosting_enabled; +} + +void disable_semihosting(void) +{ + _semihosting_enabled = false; +} +#endif + /** * smh_errno() - Read the host's errno * diff --git a/include/semihosting.h b/include/semihosting.h index 6f3c297..9816233 100644 --- a/include/semihosting.h +++ b/include/semihosting.h @@ -6,6 +6,36 @@ #ifndef _SEMIHOSTING_H #define _SEMIHOSTING_H +#if CONFIG_IS_ENABLED(SEMIHOSTING_FALLBACK) +/** + * semihosting_enabled() - Determine whether semihosting is supported + * + * Semihosting-based drivers should call this function before making other + * semihosting calls. + * + * Return: %true if a debugger is attached which supports semihosting, %false + * otherwise + */ +bool semihosting_enabled(void); + +/** + * disable_semihosting() - Cause semihosting_enabled() to return false + * + * If U-Boot ever receives an unhandled exception caused by a semihosting trap, + * the trap handler should call this function. + */ +void disable_semihosting(void); +#else +static inline bool semihosting_enabled(void) +{ + return CONFIG_IS_ENABLED(SEMIHOSTING); +} + +static inline void disable_semihosting(void) +{ +} +#endif + /** * enum smh_open_mode - Numeric file modes for use with smh_open() * MODE_READ: 'r' -- cgit v1.1 From bbe310cdaf459b0ee69534584128ed6e057568db Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Tue, 22 Mar 2022 16:59:31 -0400 Subject: arm64: Catch non-emulated semihosting calls If a debugger is not attached to U-Boot, semihosting calls will raise a synchronous abort exception. Try to catch this and disable semihosting so we can e.g. use another uart if one is available. In the immediate case, we return an error, since it is not always possible to check for semihosting beforehand (debug uart, user-initiated load command, etc.) We handle all possible semihosting instructions, which is probably overkill. However, we do need to keep track of what instruction set we're using so that we don't suppress an actual error. A future enhancement could try to determine semihosting capability by inspecting the processor state. There's an example of this at [1] for RISC-V. The equivalent for ARM would inspect the monitor modei enable/select bits of the DSCR. However, as the article notes, an exception handler is still helpful in order to catch disconnected debuggers. [1] https://tomverbeure.github.io/2021/12/30/Semihosting-on-RISCV.html#avoiding-hangs-when-a-debugger-is-not-connected Signed-off-by: Sean Anderson --- arch/arm/lib/interrupts_64.c | 47 ++++++++++++++++++++++++++++++++++++++++++++ include/semihosting.h | 11 +++++++++++ 2 files changed, 58 insertions(+) diff --git a/arch/arm/lib/interrupts_64.c b/arch/arm/lib/interrupts_64.c index 049beec..2e09141 100644 --- a/arch/arm/lib/interrupts_64.c +++ b/arch/arm/lib/interrupts_64.c @@ -5,11 +5,13 @@ */ #include +#include #include #include #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -64,6 +66,48 @@ void show_regs(struct pt_regs *regs) } /* + * Try to "emulate" a semihosting call in the event that we don't have a + * debugger attached. + */ +static bool smh_emulate_trap(struct pt_regs *regs) +{ + int size; + + if (ESR_ELx_EC(regs->esr) != ESR_ELx_EC_UNKNOWN) + return false; + + if (regs->spsr & PSR_MODE32_BIT) { + if (regs->spsr & PSR_AA32_T_BIT) { + u16 *insn = (u16 *)ALIGN_DOWN(regs->elr, 2); + + if (*insn != SMH_T32_SVC && *insn != SMH_T32_HLT) + return false; + size = 2; + } else { + u32 *insn = (u32 *)ALIGN_DOWN(regs->elr, 4); + + if (*insn != SMH_A32_SVC && *insn != SMH_A32_HLT) + return false; + size = 4; + } + } else { + u32 *insn = (u32 *)ALIGN_DOWN(regs->elr, 4); + + if (*insn != SMH_A64_HLT) + return false; + size = 4; + } + + /* Avoid future semihosting calls */ + disable_semihosting(); + + /* Just pretend the call failed */ + regs->regs[0] = -1; + regs->elr += size; + return true; +} + +/* * do_bad_sync handles the impossible case in the Synchronous Abort vector. */ void do_bad_sync(struct pt_regs *pt_regs) @@ -117,6 +161,9 @@ void do_bad_error(struct pt_regs *pt_regs) */ void do_sync(struct pt_regs *pt_regs) { + if (CONFIG_IS_ENABLED(SEMIHOSTING_FALLBACK) && + smh_emulate_trap(pt_regs)) + return; efi_restore_gd(); printf("\"Synchronous Abort\" handler, esr 0x%08lx\n", pt_regs->esr); show_regs(pt_regs); diff --git a/include/semihosting.h b/include/semihosting.h index 9816233..f1f7346 100644 --- a/include/semihosting.h +++ b/include/semihosting.h @@ -6,6 +6,17 @@ #ifndef _SEMIHOSTING_H #define _SEMIHOSTING_H +/* + * These are the encoded instructions used to indicate a semihosting trap. They + * are named like SMH_ISA_INSN, where ISA is the instruction set (e.g. + * AArch64), and INSN is the mneumonic for the instruction. + */ +#define SMH_A64_HLT 0xD45E0000 +#define SMH_A32_SVC 0xEF123456 +#define SMH_A32_HLT 0xE10F0070 +#define SMH_T32_SVC 0xDFAB +#define SMH_T32_HLT 0xBABC + #if CONFIG_IS_ENABLED(SEMIHOSTING_FALLBACK) /** * semihosting_enabled() - Determine whether semihosting is supported -- cgit v1.1 From 2332590c48ac15926d7ec23b0fa17b9ea4e305ed Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Tue, 22 Mar 2022 16:59:32 -0400 Subject: serial: smh: Initialize serial only if semihosting is enabled If semihosting is disabled, then the user has no debugger attached, and will not see any messages. Don't create a serial device in this instance, to (hopefully) fall back on another working serial device. Signed-off-by: Sean Anderson --- drivers/serial/serial_semihosting.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/serial/serial_semihosting.c b/drivers/serial/serial_semihosting.c index 7c7c5d9..62b1b22 100644 --- a/drivers/serial/serial_semihosting.c +++ b/drivers/serial/serial_semihosting.c @@ -41,6 +41,13 @@ static const struct dm_serial_ops smh_serial_ops = { .getc = smh_serial_getc, }; +static int smh_serial_bind(struct udevice *dev) +{ + if (semihosting_enabled()) + return 0; + return -ENOENT; +} + static int smh_serial_probe(struct udevice *dev) { struct smh_serial_priv *priv = dev_get_priv(dev); @@ -52,6 +59,7 @@ static int smh_serial_probe(struct udevice *dev) U_BOOT_DRIVER(smh_serial) = { .name = "serial_semihosting", .id = UCLASS_SERIAL, + .bind = smh_serial_bind, .probe = smh_serial_probe, .priv_auto = sizeof(struct smh_serial_priv), .ops = &smh_serial_ops, @@ -122,7 +130,8 @@ struct serial_device serial_smh_device = { void smh_serial_initialize(void) { - serial_register(&serial_smh_device); + if (semihosting_enabled()) + serial_register(&serial_smh_device); } __weak struct serial_device *default_serial_console(void) -- cgit v1.1 From 53b953f2ebad6263352cb1247618dc5b965863cc Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Tue, 22 Mar 2022 16:59:33 -0400 Subject: arm64: ls1046a: Support semihosting fallback Use the semihosting_enabled function to determine whether or not to enable semihosting devices. This allows for graceful fallback in the event a debugger is not attached. Signed-off-by: Sean Anderson --- arch/arm/cpu/armv8/fsl-layerscape/spl.c | 3 ++- board/freescale/ls1046ardb/ls1046ardb.c | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/spl.c b/arch/arm/cpu/armv8/fsl-layerscape/spl.c index 1a7dde3..5f09ef0 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/spl.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/spl.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -27,7 +28,7 @@ DECLARE_GLOBAL_DATA_PTR; u32 spl_boot_device(void) { - if (IS_ENABLED(CONFIG_SPL_SEMIHOSTING)) + if (semihosting_enabled()) return BOOT_DEVICE_SMH; #ifdef CONFIG_SPL_MMC return BOOT_DEVICE_MMC1; diff --git a/board/freescale/ls1046ardb/ls1046ardb.c b/board/freescale/ls1046ardb/ls1046ardb.c index 9af7cf7..f2949cf 100644 --- a/board/freescale/ls1046ardb/ls1046ardb.c +++ b/board/freescale/ls1046ardb/ls1046ardb.c @@ -32,7 +32,8 @@ DECLARE_GLOBAL_DATA_PTR; struct serial_device *default_serial_console(void) { #if IS_ENABLED(CONFIG_SEMIHOSTING_SERIAL) - return &serial_smh_device; + if (semihosting_enabled()) + return &serial_smh_device; #endif return &eserial1_device; } -- cgit v1.1 From 7a763471894feb58d5a1bdf78ea7014c7a952264 Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Tue, 22 Mar 2022 16:59:34 -0400 Subject: serial: dm: Add support for puts Some serial drivers can be vastly more efficient when printing multiple characters at once. Non-DM serial has had a puts option for these sorts of drivers; implement it for DM serial as well. Because we have to add carriage returns, we can't just pass the whole string directly to the serial driver. Instead, we print up to the newline, then print a carriage return, and then continue on. This is less efficient, but it is better than printing each character individually. It also avoids having to allocate memory just to add a few characters. Drivers may perform short writes (such as filling a FIFO) and return the number of characters written in len. We loop over them in the same way that _serial_putc loops over putc. This results in around sizeof(void *) growth for all boards with DM_SERIAL. The full implementation takes around 140 bytes. Signed-off-by: Sean Anderson Reviewed-by: Simon Glass --- drivers/serial/Kconfig | 13 +++++++++++++ drivers/serial/serial-uclass.c | 26 ++++++++++++++++++++++++-- include/serial.h | 18 ++++++++++++++++++ 3 files changed, 55 insertions(+), 2 deletions(-) diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index a07fab2..76171e7 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -133,6 +133,19 @@ config SERIAL_RX_BUFFER_SIZE help The size of the RX buffer (needs to be power of 2) +config SERIAL_PUTS + bool "Enable printing strings all at once" + depends on DM_SERIAL + help + Some serial drivers are much more efficient when printing multiple + characters at once rather than printing characters individually. This + can be because they can load a fifo, or because individual print + calls have a constant overhead. With this option set, the serial + subsystem will try to provide serial drivers with as many characters + at once as possible, instead of printing characters one by one. Most + serial drivers do not need this config to print efficiently. If + unsure, say N. + config SERIAL_SEARCH_ALL bool "Search for serial devices after default one failed" depends on DM_SERIAL diff --git a/drivers/serial/serial-uclass.c b/drivers/serial/serial-uclass.c index f30f352..10d6b80 100644 --- a/drivers/serial/serial-uclass.c +++ b/drivers/serial/serial-uclass.c @@ -200,8 +200,30 @@ static void _serial_putc(struct udevice *dev, char ch) static void _serial_puts(struct udevice *dev, const char *str) { - while (*str) - _serial_putc(dev, *str++); + struct dm_serial_ops *ops = serial_get_ops(dev); + + if (!CONFIG_IS_ENABLED(SERIAL_PUTS) || !ops->puts) { + while (*str) + _serial_putc(dev, *str++); + return; + } + + do { + const char *newline = strchrnul(str, '\n'); + size_t len = newline - str + !!*newline; + + do { + ssize_t written = ops->puts(dev, str, len); + + if (written < 0) + return; + str += written; + len -= written; + } while (len); + + if (*newline) + _serial_putc(dev, '\r'); + } while (*str); } static int __serial_getc(struct udevice *dev) diff --git a/include/serial.h b/include/serial.h index 2681d26..8c2e7ad 100644 --- a/include/serial.h +++ b/include/serial.h @@ -196,6 +196,24 @@ struct dm_serial_ops { */ int (*putc)(struct udevice *dev, const char ch); /** + * puts() - Write a string + * + * This writes a string. This function should be implemented only if + * writing multiple characters at once is more performant than just + * calling putc() in a loop. + * + * If the whole string cannot be written at once, then this function + * should return the number of characters written. Returning a negative + * error code implies that no characters were written. If this function + * returns 0, then it will be called again with the same arguments. + * + * @dev: Device pointer + * @s: The string to write + * @len: The length of the string to write. + * @return The number of characters written on success, or -ve on error + */ + ssize_t (*puts)(struct udevice *dev, const char *s, size_t len); + /** * pending() - Check if input/output characters are waiting * * This can be used to return an indication of the number of waiting -- cgit v1.1