From 832685f07c75388e4f268d15536c988cc345b5a1 Mon Sep 17 00:00:00 2001 From: Fabien Parent Date: Thu, 17 Oct 2019 21:02:05 +0200 Subject: clk: mediatek: use unsigned type for returning the clk rate mtk_clk_find_parent_rate is calling clk_get_rate to know the rate of a parent clock. clk_get_rate returns a ulong, while mtk_clk_find_parent_rate returns an int. This implicit cast creates an issue for clock rates big enough to need the full 32 bits to store its data. When that happen the clk rate will become incorrect because of the implicit cast between ulong -> int -> ulong. This commit change the return type of mtk_clk_find_parent_rate to ulong. Signed-off-by: Fabien Parent --- drivers/clk/mediatek/clk-mtk.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c index 09ae2d4..c52537c 100644 --- a/drivers/clk/mediatek/clk-mtk.c +++ b/drivers/clk/mediatek/clk-mtk.c @@ -40,7 +40,7 @@ * the accurate frequency. */ static ulong mtk_clk_find_parent_rate(struct clk *clk, int id, - const struct driver *drv) + const struct driver *drv) { struct clk parent = { .id = id, }; -- cgit v1.1 From 5dcac2b9b3bd14748b68cadd3f855369c8926f05 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Tue, 22 Oct 2019 03:31:08 +0000 Subject: clk: show more error info when uclass_get_device_by_name It will ease debug when uclass_get_device_by_name failed with more error info printed out. Signed-off-by: Peng Fan --- drivers/clk/clk.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c index 1cf9987..4c477a4 100644 --- a/drivers/clk/clk.c +++ b/drivers/clk/clk.c @@ -20,8 +20,10 @@ int clk_register(struct clk *clk, const char *drv_name, int ret; ret = uclass_get_device_by_name(UCLASS_CLK, parent_name, &parent); - if (ret) - printf("%s: UCLASS parent: 0x%p\n", __func__, parent); + if (ret) { + printf("%s: name: %s parent: %s [0x%p]\n", + __func__, name, parent->name, parent); + } debug("%s: name: %s parent: %s [0x%p]\n", __func__, name, parent->name, parent); -- cgit v1.1 From efbdad3838c37722c07de0814f07e1b65955d1e7 Mon Sep 17 00:00:00 2001 From: Giulio Benetti Date: Thu, 12 Dec 2019 23:53:19 +0100 Subject: clk: uclass: clk_get_by_name() must not be available if CONFIG_OF_PLATDATA is enabled clk_get_by_name() requires clk_get_by_id() that is not available if CONFIG_OF_PLATDATA is defined, so move clk_get_by_name() into #else condition of #if CONFIG_IS_ENABLED(OF_PLATDATA). Signed-off-by: Giulio Benetti --- drivers/clk/clk-uclass.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c index 93cb490..0df38bd 100644 --- a/drivers/clk/clk-uclass.c +++ b/drivers/clk/clk-uclass.c @@ -326,7 +326,6 @@ int clk_set_defaults(struct udevice *dev, int stage) return 0; } -# endif /* OF_PLATDATA */ int clk_get_by_name(struct udevice *dev, const char *name, struct clk *clk) { @@ -343,6 +342,7 @@ int clk_get_by_name(struct udevice *dev, const char *name, struct clk *clk) return clk_get_by_index(dev, index, clk); } +# endif /* OF_PLATDATA */ int clk_get_by_name_nodev(ofnode node, const char *name, struct clk *clk) { -- cgit v1.1 From 9fca6729c6df2bc6978a74f60c0a151e57b437d8 Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Tue, 24 Dec 2019 23:56:22 -0500 Subject: clk: Include missing headers for linux/clk-provider.h This header was missing a couple of include dependencies when included on its own. Signed-off-by: Sean Anderson --- include/linux/clk-provider.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index 02ff1a3..0ef6e68 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -8,6 +8,10 @@ */ #ifndef __LINUX_CLK_PROVIDER_H #define __LINUX_CLK_PROVIDER_H + +#include +#include +#include #include static inline void clk_dm(ulong id, struct clk *clk) -- cgit v1.1 From 90cbfa50c2b85d60f41d5e9852141058e5bad3ac Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Tue, 24 Dec 2019 23:57:47 -0500 Subject: clk: Fix error checking of dev_read_addr_ptr dev_read_addr_ptr returns NULL on error, not FDT_ADDR_T_NONE. Signed-off-by: Sean Anderson --- drivers/clk/imx/clk-imx6q.c | 2 +- drivers/clk/imx/clk-imx8mm.c | 2 +- drivers/clk/imx/clk-imx8mn.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c index 5ae4781..bd0d3e4 100644 --- a/drivers/clk/imx/clk-imx6q.c +++ b/drivers/clk/imx/clk-imx6q.c @@ -115,7 +115,7 @@ static int imx6q_clk_probe(struct udevice *dev) /* CCM clocks */ base = dev_read_addr_ptr(dev); - if (base == (void *)FDT_ADDR_T_NONE) + if (!base) return -EINVAL; clk_dm(IMX6QDL_CLK_USDHC1_SEL, diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c index a05dac7..fc41a02 100644 --- a/drivers/clk/imx/clk-imx8mm.c +++ b/drivers/clk/imx/clk-imx8mm.c @@ -323,7 +323,7 @@ static int imx8mm_clk_probe(struct udevice *dev) imx_clk_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1)); base = dev_read_addr_ptr(dev); - if (base == (void *)FDT_ADDR_T_NONE) + if (!base) return -EINVAL; clk_dm(IMX8MM_CLK_A53_SRC, diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c index 4048cc6..eb43971 100644 --- a/drivers/clk/imx/clk-imx8mn.c +++ b/drivers/clk/imx/clk-imx8mn.c @@ -293,7 +293,7 @@ static int imx8mn_clk_probe(struct udevice *dev) imx_clk_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1)); base = dev_read_addr_ptr(dev); - if (base == (void *)FDT_ADDR_T_NONE) + if (!base) return -EINVAL; clk_dm(IMX8MN_CLK_A53_SRC, -- cgit v1.1 From 3391e7772933da74b488c761a2e444b9899cbd2a Mon Sep 17 00:00:00 2001 From: Giulio Benetti Date: Fri, 17 Jan 2020 13:06:40 +0100 Subject: clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti --- drivers/clk/imx/clk-pllv3.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/clk/imx/clk-pllv3.c b/drivers/clk/imx/clk-pllv3.c index fc16416..a540a5b 100644 --- a/drivers/clk/imx/clk-pllv3.c +++ b/drivers/clk/imx/clk-pllv3.c @@ -121,10 +121,16 @@ static ulong clk_pllv3_sys_set_rate(struct clk *clk, ulong rate) { struct clk_pllv3 *pll = to_clk_pllv3(clk); unsigned long parent_rate = clk_get_parent_rate(clk); - unsigned long min_rate = parent_rate * 54 / 2; - unsigned long max_rate = parent_rate * 108 / 2; + unsigned long min_rate; + unsigned long max_rate; u32 val, div; + if (parent_rate == 0) + return -EINVAL; + + min_rate = parent_rate * 54 / 2; + max_rate = parent_rate * 108 / 2; + if (rate < min_rate || rate > max_rate) return -EINVAL; -- cgit v1.1 From d37ecaba88cc7482d9481a6ee7de84ff454ede4a Mon Sep 17 00:00:00 2001 From: Giulio Benetti Date: Fri, 17 Jan 2020 13:06:41 +0100 Subject: clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti --- drivers/clk/imx/clk-pllv3.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/clk/imx/clk-pllv3.c b/drivers/clk/imx/clk-pllv3.c index a540a5b..72e6750 100644 --- a/drivers/clk/imx/clk-pllv3.c +++ b/drivers/clk/imx/clk-pllv3.c @@ -163,6 +163,9 @@ static ulong clk_pllv3_av_get_rate(struct clk *clk) u32 div = readl(pll->base) & pll->div_mask; u64 temp64 = (u64)parent_rate; + if (mfd == 0) + return -EIO; + temp64 *= mfn; do_div(temp64, mfd); -- cgit v1.1 From 041b06a7c32f596f00dd495444a1b02568a9d492 Mon Sep 17 00:00:00 2001 From: Giulio Benetti Date: Fri, 17 Jan 2020 13:06:42 +0100 Subject: clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti --- drivers/clk/imx/clk-pllv3.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/clk/imx/clk-pllv3.c b/drivers/clk/imx/clk-pllv3.c index 72e6750..0cdb9df 100644 --- a/drivers/clk/imx/clk-pllv3.c +++ b/drivers/clk/imx/clk-pllv3.c @@ -176,13 +176,19 @@ static ulong clk_pllv3_av_set_rate(struct clk *clk, ulong rate) { struct clk_pllv3 *pll = to_clk_pllv3(clk); unsigned long parent_rate = clk_get_parent_rate(clk); - unsigned long min_rate = parent_rate * 27; - unsigned long max_rate = parent_rate * 54; + unsigned long min_rate; + unsigned long max_rate; u32 val, div; u32 mfn, mfd = 1000000; u32 max_mfd = 0x3FFFFFFF; u64 temp64; + if (parent_rate == 0) + return -EINVAL; + + min_rate = parent_rate * 27; + max_rate = parent_rate * 54; + if (rate < min_rate || rate > max_rate) return -EINVAL; -- cgit v1.1 From fb3c4d926fa52b4a4f5b887eb29d64c24eb93d40 Mon Sep 17 00:00:00 2001 From: Pedro Jardim Date: Thu, 23 Jan 2020 10:20:14 -0300 Subject: clock_imx8mq: Delete not used init_usb_clk() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Function init_usb_clk() is not used anywhere, so it can simply be deleted. This was detected by the following sparse warning: arch/arm/mach-imx/imx8m/clock_imx8mq.c:377:6: warning: no previous prototype for ‘init_usb_clk’ [-Wmissing-prototypes] void init_usb_clk(void) ^~~~~~~~~~~~ Signed-off-by: Pedro Jardim --- arch/arm/mach-imx/imx8m/clock_imx8mq.c | 22 ---------------------- 1 file changed, 22 deletions(-) diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mq.c b/arch/arm/mach-imx/imx8m/clock_imx8mq.c index 878f2be..663fe4d 100644 --- a/arch/arm/mach-imx/imx8m/clock_imx8mq.c +++ b/arch/arm/mach-imx/imx8m/clock_imx8mq.c @@ -374,28 +374,6 @@ void init_wdog_clk(void) clock_enable(CCGR_WDOG3, 1); } -void init_usb_clk(void) -{ - if (!is_usb_boot()) { - clock_enable(CCGR_USB_CTRL1, 0); - clock_enable(CCGR_USB_CTRL2, 0); - clock_enable(CCGR_USB_PHY1, 0); - clock_enable(CCGR_USB_PHY2, 0); - /* 500MHz */ - clock_set_target_val(USB_BUS_CLK_ROOT, CLK_ROOT_ON | - CLK_ROOT_SOURCE_SEL(1)); - /* 100MHz */ - clock_set_target_val(USB_CORE_REF_CLK_ROOT, CLK_ROOT_ON | - CLK_ROOT_SOURCE_SEL(1)); - /* 100MHz */ - clock_set_target_val(USB_PHY_REF_CLK_ROOT, CLK_ROOT_ON | - CLK_ROOT_SOURCE_SEL(1)); - clock_enable(CCGR_USB_CTRL1, 1); - clock_enable(CCGR_USB_CTRL2, 1); - clock_enable(CCGR_USB_PHY1, 1); - clock_enable(CCGR_USB_PHY2, 1); - } -} void init_nand_clk(void) { -- cgit v1.1 From 953d02f0016c7c8781d697c21013a967a200bfbf Mon Sep 17 00:00:00 2001 From: Pedro Jardim Date: Thu, 23 Jan 2020 10:20:51 -0300 Subject: clock_imx8mq: Make do_imx8m_showclocks() static MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Since do_imx8m_showclocks() is only used inside this file, make it 'static'. This fixes the following sparse warning: arch/arm/mach-imx/imx8m/clock_imx8mq.c:836:5: warning: no previous prototype for ‘do_imx8m_showclocks’ [-Wmissing-prototypes] int do_imx8m_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, ^~~~~~~~~~~~~~~~~~~ Signed-off-by: Pedro Jardim --- arch/arm/mach-imx/imx8m/clock_imx8mq.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mq.c b/arch/arm/mach-imx/imx8m/clock_imx8mq.c index 663fe4d..d8530cc 100644 --- a/arch/arm/mach-imx/imx8m/clock_imx8mq.c +++ b/arch/arm/mach-imx/imx8m/clock_imx8mq.c @@ -811,7 +811,7 @@ int clock_init(void) * Dump some clockes. */ #ifndef CONFIG_SPL_BUILD -int do_imx8m_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, +static int do_imx8m_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { u32 freq; -- cgit v1.1 From 852cd55ea7aef90d9408d7b3b746f3c52e3a1e42 Mon Sep 17 00:00:00 2001 From: Pedro Jardim Date: Thu, 23 Jan 2020 10:21:05 -0300 Subject: clock_imx8mq: Remove the function sscg_pll_init() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Function sscg_pll_init() is not used anywhere, so it can simply be deleted. This was found because of the following sparse warning: arch/arm/mach-imx/imx8m/clock_imx8mq.c:702:5: warning: no previous prototype for ‘sscg_pll_init’ [-Wmissing-prototypes] int sscg_pll_init(u32 pll) ^~~~~~~~~~~~~ Signed-off-by: Pedro Jardim --- arch/arm/mach-imx/imx8m/clock_imx8mq.c | 71 ---------------------------------- 1 file changed, 71 deletions(-) diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mq.c b/arch/arm/mach-imx/imx8m/clock_imx8mq.c index d8530cc..72a70d8 100644 --- a/arch/arm/mach-imx/imx8m/clock_imx8mq.c +++ b/arch/arm/mach-imx/imx8m/clock_imx8mq.c @@ -677,77 +677,6 @@ int frac_pll_init(u32 pll, enum frac_pll_out_val val) return 0; } -int sscg_pll_init(u32 pll) -{ - void __iomem *pll_cfg0, __iomem *pll_cfg1, __iomem *pll_cfg2; - u32 val_cfg0, val_cfg1, val_cfg2, val; - u32 bypass1_mask = 0x20, bypass2_mask = 0x10; - int ret; - - switch (pll) { - case ANATOP_SYSTEM_PLL1: - pll_cfg0 = &ana_pll->sys_pll1_cfg0; - pll_cfg1 = &ana_pll->sys_pll1_cfg1; - pll_cfg2 = &ana_pll->sys_pll1_cfg2; - /* 800MHz */ - val_cfg2 = SSCG_PLL_FEEDBACK_DIV_F1_VAL(3) | - SSCG_PLL_FEEDBACK_DIV_F2_VAL(3); - val_cfg1 = 0; - val_cfg0 = SSCG_PLL_CLKE_MASK | SSCG_PLL_DIV2_CLKE_MASK | - SSCG_PLL_DIV3_CLKE_MASK | SSCG_PLL_DIV4_CLKE_MASK | - SSCG_PLL_DIV5_CLKE_MASK | SSCG_PLL_DIV6_CLKE_MASK | - SSCG_PLL_DIV8_CLKE_MASK | SSCG_PLL_DIV10_CLKE_MASK | - SSCG_PLL_DIV20_CLKE_MASK | SSCG_PLL_LOCK_SEL_MASK | - SSCG_PLL_REFCLK_SEL_OSC_25M; - break; - case ANATOP_SYSTEM_PLL2: - pll_cfg0 = &ana_pll->sys_pll2_cfg0; - pll_cfg1 = &ana_pll->sys_pll2_cfg1; - pll_cfg2 = &ana_pll->sys_pll2_cfg2; - /* 1000MHz */ - val_cfg2 = SSCG_PLL_FEEDBACK_DIV_F1_VAL(3) | - SSCG_PLL_FEEDBACK_DIV_F2_VAL(4); - val_cfg1 = 0; - val_cfg0 = SSCG_PLL_CLKE_MASK | SSCG_PLL_DIV2_CLKE_MASK | - SSCG_PLL_DIV3_CLKE_MASK | SSCG_PLL_DIV4_CLKE_MASK | - SSCG_PLL_DIV5_CLKE_MASK | SSCG_PLL_DIV6_CLKE_MASK | - SSCG_PLL_DIV8_CLKE_MASK | SSCG_PLL_DIV10_CLKE_MASK | - SSCG_PLL_DIV20_CLKE_MASK | SSCG_PLL_LOCK_SEL_MASK | - SSCG_PLL_REFCLK_SEL_OSC_25M; - break; - case ANATOP_SYSTEM_PLL3: - pll_cfg0 = &ana_pll->sys_pll3_cfg0; - pll_cfg1 = &ana_pll->sys_pll3_cfg1; - pll_cfg2 = &ana_pll->sys_pll3_cfg2; - /* 800MHz */ - val_cfg2 = SSCG_PLL_FEEDBACK_DIV_F1_VAL(3) | - SSCG_PLL_FEEDBACK_DIV_F2_VAL(3); - val_cfg1 = 0; - val_cfg0 = SSCG_PLL_PLL3_CLKE_MASK | SSCG_PLL_LOCK_SEL_MASK | - SSCG_PLL_REFCLK_SEL_OSC_25M; - break; - default: - return -EINVAL; - } - - /*bypass*/ - setbits_le32(pll_cfg0, bypass1_mask | bypass2_mask); - /* set value */ - writel(val_cfg2, pll_cfg2); - writel(val_cfg1, pll_cfg1); - /*unbypass1 and wait 70us */ - writel(val_cfg0 | bypass2_mask, pll_cfg1); - - __udelay(70); - - /* unbypass2 and wait lock */ - writel(val_cfg0, pll_cfg1); - ret = readl_poll_timeout(pll_cfg0, val, val & SSCG_PLL_LOCK_MASK, 1); - if (ret) - printf("%s timeout\n", __func__); - - return ret; -} int clock_init(void) { -- cgit v1.1 From 2f39ab1649caddf748ef1eff60c40fede5995ced Mon Sep 17 00:00:00 2001 From: Pedro Jardim Date: Thu, 23 Jan 2020 10:21:53 -0300 Subject: clock_imx8mq: Make frac_pll_init() static MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Since frac_pll_init() is only used in this file, change it to 'static'. This fixes the following sparse warning: arch/arm/mach-imx/imx8m/clock_imx8mq.c:662:5: warning: no previous prototype for ‘frac_pll_init’ [-Wmissing-prototypes] Signed-off-by: Pedro Jardim --- arch/arm/mach-imx/imx8m/clock_imx8mq.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mq.c b/arch/arm/mach-imx/imx8m/clock_imx8mq.c index 72a70d8..aad9cf1 100644 --- a/arch/arm/mach-imx/imx8m/clock_imx8mq.c +++ b/arch/arm/mach-imx/imx8m/clock_imx8mq.c @@ -636,7 +636,7 @@ void dram_pll_init(ulong pll_val) ; } -int frac_pll_init(u32 pll, enum frac_pll_out_val val) +static int frac_pll_init(u32 pll, enum frac_pll_out_val val) { void __iomem *pll_cfg0, __iomem *pll_cfg1; u32 val_cfg0, val_cfg1; -- cgit v1.1