From 4d7df7f7666a2bc6b0b8980969b69c8008b90af6 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Tue, 6 Sep 2022 18:53:17 +0200 Subject: stm32mp: stm32prog: support empty flashlayout When the STM32CubeProgrammer sent a empty flashlayout.tsv file, the command stm32prog correctly parse the file but data->dev_nb = 0 and the stm32prog_devices_init operations should be skipped. Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard --- arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c index a720d0b..7067605 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c @@ -1884,6 +1884,10 @@ static void stm32prog_devices_init(struct stm32prog_data *data) if (ret) goto error; + /* empty flashlayout */ + if (!data->dev_nb) + return; + /* initialize the selected device */ for (i = 0; i < data->dev_nb; i++) { ret = init_device(data, &data->dev[i]); -- cgit v1.1 From ada8fe0c42da5341989bdf1c11d4adb23f7aae37 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Tue, 6 Sep 2022 18:53:18 +0200 Subject: stm32mp: stm32prog: change default flashlayout location to CONFIG_SYS_LOAD_ADDR Change the defaut flashlayout location, hardcoded at STM32_DDR_BASE, to CONFIG_SYS_LOAD_ADDR to avoid issue on board with reserved memory at STM32_DDR_BASE. This patch changes the command behavior for STM32MP13 and STM32MP15 platform, as CONFIG_SYS_LOAD_ADDR(0xc2000000) != STM32_DDR_BASE but without impact for serial boot with STM32CubeProgrammer. Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard --- arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c | 2 +- arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c | 8 ++++---- arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_serial.c | 2 +- arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_usb.c | 2 +- 4 files changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c b/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c index f59414e..cb9e20d 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c @@ -61,7 +61,7 @@ static int do_stm32prog(struct cmd_tbl *cmdtp, int flag, int argc, dev = (int)dectoul(argv[2], NULL); - addr = STM32_DDR_BASE; + addr = CONFIG_SYS_LOAD_ADDR; size = 0; if (argc > 3) { addr = hextoul(argv[3], NULL); diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c index 7067605..082f788 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c @@ -1388,7 +1388,7 @@ static int dfu_init_entities(struct stm32prog_data *data) char buf[ALT_BUF_LEN]; sprintf(buf, "@FlashLayout/0x%02x/1*256Ke ram %x 40000", - PHASE_FLASHLAYOUT, STM32_DDR_BASE); + PHASE_FLASHLAYOUT, CONFIG_SYS_LOAD_ADDR); ret = dfu_alt_add(dfu, "ram", NULL, buf); log_debug("dfu_alt_add(ram, NULL,%s) result %d\n", buf, ret); } @@ -1699,15 +1699,15 @@ static void stm32prog_end_phase(struct stm32prog_data *data, u64 offset) { if (data->phase == PHASE_FLASHLAYOUT) { #if defined(CONFIG_LEGACY_IMAGE_FORMAT) - if (genimg_get_format((void *)STM32_DDR_BASE) == IMAGE_FORMAT_LEGACY) { - data->script = STM32_DDR_BASE; + if (genimg_get_format((void *)CONFIG_SYS_LOAD_ADDR) == IMAGE_FORMAT_LEGACY) { + data->script = CONFIG_SYS_LOAD_ADDR; data->phase = PHASE_END; log_notice("U-Boot script received\n"); return; } #endif log_notice("\nFlashLayout received, size = %lld\n", offset); - if (parse_flash_layout(data, STM32_DDR_BASE, offset)) + if (parse_flash_layout(data, CONFIG_SYS_LOAD_ADDR, offset)) stm32prog_err("Layout: invalid FlashLayout"); return; } diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_serial.c b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_serial.c index 1a69bc3..e719568 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_serial.c +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_serial.c @@ -462,7 +462,7 @@ static void get_phase_command(struct stm32prog_data *data) length = strlen(err_msg); } if (phase == PHASE_FLASHLAYOUT) - destination = STM32_DDR_BASE; + destination = CONFIG_SYS_LOAD_ADDR; stm32prog_serial_putc(length + 5); /* Total length */ stm32prog_serial_putc(phase & 0xFF); /* partition ID */ diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_usb.c b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_usb.c index a8b57c4..bcb4d37 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_usb.c +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_usb.c @@ -90,7 +90,7 @@ static int stm32prog_cmd_read(u64 offset, void *buf, long *len) } phase = stm32prog_data->phase; if (phase == PHASE_FLASHLAYOUT) - destination = STM32_DDR_BASE; + destination = CONFIG_SYS_LOAD_ADDR; dfu_offset = stm32prog_data->offset; /* mandatory header, size = PHASE_MIN_SIZE */ -- cgit v1.1 From 3df19b8bec379be01fd6d0db5a9bb4813f8148d3 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Tue, 6 Sep 2022 18:53:19 +0200 Subject: stm32mp: stm32prog: solve warning for 64bits compilation Solve many compilation warning when stm32prog is activated on the aarch64. Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard --- arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c | 14 +++++++------- arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c | 16 ++++++++-------- arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h | 14 +++++++------- arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_serial.c | 15 +++++++-------- arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_usb.c | 4 ++-- 5 files changed, 31 insertions(+), 32 deletions(-) diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c b/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c index cb9e20d..d2666b9 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c @@ -126,21 +126,21 @@ static int do_stm32prog(struct cmd_tbl *cmdtp, int flag, int argc, char *bootm_argv[5] = { "bootm", boot_addr_start, "-", dtb_addr, NULL }; - u32 uimage = data->uimage; - u32 dtb = data->dtb; - u32 initrd = data->initrd; + const void *uimage = (void *)data->uimage; + const void *dtb = (void *)data->dtb; + const void *initrd = (void *)data->initrd; if (!dtb) bootm_argv[3] = env_get("fdtcontroladdr"); else snprintf(dtb_addr, sizeof(dtb_addr) - 1, - "0x%x", dtb); + "0x%p", dtb); snprintf(boot_addr_start, sizeof(boot_addr_start) - 1, - "0x%x", uimage); + "0x%p", uimage); if (initrd) { - snprintf(initrd_addr, sizeof(initrd_addr) - 1, "0x%x:0x%x", + snprintf(initrd_addr, sizeof(initrd_addr) - 1, "0x%p:0x%zx", initrd, data->initrd_size); bootm_argv[2] = initrd_addr; } @@ -148,7 +148,7 @@ static int do_stm32prog(struct cmd_tbl *cmdtp, int flag, int argc, printf("Booting kernel at %s %s %s...\n\n\n", boot_addr_start, bootm_argv[2], bootm_argv[3]); /* Try bootm for legacy and FIT format image */ - if (genimg_get_format((void *)uimage) != IMAGE_FORMAT_INVALID) + if (genimg_get_format(uimage) != IMAGE_FORMAT_INVALID) do_bootm(cmdtp, 0, 4, bootm_argv); else if (CONFIG_IS_ENABLED(CMD_BOOTZ)) do_bootz(cmdtp, 0, 4, bootm_argv); diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c index 082f788..0763264 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c @@ -322,7 +322,7 @@ void stm32prog_header_check(uintptr_t raw_header, struct image_header_s *header) header->image_length = 0x0; } -static u32 stm32prog_header_checksum(u32 addr, struct image_header_s *header) +static u32 stm32prog_header_checksum(uintptr_t addr, struct image_header_s *header) { u32 i, checksum; u8 *payload; @@ -398,7 +398,7 @@ static int parse_name(struct stm32prog_data *data, if (strlen(p) < sizeof(part->name)) { strcpy(part->name, p); } else { - stm32prog_err("Layout line %d: partition name too long [%d]: %s", + stm32prog_err("Layout line %d: partition name too long [%zd]: %s", i, strlen(p), p); result = -EINVAL; } @@ -537,7 +537,7 @@ int (* const parse[COL_NB_STM32])(struct stm32prog_data *data, int i, char *p, }; static int parse_flash_layout(struct stm32prog_data *data, - ulong addr, + uintptr_t addr, ulong size) { int column = 0, part_nb = 0, ret; @@ -1440,7 +1440,7 @@ int stm32prog_otp_write(struct stm32prog_data *data, u32 offset, u8 *buffer, if (offset + *size > otp_size) *size = otp_size - offset; - memcpy((void *)((u32)data->otp_part + offset), buffer, *size); + memcpy((void *)((uintptr_t)data->otp_part + offset), buffer, *size); return 0; } @@ -1479,7 +1479,7 @@ int stm32prog_otp_read(struct stm32prog_data *data, u32 offset, u8 *buffer, data->otp_part, OTP_SIZE_TA); else if (IS_ENABLED(CONFIG_ARM_SMCCC)) result = stm32_smc_exec(STM32_SMC_BSEC, STM32_SMC_READ_ALL, - (u32)data->otp_part, 0); + (unsigned long)data->otp_part, 0); if (result) goto end_otp_read; } @@ -1491,7 +1491,7 @@ int stm32prog_otp_read(struct stm32prog_data *data, u32 offset, u8 *buffer, if (offset + *size > otp_size) *size = otp_size - offset; - memcpy(buffer, (void *)((u32)data->otp_part + offset), *size); + memcpy(buffer, (void *)((uintptr_t)data->otp_part + offset), *size); end_otp_read: log_debug("%s: result %i\n", __func__, result); @@ -1521,7 +1521,7 @@ int stm32prog_otp_start(struct stm32prog_data *data) data->otp_part, OTP_SIZE_TA); } else if (IS_ENABLED(CONFIG_ARM_SMCCC)) { arm_smccc_smc(STM32_SMC_BSEC, STM32_SMC_WRITE_ALL, - (u32)data->otp_part, 0, 0, 0, 0, 0, &res); + (uintptr_t)data->otp_part, 0, 0, 0, 0, 0, &res); if (!res.a0) { switch (res.a1) { @@ -1951,7 +1951,7 @@ int stm32prog_dfu_init(struct stm32prog_data *data) return dfu_init_entities(data); } -int stm32prog_init(struct stm32prog_data *data, ulong addr, ulong size) +int stm32prog_init(struct stm32prog_data *data, uintptr_t addr, ulong size) { memset(data, 0x0, sizeof(*data)); data->read_phase = PHASE_RESET; diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h index ac30076..397506a 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h @@ -154,7 +154,7 @@ struct stm32prog_data { u32 offset; char error[255]; struct stm32prog_part_t *cur_part; - u32 *otp_part; + void *otp_part; u8 pmic_part[PMIC_SIZE]; /* SERIAL information */ @@ -165,12 +165,12 @@ struct stm32prog_data { u8 read_phase; /* bootm information */ - u32 uimage; - u32 dtb; - u32 initrd; - u32 initrd_size; + uintptr_t uimage; + uintptr_t dtb; + uintptr_t initrd; + size_t initrd_size; - u32 script; + uintptr_t script; /* OPTEE PTA NVMEM */ struct udevice *tee; @@ -209,7 +209,7 @@ char *stm32prog_get_error(struct stm32prog_data *data); } /* Main function */ -int stm32prog_init(struct stm32prog_data *data, ulong addr, ulong size); +int stm32prog_init(struct stm32prog_data *data, uintptr_t addr, ulong size); void stm32prog_clean(struct stm32prog_data *data); #ifdef CONFIG_CMD_STM32PROG_SERIAL diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_serial.c b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_serial.c index e719568..f1bed7d 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_serial.c +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_serial.c @@ -300,7 +300,7 @@ static void stm32prog_serial_putc(u8 w_byte) } /* Helper function ************************************************/ -static u8 stm32prog_start(struct stm32prog_data *data, u32 address) +static u8 stm32prog_start(struct stm32prog_data *data, uintptr_t address) { u8 ret = 0; struct dfu_entity *dfu_entity; @@ -353,7 +353,7 @@ static u8 stm32prog_start(struct stm32prog_data *data, u32 address) } else { void (*entry)(void) = (void *)address; - printf("## Starting application at 0x%x ...\n", address); + printf("## Starting application at 0x%p ...\n", (void *)address); (*entry)(); printf("## Application terminated\n"); ret = -ENOEXEC; @@ -368,9 +368,9 @@ static u8 stm32prog_start(struct stm32prog_data *data, u32 address) * @tmp_xor: Current xor value to update * Return: The address area */ -static u32 get_address(u8 *tmp_xor) +static uintptr_t get_address(u8 *tmp_xor) { - u32 address = 0x0; + uintptr_t address = 0x0; u8 data; data = stm32prog_serial_getc(); @@ -487,7 +487,7 @@ static void get_phase_command(struct stm32prog_data *data) */ static void read_memory_command(struct stm32prog_data *data) { - u32 address = 0x0; + uintptr_t address = 0x0; u8 rcv_data = 0x0, tmp_xor = 0x0; u32 counter = 0x0; @@ -532,7 +532,7 @@ static void read_memory_command(struct stm32prog_data *data) */ static void start_command(struct stm32prog_data *data) { - u32 address = 0; + uintptr_t address = 0; u8 tmp_xor = 0x0; u8 ret, rcv_data; @@ -546,8 +546,7 @@ static void start_command(struct stm32prog_data *data) return; } /* validate partition */ - ret = stm32prog_start(data, - address); + ret = stm32prog_start(data, address); if (ret) stm32prog_serial_result(ABORT_BYTE); diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_usb.c b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_usb.c index bcb4d37..be38ff2 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_usb.c +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_usb.c @@ -41,7 +41,7 @@ static int stm32prog_set_phase(struct stm32prog_data *data, u8 phase, static int stm32prog_cmd_write(u64 offset, void *buf, long *len) { u8 phase; - u32 address; + uintptr_t address; u8 *pt = buf; void (*entry)(void); int ret; @@ -58,7 +58,7 @@ static int stm32prog_cmd_write(u64 offset, void *buf, long *len) address = (pt[1] << 24) | (pt[2] << 16) | (pt[3] << 8) | pt[4]; if (phase == PHASE_RESET) { entry = (void *)address; - printf("## Starting application at 0x%x ...\n", address); + printf("## Starting application at 0x%p ...\n", entry); (*entry)(); printf("## Application terminated\n"); return 0; -- cgit v1.1 From 93b2d4d0bda27a73a8825b05a69e8e31bf4232f6 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Tue, 6 Sep 2022 18:53:20 +0200 Subject: stm32mp: stm32prog: correctly handle OTP when SMC is not supported As the SMC is only supported in SP-MIN for STM32MP15x, the associated partition should be absent when the TA NVMEM is not available in OPT-TEE in STM32MP13x. Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard --- arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c | 25 +++++++++++++++++-------- arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h | 5 +++++ 2 files changed, 22 insertions(+), 8 deletions(-) diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c index 0763264..c03ad85 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c @@ -1342,10 +1342,22 @@ static int dfu_init_entities(struct stm32prog_data *data) struct stm32prog_part_t *part; struct dfu_entity *dfu; int alt_nb; + u32 otp_size = 0; alt_nb = 1; /* number of virtual = CMD*/ - if (IS_ENABLED(CONFIG_CMD_STM32PROG_OTP)) - alt_nb++; /* OTP*/ + + if (IS_ENABLED(CONFIG_CMD_STM32PROG_OTP)) { + /* OTP_SIZE_SMC = 0 if SMC is not supported */ + otp_size = OTP_SIZE_SMC; + /* check if PTA BSEC is supported */ + ret = optee_ta_open(data); + log_debug("optee_ta_open(PTA_NVMEM) result %d\n", ret); + if (!ret && data->tee) + otp_size = OTP_SIZE_TA; + if (otp_size) + alt_nb++; /* OTP*/ + } + if (CONFIG_IS_ENABLED(DM_PMIC)) alt_nb++; /* PMIC NVMEM*/ @@ -1363,6 +1375,7 @@ static int dfu_init_entities(struct stm32prog_data *data) puts("DFU alt info setting: "); if (data->part_nb) { alt_id = 0; + ret = 0; for (phase = 1; (phase <= PHASE_LAST_USER) && (alt_id < alt_nb) && !ret; @@ -1396,12 +1409,8 @@ static int dfu_init_entities(struct stm32prog_data *data) if (!ret) ret = stm32prog_alt_add_virt(dfu, "virtual", PHASE_CMD, CMD_SIZE); - if (!ret && IS_ENABLED(CONFIG_CMD_STM32PROG_OTP)) { - ret = optee_ta_open(data); - log_debug("optee_ta result %d\n", ret); - ret = stm32prog_alt_add_virt(dfu, "OTP", PHASE_OTP, - data->tee ? OTP_SIZE_TA : OTP_SIZE_SMC); - } + if (!ret && IS_ENABLED(CONFIG_CMD_STM32PROG_OTP) && otp_size) + ret = stm32prog_alt_add_virt(dfu, "OTP", PHASE_OTP, otp_size); if (!ret && CONFIG_IS_ENABLED(DM_PMIC)) ret = stm32prog_alt_add_virt(dfu, "PMIC", PHASE_PMIC, PMIC_SIZE); diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h index 397506a..58f4b96 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h @@ -20,7 +20,12 @@ #define DEFAULT_ADDRESS 0xFFFFFFFF #define CMD_SIZE 512 +/* SMC is only supported in SPMIN for STM32MP15x */ +#ifdef CONFIG_STM32MP15x #define OTP_SIZE_SMC 1024 +#else +#define OTP_SIZE_SMC 0 +#endif #define OTP_SIZE_TA 776 #define PMIC_SIZE 8 -- cgit v1.1 From 152498d580ad666d23d55603de2e77dd27a30adb Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Wed, 7 Sep 2022 13:42:23 +0200 Subject: ARM: dts: stm32mp: alignment with v6.0-rc3 Device tree alignment with Linux kernel v6.0-rc3: - ARM: dts: stm32: add support for USB2514B onboard hub on stm32mp15xx-dkx - ARM: dts: stm32: Add alternate pinmux for RCC pin - ARM: dts: stm32: Add alternate pinmux for DCMI pins - ARM: dts: stm32: Add alternate pinmux for SPI2 pins - ARM: dts: stm32: Fix SPI2 pinmux pin comments on stm32mp15 - ARM: dts: stm32: add optee reserved memory on stm32mp135f-dk - ARM: dts: stm32: enable optee firmware and SCMI support on STM32MP13 - ARM: dts: stm32: remove the IPCC "wakeup" IRQ on stm32mp151 Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard --- arch/arm/dts/stm32mp13-u-boot.dtsi | 10 +++--- arch/arm/dts/stm32mp131.dtsi | 28 ++++++++-------- arch/arm/dts/stm32mp135f-dk.dts | 4 +-- arch/arm/dts/stm32mp15-pinctrl.dtsi | 64 +++++++++++++++++++++++++++++++++---- arch/arm/dts/stm32mp151.dtsi | 7 ++-- arch/arm/dts/stm32mp15xx-dkx.dtsi | 8 +++++ 6 files changed, 91 insertions(+), 30 deletions(-) diff --git a/arch/arm/dts/stm32mp13-u-boot.dtsi b/arch/arm/dts/stm32mp13-u-boot.dtsi index 01552ad..47a4364 100644 --- a/arch/arm/dts/stm32mp13-u-boot.dtsi +++ b/arch/arm/dts/stm32mp13-u-boot.dtsi @@ -17,6 +17,12 @@ pinctrl0 = &pinctrl; }; + firmware { + optee { + u-boot,dm-pre-reloc; + }; + }; + /* need PSCI for sysreset during board_f */ psci { u-boot,dm-pre-proper; @@ -82,10 +88,6 @@ u-boot,dm-pre-reloc; }; -&optee { - u-boot,dm-pre-reloc; -}; - &pinctrl { u-boot,dm-pre-reloc; }; diff --git a/arch/arm/dts/stm32mp131.dtsi b/arch/arm/dts/stm32mp131.dtsi index 84e16bb..a1c6d0d 100644 --- a/arch/arm/dts/stm32mp131.dtsi +++ b/arch/arm/dts/stm32mp131.dtsi @@ -27,21 +27,8 @@ interrupt-parent = <&intc>; }; - scmi_sram: sram@2ffff000 { - compatible = "mmio-sram"; - reg = <0x2ffff000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x2ffff000 0x1000>; - - scmi_shm: scmi_shm@0 { - compatible = "arm,scmi-shmem"; - reg = <0 0x80>; - }; - }; - firmware { - optee: optee { + optee { method = "smc"; compatible = "linaro,optee-tz"; }; @@ -151,6 +138,19 @@ interrupt-parent = <&intc>; ranges; + scmi_sram: sram@2ffff000 { + compatible = "mmio-sram"; + reg = <0x2ffff000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x2ffff000 0x1000>; + + scmi_shm: scmi-sram@0 { + compatible = "arm,scmi-shmem"; + reg = <0 0x80>; + }; + }; + uart4: serial@40010000 { compatible = "st,stm32h7-uart"; reg = <0x40010000 0x400>; diff --git a/arch/arm/dts/stm32mp135f-dk.dts b/arch/arm/dts/stm32mp135f-dk.dts index f436ffa..e6b8ffd 100644 --- a/arch/arm/dts/stm32mp135f-dk.dts +++ b/arch/arm/dts/stm32mp135f-dk.dts @@ -31,8 +31,8 @@ #size-cells = <1>; ranges; - optee@de000000 { - reg = <0xde000000 0x2000000>; + optee@dd000000 { + reg = <0xdd000000 0x3000000>; no-map; }; }; diff --git a/arch/arm/dts/stm32mp15-pinctrl.dtsi b/arch/arm/dts/stm32mp15-pinctrl.dtsi index d3ed103..2cc9341 100644 --- a/arch/arm/dts/stm32mp15-pinctrl.dtsi +++ b/arch/arm/dts/stm32mp15-pinctrl.dtsi @@ -151,6 +151,43 @@ }; }; + dcmi_pins_c: dcmi-2 { + pins { + pinmux = ,/* DCMI_HSYNC */ + ,/* DCMI_VSYNC */ + ,/* DCMI_PIXCLK */ + ,/* DCMI_D0 */ + ,/* DCMI_D1 */ + ,/* DCMI_D2 */ + ,/* DCMI_D3 */ + ,/* DCMI_D4 */ + ,/* DCMI_D5 */ + ,/* DCMI_D6 */ + ,/* DCMI_D7 */ + ,/* DCMI_D8 */ + ;/* DCMI_D9 */ + bias-pull-up; + }; + }; + + dcmi_sleep_pins_c: dcmi-sleep-2 { + pins { + pinmux = ,/* DCMI_HSYNC */ + ,/* DCMI_VSYNC */ + ,/* DCMI_PIXCLK */ + ,/* DCMI_D0 */ + ,/* DCMI_D1 */ + ,/* DCMI_D2 */ + ,/* DCMI_D3 */ + ,/* DCMI_D4 */ + ,/* DCMI_D5 */ + ,/* DCMI_D6 */ + ,/* DCMI_D7 */ + ,/* DCMI_D8 */ + ;/* DCMI_D9 */ + }; + }; + ethernet0_rgmii_pins_a: rgmii-0 { pins1 { pinmux = , /* ETH_RGMII_CLK125 */ @@ -923,6 +960,21 @@ }; }; + mco1_pins_a: mco1-0 { + pins { + pinmux = ; /* MCO1 */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + }; + + mco1_sleep_pins_a: mco1-sleep-0 { + pins { + pinmux = ; /* MCO1 */ + }; + }; + mco2_pins_a: mco2-0 { pins { pinmux = ; /* MCO2 */ @@ -1814,30 +1866,30 @@ spi2_pins_a: spi2-0 { pins1 { - pinmux = , /* SPI1_SCK */ - ; /* SPI1_MOSI */ + pinmux = , /* SPI2_SCK */ + ; /* SPI2_MOSI */ bias-disable; drive-push-pull; slew-rate = <1>; }; pins2 { - pinmux = ; /* SPI1_MISO */ + pinmux = ; /* SPI2_MISO */ bias-disable; }; }; spi2_pins_b: spi2-1 { pins1 { - pinmux = , /* SPI1_SCK */ - ; /* SPI1_MOSI */ + pinmux = , /* SPI2_SCK */ + ; /* SPI2_MOSI */ bias-disable; drive-push-pull; slew-rate = <1>; }; pins2 { - pinmux = ; /* SPI1_MISO */ + pinmux = ; /* SPI2_MISO */ bias-disable; }; }; diff --git a/arch/arm/dts/stm32mp151.dtsi b/arch/arm/dts/stm32mp151.dtsi index 767a06e..f0fb022 100644 --- a/arch/arm/dts/stm32mp151.dtsi +++ b/arch/arm/dts/stm32mp151.dtsi @@ -1143,10 +1143,9 @@ reg = <0x4c001000 0x400>; st,proc-id = <0>; interrupts-extended = - <&intc GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, - <&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, - <&exti 61 1>; - interrupt-names = "rx", "tx", "wakeup"; + <&exti 61 1>, + <&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "rx", "tx"; clocks = <&rcc IPCC>; wakeup-source; status = "disabled"; diff --git a/arch/arm/dts/stm32mp15xx-dkx.dtsi b/arch/arm/dts/stm32mp15xx-dkx.dtsi index 3d36cac..5a045d7 100644 --- a/arch/arm/dts/stm32mp15xx-dkx.dtsi +++ b/arch/arm/dts/stm32mp15xx-dkx.dtsi @@ -685,6 +685,14 @@ &usbh_ehci { phys = <&usbphyc_port0>; status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + /* onboard HUB */ + hub@1 { + compatible = "usb424,2514"; + reg = <1>; + vdd-supply = <&v3v3>; + }; }; &usbotg_hs { -- cgit v1.1 From 450036f4eff2f9bccb13355d7d96edf217f91ed9 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Fri, 9 Sep 2022 17:22:15 +0200 Subject: stm32mp: stm32prog: improve the partitioning trace Improve the partitioning trace done in command stm32prog: - remove the trace "partition: Done" when the GPT partitioning is not done - indicate the mmc instance used for each 'gpt write' command Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard --- arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c index c03ad85..89552d2 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c @@ -1090,7 +1090,6 @@ static int create_gpt_partitions(struct stm32prog_data *data) if (!buf) return -ENOMEM; - puts("partitions : "); /* initialize the selected device */ for (i = 0; i < data->dev_nb; i++) { /* create gpt partition support only for full update on MMC */ @@ -1098,6 +1097,7 @@ static int create_gpt_partitions(struct stm32prog_data *data) !data->dev[i].full_update) continue; + printf("partitions on mmc%d: ", data->dev[i].dev_id); offset = 0; rootfs_found = false; memset(buf, 0, buflen); @@ -1197,8 +1197,8 @@ static int create_gpt_partitions(struct stm32prog_data *data) sprintf(buf, "part list mmc %d", data->dev[i].dev_id); run_command(buf, 0); #endif + puts("done\n"); } - puts("done\n"); #ifdef DEBUG run_command("mtd list", 0); -- cgit v1.1 From 89f3745152ab1a88eb9b6629a12b4ff0efe8c61b Mon Sep 17 00:00:00 2001 From: Christophe Kerello Date: Mon, 12 Sep 2022 17:40:50 +0200 Subject: board: st: stm32mp1: use of correct compatible string to add partitions Current compatible string used to update SPI NAND and SPI NOR devices can lead to a wrong partitions update (for example, SPI NAND partitions added to SPI NOR node in the device tree). To avoid this wrong behavior, use jedec,spi-nor compatible string for SPI NOR devices and spi-nand compatible string for SPI NAND devices. Signed-off-by: Christophe Kerello Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard --- board/st/stm32mp1/stm32mp1.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/st/stm32mp1/stm32mp1.c b/board/st/stm32mp1/stm32mp1.c index 581a4df..2d98ff4 100644 --- a/board/st/stm32mp1/stm32mp1.c +++ b/board/st/stm32mp1/stm32mp1.c @@ -898,8 +898,8 @@ int mmc_get_env_dev(void) int ft_board_setup(void *blob, struct bd_info *bd) { static const struct node_info nodes[] = { - { "st,stm32f469-qspi", MTD_DEV_TYPE_NOR, }, - { "st,stm32f469-qspi", MTD_DEV_TYPE_SPINAND}, + { "jedec,spi-nor", MTD_DEV_TYPE_NOR, }, + { "spi-nand", MTD_DEV_TYPE_SPINAND}, { "st,stm32mp15-fmc2", MTD_DEV_TYPE_NAND, }, { "st,stm32mp1-fmc2-nfc", MTD_DEV_TYPE_NAND, }, }; -- cgit v1.1 From c6327ba40f59de42cfac4b6e489f4a7a1539ddf5 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Thu, 15 Sep 2022 18:11:38 +0200 Subject: arm: stm32mp: add defines for BSEC_LOCK status in stm32key command Add defines for value used in stm32key for BSEC permanent lock status and error. This patch is a preliminary step to support more lock status in BSEC driver. Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard --- arch/arm/mach-stm32mp/cmd_stm32key.c | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/arch/arm/mach-stm32mp/cmd_stm32key.c b/arch/arm/mach-stm32mp/cmd_stm32key.c index 68f2892..1899d91 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32key.c +++ b/arch/arm/mach-stm32mp/cmd_stm32key.c @@ -19,6 +19,9 @@ #define STM32_OTP_HASH_KEY_START 24 #define STM32_OTP_HASH_KEY_SIZE 8 +#define BSEC_LOCK_ERROR (-1) +#define BSEC_LOCK_PERM BIT(0) + static int get_misc_dev(struct udevice **dev) { int ret; @@ -60,14 +63,14 @@ static int read_hash_otp(bool print, bool *locked, bool *closed) val = ~0x0; ret = misc_read(dev, STM32_BSEC_LOCK(word), &lock, 4); if (ret != 4) - lock = -1; + lock = BSEC_LOCK_ERROR; if (print) - printf("OTP HASH %i: %x lock : %d\n", word, val, lock); + printf("OTP HASH %i: %x lock : %x\n", word, val, lock); if (val == ~0x0) nb_invalid++; else if (val == 0x0) nb_zero++; - if (lock == 1) + if (lock & BSEC_LOCK_PERM) nb_lock++; } @@ -77,13 +80,13 @@ static int read_hash_otp(bool print, bool *locked, bool *closed) val = 0x0; ret = misc_read(dev, STM32_BSEC_LOCK(word), &lock, 4); if (ret != 4) - lock = -1; + lock = BSEC_LOCK_ERROR; status = (val & STM32_OTP_CLOSE_MASK) == STM32_OTP_CLOSE_MASK; if (closed) *closed = status; if (print) - printf("OTP %d: closed status: %d lock : %d\n", word, status, lock); + printf("OTP %d: closed status: %d lock : %x\n", word, status, lock); status = (nb_lock == STM32_OTP_HASH_KEY_SIZE); if (locked) @@ -128,7 +131,7 @@ static int fuse_hash_value(u32 addr, bool print) return ret; } /* on success, lock the OTP for HASH key */ - val = 1; + val = BSEC_LOCK_PERM; ret = misc_write(dev, STM32_BSEC_LOCK(word), &val, 4); if (ret != 4) { log_err("Lock OTP %i failed\n", word); -- cgit v1.1 From 8921b3dccd24da7e2d1c7ea6ccb56d065ec588c6 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Thu, 15 Sep 2022 18:11:39 +0200 Subject: arm: stm32mp: introduced read_close_status function in stm32key command Split the read_hash_otp function and introduce the helper function read_close_status to read the close status in OTP separately of the PKH. This patch is a preliminary step for STM32MP13 support. Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard --- arch/arm/mach-stm32mp/cmd_stm32key.c | 107 +++++++++++++++++++++-------------- 1 file changed, 65 insertions(+), 42 deletions(-) diff --git a/arch/arm/mach-stm32mp/cmd_stm32key.c b/arch/arm/mach-stm32mp/cmd_stm32key.c index 1899d91..68f9b1a 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32key.c +++ b/arch/arm/mach-stm32mp/cmd_stm32key.c @@ -45,18 +45,13 @@ static void read_hash_value(u32 addr) } } -static int read_hash_otp(bool print, bool *locked, bool *closed) +static int read_hash_otp(struct udevice *dev, bool print, bool *locked) { - struct udevice *dev; int i, word, ret; int nb_invalid = 0, nb_zero = 0, nb_lock = 0; u32 val, lock; bool status; - ret = get_misc_dev(&dev); - if (ret) - return ret; - for (i = 0, word = STM32_OTP_HASH_KEY_START; i < STM32_OTP_HASH_KEY_SIZE; i++, word++) { ret = misc_read(dev, STM32_BSEC_OTP(word), &val, 4); if (ret != 4) @@ -74,20 +69,6 @@ static int read_hash_otp(bool print, bool *locked, bool *closed) nb_lock++; } - word = STM32_OTP_CLOSE_ID; - ret = misc_read(dev, STM32_BSEC_OTP(word), &val, 4); - if (ret != 4) - val = 0x0; - ret = misc_read(dev, STM32_BSEC_LOCK(word), &lock, 4); - if (ret != 4) - lock = BSEC_LOCK_ERROR; - - status = (val & STM32_OTP_CLOSE_MASK) == STM32_OTP_CLOSE_MASK; - if (closed) - *closed = status; - if (print) - printf("OTP %d: closed status: %d lock : %x\n", word, status, lock); - status = (nb_lock == STM32_OTP_HASH_KEY_SIZE); if (locked) *locked = status; @@ -108,16 +89,40 @@ static int read_hash_otp(bool print, bool *locked, bool *closed) return 0; } -static int fuse_hash_value(u32 addr, bool print) +static int read_close_status(struct udevice *dev, bool print, bool *closed) +{ + int word, ret, result; + u32 val, lock; + bool status; + + result = 0; + word = STM32_OTP_CLOSE_ID; + ret = misc_read(dev, STM32_BSEC_OTP(word), &val, 4); + if (ret < 0) + result = ret; + if (ret != 4) + val = 0x0; + + ret = misc_read(dev, STM32_BSEC_LOCK(word), &lock, 4); + if (ret < 0) + result = ret; + if (ret != 4) + lock = BSEC_LOCK_ERROR; + + status = (val & STM32_OTP_CLOSE_MASK) == STM32_OTP_CLOSE_MASK; + if (closed) + *closed = status; + if (print) + printf("OTP %d: closed status: %d lock : %x\n", word, status, lock); + + return result; +} + +static int fuse_hash_value(struct udevice *dev, u32 addr, bool print) { - struct udevice *dev; u32 word, val; int i, ret; - ret = get_misc_dev(&dev); - if (ret) - return ret; - for (i = 0, word = STM32_OTP_HASH_KEY_START; i < STM32_OTP_HASH_KEY_SIZE; i++, word++, addr += 4) { @@ -158,10 +163,20 @@ static int confirm_prog(void) static int do_stm32key_read(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { + struct udevice *dev; u32 addr; + int ret; + + ret = get_misc_dev(&dev); if (argc == 1) { - read_hash_otp(true, NULL, NULL); + if (ret) + return CMD_RET_FAILURE; + read_hash_otp(dev, true, NULL); + ret = read_close_status(dev, true, NULL); + if (ret) + return CMD_RET_FAILURE; + return CMD_RET_SUCCESS; } @@ -176,8 +191,10 @@ static int do_stm32key_read(struct cmd_tbl *cmdtp, int flag, int argc, char *con static int do_stm32key_fuse(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { + struct udevice *dev; u32 addr; - bool yes = false, lock, closed; + int ret; + bool yes = false, lock; if (argc < 2) return CMD_RET_USAGE; @@ -192,20 +209,23 @@ static int do_stm32key_fuse(struct cmd_tbl *cmdtp, int flag, int argc, char *con if (!addr) return CMD_RET_USAGE; - if (read_hash_otp(!yes, &lock, &closed) != -ENOENT) { + ret = get_misc_dev(&dev); + if (ret) + return CMD_RET_FAILURE; + + if (read_hash_otp(dev, !yes, &lock) != -ENOENT) { printf("Error: can't fuse again the OTP\n"); return CMD_RET_FAILURE; } - - if (lock || closed) { - printf("Error: invalid OTP configuration (lock=%d, closed=%d)\n", lock, closed); + if (lock) { + printf("Error: PKH is locked\n"); return CMD_RET_FAILURE; } if (!yes && !confirm_prog()) return CMD_RET_FAILURE; - if (fuse_hash_value(addr, !yes)) + if (fuse_hash_value(dev, addr, !yes)) return CMD_RET_FAILURE; printf("Hash key updated !\n"); @@ -227,28 +247,31 @@ static int do_stm32key_close(struct cmd_tbl *cmdtp, int flag, int argc, char *co yes = true; } - ret = read_hash_otp(!yes, &lock, &closed); - if (ret) { - if (ret == -ENOENT) - printf("Error: OTP not programmed!\n"); + ret = get_misc_dev(&dev); + if (ret) + return CMD_RET_FAILURE; + + if (read_close_status(dev, !yes, &closed)) return CMD_RET_FAILURE; - } if (closed) { printf("Error: already closed!\n"); return CMD_RET_FAILURE; } + /* check PKH status before to close */ + ret = read_hash_otp(dev, !yes, &lock); + if (ret) { + if (ret == -ENOENT) + printf("Error: OTP not programmed!\n"); + return CMD_RET_FAILURE; + } if (!lock) printf("Warning: OTP not locked!\n"); if (!yes && !confirm_prog()) return CMD_RET_FAILURE; - ret = get_misc_dev(&dev); - if (ret) - return CMD_RET_FAILURE; - val = STM32_OTP_CLOSE_MASK; ret = misc_write(dev, STM32_BSEC_OTP(STM32_OTP_CLOSE_ID), &val, 4); if (ret != 4) { -- cgit v1.1 From fd1f4c9abd8eba06c5ad1169a03bd28b4c2e54a7 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Thu, 15 Sep 2022 18:11:40 +0200 Subject: arm: stm32mp: support several key in command stm32key Update the command stm32key to support several keys selected by key name and managed by the new sub-command: stm32key list stm32key select [] stm32key read -a This patch doesn't change the STM32MP15 behavior, only PKH is supported, but it is a preliminary patch for STM32MP13 support. Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard --- arch/arm/mach-stm32mp/cmd_stm32key.c | 195 ++++++++++++++++++++++++++--------- 1 file changed, 149 insertions(+), 46 deletions(-) diff --git a/arch/arm/mach-stm32mp/cmd_stm32key.c b/arch/arm/mach-stm32mp/cmd_stm32key.c index 68f9b1a..4eac560 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32key.c +++ b/arch/arm/mach-stm32mp/cmd_stm32key.c @@ -15,9 +15,37 @@ #define STM32_OTP_CLOSE_ID 0 #define STM32_OTP_CLOSE_MASK BIT(6) -/* HASH of key: 8 OTPs, starting with OTP24) */ -#define STM32_OTP_HASH_KEY_START 24 -#define STM32_OTP_HASH_KEY_SIZE 8 +/* PKH is the first element of the key list */ +#define STM32KEY_PKH 0 + +struct stm32key { + char *name; + char *desc; + u8 start; + u8 size; +}; + +const struct stm32key stm32mp15_list[] = { + [STM32KEY_PKH] = { + .name = "PKH", + .desc = "Hash of the ECC Public Key (ECDSA is the authentication algorithm)", + .start = 24, + .size = 8, + } +}; + +/* index of current selected key in stm32key list, 0 = PKH by default */ +static u8 stm32key_index; + +static u8 get_key_nb(void) +{ + return ARRAY_SIZE(stm32mp15_list); +} + +static const struct stm32key *get_key(u8 index) +{ + return &stm32mp15_list[index]; +} #define BSEC_LOCK_ERROR (-1) #define BSEC_LOCK_PERM BIT(0) @@ -33,26 +61,25 @@ static int get_misc_dev(struct udevice **dev) return ret; } -static void read_hash_value(u32 addr) +static void read_key_value(const struct stm32key *key, u32 addr) { int i; - printf("Read KEY at 0x%x\n", addr); - for (i = 0; i < STM32_OTP_HASH_KEY_SIZE; i++) { - printf("OTP value %i: %x\n", STM32_OTP_HASH_KEY_START + i, - __be32_to_cpu(*(u32 *)addr)); + for (i = 0; i < key->size; i++) { + printf("%s OTP %i: [%08x] %08x\n", key->name, key->start + i, + addr, __be32_to_cpu(*(u32 *)addr)); addr += 4; } } -static int read_hash_otp(struct udevice *dev, bool print, bool *locked) +static int read_key_otp(struct udevice *dev, const struct stm32key *key, bool print, bool *locked) { int i, word, ret; - int nb_invalid = 0, nb_zero = 0, nb_lock = 0; + int nb_invalid = 0, nb_zero = 0, nb_lock = 0, nb_lock_err = 0; u32 val, lock; bool status; - for (i = 0, word = STM32_OTP_HASH_KEY_START; i < STM32_OTP_HASH_KEY_SIZE; i++, word++) { + for (i = 0, word = key->start; i < key->size; i++, word++) { ret = misc_read(dev, STM32_BSEC_OTP(word), &val, 4); if (ret != 4) val = ~0x0; @@ -60,29 +87,33 @@ static int read_hash_otp(struct udevice *dev, bool print, bool *locked) if (ret != 4) lock = BSEC_LOCK_ERROR; if (print) - printf("OTP HASH %i: %x lock : %x\n", word, val, lock); + printf("%s OTP %i: %08x lock : %08x\n", key->name, word, val, lock); if (val == ~0x0) nb_invalid++; else if (val == 0x0) nb_zero++; if (lock & BSEC_LOCK_PERM) nb_lock++; + if (lock & BSEC_LOCK_ERROR) + nb_lock_err++; } - status = (nb_lock == STM32_OTP_HASH_KEY_SIZE); + status = nb_lock_err || (nb_lock == key->size); if (locked) *locked = status; - if (!status && print) - printf("Hash of key is not locked!\n"); + if (nb_lock_err && print) + printf("%s lock is invalid!\n", key->name); + else if (!status && print) + printf("%s is not locked!\n", key->name); - if (nb_invalid == STM32_OTP_HASH_KEY_SIZE) { + if (nb_invalid == key->size) { if (print) - printf("Hash of key is invalid!\n"); + printf("%s is invalid!\n", key->name); return -EINVAL; } - if (nb_zero == STM32_OTP_HASH_KEY_SIZE) { + if (nb_zero == key->size) { if (print) - printf("Hash of key is free!\n"); + printf("%s is free!\n", key->name); return -ENOENT; } @@ -113,33 +144,31 @@ static int read_close_status(struct udevice *dev, bool print, bool *closed) if (closed) *closed = status; if (print) - printf("OTP %d: closed status: %d lock : %x\n", word, status, lock); + printf("OTP %d: closed status: %d lock : %08x\n", word, status, lock); return result; } -static int fuse_hash_value(struct udevice *dev, u32 addr, bool print) +static int fuse_key_value(struct udevice *dev, const struct stm32key *key, u32 addr, bool print) { u32 word, val; int i, ret; - for (i = 0, word = STM32_OTP_HASH_KEY_START; - i < STM32_OTP_HASH_KEY_SIZE; - i++, word++, addr += 4) { + for (i = 0, word = key->start; i < key->size; i++, word++, addr += 4) { val = __be32_to_cpu(*(u32 *)addr); if (print) - printf("Fuse OTP %i : %x\n", word, val); + printf("Fuse %s OTP %i : %08x\n", key->name, word, val); ret = misc_write(dev, STM32_BSEC_OTP(word), &val, 4); if (ret != 4) { - log_err("Fuse OTP %i failed\n", word); + log_err("Fuse %s OTP %i failed\n", key->name, word); return ret; } - /* on success, lock the OTP for HASH key */ + /* on success, lock the OTP for the key */ val = BSEC_LOCK_PERM; ret = misc_write(dev, STM32_BSEC_LOCK(word), &val, 4); if (ret != 4) { - log_err("Lock OTP %i failed\n", word); + log_err("Lock %s OTP %i failed\n", key->name, word); return ret; } } @@ -161,36 +190,99 @@ static int confirm_prog(void) return 0; } +static void display_key_info(const struct stm32key *key) +{ + printf("%s : %s\n", key->name, key->desc); + printf("\tOTP%d..%d\n", key->start, key->start + key->size); +} + +static int do_stm32key_list(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) +{ + int i; + + for (i = 0; i < get_key_nb(); i++) + display_key_info(get_key(i)); + + return CMD_RET_SUCCESS; +} + +static int do_stm32key_select(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) +{ + const struct stm32key *key; + int i; + + if (argc == 1) { + printf("Selected key:\n"); + key = get_key(stm32key_index); + display_key_info(key); + return CMD_RET_SUCCESS; + } + + for (i = 0; i < get_key_nb(); i++) { + key = get_key(i); + if (!strcmp(key->name, argv[1])) { + printf("%s selected\n", key->name); + stm32key_index = i; + return CMD_RET_SUCCESS; + } + } + + printf("Unknown key %s\n", argv[1]); + + return CMD_RET_FAILURE; +} + static int do_stm32key_read(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { + const struct stm32key *key; struct udevice *dev; u32 addr; - int ret; + int ret, i; + int result; ret = get_misc_dev(&dev); if (argc == 1) { if (ret) return CMD_RET_FAILURE; - read_hash_otp(dev, true, NULL); - ret = read_close_status(dev, true, NULL); + key = get_key(stm32key_index); + ret = read_key_otp(dev, key, true, NULL); + if (ret != -ENOENT) + return CMD_RET_FAILURE; + return CMD_RET_SUCCESS; + } + + if (!strcmp("-a", argv[1])) { if (ret) return CMD_RET_FAILURE; + result = CMD_RET_SUCCESS; + for (i = 0; i < get_key_nb(); i++) { + key = get_key(i); + ret = read_key_otp(dev, key, true, NULL); + if (ret != -ENOENT) + result = CMD_RET_FAILURE; + } + ret = read_close_status(dev, true, NULL); + if (ret) + result = CMD_RET_FAILURE; - return CMD_RET_SUCCESS; + return result; } addr = hextoul(argv[1], NULL); if (!addr) return CMD_RET_USAGE; - read_hash_value(addr); + key = get_key(stm32key_index); + printf("Read %s at 0x%08x\n", key->name, addr); + read_key_value(key, addr); return CMD_RET_SUCCESS; } static int do_stm32key_fuse(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { + const struct stm32key *key = get_key(stm32key_index); struct udevice *dev; u32 addr; int ret; @@ -213,28 +305,34 @@ static int do_stm32key_fuse(struct cmd_tbl *cmdtp, int flag, int argc, char *con if (ret) return CMD_RET_FAILURE; - if (read_hash_otp(dev, !yes, &lock) != -ENOENT) { + if (read_key_otp(dev, key, !yes, &lock) != -ENOENT) { printf("Error: can't fuse again the OTP\n"); return CMD_RET_FAILURE; } if (lock) { - printf("Error: PKH is locked\n"); + printf("Error: %s is locked\n", key->name); return CMD_RET_FAILURE; } + if (!yes) { + printf("Writing %s with\n", key->name); + read_key_value(key, addr); + } + if (!yes && !confirm_prog()) return CMD_RET_FAILURE; - if (fuse_hash_value(dev, addr, !yes)) + if (fuse_key_value(dev, key, addr, !yes)) return CMD_RET_FAILURE; - printf("Hash key updated !\n"); + printf("%s updated !\n", key->name); return CMD_RET_SUCCESS; } static int do_stm32key_close(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { + const struct stm32key *key; bool yes, lock, closed; struct udevice *dev; u32 val; @@ -260,14 +358,15 @@ static int do_stm32key_close(struct cmd_tbl *cmdtp, int flag, int argc, char *co } /* check PKH status before to close */ - ret = read_hash_otp(dev, !yes, &lock); + key = get_key(STM32KEY_PKH); + ret = read_key_otp(dev, key, !yes, &lock); if (ret) { if (ret == -ENOENT) - printf("Error: OTP not programmed!\n"); + printf("Error: %s not programmed!\n", key->name); return CMD_RET_FAILURE; } if (!lock) - printf("Warning: OTP not locked!\n"); + printf("Warning: %s not locked!\n", key->name); if (!yes && !confirm_prog()) return CMD_RET_FAILURE; @@ -275,7 +374,7 @@ static int do_stm32key_close(struct cmd_tbl *cmdtp, int flag, int argc, char *co val = STM32_OTP_CLOSE_MASK; ret = misc_write(dev, STM32_BSEC_OTP(STM32_OTP_CLOSE_ID), &val, 4); if (ret != 4) { - printf("Error: can't update OTP\n"); + printf("Error: can't update OTP %d\n", STM32_OTP_CLOSE_ID); return CMD_RET_FAILURE; } @@ -285,11 +384,15 @@ static int do_stm32key_close(struct cmd_tbl *cmdtp, int flag, int argc, char *co } static char stm32key_help_text[] = - "read []: Read the hash stored at addr in memory or in OTP\n" - "stm32key fuse [-y] : Fuse hash stored at addr in OTP\n" - "stm32key close [-y] : Close the device, the hash stored in OTP\n"; - -U_BOOT_CMD_WITH_SUBCMDS(stm32key, "Fuse ST Hash key", stm32key_help_text, + "list : list the supported key with description\n" + "stm32key select [] : Select the key identified by or display the key used for read/fuse command\n" + "stm32key read [ | -a ] : Read the curent key at or current / all (-a) key in OTP\n" + "stm32key fuse [-y] : Fuse the current key at addr in OTP\n" + "stm32key close [-y] : Close the device\n"; + +U_BOOT_CMD_WITH_SUBCMDS(stm32key, "Manage key on STM32", stm32key_help_text, + U_BOOT_SUBCMD_MKENT(list, 1, 0, do_stm32key_list), + U_BOOT_SUBCMD_MKENT(select, 2, 0, do_stm32key_select), U_BOOT_SUBCMD_MKENT(read, 2, 0, do_stm32key_read), U_BOOT_SUBCMD_MKENT(fuse, 3, 0, do_stm32key_fuse), U_BOOT_SUBCMD_MKENT(close, 2, 0, do_stm32key_close)); -- cgit v1.1 From e83cef87a847d10aa2c46308bd8ac870bf56deee Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Thu, 15 Sep 2022 18:11:41 +0200 Subject: arm: stm32mp: adapt the command stm32key for STM32MP13x Change the mask of OTP0 used to close the device on STM32MP - STM32MP15x: bit 6 of OPT0 - STM32MP13x: 0b111111 = 0x3F for OTP_SECURED closed device And support the 2 keys for STM32MP13x - PKHTH : Hash of the 8 ECC Public Keys Hashes Table (ECDSA is the authentication algorithm) - EDMK : Encryption/Decryption Master Key Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard --- arch/arm/mach-stm32mp/cmd_stm32key.c | 52 +++++++++++++++++++++++++++++++----- 1 file changed, 45 insertions(+), 7 deletions(-) diff --git a/arch/arm/mach-stm32mp/cmd_stm32key.c b/arch/arm/mach-stm32mp/cmd_stm32key.c index 4eac560..278253e 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32key.c +++ b/arch/arm/mach-stm32mp/cmd_stm32key.c @@ -11,9 +11,14 @@ #include #include -/* Closed device : bit 6 of OPT0*/ +/* + * Closed device: OTP0 + * STM32MP15x: bit 6 of OPT0 + * STM32MP13x: 0b111111 = 0x3F for OTP_SECURED closed device + */ #define STM32_OTP_CLOSE_ID 0 -#define STM32_OTP_CLOSE_MASK BIT(6) +#define STM32_OTP_STM32MP13x_CLOSE_MASK 0x3F +#define STM32_OTP_STM32MP15x_CLOSE_MASK BIT(6) /* PKH is the first element of the key list */ #define STM32KEY_PKH 0 @@ -25,6 +30,21 @@ struct stm32key { u8 size; }; +const struct stm32key stm32mp13_list[] = { + [STM32KEY_PKH] = { + .name = "PKHTH", + .desc = "Hash of the 8 ECC Public Keys Hashes Table (ECDSA is the authentication algorithm)", + .start = 24, + .size = 8, + }, + { + .name = "EDMK", + .desc = "Encryption/Decryption Master Key", + .start = 92, + .size = 4, + } +}; + const struct stm32key stm32mp15_list[] = { [STM32KEY_PKH] = { .name = "PKH", @@ -39,12 +59,29 @@ static u8 stm32key_index; static u8 get_key_nb(void) { - return ARRAY_SIZE(stm32mp15_list); + if (IS_ENABLED(CONFIG_STM32MP13x)) + return ARRAY_SIZE(stm32mp13_list); + + if (IS_ENABLED(CONFIG_STM32MP15x)) + return ARRAY_SIZE(stm32mp15_list); } static const struct stm32key *get_key(u8 index) { - return &stm32mp15_list[index]; + if (IS_ENABLED(CONFIG_STM32MP13x)) + return &stm32mp13_list[index]; + + if (IS_ENABLED(CONFIG_STM32MP15x)) + return &stm32mp15_list[index]; +} + +static u32 get_otp_close_mask(void) +{ + if (IS_ENABLED(CONFIG_STM32MP13x)) + return STM32_OTP_STM32MP13x_CLOSE_MASK; + + if (IS_ENABLED(CONFIG_STM32MP15x)) + return STM32_OTP_STM32MP15x_CLOSE_MASK; } #define BSEC_LOCK_ERROR (-1) @@ -123,7 +160,7 @@ static int read_key_otp(struct udevice *dev, const struct stm32key *key, bool pr static int read_close_status(struct udevice *dev, bool print, bool *closed) { int word, ret, result; - u32 val, lock; + u32 val, lock, mask; bool status; result = 0; @@ -140,7 +177,8 @@ static int read_close_status(struct udevice *dev, bool print, bool *closed) if (ret != 4) lock = BSEC_LOCK_ERROR; - status = (val & STM32_OTP_CLOSE_MASK) == STM32_OTP_CLOSE_MASK; + mask = get_otp_close_mask(); + status = (val & mask) == mask; if (closed) *closed = status; if (print) @@ -371,7 +409,7 @@ static int do_stm32key_close(struct cmd_tbl *cmdtp, int flag, int argc, char *co if (!yes && !confirm_prog()) return CMD_RET_FAILURE; - val = STM32_OTP_CLOSE_MASK; + val = get_otp_close_mask(); ret = misc_write(dev, STM32_BSEC_OTP(STM32_OTP_CLOSE_ID), &val, 4); if (ret != 4) { printf("Error: can't update OTP %d\n", STM32_OTP_CLOSE_ID); -- cgit v1.1 From 86d5a06ae3b826bf7b4627e926afd5378d88c574 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Fri, 16 Sep 2022 16:52:57 +0200 Subject: configs: stm32mp1: cleanup config file Remove the unnecessary comment after the CONFIG_SYS_BOOTM_LEN migration to Kconfig. Fixes: c45568cc4e51 ("Convert CONFIG_SYS_BOOTM_LEN to Kconfig") Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard --- include/configs/stm32mp13_common.h | 2 -- include/configs/stm32mp15_common.h | 2 -- 2 files changed, 4 deletions(-) diff --git a/include/configs/stm32mp13_common.h b/include/configs/stm32mp13_common.h index 3ca65ea..78089b9 100644 --- a/include/configs/stm32mp13_common.h +++ b/include/configs/stm32mp13_common.h @@ -21,8 +21,6 @@ */ #define CONFIG_SYS_BOOTMAPSZ SZ_256M -/* Extend size of kernel image for uncompression */ - /*MMC SD*/ #define CONFIG_SYS_MMC_MAX_DEVICE 2 diff --git a/include/configs/stm32mp15_common.h b/include/configs/stm32mp15_common.h index c5412ff..bd8e16b 100644 --- a/include/configs/stm32mp15_common.h +++ b/include/configs/stm32mp15_common.h @@ -21,8 +21,6 @@ */ #define CONFIG_SYS_BOOTMAPSZ SZ_256M -/* Extend size of kernel image for uncompression */ - /*MMC SD*/ #define CONFIG_SYS_MMC_MAX_DEVICE 3 -- cgit v1.1 From 9f7c58dc0deacd6c453ac628953741f1a6a68126 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Wed, 21 Sep 2022 09:37:13 +0200 Subject: ARM: dts: stm32mp15: update DDR node Remove the unnecessary nodes for TFABOOT and keep the mandatory part in SOC dtsi, only the DDRCTRL and DDRPHY addresses. This patch allows to manage the DDR configuration setting in U-Boot device tree only if it is needed, when CONFIG_SPL is defined. With TFABOOT, the DDR configuration is done in TF-A BL2 and the DDR size is dynamically computed in U-Boot since commit d72e7bbe7c28 ("ram: stm32mp1: compute DDR size from DDRCTL registers"). Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard --- arch/arm/dts/stm32mp15-ddr.dtsi | 16 ++++++++++++++++ arch/arm/dts/stm32mp15-u-boot.dtsi | 14 -------------- arch/arm/dts/stm32mp157a-dk1-scmi-u-boot.dtsi | 1 - arch/arm/dts/stm32mp157c-ed1-scmi-u-boot.dtsi | 1 - 4 files changed, 16 insertions(+), 16 deletions(-) diff --git a/arch/arm/dts/stm32mp15-ddr.dtsi b/arch/arm/dts/stm32mp15-ddr.dtsi index 0aac913..d02f79d 100644 --- a/arch/arm/dts/stm32mp15-ddr.dtsi +++ b/arch/arm/dts/stm32mp15-ddr.dtsi @@ -4,7 +4,22 @@ */ #include +#ifdef CONFIG_SPL &ddr { + clocks = <&rcc AXIDCG>, + <&rcc DDRC1>, + <&rcc DDRC2>, + <&rcc DDRPHYC>, + <&rcc DDRCAPB>, + <&rcc DDRPHYCAPB>; + + clock-names = "axidcg", + "ddrc1", + "ddrc2", + "ddrphyc", + "ddrcapb", + "ddrphycapb"; + config-DDR_MEM_COMPATIBLE { u-boot,dm-pre-reloc; @@ -119,6 +134,7 @@ status = "okay"; }; }; +#endif #undef DDR_MEM_COMPATIBLE #undef DDR_MEM_NAME diff --git a/arch/arm/dts/stm32mp15-u-boot.dtsi b/arch/arm/dts/stm32mp15-u-boot.dtsi index d9d0474..d5c87d2 100644 --- a/arch/arm/dts/stm32mp15-u-boot.dtsi +++ b/arch/arm/dts/stm32mp15-u-boot.dtsi @@ -53,20 +53,6 @@ reg = <0x5a003000 0x550 0x5a004000 0x234>; - clocks = <&rcc AXIDCG>, - <&rcc DDRC1>, - <&rcc DDRC2>, - <&rcc DDRPHYC>, - <&rcc DDRCAPB>, - <&rcc DDRPHYCAPB>; - - clock-names = "axidcg", - "ddrc1", - "ddrc2", - "ddrphyc", - "ddrcapb", - "ddrphycapb"; - status = "okay"; }; }; diff --git a/arch/arm/dts/stm32mp157a-dk1-scmi-u-boot.dtsi b/arch/arm/dts/stm32mp157a-dk1-scmi-u-boot.dtsi index 2db045e..1209dfe 100644 --- a/arch/arm/dts/stm32mp157a-dk1-scmi-u-boot.dtsi +++ b/arch/arm/dts/stm32mp157a-dk1-scmi-u-boot.dtsi @@ -5,7 +5,6 @@ #include #include "stm32mp15-scmi-u-boot.dtsi" -#include "stm32mp15-ddr3-1x4Gb-1066-binG.dtsi" / { aliases { diff --git a/arch/arm/dts/stm32mp157c-ed1-scmi-u-boot.dtsi b/arch/arm/dts/stm32mp157c-ed1-scmi-u-boot.dtsi index 54662f7..c265745 100644 --- a/arch/arm/dts/stm32mp157c-ed1-scmi-u-boot.dtsi +++ b/arch/arm/dts/stm32mp157c-ed1-scmi-u-boot.dtsi @@ -5,7 +5,6 @@ #include #include "stm32mp15-scmi-u-boot.dtsi" -#include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi" / { aliases { -- cgit v1.1 From 9f603e2fff19507cc907faa3c5f3f2f51f1b2eaf Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Fri, 23 Sep 2022 13:20:33 +0200 Subject: ARM: dts: stm32: DT sync with kernel v6.0-rc4 for MCU's boards Device tree alignment with kernel v6.0-rc4. Signed-off-by: Patrice Chotard Reviewed-by: Patrick Delaunay --- arch/arm/dts/stm32429i-eval-u-boot.dtsi | 2 +- arch/arm/dts/stm32746g-eval.dts | 18 ++++-- arch/arm/dts/stm32f4-pinctrl.dtsi | 2 +- arch/arm/dts/stm32f429-disco-u-boot.dtsi | 8 +-- arch/arm/dts/stm32f429-disco.dts | 20 +++++-- arch/arm/dts/stm32f429-pinctrl.dtsi | 94 +++++++++++++++---------------- arch/arm/dts/stm32f429.dtsi | 69 ++++------------------- arch/arm/dts/stm32f469-disco-u-boot.dtsi | 7 +-- arch/arm/dts/stm32f469-disco.dts | 24 ++++++-- arch/arm/dts/stm32f469-pinctrl.dtsi | 96 +++++++++++++++----------------- arch/arm/dts/stm32f7-pinctrl.dtsi | 2 +- arch/arm/dts/stm32f7-u-boot.dtsi | 2 +- arch/arm/dts/stm32f746-disco.dts | 12 ++++ arch/arm/dts/stm32f746.dtsi | 67 ++-------------------- arch/arm/dts/stm32f769-disco.dts | 18 ++++-- arch/arm/dts/stm32h743.dtsi | 19 ++----- arch/arm/dts/stm32h743i-disco.dts | 8 +-- arch/arm/dts/stm32h743i-eval.dts | 8 +-- arch/arm/dts/stm32h750i-art-pi.dts | 8 +-- 19 files changed, 209 insertions(+), 275 deletions(-) diff --git a/arch/arm/dts/stm32429i-eval-u-boot.dtsi b/arch/arm/dts/stm32429i-eval-u-boot.dtsi index fcab9ae..030da47 100644 --- a/arch/arm/dts/stm32429i-eval-u-boot.dtsi +++ b/arch/arm/dts/stm32429i-eval-u-boot.dtsi @@ -218,6 +218,6 @@ }; }; -&timer5 { +&timers5 { u-boot,dm-pre-reloc; }; diff --git a/arch/arm/dts/stm32746g-eval.dts b/arch/arm/dts/stm32746g-eval.dts index 9940cf1..0e6445a 100644 --- a/arch/arm/dts/stm32746g-eval.dts +++ b/arch/arm/dts/stm32746g-eval.dts @@ -45,12 +45,10 @@ }; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; autorepeat; - button@0 { + button-0 { label = "Wake up"; linux,code = ; gpios = <&gpioc 13 0>; @@ -160,6 +158,18 @@ bus-width = <4>; }; +&timers5 { + /* Override timer5 to act as clockevent */ + compatible = "st,stm32-timer"; + interrupts = <50>; + status = "okay"; + /delete-property/#address-cells; + /delete-property/#size-cells; + /delete-property/clock-names; + /delete-node/pwm; + /delete-node/timer@4; +}; + &usart1 { pinctrl-0 = <&usart1_pins_a>; pinctrl-names = "default"; diff --git a/arch/arm/dts/stm32f4-pinctrl.dtsi b/arch/arm/dts/stm32f4-pinctrl.dtsi index adf5026..46815c9 100644 --- a/arch/arm/dts/stm32f4-pinctrl.dtsi +++ b/arch/arm/dts/stm32f4-pinctrl.dtsi @@ -9,7 +9,7 @@ / { soc { - pinctrl: pin-controller { + pinctrl: pinctrl@40020000 { #address-cells = <1>; #size-cells = <1>; ranges = <0 0x40020000 0x3000>; diff --git a/arch/arm/dts/stm32f429-disco-u-boot.dtsi b/arch/arm/dts/stm32f429-disco-u-boot.dtsi index c993f86..45f8996 100644 --- a/arch/arm/dts/stm32f429-disco-u-boot.dtsi +++ b/arch/arm/dts/stm32f429-disco-u-boot.dtsi @@ -27,10 +27,6 @@ soc { u-boot,dm-pre-reloc; - pin-controller { - u-boot,dm-pre-reloc; - }; - fmc: fmc@A0000000 { compatible = "st,stm32-fmc"; reg = <0xa0000000 0x1000>; @@ -123,6 +119,8 @@ }; &pinctrl { + u-boot,dm-pre-reloc; + usart1_pins_a: usart1-0 { u-boot,dm-pre-reloc; pins1 { @@ -193,6 +191,6 @@ u-boot,dm-pre-reloc; }; -&timer5 { +&timers5 { u-boot,dm-pre-reloc; }; diff --git a/arch/arm/dts/stm32f429-disco.dts b/arch/arm/dts/stm32f429-disco.dts index 42477c8..30daabd 100644 --- a/arch/arm/dts/stm32f429-disco.dts +++ b/arch/arm/dts/stm32f429-disco.dts @@ -39,12 +39,10 @@ }; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; autorepeat; - button@0 { + button-0 { label = "User"; linux,code = ; gpios = <&gpioa 0 0>; @@ -152,7 +150,7 @@ display: display@1{ /* Connect panel-ilitek-9341 to ltdc */ - compatible = "st,sf-tc240t-9370-t"; + compatible = "st,sf-tc240t-9370-t", "ilitek,ili9341"; reg = <1>; spi-3wire; spi-max-frequency = <10000000>; @@ -165,6 +163,18 @@ }; }; +&timers5 { + /* Override timer5 to act as clockevent */ + compatible = "st,stm32-timer"; + interrupts = <50>; + status = "okay"; + /delete-property/#address-cells; + /delete-property/#size-cells; + /delete-property/clock-names; + /delete-node/pwm; + /delete-node/timer@4; +}; + &usart1 { pinctrl-0 = <&usart1_pins_a>; pinctrl-names = "default"; diff --git a/arch/arm/dts/stm32f429-pinctrl.dtsi b/arch/arm/dts/stm32f429-pinctrl.dtsi index 575c7ee..5be171e 100644 --- a/arch/arm/dts/stm32f429-pinctrl.dtsi +++ b/arch/arm/dts/stm32f429-pinctrl.dtsi @@ -6,54 +6,50 @@ #include "stm32f4-pinctrl.dtsi" -/ { - soc { - pinctrl: pin-controller { - compatible = "st,stm32f429-pinctrl"; - - gpioa: gpio@40020000 { - gpio-ranges = <&pinctrl 0 0 16>; - }; - - gpiob: gpio@40020400 { - gpio-ranges = <&pinctrl 0 16 16>; - }; - - gpioc: gpio@40020800 { - gpio-ranges = <&pinctrl 0 32 16>; - }; - - gpiod: gpio@40020c00 { - gpio-ranges = <&pinctrl 0 48 16>; - }; - - gpioe: gpio@40021000 { - gpio-ranges = <&pinctrl 0 64 16>; - }; - - gpiof: gpio@40021400 { - gpio-ranges = <&pinctrl 0 80 16>; - }; - - gpiog: gpio@40021800 { - gpio-ranges = <&pinctrl 0 96 16>; - }; - - gpioh: gpio@40021c00 { - gpio-ranges = <&pinctrl 0 112 16>; - }; - - gpioi: gpio@40022000 { - gpio-ranges = <&pinctrl 0 128 16>; - }; - - gpioj: gpio@40022400 { - gpio-ranges = <&pinctrl 0 144 16>; - }; - - gpiok: gpio@40022800 { - gpio-ranges = <&pinctrl 0 160 8>; - }; - }; +&pinctrl { + compatible = "st,stm32f429-pinctrl"; + + gpioa: gpio@40020000 { + gpio-ranges = <&pinctrl 0 0 16>; + }; + + gpiob: gpio@40020400 { + gpio-ranges = <&pinctrl 0 16 16>; + }; + + gpioc: gpio@40020800 { + gpio-ranges = <&pinctrl 0 32 16>; + }; + + gpiod: gpio@40020c00 { + gpio-ranges = <&pinctrl 0 48 16>; + }; + + gpioe: gpio@40021000 { + gpio-ranges = <&pinctrl 0 64 16>; + }; + + gpiof: gpio@40021400 { + gpio-ranges = <&pinctrl 0 80 16>; + }; + + gpiog: gpio@40021800 { + gpio-ranges = <&pinctrl 0 96 16>; + }; + + gpioh: gpio@40021c00 { + gpio-ranges = <&pinctrl 0 112 16>; + }; + + gpioi: gpio@40022000 { + gpio-ranges = <&pinctrl 0 128 16>; + }; + + gpioj: gpio@40022400 { + gpio-ranges = <&pinctrl 0 144 16>; + }; + + gpiok: gpio@40022800 { + gpio-ranges = <&pinctrl 0 160 8>; }; }; diff --git a/arch/arm/dts/stm32f429.dtsi b/arch/arm/dts/stm32f429.dtsi index a81e916..e5b13ac 100644 --- a/arch/arm/dts/stm32f429.dtsi +++ b/arch/arm/dts/stm32f429.dtsi @@ -52,14 +52,6 @@ }; }; - timer2: timer@40000000 { - compatible = "st,stm32-timer"; - reg = <0x40000000 0x400>; - interrupts = <28>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>; - status = "disabled"; - }; - timers2: timers@40000000 { #address-cells = <1>; #size-cells = <0>; @@ -82,14 +74,6 @@ }; }; - timer3: timer@40000400 { - compatible = "st,stm32-timer"; - reg = <0x40000400 0x400>; - interrupts = <29>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>; - status = "disabled"; - }; - timers3: timers@40000400 { #address-cells = <1>; #size-cells = <0>; @@ -112,14 +96,6 @@ }; }; - timer4: timer@40000800 { - compatible = "st,stm32-timer"; - reg = <0x40000800 0x400>; - interrupts = <30>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>; - status = "disabled"; - }; - timers4: timers@40000800 { #address-cells = <1>; #size-cells = <0>; @@ -142,13 +118,6 @@ }; }; - timer5: timer@40000c00 { - compatible = "st,stm32-timer"; - reg = <0x40000c00 0x400>; - interrupts = <50>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>; - }; - timers5: timers@40000c00 { #address-cells = <1>; #size-cells = <0>; @@ -171,14 +140,6 @@ }; }; - timer6: timer@40001000 { - compatible = "st,stm32-timer"; - reg = <0x40001000 0x400>; - interrupts = <54>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>; - status = "disabled"; - }; - timers6: timers@40001000 { #address-cells = <1>; #size-cells = <0>; @@ -195,14 +156,6 @@ }; }; - timer7: timer@40001400 { - compatible = "st,stm32-timer"; - reg = <0x40001400 0x400>; - interrupts = <55>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>; - status = "disabled"; - }; - timers7: timers@40001400 { #address-cells = <1>; #size-cells = <0>; @@ -242,8 +195,6 @@ }; timers13: timers@40001c00 { - #address-cells = <1>; - #size-cells = <0>; compatible = "st,stm32-timers"; reg = <0x40001C00 0x400>; clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM13)>; @@ -258,8 +209,6 @@ }; timers14: timers@40002000 { - #address-cells = <1>; - #size-cells = <0>; compatible = "st,stm32-timers"; reg = <0x40002000 0x400>; clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM14)>; @@ -525,7 +474,7 @@ }; }; - sdio: sdio@40012c00 { + sdio: mmc@40012c00 { compatible = "arm,pl180", "arm,primecell"; arm,primecell-periphid = <0x00880180>; reg = <0x40012c00 0x400>; @@ -592,8 +541,6 @@ }; timers10: timers@40014400 { - #address-cells = <1>; - #size-cells = <0>; compatible = "st,stm32-timers"; reg = <0x40014400 0x400>; clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM10)>; @@ -608,8 +555,6 @@ }; timers11: timers@40014800 { - #address-cells = <1>; - #size-cells = <0>; compatible = "st,stm32-timers"; reg = <0x40014800 0x400>; clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM11)>; @@ -668,7 +613,7 @@ status = "disabled"; }; - rcc: rcc@40023810 { + rcc: rcc@40023800 { #reset-cells = <1>; #clock-cells = <2>; compatible = "st,stm32f42xx-rcc", "st,stm32-rcc"; @@ -726,6 +671,16 @@ status = "disabled"; }; + dma2d: dma2d@4002b000 { + compatible = "st,stm32-dma2d"; + reg = <0x4002b000 0xc00>; + interrupts = <90>; + resets = <&rcc STM32F4_AHB1_RESET(DMA2D)>; + clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA2D)>; + clock-names = "dma2d"; + status = "disabled"; + }; + usbotg_hs: usb@40040000 { compatible = "snps,dwc2"; reg = <0x40040000 0x40000>; diff --git a/arch/arm/dts/stm32f469-disco-u-boot.dtsi b/arch/arm/dts/stm32f469-disco-u-boot.dtsi index cd17362..ee0c82b 100644 --- a/arch/arm/dts/stm32f469-disco-u-boot.dtsi +++ b/arch/arm/dts/stm32f469-disco-u-boot.dtsi @@ -28,9 +28,6 @@ soc { u-boot,dm-pre-reloc; - pin-controller { - u-boot,dm-pre-reloc; - }; fmc: fmc@A0000000 { compatible = "st,stm32-fmc"; @@ -138,6 +135,8 @@ }; &pinctrl { + u-boot,dm-pre-reloc; + fmc_pins_d32: fmc_d32@0 { u-boot,dm-pre-reloc; pins @@ -256,6 +255,6 @@ u-boot,dm-pre-reloc; }; -&timer5 { +&timers5 { u-boot,dm-pre-reloc; }; diff --git a/arch/arm/dts/stm32f469-disco.dts b/arch/arm/dts/stm32f469-disco.dts index 23d87ee..6e0ffc1 100644 --- a/arch/arm/dts/stm32f469-disco.dts +++ b/arch/arm/dts/stm32f469-disco.dts @@ -19,7 +19,7 @@ stdout-path = "serial0:115200n8"; }; - memory@00000000 { + memory@0 { device_type = "memory"; reg = <0x00000000 0x1000000>; }; @@ -63,12 +63,10 @@ }; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; autorepeat; - button@0 { + button-0 { label = "User"; linux,code = ; gpios = <&gpioa 0 GPIO_ACTIVE_HIGH>; @@ -93,6 +91,10 @@ clock-frequency = <8000000>; }; +&dma2d { + status = "okay"; +}; + &dsi { #address-cells = <1>; #size-cells = <0>; @@ -185,6 +187,18 @@ bus-width = <4>; }; +&timers5 { + /* Override timer5 to act as clockevent */ + compatible = "st,stm32-timer"; + interrupts = <50>; + status = "okay"; + /delete-property/#address-cells; + /delete-property/#size-cells; + /delete-property/clock-names; + /delete-node/pwm; + /delete-node/timer@4; +}; + &usart3 { pinctrl-0 = <&usart3_pins_a>; pinctrl-names = "default"; diff --git a/arch/arm/dts/stm32f469-pinctrl.dtsi b/arch/arm/dts/stm32f469-pinctrl.dtsi index 1e2bb01..0610407 100644 --- a/arch/arm/dts/stm32f469-pinctrl.dtsi +++ b/arch/arm/dts/stm32f469-pinctrl.dtsi @@ -5,55 +5,51 @@ #include "stm32f4-pinctrl.dtsi" -/ { - soc { - pinctrl: pin-controller { - compatible = "st,stm32f469-pinctrl"; - - gpioa: gpio@40020000 { - gpio-ranges = <&pinctrl 0 0 16>; - }; - - gpiob: gpio@40020400 { - gpio-ranges = <&pinctrl 0 16 16>; - }; - - gpioc: gpio@40020800 { - gpio-ranges = <&pinctrl 0 32 16>; - }; - - gpiod: gpio@40020c00 { - gpio-ranges = <&pinctrl 0 48 16>; - }; - - gpioe: gpio@40021000 { - gpio-ranges = <&pinctrl 0 64 16>; - }; - - gpiof: gpio@40021400 { - gpio-ranges = <&pinctrl 0 80 16>; - }; - - gpiog: gpio@40021800 { - gpio-ranges = <&pinctrl 0 96 16>; - }; - - gpioh: gpio@40021c00 { - gpio-ranges = <&pinctrl 0 112 16>; - }; - - gpioi: gpio@40022000 { - gpio-ranges = <&pinctrl 0 128 16>; - }; - - gpioj: gpio@40022400 { - gpio-ranges = <&pinctrl 0 144 6>, - <&pinctrl 12 156 4>; - }; - - gpiok: gpio@40022800 { - gpio-ranges = <&pinctrl 3 163 5>; - }; - }; +&pinctrl { + compatible = "st,stm32f469-pinctrl"; + + gpioa: gpio@40020000 { + gpio-ranges = <&pinctrl 0 0 16>; + }; + + gpiob: gpio@40020400 { + gpio-ranges = <&pinctrl 0 16 16>; + }; + + gpioc: gpio@40020800 { + gpio-ranges = <&pinctrl 0 32 16>; + }; + + gpiod: gpio@40020c00 { + gpio-ranges = <&pinctrl 0 48 16>; + }; + + gpioe: gpio@40021000 { + gpio-ranges = <&pinctrl 0 64 16>; + }; + + gpiof: gpio@40021400 { + gpio-ranges = <&pinctrl 0 80 16>; + }; + + gpiog: gpio@40021800 { + gpio-ranges = <&pinctrl 0 96 16>; + }; + + gpioh: gpio@40021c00 { + gpio-ranges = <&pinctrl 0 112 16>; + }; + + gpioi: gpio@40022000 { + gpio-ranges = <&pinctrl 0 128 16>; + }; + + gpioj: gpio@40022400 { + gpio-ranges = <&pinctrl 0 144 6>, + <&pinctrl 12 156 4>; + }; + + gpiok: gpio@40022800 { + gpio-ranges = <&pinctrl 3 163 5>; }; }; diff --git a/arch/arm/dts/stm32f7-pinctrl.dtsi b/arch/arm/dts/stm32f7-pinctrl.dtsi index fe4cfda..8f37aef 100644 --- a/arch/arm/dts/stm32f7-pinctrl.dtsi +++ b/arch/arm/dts/stm32f7-pinctrl.dtsi @@ -9,7 +9,7 @@ / { soc { - pinctrl: pin-controller { + pinctrl: pinctrl@40020000 { #address-cells = <1>; #size-cells = <1>; ranges = <0 0x40020000 0x3000>; diff --git a/arch/arm/dts/stm32f7-u-boot.dtsi b/arch/arm/dts/stm32f7-u-boot.dtsi index c1b2ac2..0ba8031 100644 --- a/arch/arm/dts/stm32f7-u-boot.dtsi +++ b/arch/arm/dts/stm32f7-u-boot.dtsi @@ -119,7 +119,7 @@ u-boot,dm-pre-reloc; }; -&timer5 { +&timers5 { u-boot,dm-pre-reloc; }; diff --git a/arch/arm/dts/stm32f746-disco.dts b/arch/arm/dts/stm32f746-disco.dts index 9430dc0..1ed58f2 100644 --- a/arch/arm/dts/stm32f746-disco.dts +++ b/arch/arm/dts/stm32f746-disco.dts @@ -73,6 +73,18 @@ bus-width = <4>; }; +&timers5 { + /* Override timer5 to act as clockevent */ + compatible = "st,stm32-timer"; + interrupts = <50>; + status = "okay"; + /delete-property/#address-cells; + /delete-property/#size-cells; + /delete-property/clock-names; + /delete-node/pwm; + /delete-node/timer@4; +}; + &usart1 { pinctrl-0 = <&usart1_pins_b>; pinctrl-names = "default"; diff --git a/arch/arm/dts/stm32f746.dtsi b/arch/arm/dts/stm32f746.dtsi index 78facde..c97b3d0 100644 --- a/arch/arm/dts/stm32f746.dtsi +++ b/arch/arm/dts/stm32f746.dtsi @@ -39,14 +39,6 @@ }; soc { - timer2: timer@40000000 { - compatible = "st,stm32-timer"; - reg = <0x40000000 0x400>; - interrupts = <28>; - clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>; - status = "disabled"; - }; - timers2: timers@40000000 { #address-cells = <1>; #size-cells = <0>; @@ -69,14 +61,6 @@ }; }; - timer3: timer@40000400 { - compatible = "st,stm32-timer"; - reg = <0x40000400 0x400>; - interrupts = <29>; - clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>; - status = "disabled"; - }; - timers3: timers@40000400 { #address-cells = <1>; #size-cells = <0>; @@ -99,14 +83,6 @@ }; }; - timer4: timer@40000800 { - compatible = "st,stm32-timer"; - reg = <0x40000800 0x400>; - interrupts = <30>; - clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>; - status = "disabled"; - }; - timers4: timers@40000800 { #address-cells = <1>; #size-cells = <0>; @@ -129,13 +105,6 @@ }; }; - timer5: timer@40000c00 { - compatible = "st,stm32-timer"; - reg = <0x40000c00 0x400>; - interrupts = <50>; - clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>; - }; - timers5: timers@40000c00 { #address-cells = <1>; #size-cells = <0>; @@ -158,14 +127,6 @@ }; }; - timer6: timer@40001000 { - compatible = "st,stm32-timer"; - reg = <0x40001000 0x400>; - interrupts = <54>; - clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>; - status = "disabled"; - }; - timers6: timers@40001000 { #address-cells = <1>; #size-cells = <0>; @@ -182,14 +143,6 @@ }; }; - timer7: timer@40001400 { - compatible = "st,stm32-timer"; - reg = <0x40001400 0x400>; - interrupts = <55>; - clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>; - status = "disabled"; - }; - timers7: timers@40001400 { #address-cells = <1>; #size-cells = <0>; @@ -229,8 +182,6 @@ }; timers13: timers@40001c00 { - #address-cells = <1>; - #size-cells = <0>; compatible = "st,stm32-timers"; reg = <0x40001C00 0x400>; clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM13)>; @@ -245,8 +196,6 @@ }; timers14: timers@40002000 { - #address-cells = <1>; - #size-cells = <0>; compatible = "st,stm32-timers"; reg = <0x40002000 0x400>; clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM14)>; @@ -313,7 +262,6 @@ clocks = <&rcc 1 CLK_I2C1>; #address-cells = <1>; #size-cells = <0>; - i2c-analog-filter; status = "disabled"; }; @@ -326,20 +274,18 @@ clocks = <&rcc 1 CLK_I2C2>; #address-cells = <1>; #size-cells = <0>; - i2c-analog-filter; status = "disabled"; }; - i2c3: i2c@40005C00 { + i2c3: i2c@40005c00 { compatible = "st,stm32f7-i2c"; - reg = <0x40005C00 0x400>; + reg = <0x40005c00 0x400>; interrupts = <72>, <73>; resets = <&rcc STM32F7_APB1_RESET(I2C3)>; clocks = <&rcc 1 CLK_I2C3>; #address-cells = <1>; #size-cells = <0>; - i2c-analog-filter; status = "disabled"; }; @@ -352,7 +298,6 @@ clocks = <&rcc 1 CLK_I2C4>; #address-cells = <1>; #size-cells = <0>; - i2c-analog-filter; status = "disabled"; }; @@ -441,7 +386,7 @@ status = "disabled"; }; - sdio2: sdio2@40011c00 { + sdio2: mmc@40011c00 { compatible = "arm,pl180", "arm,primecell"; arm,primecell-periphid = <0x00880180>; reg = <0x40011c00 0x400>; @@ -452,7 +397,7 @@ status = "disabled"; }; - sdio1: sdio1@40012c00 { + sdio1: mmc@40012c00 { compatible = "arm,pl180", "arm,primecell"; arm,primecell-periphid = <0x00880180>; reg = <0x40012c00 0x400>; @@ -499,8 +444,6 @@ }; timers10: timers@40014400 { - #address-cells = <1>; - #size-cells = <0>; compatible = "st,stm32-timers"; reg = <0x40014400 0x400>; clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM10)>; @@ -515,8 +458,6 @@ }; timers11: timers@40014800 { - #address-cells = <1>; - #size-cells = <0>; compatible = "st,stm32-timers"; reg = <0x40014800 0x400>; clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM11)>; diff --git a/arch/arm/dts/stm32f769-disco.dts b/arch/arm/dts/stm32f769-disco.dts index 03cfbd7..6f93fc7 100644 --- a/arch/arm/dts/stm32f769-disco.dts +++ b/arch/arm/dts/stm32f769-disco.dts @@ -39,12 +39,10 @@ }; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; autorepeat; - button@0 { + button-0 { label = "User"; linux,code = ; gpios = <&gpioa 0 GPIO_ACTIVE_HIGH>; @@ -103,6 +101,18 @@ bus-width = <4>; }; +&timers5 { + /* Override timer5 to act as clockevent */ + compatible = "st,stm32-timer"; + interrupts = <50>; + status = "okay"; + /delete-property/#address-cells; + /delete-property/#size-cells; + /delete-property/clock-names; + /delete-node/pwm; + /delete-node/timer@4; +}; + &usart1 { pinctrl-0 = <&usart1_pins_a>; pinctrl-names = "default"; diff --git a/arch/arm/dts/stm32h743.dtsi b/arch/arm/dts/stm32h743.dtsi index dbfebf0..ceb629c 100644 --- a/arch/arm/dts/stm32h743.dtsi +++ b/arch/arm/dts/stm32h743.dtsi @@ -124,7 +124,6 @@ <32>; resets = <&rcc STM32H7_APB1L_RESET(I2C1)>; clocks = <&rcc I2C1_CK>; - i2c-analog-filter; status = "disabled"; }; @@ -137,7 +136,6 @@ <34>; resets = <&rcc STM32H7_APB1L_RESET(I2C2)>; clocks = <&rcc I2C2_CK>; - i2c-analog-filter; status = "disabled"; }; @@ -150,7 +148,6 @@ <73>; resets = <&rcc STM32H7_APB1L_RESET(I2C3)>; clocks = <&rcc I2C3_CK>; - i2c-analog-filter; status = "disabled"; }; @@ -337,12 +334,12 @@ dma-requests = <32>; }; - sdmmc1: sdmmc@52007000 { + sdmmc1: mmc@52007000 { compatible = "arm,pl18x", "arm,primecell"; arm,primecell-periphid = <0x10153180>; reg = <0x52007000 0x1000>; interrupts = <49>; - interrupt-names = "cmd_irq"; + interrupt-names = "cmd_irq"; clocks = <&rcc SDMMC1_CK>; clock-names = "apb_pclk"; resets = <&rcc STM32H7_AHB3_RESET(SDMMC1)>; @@ -351,18 +348,19 @@ max-frequency = <120000000>; }; - sdmmc2: sdmmc@48022400 { + sdmmc2: mmc@48022400 { compatible = "arm,pl18x", "arm,primecell"; arm,primecell-periphid = <0x10153180>; reg = <0x48022400 0x400>; interrupts = <124>; - interrupt-names = "cmd_irq"; + interrupt-names = "cmd_irq"; clocks = <&rcc SDMMC2_CK>; clock-names = "apb_pclk"; resets = <&rcc STM32H7_AHB2_RESET(SDMMC2)>; cap-sd-highspeed; cap-mmc-highspeed; max-frequency = <120000000>; + status = "disabled"; }; exti: interrupt-controller@58000000 { @@ -398,7 +396,6 @@ <96>; resets = <&rcc STM32H7_APB4_RESET(I2C4)>; clocks = <&rcc I2C4_CK>; - i2c-analog-filter; status = "disabled"; }; @@ -452,8 +449,6 @@ }; lptimer4: timer@58002c00 { - #address-cells = <1>; - #size-cells = <0>; compatible = "st,stm32-lptimer"; reg = <0x58002c00 0x400>; clocks = <&rcc LPTIM4_CK>; @@ -468,8 +463,6 @@ }; lptimer5: timer@58003000 { - #address-cells = <1>; - #size-cells = <0>; compatible = "st,stm32-lptimer"; reg = <0x58003000 0x400>; clocks = <&rcc LPTIM5_CK>; @@ -554,7 +547,7 @@ status = "disabled"; }; - pinctrl: pin-controller@58020000 { + pinctrl: pinctrl@58020000 { #address-cells = <1>; #size-cells = <1>; compatible = "st,stm32h743-pinctrl"; diff --git a/arch/arm/dts/stm32h743i-disco.dts b/arch/arm/dts/stm32h743i-disco.dts index 3a01ebd..b31188f 100644 --- a/arch/arm/dts/stm32h743i-disco.dts +++ b/arch/arm/dts/stm32h743i-disco.dts @@ -41,10 +41,10 @@ &mac { status = "disabled"; - pinctrl-0 = <ðernet_rmii>; - pinctrl-names = "default"; - phy-mode = "rmii"; - phy-handle = <&phy0>; + pinctrl-0 = <ðernet_rmii>; + pinctrl-names = "default"; + phy-mode = "rmii"; + phy-handle = <&phy0>; mdio0 { #address-cells = <1>; diff --git a/arch/arm/dts/stm32h743i-eval.dts b/arch/arm/dts/stm32h743i-eval.dts index 38cc7fa..5c5d805 100644 --- a/arch/arm/dts/stm32h743i-eval.dts +++ b/arch/arm/dts/stm32h743i-eval.dts @@ -115,10 +115,10 @@ &mac { status = "disabled"; - pinctrl-0 = <ðernet_rmii>; - pinctrl-names = "default"; - phy-mode = "rmii"; - phy-handle = <&phy0>; + pinctrl-0 = <ðernet_rmii>; + pinctrl-names = "default"; + phy-mode = "rmii"; + phy-handle = <&phy0>; mdio0 { #address-cells = <1>; diff --git a/arch/arm/dts/stm32h750i-art-pi.dts b/arch/arm/dts/stm32h750i-art-pi.dts index 2a4d1cb..c7c7132 100644 --- a/arch/arm/dts/stm32h750i-art-pi.dts +++ b/arch/arm/dts/stm32h750i-art-pi.dts @@ -87,10 +87,10 @@ &mac { status = "disabled"; - pinctrl-0 = <ðernet_rmii>; - pinctrl-names = "default"; - phy-mode = "rmii"; - phy-handle = <&phy0>; + pinctrl-0 = <ðernet_rmii>; + pinctrl-names = "default"; + phy-mode = "rmii"; + phy-handle = <&phy0>; mdio0 { #address-cells = <1>; -- cgit v1.1 From 6ee64732b1cc5a1a87e782d1c53dba3ec21cf6e4 Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Tue, 20 Sep 2022 18:04:30 +0200 Subject: configs: stm32f746-disco: Fix SPL boot Commit 'b4b9a00ed593 ("Convert CONFIG_SYS_SPL_ARGS_ADDR to Kconfig")' replaces CONFIG_SYS_FDT_BASE by CONFIG_SYS_SPL_ARGS_ADDR. As CONFIG_SYS_SPL_ARGS_ADDR enables additional code when enable, it increases SPL size over the initial 0x8000 limit. Increase the SPL size to 0x9000 to fix SPL boot. Set SPL_SIZE_LIMIT to 0x9000 to avoid similar issue in the future. Fixes 'b4b9a00ed593 ("Convert CONFIG_SYS_SPL_ARGS_ADDR to Kconfig")' Signed-off-by: Patrice Chotard Reviewed-by: Patrick Delaunay Tested-by: Waldemar Brodkorb --- configs/stm32f746-disco_spl_defconfig | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/configs/stm32f746-disco_spl_defconfig b/configs/stm32f746-disco_spl_defconfig index e7b1acc..5e8a8aaf 100644 --- a/configs/stm32f746-disco_spl_defconfig +++ b/configs/stm32f746-disco_spl_defconfig @@ -1,6 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_STM32=y -CONFIG_SYS_TEXT_BASE=0x08008000 +CONFIG_SYS_TEXT_BASE=0x08009000 CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_SYS_MALLOC_F_LEN=0xE00 CONFIG_SPL_GPIO=y @@ -13,10 +13,11 @@ CONFIG_SPL_TEXT_BASE=0x8000000 CONFIG_SYS_PROMPT="U-Boot > " CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL_SIZE_LIMIT=0x9000 CONFIG_STM32F7=y CONFIG_TARGET_STM32F746_DISCO=y CONFIG_SPL=y -CONFIG_SYS_LOAD_ADDR=0x8008000 +CONFIG_SYS_LOAD_ADDR=0x8009000 CONFIG_BUILD_TARGET="u-boot-with-spl.bin" CONFIG_DISTRO_DEFAULTS=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y @@ -29,7 +30,7 @@ CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk consoleblank=0 ignore_loglevel" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_BOARD_LATE_INIT=y -CONFIG_SPL_PAD_TO=0x8000 +CONFIG_SPL_PAD_TO=0x9000 CONFIG_SPL_NO_BSS_LIMIT=y CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y -- cgit v1.1 From c8b577ce829191ec61a785f816453de184253635 Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Tue, 20 Sep 2022 18:04:31 +0200 Subject: configs: stm32f769-disco: Fix SPL boot Commit 'b4b9a00ed593 ("Convert CONFIG_SYS_SPL_ARGS_ADDR to Kconfig")' replaces CONFIG_SYS_FDT_BASE by CONFIG_SYS_SPL_ARGS_ADDR. As CONFIG_SYS_SPL_ARGS_ADDR enables additional code when enable, it increases SPL size over the initial 0x8000 limit. Increase the SPL size to 0x9000 to fix SPL boot. Set SPL_SIZE_LIMIT to 0x9000 to avoid similar issue in the future. Fixes 'b4b9a00ed593 ("Convert CONFIG_SYS_SPL_ARGS_ADDR to Kconfig")' Signed-off-by: Patrice Chotard Reviewed-by: Patrick Delaunay Tested-by: Waldemar Brodkorb --- configs/stm32f769-disco_spl_defconfig | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/configs/stm32f769-disco_spl_defconfig b/configs/stm32f769-disco_spl_defconfig index 19d2c24..b56d88f 100644 --- a/configs/stm32f769-disco_spl_defconfig +++ b/configs/stm32f769-disco_spl_defconfig @@ -1,6 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_STM32=y -CONFIG_SYS_TEXT_BASE=0x08008000 +CONFIG_SYS_TEXT_BASE=0x08009000 CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_SYS_MALLOC_F_LEN=0xE00 CONFIG_SPL_GPIO=y @@ -13,10 +13,11 @@ CONFIG_SPL_TEXT_BASE=0x8000000 CONFIG_SYS_PROMPT="U-Boot > " CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL_SIZE_LIMIT=0x9000 CONFIG_STM32F7=y CONFIG_TARGET_STM32F746_DISCO=y CONFIG_SPL=y -CONFIG_SYS_LOAD_ADDR=0x8008000 +CONFIG_SYS_LOAD_ADDR=0x8009000 CONFIG_BUILD_TARGET="u-boot-with-spl.bin" CONFIG_DISTRO_DEFAULTS=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y @@ -28,7 +29,7 @@ CONFIG_AUTOBOOT_STOP_STR=" " CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk consoleblank=0 ignore_loglevel" # CONFIG_DISPLAY_CPUINFO is not set -CONFIG_SPL_PAD_TO=0x8000 +CONFIG_SPL_PAD_TO=0x9000 CONFIG_SPL_NO_BSS_LIMIT=y CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y -- cgit v1.1 From 4f174e6ffab693510a9ac23c873017423f8d017e Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Tue, 20 Sep 2022 18:04:32 +0200 Subject: configs: stm32746g-eval: Fix SPL boot Commit 'b4b9a00ed593 ("Convert CONFIG_SYS_SPL_ARGS_ADDR to Kconfig")' replaces CONFIG_SYS_FDT_BASE by CONFIG_SYS_SPL_ARGS_ADDR. As CONFIG_SYS_SPL_ARGS_ADDR enables additional code when enable, it increases SPL size over the initial 0x8000 limit. Increase the SPL size to 0x9000 to fix SPL boot. Set SPL_SIZE_LIMIT to 0x9000 to avoid similar issue in the future. Fixes 'b4b9a00ed593 ("Convert CONFIG_SYS_SPL_ARGS_ADDR to Kconfig")' Signed-off-by: Patrice Chotard Reviewed-by: Patrick Delaunay Tested-by: Waldemar Brodkorb --- configs/stm32746g-eval_spl_defconfig | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/configs/stm32746g-eval_spl_defconfig b/configs/stm32746g-eval_spl_defconfig index a3b7146..d8d55c2 100644 --- a/configs/stm32746g-eval_spl_defconfig +++ b/configs/stm32746g-eval_spl_defconfig @@ -1,6 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_STM32=y -CONFIG_SYS_TEXT_BASE=0x08008000 +CONFIG_SYS_TEXT_BASE=0x08009000 CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_SYS_MALLOC_F_LEN=0xE00 CONFIG_SPL_GPIO=y @@ -13,10 +13,11 @@ CONFIG_SPL_TEXT_BASE=0x8000000 CONFIG_SYS_PROMPT="U-Boot > " CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL_SIZE_LIMIT=0x9000 CONFIG_STM32F7=y CONFIG_TARGET_STM32F746_DISCO=y CONFIG_SPL=y -CONFIG_SYS_LOAD_ADDR=0x8008000 +CONFIG_SYS_LOAD_ADDR=0x8009000 CONFIG_BUILD_TARGET="u-boot-with-spl.bin" CONFIG_DISTRO_DEFAULTS=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y @@ -29,7 +30,7 @@ CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk consoleblank=0 ignore_loglevel" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_BOARD_LATE_INIT=y -CONFIG_SPL_PAD_TO=0x8000 +CONFIG_SPL_PAD_TO=0x9000 CONFIG_SPL_NO_BSS_LIMIT=y CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y -- cgit v1.1 From 4b2bcca5c37720c5c905022f4dcbb5a054267d7c Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Tue, 20 Sep 2022 18:04:33 +0200 Subject: configs: stm32f746-disco: Fix CONFIG_SYS_SPL_ARGS_ADDR STM32F746 embeds 1 MB of internal flash [0x08000000-0x080fffff], fix CONFIG_SYS_SPL_ARGS_ADDR accordingly It solves hard fault when jumping from SPL to U-Boot. Signed-off-by: Patrice Chotard Reviewed-by: Patrick Delaunay Tested-by: Waldemar Brodkorb --- configs/stm32f746-disco_spl_defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configs/stm32f746-disco_spl_defconfig b/configs/stm32f746-disco_spl_defconfig index 5e8a8aaf..d4a65bd 100644 --- a/configs/stm32f746-disco_spl_defconfig +++ b/configs/stm32f746-disco_spl_defconfig @@ -36,7 +36,7 @@ CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_MTD_SUPPORT=y CONFIG_SPL_XIP_SUPPORT=y -CONFIG_SYS_SPL_ARGS_ADDR=0x81c0000 +CONFIG_SYS_SPL_ARGS_ADDR=0x80c0000 CONFIG_SPL_DM_RESET=y CONFIG_SYS_PBSIZE=1050 CONFIG_CMD_GPT=y -- cgit v1.1 From ab5c4e5b0f34b4341dcb17c5234c08130bd251c2 Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Tue, 20 Sep 2022 18:04:34 +0200 Subject: configs: stm32746g-eval: Fix CONFIG_SYS_SPL_ARGS_ADDR STM32F746 embeds 1 MB of internal flash [0x08000000-0x080fffff], fix CONFIG_SYS_SPL_ARGS_ADDR accordingly It solves hard fault when jumping from SPL to U-Boot. Signed-off-by: Patrice Chotard Reviewed-by: Patrick Delaunay Tested-by: Waldemar Brodkorb --- configs/stm32746g-eval_spl_defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configs/stm32746g-eval_spl_defconfig b/configs/stm32746g-eval_spl_defconfig index d8d55c2..28f522b 100644 --- a/configs/stm32746g-eval_spl_defconfig +++ b/configs/stm32746g-eval_spl_defconfig @@ -36,7 +36,7 @@ CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_MTD_SUPPORT=y CONFIG_SPL_XIP_SUPPORT=y -CONFIG_SYS_SPL_ARGS_ADDR=0x81c0000 +CONFIG_SYS_SPL_ARGS_ADDR=0x80c0000 CONFIG_SPL_DM_RESET=y CONFIG_SYS_PBSIZE=1050 CONFIG_CMD_GPT=y -- cgit v1.1 From 3cc471d30a1f7b47f0c9d2bd9874097d4b226659 Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Tue, 20 Sep 2022 18:04:35 +0200 Subject: configs: stm32f769-disco: Fix internal flash size arch-stm32f7/stm32.h file is shared between STM32F746 and STM32F769 MCUs. But STM32F769 embeds 2MB of internal flash instead of 1MB for STM32F746. The flash layout is quite similar between the 2 SoCs : STM32F746 STM32F769 4 * 32KB sectors 4 * 32KB sectors 1 * 128KB sector 1 * 128KB sector 3 * 256KB sectors 7 * 256KB sectors Update sect_sz_kb[] structure and SYS_MAX_FLASH_SECT accordingly. Signed-off-by: Patrice Chotard Reviewed-by: Patrick Delaunay Tested-by: Waldemar Brodkorb --- arch/arm/include/asm/arch-stm32f7/stm32.h | 6 +++--- configs/stm32f769-disco_defconfig | 2 +- configs/stm32f769-disco_spl_defconfig | 2 +- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/include/asm/arch-stm32f7/stm32.h b/arch/arm/include/asm/arch-stm32f7/stm32.h index 3451e74..57db839 100644 --- a/arch/arm/include/asm/arch-stm32f7/stm32.h +++ b/arch/arm/include/asm/arch-stm32f7/stm32.h @@ -10,9 +10,9 @@ #include static const u32 sect_sz_kb[CONFIG_SYS_MAX_FLASH_SECT] = { - [0 ... 3] = 32 * 1024, - [4] = 128 * 1024, - [5 ... 7] = 256 * 1024 + [0 ... 3] = 32 * 1024, + [4] = 128 * 1024, + [5 ... CONFIG_SYS_MAX_FLASH_SECT - 1] = 256 * 1024 }; #endif /* _ASM_ARCH_HARDWARE_H */ diff --git a/configs/stm32f769-disco_defconfig b/configs/stm32f769-disco_defconfig index 423af74..5b5307c 100644 --- a/configs/stm32f769-disco_defconfig +++ b/configs/stm32f769-disco_defconfig @@ -41,7 +41,7 @@ CONFIG_MTD=y CONFIG_DM_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_STM32_FLASH=y -CONFIG_SYS_MAX_FLASH_SECT=8 +CONFIG_SYS_MAX_FLASH_SECT=12 CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/stm32f769-disco_spl_defconfig b/configs/stm32f769-disco_spl_defconfig index b56d88f..b5d54b4 100644 --- a/configs/stm32f769-disco_spl_defconfig +++ b/configs/stm32f769-disco_spl_defconfig @@ -63,7 +63,7 @@ CONFIG_MTD=y CONFIG_DM_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_STM32_FLASH=y -CONFIG_SYS_MAX_FLASH_SECT=8 +CONFIG_SYS_MAX_FLASH_SECT=12 CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_STMICRO=y -- cgit v1.1 From 2b5dee9485eb52875df801a414838d75b000604d Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Tue, 20 Sep 2022 18:04:36 +0200 Subject: configs: stm32f746-disco: Remove CONFIG_SYS_UBOOT_START flag By pressing "c" key during SPL execution, we force U-boot execution instead of a kernel XIP image. This fixes a hard fault when booting stm32f746-disco in SPL with "c" key pressed during SPL execution. U-Boot SPL 2022.10-rc5-00009-g40d02baa91 (Sep 20 2022 - 17:21:21 +0200) Trying to boot from XIP Hard fault pc : 080083fc lr : 08000d1b xPSR : 21000000 r12 : 2004f108 r3 : 080083fd r2 : 00000028 r1 : 2004f0c8 r0 : 2004f0e4 Resetting CPU ... This is due to SYS_UBOOT_START flag set to 0x080083FD which is not correct. If unset, SYS_UBOOT_START is set by default to CONFIG_SYS_TEXT_BASE which match with our requirement. Signed-off-by: Patrice Chotard Reviewed-by: Patrick Delaunay Tested-by: Waldemar Brodkorb --- include/configs/stm32f746-disco.h | 1 - 1 file changed, 1 deletion(-) diff --git a/include/configs/stm32f746-disco.h b/include/configs/stm32f746-disco.h index 64c1bc7..b0ec226 100644 --- a/include/configs/stm32f746-disco.h +++ b/include/configs/stm32f746-disco.h @@ -34,7 +34,6 @@ BOOTENV #define CONFIG_SYS_MONITOR_LEN (512 * 1024) -#define CONFIG_SYS_UBOOT_START 0x080083FD #define CONFIG_SYS_UBOOT_BASE (CONFIG_SYS_FLASH_BASE + \ CONFIG_SPL_PAD_TO) -- cgit v1.1 From 762d410e0db94c41b8d7f1ec85e47f7474655ad8 Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Mon, 26 Sep 2022 17:59:36 +0200 Subject: configs: increase SYS_MALLOC_F_LEN for STM32 MCU's board Some STM32 MCU's board need their SYS_MALLOC_F_LEN value enlarged to avoid the "alloc space exhausted" error message during their boot process. Use the default SYS_MALLOC_F_LEN value which is set to 0x2000 in Kconfig. Signed-off-by: Patrice Chotard Reviewed-by: Patrick Delaunay --- configs/stm32746g-eval_defconfig | 1 - configs/stm32746g-eval_spl_defconfig | 1 - configs/stm32f429-discovery_defconfig | 1 - configs/stm32f429-evaluation_defconfig | 1 - configs/stm32f469-discovery_defconfig | 1 - configs/stm32f746-disco_defconfig | 1 - configs/stm32f746-disco_spl_defconfig | 1 - configs/stm32f769-disco_defconfig | 1 - configs/stm32f769-disco_spl_defconfig | 1 - configs/stm32h743-disco_defconfig | 1 - configs/stm32h743-eval_defconfig | 1 - configs/stm32h750-art-pi_defconfig | 1 - 12 files changed, 12 deletions(-) diff --git a/configs/stm32746g-eval_defconfig b/configs/stm32746g-eval_defconfig index 58232a7..7200446 100644 --- a/configs/stm32746g-eval_defconfig +++ b/configs/stm32746g-eval_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_ARCH_STM32=y CONFIG_SYS_TEXT_BASE=0x08000000 CONFIG_SYS_MALLOC_LEN=0x100000 -CONFIG_SYS_MALLOC_F_LEN=0xE00 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x2000 CONFIG_DEFAULT_DEVICE_TREE="stm32746g-eval" diff --git a/configs/stm32746g-eval_spl_defconfig b/configs/stm32746g-eval_spl_defconfig index 28f522b..ff42952 100644 --- a/configs/stm32746g-eval_spl_defconfig +++ b/configs/stm32746g-eval_spl_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_ARCH_STM32=y CONFIG_SYS_TEXT_BASE=0x08009000 CONFIG_SYS_MALLOC_LEN=0x100000 -CONFIG_SYS_MALLOC_F_LEN=0xE00 CONFIG_SPL_GPIO=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y diff --git a/configs/stm32f429-discovery_defconfig b/configs/stm32f429-discovery_defconfig index e6e595d..914ac14 100644 --- a/configs/stm32f429-discovery_defconfig +++ b/configs/stm32f429-discovery_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_ARCH_STM32=y CONFIG_SYS_TEXT_BASE=0x08000000 CONFIG_SYS_MALLOC_LEN=0x0200000 -CONFIG_SYS_MALLOC_F_LEN=0xF00 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x20000 diff --git a/configs/stm32f429-evaluation_defconfig b/configs/stm32f429-evaluation_defconfig index 073f271..af7a8bf 100644 --- a/configs/stm32f429-evaluation_defconfig +++ b/configs/stm32f429-evaluation_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_ARCH_STM32=y CONFIG_SYS_TEXT_BASE=0x08000000 CONFIG_SYS_MALLOC_LEN=0x100000 -CONFIG_SYS_MALLOC_F_LEN=0xF00 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x2000 CONFIG_DEFAULT_DEVICE_TREE="stm32429i-eval" diff --git a/configs/stm32f469-discovery_defconfig b/configs/stm32f469-discovery_defconfig index bd36932..90680fd 100644 --- a/configs/stm32f469-discovery_defconfig +++ b/configs/stm32f469-discovery_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_ARCH_STM32=y CONFIG_SYS_TEXT_BASE=0x08000000 CONFIG_SYS_MALLOC_LEN=0x100000 -CONFIG_SYS_MALLOC_F_LEN=0xF00 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x2000 CONFIG_DEFAULT_DEVICE_TREE="stm32f469-disco" diff --git a/configs/stm32f746-disco_defconfig b/configs/stm32f746-disco_defconfig index ed537b0..a8edf11 100644 --- a/configs/stm32f746-disco_defconfig +++ b/configs/stm32f746-disco_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_ARCH_STM32=y CONFIG_SYS_TEXT_BASE=0x08000000 CONFIG_SYS_MALLOC_LEN=0x100000 -CONFIG_SYS_MALLOC_F_LEN=0xE00 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x2000 CONFIG_DEFAULT_DEVICE_TREE="stm32f746-disco" diff --git a/configs/stm32f746-disco_spl_defconfig b/configs/stm32f746-disco_spl_defconfig index d4a65bd..0e358e8 100644 --- a/configs/stm32f746-disco_spl_defconfig +++ b/configs/stm32f746-disco_spl_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_ARCH_STM32=y CONFIG_SYS_TEXT_BASE=0x08009000 CONFIG_SYS_MALLOC_LEN=0x100000 -CONFIG_SYS_MALLOC_F_LEN=0xE00 CONFIG_SPL_GPIO=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y diff --git a/configs/stm32f769-disco_defconfig b/configs/stm32f769-disco_defconfig index 5b5307c..3e7b5bd 100644 --- a/configs/stm32f769-disco_defconfig +++ b/configs/stm32f769-disco_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_ARCH_STM32=y CONFIG_SYS_TEXT_BASE=0x08000000 CONFIG_SYS_MALLOC_LEN=0x100000 -CONFIG_SYS_MALLOC_F_LEN=0xE00 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x2000 CONFIG_DEFAULT_DEVICE_TREE="stm32f769-disco" diff --git a/configs/stm32f769-disco_spl_defconfig b/configs/stm32f769-disco_spl_defconfig index b5d54b4..f0a1b66 100644 --- a/configs/stm32f769-disco_spl_defconfig +++ b/configs/stm32f769-disco_spl_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_ARCH_STM32=y CONFIG_SYS_TEXT_BASE=0x08009000 CONFIG_SYS_MALLOC_LEN=0x100000 -CONFIG_SYS_MALLOC_F_LEN=0xE00 CONFIG_SPL_GPIO=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y diff --git a/configs/stm32h743-disco_defconfig b/configs/stm32h743-disco_defconfig index d33da43..8c62c70 100644 --- a/configs/stm32h743-disco_defconfig +++ b/configs/stm32h743-disco_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_ARCH_STM32=y CONFIG_SYS_TEXT_BASE=0x08000000 CONFIG_SYS_MALLOC_LEN=0x100000 -CONFIG_SYS_MALLOC_F_LEN=0xF00 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x2000 CONFIG_DEFAULT_DEVICE_TREE="stm32h743i-disco" diff --git a/configs/stm32h743-eval_defconfig b/configs/stm32h743-eval_defconfig index a72de48..1ff6b50 100644 --- a/configs/stm32h743-eval_defconfig +++ b/configs/stm32h743-eval_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_ARCH_STM32=y CONFIG_SYS_TEXT_BASE=0x08000000 CONFIG_SYS_MALLOC_LEN=0x100000 -CONFIG_SYS_MALLOC_F_LEN=0xF00 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x2000 CONFIG_DEFAULT_DEVICE_TREE="stm32h743i-eval" diff --git a/configs/stm32h750-art-pi_defconfig b/configs/stm32h750-art-pi_defconfig index b8296a9..a5fce5e 100644 --- a/configs/stm32h750-art-pi_defconfig +++ b/configs/stm32h750-art-pi_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_ARCH_STM32=y CONFIG_SYS_TEXT_BASE=0x90000000 CONFIG_SYS_MALLOC_LEN=0x100000 -CONFIG_SYS_MALLOC_F_LEN=0xF00 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x2000 CONFIG_DEFAULT_DEVICE_TREE="stm32h750i-art-pi" -- cgit v1.1