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2019-04-14arm64: allwinner: sun50i: Sync H6 dts(i) files from LinuxJagan Teki1-0/+11
Usually the Linux dts changes were synced in specific tags in Allwinner, to keep track for whats been synced so-far and plan for future syncs. But this patch sync sun50i-h6* dts(i) files from Linux w/o any specific tag since these dts(i) changes are required for new H6 boards support. Linux commit details about the sun50i-h6* sync: "arm64: dts: allwinner: h6: move MMC pinctrl to dtsi" (sha1: 6ba2e45d57afdfd982d12f168edd6a79a65075d8) Linux commit details about the sun8i-tcon-top.h sync: "dt-bindings: display: sunxi-drm: Add TCON TOP description" (sha1: 59a9c39544cd1e5952c2a33028d71aa8180648f8) Part of the sync initiated by 'Clément Péron'. Signed-off-by: Clément Péron <peron.clem@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-04-14Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini2-5/+6
Conflicts: arch/arm/dts/armada-385-amc.dts arch/arm/dts/armada-xp-theadorable.dts arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi Signed-off-by: Tom Rini <trini@konsulko.com>
2019-04-13Merge tag 'pull-12apr19' of git://git.denx.de/u-boot-dmTom Rini3-38/+169
fdtdec tests and improvements for carve-outs pinctrl race-condition fix various other fixes in sandbox, sound, mkimage, etc.
2019-04-13Merge tag 'mips-pull-2019-04-12' of git://git.denx.de/u-boot-mipsTom Rini3-2/+71
- mt76xx: add USB support, small fixes - ath79: small fixes, add support for QCA9563 SoC and AP152 reference board - mscc: small fixes, add network support for JR2 and ServalT SoCs - bmips: small fixes, enable more drivers for ARM specific BCM6858 and BCM63158 SoCs - MIPS: fix redundant relocation of initrd images
2019-04-12Merge tag 'u-boot-stm32-20190412' of https://github.com/patrickdelaunay/u-bootTom Rini5-160/+210
stm32 patches for v2019.07-rc1 - Add trusted boot with TF-A for stm32mp1 - stm32mp1 dts files sync'ed with Linux version - add STM32MP1 Discovery boards (DK1 and DK2) - add STMFX gpio expander driver - misc improvement for stm3mp1 supports - rename stpmu1 to stpmic1 (official name) - stm32_qspi: move to exec_op (spi nor driver for stm32 mpu and mcu) - add STM32 FMC2 NAND flash controller driver
2019-04-12Merge branch 'master' of git://git.denx.de/u-boot-i2cTom Rini1-0/+2
2019-04-12Merge git://git.denx.de/u-boot-marvellTom Rini13-44/+51
- Misc dts files sync'ed with Linux version (Chris) - Orion watchdog fix (Chris) - kwbimage changed to also support Marvell bin_hdr binary (Chris) - Add DM support to enable CONFIG_BLK for sata_mv (Stefan) - Enable BLK on multiple platforms (Stefan) - Misc minor fixes to AXP theadorable board (Stefan) - Correct logic for DM_SCSI + unconverted drivers check (stefan) - Misc changes to kirkwood to enable DM_USB here (Chris) - Change ahci_mvebu to enable usage on A38x (Baruch) - Update the kirkwood entry in git-mailrc (Baruch) - Misc minor improvements (turris, documentation) (Baruch) - Enhance sata_mv to support Kirkwood as well (Michael) - Add wdt command (Michael) - Add Marvell integrated CPUs (MSYS) support with DB-XC3-24G4XG board support (Chris)
2019-04-12configs: vcoreiii: Change CONFIG_ENV_SIZEHoratiu Vultur1-1/+1
Shrink the environment size for 3 reasons: - reading the environment it is slow, therefore having a smaller env improves the speed. - usually in the environment there are only few variables, therefore the enviromnent is almost empty. - because the same image can run on different boards which may have different flashes with different page sizes, the CONFIG_ENV_SECT_SIZE can't be change, it is set to least common multiple of the page sizes. Adding this change improves the boot time. Before update for reading the entire environment it took ~850 msec, after the change it takes ~40 msecs. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
2019-04-12net: mscc: jaguar2: Add ethenet nodes for Jaguar2.Horatiu Vultur1-0/+19
Add ethernet nodes for Jaguar2 SoCs family. There are 3 pcb in this family: pcb110, pcb111 and pcb112. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
2019-04-12net: Add MSCC Jaguar2 network driver.Horatiu Vultur1-1/+1
Add network driver for Microsemi Ethernet switch. It is present on Jaguar2 SoCs. Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
2019-04-12mips: add initial support for qca956x referenced boardRosy Song1-0/+50
QCA9563 is CPU used on AP152 board : Clock speed : 750 MHz , Arch : Mips 74Kc, Eth : SGMII interface, MIMO config : 3 * 3 450M, 2 * USB 2.0, Signed-off-by: Rosy Song <rosysong@rosinson.com> Changes for v2: - coding style cleanup - remove ununsed flash chip in defconfig - enable automatic icache / dcache size in defconfig Changes for v3: - add detailed information for qca956x in commit message Changes for v4: - remove pre-configured network settings in ap152.h Changes for v5: - coding style cleanup
2019-04-12stpmic1: add NVM update support in fuse commandPatrick Delaunay1-0/+7
Add functions to read/update the non volatile memory of STPMIC1 (8 bytes-register at 0xF8 address) and allow access with fuse command (bank=1, word > 0xF8). For example: STM32MP> fuse read 1 0xf8 8 Reading bank 1: Word 0x000000f8: 000000ee 00000092 000000c0 00000002 Word 0x000000fc: 000000f2 00000080 00000002 00000033 Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-04-12stpmic1: update register namesPatrick Delaunay1-40/+58
Alignment with STPMIC1 datasheet s/MAIN_CONTROL_REG/MAIN_CR/g s/MASK_RESET_BUCK/BUCKS_MRST_CR/g s/MASK_RESET_LDOS/LDOS_MRST_CR/g s/BUCKX_CTRL_REG/BUCKX_MAIN_CR/g s/VREF_CTRL_REG/REFDDR_MAIN_CR/g s/LDOX_CTRL_REG/LDOX_MAIN_CR/g s/USB_CTRL_REG/BST_SW_CR/g s/STPMIC1_NVM_USER_STATUS_REG/STPMIC1_NVM_SR/g s/STPMIC1_NVM_USER_CONTROL_REG/STPMIC1_NVM_CR/g and update all the associated defines. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-04-12power: rename stpmu1 to official name stpmic1Patrick Delaunay2-115/+108
Alignment with kernel driver name & binding introduced by https://patchwork.kernel.org/cover/10761943/ to use the final marketing name = STPMIC1. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
2019-04-12power: stpmu1: rename files to stpmic1Patrick Delaunay2-0/+0
Prepare file modification for kernel alignment and rename driver to stpmic1. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
2019-04-12stm32mp1: activated some configurationPatrick Delaunay1-0/+4
Add configuration useful for test - FIT support - MEMTEST - DFU - CACHE - TIME - TIMER Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-04-12stm32mp1: update memory layoutPatrick Delaunay1-5/+14
Update the memory layout to be aligned with other platform and avoid overlap with 32MB Linux kernel (multiv7 image). + Kernel => 32MiB offset = 0xC2000000 and increase the bootm size to 32MiB + FDT => 64MiB offset = 0xc4000000 + SCRIPT => 65Mib offset = 0xc4100000 + PXESCRIPT => 66Mib offset = 0xc4200000 + SPLASHIMAGE => 67Mib offset = 0xc4300000 + RAMDISK => 68Mib offset = 0xc4400000 (not limited size) In sources/boot/u-boot/doc/README.distro + kernel_addr_r: A size of 16MB for the kernel is likely adequate. + pxefile_addr_r: A size of 1MB for extlinux.conf is more than adequate. + fdt_addr_r: A size of 1MB for the FDT/DTB seems reasonable. + ramdisk_addr_r: It is recommended that this location be highest in RAM out of fdt_addr_, kernel_addr_r, and ramdisk_addr_r, so that the RAM disk can vary in size and use any available RAM. + pxefile_addr_r: A size of 1MB for extlinux.conf is more than adequate. + scriptaddr: A size of 1MB for extlinux.conf is more than adequate. For suggestions on memory locations for ARM systems, you must follow the guidelines specified in Documentation/arm/Booting in the Linux kernel tree. And in sources/linux-stm32mp/Documentation/arm/Booting The zImage may also be placed in system RAM and called there. The kernel should be placed in the first 128MiB of RAM. It is recommended that it is loaded above 32MiB in order to avoid the need to relocate prior to decompression, which will make the boot process slightly faster. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-04-12stm32mp1: update bootcmdPatrick Delaunay1-10/+27
Clearly separate bootcmd for stm32mp1 board (bootcmd_stm32mp) and preboot management. That solve issue for fastboot continue command. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-04-12stm32mp1: add trusted boot with TF-APatrick Delaunay1-0/+2
Add support of trusted boot, using TF-A as first stage bootloader, The boot sequence is BootRom >=> TF-A.stm32 (clock & DDR) >=> U-Boot.stm32 The TF-A monitor provides secure monitor with support of SMC - proprietary to manage secure devices (BSEC for example) - PSCI for power The same device tree is used for STMicroelectronics boards with basic boot and with trusted boot. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-04-12ti: keystone2: Move CONFIG_ISW_ENTRY_ADDR to a common placeTom Rini5-15/+3
The ISW_ENTRY_ADDR Kconfig option under mach-omap2 isn't a SoC specific notion but rather "where is our previous stage loaded in memory?" option. Make use of this on ARCH_KEYSTONE rather than SPL_TEXT_BASE for our HS builds that are not using SPL anyhow. Cc: Vitaly Andrianov <vitalya@ti.com> Cc: Andrew F. Davis <afd@ti.com> Cc: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com?
2019-04-12board: ti: am335x: Add platdata for cpsw in SPLFaiz Abbas1-0/+17
The SPL image overflows when cpsw dt nodes are added and SPL_OF_CONTROL is enabled. Use static platdata instead to save space. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2019-04-12net: ti: cpsw-common: Isolate getting syscon address from assigning macidFaiz Abbas1-1/+6
ti_cm_get_macid() is used to get a syscon node from the dt, read the efuse address and then assign the macid read from the address. Divide these two steps into separate functions one of which can be called from ofdata_to_platdata() while the other can be called from _probe(). This ensures that platdata can be assigned statically in a board file when OF_CONTROL is not enabled. Also add a macid_sel_compat in private data to get information about the macid byte placement. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2019-04-12net: ti: cpsw: Move cpsw_phy_sel() to _probe()Faiz Abbas1-0/+1
cpsw_phy_sel() is a configuration step that should not be in ofdata_to_platdata(). Add phy_sel_compat to the cpsw_platform_data structure so that it is accessible in _probe. Then move the call of cpsw_phy_sel() to _probe. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2019-04-12net: Add priv_pdata to eth_pdataFaiz Abbas1-0/+2
Add a priv member for eth_pdata for platform specific platform data. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2019-04-12firmware: Add support for querying msmc memoryLokesh Vutla1-0/+4
DMSC can use certain amount of msmc memory available in the system. Also certain part of msmc memory can be marked as L3 cache using board config. But users might not know what size is being used and the remaining available msmc memory. In order to fix this TISCI protocol provides a messages that can query the available msmc memory in the system. Add support for this message. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-04-12configs: ti_omap5_common: Add NAND environment settingsFaiz Abbas3-2/+29
Now that NAND is supported on DRA71x include various NAND environment settings Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2019-04-12davinci: da850evm/omapl138-lcdk: Move BSS to SDRAM because SRAM is fullAdam Ford2-1/+5
In order to fully support SPL_OF_CONTROL, we need BSS to be a bit larger. This patch relocates BSS to SDRAM instead of SRAM which is similar to how ARMv7 boards (like OMAP2+) do it. This means two new variables are required: CONFIG_SPL_BSS_START_ADDR set to DAVINCI_DDR_EMIF_DATA_BASE CONFIG_SPL_BSS_MAX_SIZE is set to 0x1080000 which is 1 byte before the location where U-Boot will load. Signed-off-by: Adam Ford <aford173@gmail.com>
2019-04-12am335x, guardian: Add support for the bosch guardian boardSjoerd Simons1-0/+111
Add support for the Bosch Guardian board. CPU : AM335X-GP rev 2.1 Model: Bosch AM335x Guardian I2C: ready DRAM: 256 MiB NAND: 512 MiB MMC: OMAP SD/MMC: 0 Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Signed-off-by: Martyn Welch <martyn.welch@collabora.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Felix Brack <fb@ltec.ch>
2019-04-12dm: spi: Read default speed and mode values from DTPatrick Delaunay1-4/+5
This patch update the behavior introduced by commit 96907c0fe50a ("dm: spi: Read default speed and mode values from DT") In case of DT boot, don't read default speed and mode for SPI from CONFIG_* but instead read from DT node. This will make sure that boards with multiple SPI/QSPI controllers can be probed at different bus frequencies and SPI modes. Remove also use in boards of the value speed=0 (no more supported) for ENV in SPI by using CONFIG_ENV_SPI_MAX_HZ=0. DT values will be always used when available (full DM support of SPI slave with available DT node) even if speed and mode are requested; for example in splash screen support (in splash_sf_read_raw) or in SPL boot (in spl_spi_load_image). The caller of spi_get_bus_and_cs() no more need to force speed=0. But the current behavior don't change if the SPI slave is not present (device with generic driver is created automatically) or if platdata is used (CONFIG_OF_PLATDATA). Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
2019-04-12mtd: fix mtd_oobavail() incoherent returned valueMiquel Raynal1-1/+1
mtd_oobavail() returns either mtd->oovabail or mtd->oobsize. Both values are unsigned 32-bit entities, so there is no reason to pretend returning a signed one. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-04-12arm: mvebu: Add DB-XC3-24G4XG boardChris Packham1-0/+41
The DB-XC3-24G4XG is a switch development board from Marvell. It can either use and external CPU card such as the db-88f6820-amc or the internal CPU that is integrated into the switch. Add support for running U-Boot on the internal CPU and enable the USB, SPI and NAND peripherals. For now this needs the bin_hdr from the Marvell U-Boot for this board. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
2019-04-12arm: kirkwood: lsxl: enable DM for SATAMichael Walle1-13/+10
Switch from legacy IDE driver to sata_mv driver. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
2019-04-12arm: mvebu: turris_omnia: select Kconfig SPI_FLASH_SPANSIONBaruch Siach1-2/+0
Signed-off-by: Baruch Siach <baruch@tkos.co.il> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
2019-04-12mvebu: drop dangling SPI flash comments and #ifdefsBaruch Siach11-29/+0
Following commits abe66b1b5dec ("Convert CONFIG_ENV_SPI_* to Kconfig") and 14453fbfadc2f ("Convert CONFIG_SF_DEFAULT_* to Kconfig") remove dandling comment lines and empty #ifdef sections. Cc: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
2019-04-11fdtdec: Implement carveout support functionsThierry Reding1-0/+81
The fdtdec_get_carveout() and fdtdec_set_carveout() function can be used to read a carveout from a given node or add a carveout to a given node using the standard device tree bindings (involving reserved-memory nodes and the memory-region property). Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-04-11fdtdec: Implement fdtdec_add_reserved_memory()Thierry Reding1-0/+48
This function can be used to add subnodes in the /reserved-memory node. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-04-11fdtdec: Implement fdtdec_set_phandle()Thierry Reding1-0/+11
This function can be used to set a phandle for a given node. Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-04-11fdtdec: Add fdt_{addr, size}_unpack() helpersThierry Reding1-0/+25
These helpers can be used to unpack variables of type fdt_addr_t and fdt_size_t into a pair of 32-bit variables. This is useful in cases where such variables need to be written to properties (such as "reg") of a device tree node where they need to be split into cells. Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-04-11fdtdec: Add cpu_to_fdt_{addr, size}() macrosThierry Reding1-0/+4
These macros are useful for converting the endianness of variables of type fdt_addr_t and fdt_size_t. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-04-11dm: remove unused function dm_fdt_pre_relocPatrick Delaunay1-26/+0
The function dm_ofnode_pre_reloc should be used instead of the function dm_fdt_pre_reloc and avoid duplicated code. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2019-04-11dm: pinctrl: Remove obsolete function pinctrl_decode_pin_config_dm().Christoph Muellner1-12/+0
This reverts commit 5ff776889212c080e3d1a33634ac904405ed6845. As noted in the comment, the function pinctrl_decode_pin_config_dm() only served as a temporary solution. Since the function has no users anymore, we can remove it again. Signed-off-by: Christoph Muellner <christoph.muellner@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2019-04-11soc: keystone: Merge into ti specific directoryVignesh R1-3/+0
Merge drivers/soc/keystone/ into drivers/soc/ti/ and convert CONFIG_TI_KEYSTONE_SERDES into Kconfig. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2019-04-11dma: ti: add driver to K3 UDMAVignesh R2-0/+55
The UDMA-P is intended to perform similar (but significantly upgraded) functions as the packet-oriented DMA used on previous SoC devices. The UDMA-P module supports the transmission and reception of various packet types. The UDMA-P also supports acting as both a UTC and UDMA-C for its internal channels. Channels in the UDMA-P can be configured to be either Packet-Based or Third-Party channels on a channel by channel basis. The initial driver supports: - MEM_TO_MEM (TR mode) - DEV_TO_MEM (Packet mode) - MEM_TO_DEV (Packet mode) Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Vignesh R <vigneshr@ti.com>
2019-04-11soc: ti: k3: add CPPI5 description and helpersGrygorii Strashko1-0/+995
Add TI Communications Port Programming Interface (CPPI) 5 interface description and helpers Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2019-04-11soc: ti: k3: add navss ringacc driverGrygorii Strashko1-0/+236
The Ring Accelerator (RINGACC or RA) provides hardware acceleration to enable straightforward passing of work between a producer and a consumer. There is one RINGACC module per NAVSS on TI AM65x SoCs. The RINGACC converts constant-address read and write accesses to equivalent read or write accesses to a circular data structure in memory. The RINGACC eliminates the need for each DMA controller which needs to access ring elements from having to know the current state of the ring (base address, current offset). The DMA controller performs a read or write access to a specific address range (which maps to the source interface on the RINGACC) and the RINGACC replaces the address for the transaction with a new address which corresponds to the head or tail element of the ring (head for reads, tail for writes). Since the RINGACC maintains the state, multiple DMA controllers or channels are allowed to coherently share the same rings as applicable. The RINGACC is able to place data which is destined towards software into cached memory directly. Supported ring modes: - Ring Mode - Messaging Mode - Credentials Mode - Queue Manager Mode TI-SCI integration: Texas Instrument's System Control Interface (TI-SCI) Message Protocol now has control over Ringacc module resources management (RM) and Rings configuration. The Ringacc driver manages Rings allocation by itself now and requests TI-SCI firmware to allocate and configure specific Rings only. It's done this way because, Linux driver implements two stage Rings allocation and configuration (allocate ring and configure ring) while TI-SCI Message Protocol supports only one combined operation (allocate+configure). Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Vignesh R <vigneshr@ti.com>
2019-04-11firmware: ti_sci: Add support for NAVSS resource managementGrygorii Strashko1-0/+300
Texas Instruments' System Control Interface (TI-SCI) Message Protocol abstracts management of NAVSS resources, like PSI-L pairing and unpairing, UDMAP tx/rx/flow configuration and Rings. This patch adds support for requesting and configuring such resources from TI-SCI firmware. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Vignesh R <vigneshr@ti.com>
2019-04-11Merge branch 'master' of git://git.denx.de/u-boot-shTom Rini13-72/+66
- Various rmobile fixes
2019-04-11DM: I2C: Introduce 'u-boot, i2c-transaction-bytes' propertyLukasz Majewski1-0/+2
The 'u-boot,i2c-transaction-bytes' device tree property provides information regarding number of bytes transferred by a device in a single transaction. This change is necessary to avoid hanging devices after soft reset. One notable example is communication with MC34708 device: 1. Reset when communicating with MC34708 via I2C. 2. The u-boot (after reboot -f) tries to setup the I2C and then calls force_idle_bus. In the same time MC34708 still has some data to be sent (as it transfers data in 24 bits chunks). 3. The force_idle_bus() is not able to make the bus idle as 8 SCL clocks may be not enough to have the full transmission. 4. We end up with I2C inconsistency with MC34708. This PMIC device requires 24+ SCL cycles to make finish any pending I2C transmission. Signed-off-by: Lukasz Majewski <lukma@denx.de>
2019-04-09fs: Add a new command to create symbolic linksJean-Jacques Hiblot1-0/+2
The command line is: ln <interface> <dev[:part]> target linkname Currently symbolic links are supported only in ext4 and only if the option CMD_EXT4_WRITE is enabled. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2019-04-09fs: ext4: Add support for the creation of symbolic linksJean-Jacques Hiblot1-1/+2
Re-use the functions used to write/create a file, to support creation of a symbolic link. The difference with a regular file are small: - The inode mode is flagged with S_IFLNK instead of S_IFREG - The ext2_dirent's filetype is FILETYPE_SYMLINK instead of FILETYPE_REG - Instead of storing the content of a file in allocated blocks, the path to the target is stored. And if the target's path is short enough, no block is allocated and the target's path is stored in ext2_inode.b.symlink As with regulars files, if a file/symlink with the same name exits, it is unlinked first and then re-created. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> [trini: Fix ext4 env code] Signed-off-by: Tom Rini <trini@konsulko.com>
generated by cgit v1.1 at 2024-11-16 11:53:10 +0000