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2013-06-26image: Add support for signing of FIT configurationsSimon Glass1-0/+16
While signing images is useful, it does not provide complete protection against several types of attack. For example, it it possible to create a FIT with the same signed images, but with the configuration changed such that a different one is selected (mix and match attack). It is also possible to substitute a signed image from an older FIT version into a newer FIT (roll-back attack). Add support for signing of FIT configurations using the libfdt's region support. Please see doc/uImage.FIT/signature.txt for more information. Signed-off-by: Simon Glass <sjg@chromium.org>
2013-06-26libfdt: Add fdt_find_regions()Simon Glass1-0/+64
Add a function to find regions in device tree given a list of nodes to include and properties to exclude. See the header file for full documentation. Signed-off-by: Simon Glass <sjg@chromium.org>
2013-06-26image: Add RSA support for image signingSimon Glass1-0/+108
RSA provides a public key encryption facility which is ideal for image signing and verification. Images are signed using a private key by mkimage. Then at run-time, the images are verified using a private key. This implementation uses openssl for the host part (mkimage). To avoid bringing large libraries into the U-Boot binary, the RSA public key is encoded using a simple numeric representation in the device tree. Signed-off-by: Simon Glass <sjg@chromium.org>
2013-06-26image: Support signing of imagesSimon Glass1-4/+55
Add support for signing images using a new signature node. The process is handled by fdt_add_verification_data() which now takes parameters to provide the keys and related information. Signed-off-by: Simon Glass <sjg@chromium.org>
2013-06-26image: Add signing infrastructureSimon Glass1-2/+88
Add a structure to describe an algorithm which can sign and (later) verify images. Signed-off-by: Simon Glass <sjg@chromium.org>
2013-06-26x86: config: Add tracing optionsSimon Glass1-0/+7
Add configs to enable tracing when it is needed. Signed-off-by: Simon Glass <sjg@chromium.org>
2013-06-26exynos: config: Add tracing optionsSimon Glass1-0/+8
Add tracing to Exynos5 boards, so that tracing can be enabled when building with 'make FTRACE=1'. We use a 16MB trace buffer. Signed-off-by: Simon Glass <sjg@chromium.org>
2013-06-26Add a 'fake' go command to the bootm commandSimon Glass1-1/+2
For tracing it is useful to run as much of U-Boot as possible so as to get a complete picture. Quite a bit of work happens in bootm, and we don't want to have to stop tracing before bootm starts. Add a way of doing a 'fake' boot of the OS - which does everything up to the point where U-Boot is about to jump to the OS image. This allows tracing to record right until the end. This requires arch support to work. Signed-off-by: Simon Glass <sjg@chromium.org>
2013-06-26Refactor the bootm command to reduce code duplicationSimon Glass1-7/+9
At present the bootm code is mostly duplicated for the plain 'bootm' command and its sub-command variant. This makes the code harder to maintain and means that changes must be made to several places. Introduce do_bootm_states() which performs selected portions of the bootm work, so that both plain 'bootm' and 'bootm <sub_command>' can use the same code. Additional duplication exists in bootz, so tidy that up as well. This is not intended to change behaviour, apart from minor fixes where the previously-duplicated code missed some chunks of code. Signed-off-by: Simon Glass <sjg@chromium.org>
2013-06-26sandbox: Support trace featureSimon Glass1-0/+13
Support tracing on sandbox by adding suitable CONFIG options. To enable it, compile U-Boot with FTRACE=1. The timer functions are marked to skip tracing, since these are called from the tracing code itself, and we want to avoid an infinite loop. Signed-off-by: Simon Glass <sjg@chromium.org>
2013-06-26Add trace support to generic boardSimon Glass1-0/+3
Add hooks for tracing to generic board, including: - allow early tracing to start early as possible in U-Boot - reserve memory for trace buffer - copy early trace buffer to main trace buffer after relocation - setup full tracing support after relocation Signed-off-by: Simon Glass <sjg@chromium.org>
2013-06-26Add trace librarySimon Glass2-0/+129
Add a library which supports tracing of execution using built-in gcc features and a microsecond timer. This can be used to record a list of function which are executed, along with a timestamp for each. Later this information can be sent to the host for processing. Signed-off-by: Simon Glass <sjg@chromium.org>
2013-06-26Add function to print a number with grouped digitsSimon Glass1-0/+11
Move bootstage's numbering printing code into a generic place so that it can be used by tracing also. Signed-off-by: Simon Glass <sjg@chromium.org>
2013-06-26pci: Convert extern inline functions to static inlineSimon Glass1-2/+2
I am not sure of the meaning of extern inline, but this gives errors when building with function instrumenting enabled. Change these functions to static inline. Signed-off-by: Simon Glass <sjg@chromium.org>
2013-06-26cros: exynos: enable cros-ec for smdk5250Hung-ying Tyan1-1/+9
This patch initiates cros-ec in board_init() to enable it for smdk5250. This patch depends on the patch in the MMC series that brings in exynos5-dt.c. Refer to http://patchwork.ozlabs.org/patch/240084. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Vincent Palatin <vpalatin@chromium.org> Signed-off-by: Hung-ying Tyan <tyanh@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
2013-06-26cros: adds cros_ec keyboard driverHung-ying Tyan1-0/+1
This patch adds the driver for keyboard that's controlled by ChromeOS EC. Signed-off-by: Randall Spangler <rspangler@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Vincent Palatin <vpalatin@chromium.org> Signed-off-by: Hung-ying Tyan <tyanh@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
2013-06-26cros: exynos: add SPI support for cros_ecHung-ying Tyan1-0/+16
This patch adds SPI support for carrying out the cros_ec protocol. Signed-off-by: Hung-ying Tyan <tyanh@chromium.org> Signed-off-by: Randall Spangler <rspangler@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
2013-06-26cros: add cros_ec driverHung-ying Tyan4-0/+1934
This patch adds the cros_ec driver that implements the protocol for communicating with Google's ChromeOS embedded controller. Signed-off-by: Bernie Thompson <bhthompson@chromium.org> Signed-off-by: Bill Richardson <wfrichar@chromium.org> Signed-off-by: Che-Liang Chiou <clchiou@chromium.org> Signed-off-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: Hung-ying Tyan <tyanh@chromium.org> Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org> Signed-off-by: Randall Spangler <rspangler@chromium.org> Signed-off-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Vincent Palatin <vpalatin@chromium.org> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2013-06-24Merge branch 'master' of git://git.denx.de/u-boot-netTom Rini8-1/+28
2013-06-24net: add Faraday FTMAC110 10/100Mbps ethernet supportKuo-Jung Su1-0/+1
Faraday FTMAC110 10/100Mbps supports half-word data transfer for Linux. However it has a weird DMA alignment issue: (1) Tx DMA Buffer Address: 1 bytes aligned: Invalid 2 bytes aligned: O.K 4 bytes aligned: O.K (2) Rx DMA Buffer Address: 1 bytes aligned: Invalid 2 bytes aligned: O.K 4 bytes aligned: Invalid!!! Signed-off-by: Kuo-Jung Su <dantesu@faraday-tech.com> Cc: Joe Hershberger <joe.hershberger@gmail.com> Cc: Tom Rini <trini@ti.com>
2013-06-24net: phy: supplement support for Micrel's KSZ9031SARTRE Leo1-0/+11
Add function ksz9031_phy_extended_write and ksz9031_phy_extended_read Signed-off-by: Leo Sartre <lsartre@adeneo-embedded.com>
2013-06-24ARM: at91sam9n12: add network support with ksz8851_16mllBo Shen1-0/+4
add network support with ksz8851_16mll on at91sam9n12ek board Signed-off-by: Bo Shen <voice.shen@atmel.com> Acked-by: Andreas Bießmann <andreas.devel@googlemail.com>
2013-06-24net: ks8851_mll: add ethernet supportRoberto Cerati1-0/+1
The device interface is 16 bits wide. All the available packets are read from the incoming fifo. Signed-off-by: Roberto Cerati <roberto.cerati@bticino.it> Signed-off-by: Raffaele Recalcati <raffaele.recalcati@bticino.it> [voice.shen@atmel.com: address comments from review results] [voice.shen@atmel.com: clean up for submit] Signed-off-by: Bo Shen <voice.shen@atmel.com> Tested-by: Raffaele Recalcati <raffaele.recalcati@bticino.it>
2013-06-24add support for Xilinx 1000BASE-X phy (GTX)Charles Coldwell2-0/+6
commit 39695029bc15041c809df3db4ba19bd729c447fa Author: Charles Coldwell <coldwell@ll.mit.edu> Date: Tue Feb 19 08:27:33 2013 -0500 Changes to support the Xilinx 1000BASE-X phy (GTX/MGT) Signed-off-by: Charles Coldwell <coldwell@ll.mit.edu>
2013-06-24net: make IPaddr type big endianKim Phillips1-1/+1
for use with sparse. Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Cc: Joe Hershberger <joe.hershberger@gmail.com>
2013-06-24bootz: un-staticize do_bootzRob Herring1-0/+2
Make do_bootz available for other functions like do_bootm is. Signed-off-by: Rob Herring <rob.herring@calxeda.com>
2013-06-24phy: export genphy_parse_link()Yegor Yefremov1-0/+1
Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
2013-06-24net: Add sunxi (Allwinner) wemac driverHenrik Nordström1-0/+1
This patch adds support for the WEMAC, the ethernet controller included in the Allwinner A10 SoC. It will get used in the upcoming A10 board support. From: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Henrik Nordstrom <henrik@henriknordstrom.net>
2013-06-24Merge branch 'master' of git://git.denx.de/u-boot-mpc5xxxTom Rini1-17/+11
2013-06-24Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini1-0/+10
2013-06-24ac14xx: rephrase network boot config for developmentGerhard Sittig1-8/+9
- remove the builtin 'rootpath' spec (according to U-Boot project policy) and require user provided environments to contain these - rephrase the evaluation of the 'muster_nr' approach which allows to quickly switch among several network boot setups (make the setting transparent when empty, resulting in default DULG behaviour) - reduce the ARP timeout for faster network boot Signed-off-by: Gerhard Sittig <gsi@denx.de>
2013-06-24ac14xx: use the official product name everywhereGerhard Sittig1-5/+5
remove remaining "k6" code names, switch to the official 'ac14xx' name Signed-off-by: Gerhard Sittig <gsi@denx.de>
2013-06-24ac14xx: remove obsolete board config itemsGerhard Sittig1-6/+0
- use the default baudrate table for serial communication - remove hostname/boofile/rootpath defines which were not referenced elsewhere Signed-off-by: Gerhard Sittig <gsi@denx.de>
2013-06-24ac14xx: cleanup comments in the board supportGerhard Sittig1-3/+2
fix typos, minor rephrasing, remove obsolete notes and TODO items Signed-off-by: Gerhard Sittig <gsi@denx.de>
2013-06-23sf: Add flag status register polling supportJagannadha Sutradharudu Teki1-0/+3
Flag status register polling is required for micron 512Mb flash devices onwards, for performing erase/program operations. Like polling for WIP(Write-In-Progress) bit in read status register, spi_flash_cmd_wait_ready will poll for PEC(Program-Erase-Control) bit in flag status register. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2013-06-23sf: Add bank addr code in CONFIG_SPI_FLASH_BARJagannadha Sutradharudu Teki1-1/+2
Defined bank addr code on CONFIG_SPI_FLASH_BAR macro, to reduce the size for existing boards which has < 16Mbytes SPI flashes. It's upto user which has provision to use the bank addr code for flashes which has > 16Mbytes. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2013-06-23sf: Read flash bank addr register at probe timeJagannadha Sutradharudu Teki1-0/+2
Read the flash bank addr register to get the state of bank in a perticular flash. and also bank write happens only when there is a change in bank selection from user. bank read only valid for flashes which has > 16Mbytes those are opearted in 3-byte addr mode, each bank occupies 16Mytes. Suppose if the flash has 64Mbytes size consists of 4 banks like bank0, bank1, bank2 and bank3. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2013-06-23sf: Discover the bank addr commandsJagannadha Sutradharudu Teki1-0/+4
Bank/Extended addr commands are specific to particular flash vendor so discover them based on the idocode0. Assign the discovered bank commands to spi_flash members so-that the bank read/write will use their specific operations. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2013-06-22Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini14-17/+87
2013-06-21remove all references to .dynsymAlbert ARIBAUD1-3/+0
Discard all .dynsym sections from linker scripts Remove all __dynsym_start definitions from linker scripts Remove all __dynsym_start references from the codebase Note: this touches include/asm-generic/sections.h, which is not ARM-specific, but actual uses of __dynsym_start are only in ARM, so this patch can safely go through the ARM repository. Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net> Tested-by: Lubomir Popov <lpopov@mm-sol.com> Tested-by: Jeroen Hofstee <jeroen@myspectrum.nl> Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-06-20powerpc/85xx: Add P1023RDB board supportChunhe Lan1-0/+401
P1023RDB Specification: ----------------------- Memory subsystem: 512MB DDR3 (Fixed DDR on board) 64MB NOR flash 128MB NAND flash Ethernet: eTSEC1: Connected to Atheros AR8035 GETH PHY eTSEC2: Connected to Atheros AR8035 GETH PHY PCIe: Three mini-PCIe slots USB: Two USB2.0 Type A ports I2C: AT24C08 8K Board EEPROM (8 bit address) Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com> Cc: Scott Wood <scottwood@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-20common/Makefile: Add new symbol CONFIG_SPL_ENV_SUPPORT for environment in SPLYing Zhang3-0/+3
There will need the environment in SPL for reasons other than network support (in particular, hwconfig contains info for how to set up DDR). Add a new symbol CONFIG_SPL_ENV_SUPPORT to replace CONFIG_SPL_NET_SUPPORT for environment in common/Makefile. Signed-off-by: Ying Zhang <b40530@freescale.com> Reviewed-by: Tom Rini <trini@ti.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-20board/b4860qds: Relax NOR flash teadc timing parameterPrabhakar Kushwaha1-1/+1
Relax parameters to give address latching more time to setup. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-20powerpc/t4qds: Slave module for boot from SRIO and PCIELiu Gang1-7/+27
When a T4 board boots from SRIO or PCIE, it needs to finish these processes: 1. Set all the cores in holdoff status. 2. Set the boot location to one PCIE or SRIO interface by RCW. 3. Set a specific TLB entry for the boot process. 4. Set a LAW entry with the TargetID of one PCIE or SRIO for the boot. 5. Set a specific TLB entry in order to fetch ucode and ENV from master. 6. Set a LAW entry with the TargetID one of the PCIE ports for ucode and ENV. 7. Slave's u-boot image should be generated specifically by make xxxx_SRIO_PCIE_BOOT_config. This will set SYS_TEXT_BASE=0xFFF80000 and other configurations. For more information about the feature of Boot from SRIO/PCIE, please refer to the document doc/README.srio-pcie-boot-corenet. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-20powerpc/t4qds: Enable master module for Boot from SRIO and PCIELiu Gang1-0/+1
T4 can support the feature of Boot from SRIO/PCIE, and the macro "CONFIG_SRIO_PCIE_BOOT_MASTER" will enable the master module of this feature when building the u-boot image. You can get some description about this macro in README file, and for more information about the feature of Boot from SRIO/PCIE, please refer to the document doc/README.srio-pcie-boot-corenet. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-20powerpc/b4860qds: Slave module for boot from SRIO and PCIELiu Gang1-5/+27
When a b4860qds board boots from SRIO or PCIE, it needs to finish these processes: 1. Set all the cores in holdoff status. 2. Set the boot location to one PCIE or SRIO interface by RCW. 3. Set a specific TLB entry for the boot process. 4. Set a LAW entry with the TargetID of one PCIE or SRIO for the boot. 5. Set a specific TLB entry in order to fetch ucode and ENV from master. 6. Set a LAW entry with the TargetID one of the PCIE ports for ucode and ENV. 7. Slave's u-boot image should be generated specifically by make xxxx_SRIO_PCIE_BOOT_config. This will set SYS_TEXT_BASE=0xFFF80000 and other configurations. For more information about the feature of Boot from SRIO/PCIE, please refer to the document doc/README.srio-pcie-boot-corenet. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-20powerpc/b4860qds: Enable master module for boot from SRIO and PCIELiu Gang1-0/+1
B4860QDS can support the feature of Boot from SRIO/PCIE, and the macro "CONFIG_SRIO_PCIE_BOOT_MASTER" will enable the master module of this feature when building the u-boot image. You can get some description about this macro in README file, and for more information about the feature of Boot from SRIO/PCIE, please refer to the document doc/README.srio-pcie-boot-corenet. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-20powerpc/boot: Change the macro of Boot from SRIO and PCIE master moduleLiu Gang4-3/+4
Currently, the macro "CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER" can enable the master module of Boot from SRIO and PCIE on a platform. But this is not a silicon feature, it's just a specific booting mode based on the SRIO and PCIE interfaces. So it's inappropriate to put the macro into the file arch/powerpc/include/asm/config_mpc85xx.h. Change the macro "CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER" to "CONFIG_SRIO_PCIE_BOOT_MASTER", remove them from arch/powerpc/include/asm/config_mpc85xx.h file, and add those macros in configuration header file of each board which can support the master module of Boot from SRIO and PCIE. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-20board/bsc9131rdb: Update default boot environment settingsPriyanka Jain1-1/+3
BSC9131RDB has 1GB DDR. Out of this, only 880MB is passed on to Linux via bootm_size. Remaining -16MB is reserved for PowerPC-DSP shared control area -128MB is reserved for DSP private area. Also 256MB, out of this 880MB is required for data communication between PowerPC and DSP core. For this bootargs are modified to pass parameter to create 1 hugetlb page of 256MB via default_hugepagesz, hugepagesz and hugepages Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-20board/bsc9131rdb: Add DSP side tlb and lawsPriyanka Jain1-0/+5
BSC9131RDB is a Freescale Reference Design Board for BSC9131 SoC which is a integrated device that contains one powerpc e500v2 core and one DSP starcore. To support DSP starcore -Creating LAW and TLB for DSP-CCSR space. -Creating LAW for DSP-core subsystem M2 memory Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
generated by cgit v1.1 at 2024-07-15 22:53:02 +0000