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2020-10-20Merge https://gitlab.denx.de/u-boot/custodians/u-boot-shWIP/20Oct2020Tom Rini2-0/+86
- Assorted R-Car Gen3 updates
2020-10-20arm: dts: r8a774c0: Import DTS from Linux 5.9Lad Prabhakar2-0/+86
Import R8A774C0 (RZ/G2E) SoC DTSI and headers from Linux 5.9 commit bbf5c979011a ("Linux 5.9"). Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
2020-10-20usb: common: add define of usb_speed_string()Chunfeng Yun1-4/+0
There is only declaration of usb_speed_string(), but no definition, so add it to avoid build error when call it. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-10-20usb: add USB_SPEED_SUPER_PLUSChunfeng Yun1-0/+1
Add enum USB_SPEED_SUPER_PLUS for USB3.1 Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-10-19Merge tag 'u-boot-atmel-2021.01-b' of ↵Tom Rini1-1/+2
https://gitlab.denx.de/u-boot/custodians/u-boot-atmel Second set of u-boot-atmel features for 2021.01 cycle: This feature set brings the rework of the clock tree for sam9x60 SoC. This makes the clock tree fully compatible with Common Clock Framework and allows full clock configuration in U-Boot. This means that the sam9x60 boards can boot now using U-Boot. This also includes the definitions for sam9x60 SiPs and a divisor fix for the clock on sama7g5 SoC.
2020-10-19board: atmel: sam9x60ek: add SYS_MALLOC_F_LEN to SYS_INIT_SP_ADDRClaudiu Beznea1-1/+2
Heap base address is computed based on SYS_INIT_SP_ADDR by subtracting the SYS_MALLOC_F_LEN value in board_init_f_init_reserve(). Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-10-18configs: migrate CONFIG_BMP_16/24/32BPP to defconfigsPatrick Delaunay37-60/+0
Done with: ./tools/moveconfig.py BMP_16BPP BMP_24BPP BMP_32BPP Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-18configs: migrate CONFIG_VIDEO_BMP_RLE8 to defconfigsPatrick Delaunay35-36/+0
Done with: ./tools/moveconfig.py VIDEO_BMP_RLE8 Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-18configs: migrate CONFIG_VIDEO_BMP_GZIP to defconfigsPatrick Delaunay7-7/+0
Done with: ./tools/moveconfig.py VIDEO_BMP_GZIP The 3 suspicious migration because CMD_BMP and SPLASH_SCREEN are not activated in these defconfigs: - trats_defconfig - s5pc210_universal_defconfig - trats2_defconfig Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-18video: dw-mipi-dsi: permit configuring the escape clock rateNeil Armstrong1-0/+1
The Amlogic D-PHY in the Amlogic AXG SoC Family does support a frequency higher than 10MHz for the TX Escape Clock, thus make the target rate configurable. This is based on the Linux commit [1] and adapted to the U-Boot driver. [1] a328ca7e4af3 ("drm/bridge: dw-mipi-dsi: permit configuring the escape clock rate") Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2020-10-18video: dw-mipi-dsi: driver-specific configuration of phy timingsNeil Armstrong1-0/+16
The timing values for dw-dsi are often dependent on the used display and according to Philippe Cornu will most likely also depend on the used phy technology in the soc-specific implementation. To solve this and allow specific implementations to define them as needed add a new get_timing callback to phy_ops and call this from the dphy_timing function to retrieve the necessary values for the specific mode. This is based on the Linux commit [1] and adapted to the U-Boot driver. [1] 25ed8aeb9c39 ("drm/bridge/synopsys: dsi: driver-specific configuration of phy timings") Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2020-10-16dm: Don't undefine dev_xxx macrosSean Anderson1-20/+0
Now that linux/compat.h does not define these macros, we do not need to undefine them. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-16linux/compat.h: Remove redefinition of dev_xxx macrosSean Anderson1-28/+0
All users of these functions now include dm/device_compat.h directly. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-15Merge tag 'mmc-2020-10-14' of ↵Tom Rini3-8/+69
https://gitlab.denx.de/u-boot/custodians/u-boot-mmc - fsl_esdhc_imx cleanup - not send cm13 if send_status is 0. - Add reinit API - Add mmc HS400 for fsl_esdhc - Several cleanup for fsl_esdhc - Add ADMA2 for sdhci
2020-10-14Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvellTom Rini1-7/+0
- Octeon TX: Add NAND driver (Suneel) - Octeon TX: Add NIC driver driver (Suneel) - Octeon TX2: Add NIC driver driver (Suneel) - Armada 8040: Add iEi Puzzle-M80 board support (Luka) - Armada A37xx SPI: Add support for CS-GPIO (George) - Espressobin: Use Linux model/compatible strings (Andre) - Espressobin: Add armada-3720-espressobin-emmc.dts from Linux (Andre) - Armada A37xx: Small cleanup of config header (Pali)
2020-10-14global_data.h: add Sphinx documentationHeinrich Schuchardt1-55/+317
Add the missing Sphinx documentation for struct global_data and gd_board_type(). Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-14global_data.h: convert GD_FLG_* to enumHeinrich Schuchardt1-22/+84
Sphinx documentation is only available for enums not for #defines. Anyway it is better to keep related definitions in an enum. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-14bootm: add {arch,board}_preboot_os() to bootm.hHeinrich Schuchardt1-0/+10
Functions that are used in multiple C modules should be defined in an include. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Michael Walle <michael@walle.cc>
2020-10-14cmd: Fixup DT to pass PStore Ramoops parametersFrédéric Danis1-0/+3
To simplify configuration and keep synchronized the PStore/Ramoops between U-Boot and the Linux kernel, this commit dynamically adds the Ramoops parameters defined in the U-Boot session to the Device Tree. Signed-off-by: Frédéric Danis <frederic.danis@collabora.com> Cc: Tom Rini <trini@konsulko.com> Cc: Heinrich Schuchardt <xypron.glpk@gmx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Heiko Schocher <hs@denx.de>
2020-10-14mmc: fsl_esdhc: add ADMA2 supportMichael Walle1-0/+14
Newer eSDHC controllers support ADMA2 descriptor tables which support 64bit DMA addresses. One notable user of addresses in the upper memory segment is the EFI loader. If support is enabled, but the controller doesn't support ADMA2, we will fall back to SDMA (and thus 32 bit DMA addresses only). Signed-off-by: Michael Walle <michael@walle.cc>
2020-10-14arm: mvebu: Remove old comments from configs/mvebu_armada-37xx.h filePali Rohár1-7/+0
These comments are relict for old, now removed config options. So remove these obsoleted comments too. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
2020-10-12fit: cipher: aes: allow to store the IV in the FIT imagePhilippe Reynes2-3/+5
Binaries may be encrypted in a FIT image with AES. This algo needs a key and an IV (Initialization Vector). The IV is provided in a file (pointer by iv-name-hint in the ITS file) when building the ITB file. This commits adds provide an alternative way to manage the IV. If the property iv-name-hint is not provided in the ITS file, the tool mkimage will generate an random IV and store it in the FIT image. Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
2020-10-12Merge branch 'for-next' of https://github.com/lftan/u-bootTom Rini1-4/+5
2020-10-12Merge tag 'ti-v2021.01-rc1' of ↵Tom Rini3-12/+8
https://gitlab.denx.de/u-boot/custodians/u-boot-ti - Minor cleanup on K3 env variables - Fix OSPI compatible for J721e - Drop unused property in omap-usb2-phy - Update Maintainer for am335x-guardian board.
2020-10-12mmc: sdhci: move the ADMA2 table handling into own moduleMichael Walle1-3/+5
There are other (non-SDHCI) controllers which supports ADMA2 descriptor tables, namely the Freescale eSDHC. Instead of copying the code, move it into an own module. Signed-off-by: Michael Walle <michael@walle.cc>
2020-10-12mmc: fsl_esdhc: support eMMC HS400 modeYangbo Lu1-0/+12
The process for eMMC HS400 mode for eSDHC is, 1. Perform the Tuning Process at the HS400 target operating frequency. Latched the clock division value. 2. if read transaction, then set the SDTIMNGCTL[FLW_CTL_BG]. 3. Switch to High Speed mode and then set the card clock frequency to a value not greater than 52Mhz 4. Clear TBCTL[TB_EN],tuning block enable bit. 5. Change to 8 bit DDR Mode 6. Switch the card to HS400 mode. 7. Set TBCTL[TB_EN], tuning block enable bit. 8. Clear SYSCTL[SDCLKEN] 9. Wait for PRSSTAT[SDSTB] to be set 10. Change the clock division to latched value.Set TBCTL[HS 400 mode] and Set SDCLKCTL[CMD_CLK_CTRL] 11. Set SYSCTL[SDCLKEN] 12. Wait for PRSSTAT[SDSTB] to be set 13. Set DLLCFG0[DLL_ENABLE] and DLLCFG0[DLL_FREQ_SEL]. 14. Wait for delay chain to lock. 15. Set TBCTL[HS400_WNDW_ADJUST] 16. Again clear SYSCTL[SDCLKEN] 17. Wait for PRSSTAT[SDSTB] to be set 18. Set ESDHCCTL[FAF] 19. Wait for ESDHCCTL[FAF] to be cleared 20. Set SYSCTL[SDCLKEN] 21. Wait for PRSSTAT[SDSTB] to be set. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
2020-10-12mmc: add a mmc_hs400_prepare_ddr() interfaceYangbo Lu1-1/+14
Add a mmc_hs400_prepare_ddr() interface for controllers which needs preparation before switching to DDR mode for HS400 mode. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
2020-10-12mmc: add a hs400_tuning flagYangbo Lu1-0/+1
Some controllers may have difference between HS200 tuning and HS400 tuning, such as different registers setting, different procedure, or different errata. This patch is to add a hs400_tuning flag to identify the tuning for HS400 mode. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
2020-10-12mmc: fsl_esdhc: support tuning for eMMC HS200Yangbo Lu1-4/+13
Support tuning process for eMMC HS200 for eSDHC. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
2020-10-12mmc: add a reinit() APIYangbo Lu1-0/+10
For DM_MMC, the controller re-initialization is needed to clear old configuration for mmc rescan. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2020-10-12configs: am65x_evm: Use DEFAULT_LINUX_BOOT_ENV and remove overlayaddrNishanth Menon1-5/+3
Use DEFAULT_LINUX_BOOT_ENV to define the standard addresses used in rest of TI platforms as defined in ti_armv7_common.h This avoids the standard pitfalls we've had with kernel images and fdt addresses stomping on each other. As part of this process, redefine overlayaddr to be dtboaddr (defined in ti_armv7_common.h for this very purpose) and get rid of the definition of overlayaddr.. Signed-off-by: Nishanth Menon <nm@ti.com>
2020-10-12configs: j721e_evm: Get rid of overlayaddrNishanth Menon1-1/+0
Now that we dont have any further users of overlayaddr, get rid of it. Signed-off-by: Nishanth Menon <nm@ti.com>
2020-10-12env: ti: ufs: Use dtboaddr instead of overlayaddrNishanth Menon1-2/+2
Use dtboaddr to define the overlay address common to all TI platforms instead of creating a new overlayaddr for the purpose. Signed-off-by: Nishanth Menon <nm@ti.com>
2020-10-12configs: j721e_evm: Use DEFAULT_LINUX_BOOT_ENVNishanth Menon1-5/+4
Use DEFAULT_LINUX_BOOT_ENV to define the standard addresses used in rest of TI platforms as defined in ti_armv7_common.h This avoids the standard pitfalls we've had with kernel images and fdt addresses stomping on each other. As part of this process, redefine overlayaddr to be dtboaddr (defined in ti_armv7_common.h for this very purpose).. we will get rid of overlayaddr later in the series. Signed-off-by: Nishanth Menon <nm@ti.com>
2020-10-10net: Expose some errors generated in net_initSean Anderson1-1/+1
net_init does not always succeed, and there is no existing mechanism to discover errors. This patch allows callers of net_init (such as net_init) to handle errors. The root issue is that eth_get_dev can fail, but net_init_loop doesn't expose that. The ideal way to fix eth_get_dev would be to return an error with ERR_PTR, but there are a lot of callers, and all of them just check if it's NULL. Another approach would be to change the signature to something like int eth_get_dev(struct udevice **pdev) but that would require rewriting all of the many callers. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-10log: Add a way to enable/disable a log deviceSimon Glass1-0/+17
At present all log devices are enabled by default. Add a function to allow devices to be disabled or enabled at runtime. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-10-10log: Add a flag to enable log driversSimon Glass1-1/+10
At present there is no way to disable a log driver. But the syslog driver causes (attempted) network traffic in sandbox every time a log message is printed, which is often. Add a flag to enable a log driver. Adjust struct log_device to use a short for next_filter_num so that no more memory is used for devices. Also fix a missing line in the struct log_driver comment while here. To maintain compatibility, enable it for all drivers for now. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-10-10log: Allow LOG_DEBUG to always enable log outputSimon Glass1-4/+14
At present if CONFIG_LOG enabled, putting LOG_DEBUG at the top of a file (before log.h inclusion) causes _log() to be executed for every log() call, regardless of the build- or run-time logging level. However there is no guarantee that the log record will actually be displayed. If the current log level is lower than LOGL_DEBUG then it will not be. Add a way to signal that the log record should always be displayed and update log_passes_filters() to handle this. With the new behaviour, log_debug() will always log if LOG_DEBUG is enabled. Move log_test_syslog_nodebug() into its own file since it cannot be made to work where it is, with LOG_DEBUG defined. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-10-09fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM MailboxChee Hong Ang1-4/+5
Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-10-08qemu-arm: Remove need to specify flash banksAndre Przywara1-7/+1
Currently we hard-code the number and initial addresses of QEMU's flash banks, even though our code is perfectly able to gather the same information from the DTB provided by QEMU. This is especially annoying, since we have two slightly different U-Boot configurations ("bare-metal" vs. loaded via Arm Trusted Firmware), which need to be selected at build time. Drop the two hard coded alternatives, and use CONFIG_SYS_MAX_FLASH_BANKS_DETECT instead, which relies on the DTB to figure out the actual flash configuration at runtime. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2020-10-08pinctrl: Add support for Kendryte K210 FPIOASean Anderson1-0/+277
The Fully-Programmable Input/Output Array (FPIOA) device controls pin multiplexing on the K210. The FPIOA can remap any supported function to any multifunctional IO pin. It can also perform basic GPIO functions, such as reading the current value of a pin. However, GPIO functionality remains largely unimplemented (in favor of the dedicated GPIO peripherals). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-08test: pinmux: Add test for pin muxingSean Anderson1-0/+19
This extends the pinctrl-sandbox driver to support pin muxing, and adds a test for that behaviour. The test is done in C and not python (like the existing tests for the pinctrl uclass) because it needs to call pinctrl_select_state. Another option could be to add a command that invokes pinctrl_select_state and then test everything in test/py/tests/test_pinmux.py. The pinctrl-sandbox driver now mimics the way that many pinmux devices work. There are two groups of pins which are muxed together, as well as four pins which are muxed individually. I have tried to test all normal paths. However, very few error cases are explicitly checked for. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-08pinctrl: Reformat documentation in dm/pinctrl.hSean Anderson1-162/+339
This normalizes the documentation to conform to kernel-doc style [1]. It also moves the documentation for pinctrl_ops inline, and adds argument and return-value documentation. I have kept the usual function style for these comments. I could not find any existing examples of function documentation inside structs. [1] https://www.kernel.org/doc/html/latest/doc-guide/kernel-doc.html Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-08pinctrl: Add pinmux property support to pinctrl-genericSean Anderson1-8/+13
The pinmux property allows for smaller and more compact device trees, especially when there are many pins which need to be assigned individually. Instead of specifying an array of strings to be parsed as pins and a function property, the pinmux property contains an array of integers representing pinmux groups. A pinmux group consists of the pin identifier and mux settings represented as a single integer or an array of integers. Each individual pin controller driver specifies the exact format of a pinmux group. As specified in the Linux documentation, a pinmux group may be multiple integers long. However, no existing drivers use multi-integer pinmux groups, so I have chosen to omit this feature. This makes the implementation easier, since there is no need to allocate a buffer to do endian conversions. Support for the pinmux property is done differently than in Linux. As far as I can tell, inversion of control is used when implementing support for the pins and groups properties to avoid allocating. This results in some duplication of effort; every property in a config node is parsed once for each pin in that node. This is not such an overhead with pins and groups properties, since having multiple pins in one config node does not occur especially often. However, the semantics of the pinmux property make such a configuration much more appealing. A future patch could parse all config properties at once and store them in an array. This would make it easier to create drivers which do not function solely as callbacks from pinctrl-generic. This commit increases the size of the sandbox build by approximately 48 bytes. However, it also decreases the size of the K210 device tree by 2 KiB from the previous version of this series. The documentation has been updated from the last Linux commit before it was split off into yaml files. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-07Merge tag 'mips-pull-2020-10-07' of ↵Tom Rini1-2/+9
https://gitlab.denx.de/u-boot/custodians/u-boot-mips - mips: octeon: add support for DDR4 memory controller - mips: octeon: add support for DWC3 USB - mips: octeon: add support for booting Linux
2020-10-07mips: octeon: octeon_common.h: Increase CONFIG_SYS_BOOTM_LENStefan Roese1-0/+2
Increase CONFIG_SYS_BOOTM_LEN to 64MiB for Linux kernel booting. Signed-off-by: Stefan Roese <sr@denx.de>
2020-10-07mips: octeon: octeon_ebb7304: Add DDR4 supportStefan Roese1-3/+8
This patch adds the board specific configuration (struct) for the Octeon 3 EBB7304 EVK. This struct is ported from the 2013er Cavium / Marvell U-Boot repository. Also, the Octeon RAM driver is enabled in the board defconfig for its usage. Tested with one and two DIMMs on the EBB7304 EVK (8 & 16 GiB). Signed-off-by: Stefan Roese <sr@denx.de>
2020-10-06Merge tag 'dm-pull-6oct20' of git://git.denx.de/u-boot-dmTom Rini5-13/+66
bloblist enhancement for alignment Update ofnode/dev_read phandle function sandbox keyboard enhancements and fixes
2020-10-06dm: add cells_count parameter in *_count_phandle_with_argsPatrick Delaunay3-5/+10
The cell_count argument is required when cells_name is NULL. This patch adds this parameter in live tree API - of_count_phandle_with_args - ofnode_count_phandle_with_args - dev_count_phandle_with_args This parameter solves issue when these API is used to count the number of element of a cell without cell name. This parameter allow to force the size cell. For example: count = dev_count_phandle_with_args(dev, "array", NULL, 3); Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-06dm: update test on of_offset in ofnode_validPatrick Delaunay1-1/+1
Update the test for node.of_offset because an invalid offset is not always set to -1 because the return value of the libfdt functions are: + an error with a value < 0 + a valid offset with value >=0 For example, in ofnode_get_by_phandle() function, we have: node.of_offset = fdt_node_offset_by_phandle(gd->fdt_blob, phandle); and this function can return -FDT_ERR_BADPHANDLE (-6). Without this patch, the added test dm_test_ofnode_get_by_phandle failed. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
generated by cgit v1.1 at 2024-09-09 16:59:19 +0000