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2024-04-26Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-mmcWIP/26Apr2024Tom Rini6-25/+81
2024-04-26Merge tag 'u-boot-rockchip-20240426' of ↵Tom Rini9-35/+200
https://source.denx.de/u-boot/custodians/u-boot-rockchip Please pull the updates for rockchip platform: - dts sync for rk3308; - sdram: Support getting banks from TPL for rk3568 and rk3588; - dts and config clean and sync up for rk3568/rk3588; - Other misc fixes; CI: https://source.denx.de/u-boot/custodians/u-boot-rockchip/-/pipelines/20543
2024-04-26rockchip: io-domain: Add support for RK3328Jonas Karlman2-1/+39
Port the RK3328 part of the Rockchip IO-domain driver from linux. This differs from linux version in that pmu io iodomain bit is enabled in the write ops instead of in an init ops as in linux, this way we can avoid keeping a full state of all supply that have been configured. Enable by default on all RK3328 boards, skip rk3328-evb because this target is typically also used on miscellaneous boards and boxes not fully supported by U-Boot. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2024-04-26mmc: rockchip_sdhci: Fix 4 blocks PIO mode read limit for RK35xxJonas Karlman1-10/+16
The commit 2cc6cde647e2 ("mmc: rockchip_sdhci: Limit number of blocks read in a single command") introduced a limit of number of blocks to read to fix a Data End Bit Error on RK3568 and RK3588. This had a side affect of significant slowing down reading FIT from eMMC. After the commit 6de9d7b2f13c ("rockchip: rk35xx: Enable eMMC HS200 mode by default") the limit of number of blocks to read workaround is no longer necessary and at HS200+ a Data End Bit Error is no longer happening using PIO mode. Change this limitation to allow reading more than 4 blocks with a single CMD18 command in PIO mode at HS200+ speed, keep using the 4 blocks limitation when loadig FIT from eMMC at lower speed than HS200. Fixes: 2cc6cde647e2 ("mmc: rockchip_sdhci: Limit number of blocks read in a single command") Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Dragan Simic <dsimic@manjaro.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2024-04-26clk: rockchip: rk356x: Fix set rate of SCLK_SFC clockJonas Karlman1-20/+12
The SCLK_SFC can be set to a rate of 24, 50, 75, 100, 125 or 150 MHz. However, clk_set_rate() will fail unless one of those exact rates are used, and with newer and updated device tree files that contain spi-max-frequency values that does not exactly match these rates use of SPI flash may fail. Fix this by using the highest possible rate that exceeds or is equal to the requested rate. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2024-04-26clk: rockchip: rk3588: Add REF_CLK_USB3OTGx supportJonas Karlman1-0/+6
The REF_CLK_USB3OTGx clocks is used as reference clock for USB3 block. Add simple support to get rate of REF_CLK_USB3OTGx clocks to fix reference clock period configuration. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Quentin Schulz <quentin.schulz@theobroma-systems.com> Acked-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2024-04-26clk: rockchip: rk356x: Add CLK_USB3OTGx_REF supportJonas Karlman1-0/+4
The CLK_USB3OTGx_REF clocks is used as reference clock for USB3 block. Add simple support to get rate of CLK_USB3OTGx_REF clocks to fix reference clock period configuration. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Acked-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2024-04-26rockchip: rk3308: Move cru and grf include files to arch-rockchipJonas Karlman3-3/+3
Move cru_rk3308.h and grf_rk3308.h to arch-rockchip to match path used for all other Rockchip SoCs. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2024-04-26rockchip: rk3308: Sync device tree from linux v6.8Jonas Karlman1-1/+1
Sync device tree from linux v6.8 and rename the rockchip,rk3308-mac compatible in gmac_rockchip driver to match upstream linux. Also move rk3308-roc-cc gmac node to u-boot.dtsi to not break features not enabled in upstream device tree. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2024-04-26phy: rockchip-inno-usb2: Add support for RK3308Jonas Karlman1-0/+20
Add clkout_ctl and phy_sus regs to support USB2PHY for RK3308. Based on linux commit 31f840e7ff3e ("phy: phy-rockchip-inno-usb2: add support for RK3308 USB phy"). Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2024-04-26clk: rockchip: rk3308: Add dummy support for USB480M clockJonas Karlman1-0/+4
Add dummy support for setting parent of USB480M clock. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2024-04-26clk: rockchip: rk3308: Add support for SCLK_RTC32K clockFinley Xiao1-0/+95
Add support to get and set the SCLK_RTC32K clock rate. Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com> [jonas@kwiboo.se: Update commit message] Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2024-04-26mmc: arm_pl180: Limit data transfer to U16_MAXMaximilian Brune1-0/+10
Currently fetching files bigger that cause a data transfer greater than U16_MAX fails. The reason is that the specification defines the datalength register as a 16 bit wide register, but in u-boot it is used as if it is an 32 bit register. Therefore values greater than U16_MAX cause an infinite loop inside u-boot. U-boot expects to get more data from interface/hardware then it will ever get and therefore inifintely waits for more data that will never come. Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2024-04-26mmc: sdhci: programmable clock calculation needs multiplier +1cmachida1-0/+9
According to the SD Host Controller Simplified Specification v4.20, the multiplier value M is one more than the Clock Multiplier field. Copied code from Linux project. drivers/mmc/host/sdhci.c line 4405 Signed-off-by: cmachida <curtis.machida@intel.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Sean Anderson <sean.anderson@seco.com>
2024-04-26mmc: Add support for the no-mmc-hs400 propJonas Karlman1-0/+3
The linux commit f722e650d965 ("mmc: core: add support for disabling HS400 mode via DT") added support for a no-mmc-hs400 prop. Add support for the no-mmc-hs400 prop to disable HS400 host caps. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Dragan Simic <dsimic@manjaro.org> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2024-04-26mmc: Imply HS200 cap with mmc-hs400 prop to match linuxJonas Karlman1-2/+2
eMMC nodes in linux device tree files typically only contain a mmc-hs400 prop to signal support for both HS400 and HS200. However, U-Boot require an explicit mmc-hs200 prop to signal support for the HS200 mode. Fix this by follow linux and imply HS200 cap when HS400 cap is signaled using a mmc-hs400 prop. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Dragan Simic <dsimic@manjaro.org> Reviewed-by: Quentin Schulz <quentin.schulz@theobrma-systems.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2024-04-26mmc: Support 32-bit only ADMA on 64-bit platformsGreg Malysa3-6/+23
Some arm64 platforms may include SDIO host controllers that only support 32-bit ADMA. While the Linux kernel detects which size is supported and adjusts the descriptor size used dynamically, the previous u-boot implementation statically selected between the two depending on whether DMA_ADDR_T_64BIT was defined. Because the static selection is already in place and effective for most platforms, this patch logically separates "64 bit addresses are used for DMA on this platform" and "64 bit addresses are used by the SDIO host controller for ADMA" in order to support the small number of platforms where these statements are not equivalent. Using 32 bits is opt-in and existing 64 bit platforms should be unaffected by this change. Co-developed-by: Nathan Barrett-Morrison <nathan.morrison@timesys.com> Signed-off-by: Nathan Barrett-Morrison <nathan.morrison@timesys.com> Co-developed-by: Ian Roberts <ian.roberts@timesys.com> Signed-off-by: Ian Roberts <ian.roberts@timesys.com> Signed-off-by: Greg Malysa <greg.malysa@timesys.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2024-04-26mmc: sdhci: introduce adma_write_desc() hook to struct sdhci_opsIan Roberts3-17/+34
Add this hook so that it can be overridden with driver specific implementations. We also let the original sdhci_adma_write_desc() accept &desc so that the function can set its new value. Then export the function so that it could be reused by driver's specific implementations. The above is a port of Linux kernel commit 54552e4948cbf In addition, allow drivers to allocate their own ADMA descriptor tables if additional space is required. Finally, fix the assignment of adma_addr to fix compiler warning on 64-bit platforms that still use 32-bit DMA addressing. Co-developed-by: Nathan Barrett-Morrison <nathan.morrison@timesys.com> Signed-off-by: Nathan Barrett-Morrison <nathan.morrison@timesys.com> Co-developed-by: Greg Malysa <greg.malysa@timesys.com> Signed-off-by: Greg Malysa <greg.malysa@timesys.com> Signed-off-by: Ian Roberts <ian.roberts@timesys.com>
2024-04-26tee: sandbox: check for buffer sizeIgor Opaniuk1-3/+7
Add additional check for buffer size when reading out persistent storage value and provide back actual value size. Signed-off-by: Igor Opaniuk <igor.opaniuk@gmail.com> Reviewed-by: Oleksandr Suvorov <cryosay@gmail.com> Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2024-04-23Merge https://source.denx.de/u-boot/custodians/u-boot-snapdragonTom Rini36-150/+3601
Support is added for 5 new Qualcomm SoCs: * QCM2290 and SM6115 are low and mid range SoCs used on the RB1 and RB2 respectively. SM6115 is also used in some mid-range smartphones/tablets. Initial support includes buttons and USB (host and gadget). * SM8250 is a flagship SoC from 2020 used on the RB5, as well as many flagship smartphones. The board can boot to a U-Boot prompt, but is missing regulators necessary for USB support. * SM8550, and SM8650 are flagship mobile SoCs from 2023 and 2024 respectively. Found on many high end smartphones. In addition: * Support is added for the Schneider HMIBSC board. * mach-snapdragon switches to OF_UPSTREAM * IPQ40xx gets several regressions fixed and some overall cleanup. * The MSM serial driver gains the ability to generate the bit-clock automatically, no longer relying on a custom DT property. * The Qualcomm SMMU driver gets a generic compatible (so per-SoC compatibles don't need to be added). * Support for the GENI I2C controller is added. * The qcom SPMI driver has SPMI v5 support fixed, and v7 support added. * The qcom sdhci driver gets some fixes for SDCC v5 support. * SDM845 gains sdcard support * Support is added for the Synopsys eUSB2 PHY driver (used on SM8550 and SM8650) * SYS_INIT_SP_BSS_OFFSET is set to 1.5M to give us more space for FDTs. * RB2 gets a work-around to fix the USB dr_mode property before booting Linux.
2024-04-23i2c: Add support for Qualcomm Generic Interface (GENI) I2C controllerNeil Armstrong3-0/+586
Add Support for the Qualcomm Generic Interface (GENI) I2C interface found on newer Qualcomm SoCs. The Generic Interface (GENI) is a firmware based Qualcomm Universal Peripherals (QUP) Serial Engine (SE) Wrapper which can support multiple bus protocols depending on the firmware type loaded at early boot time based on system configuration. It also supports the "I2C Master Hub" which is a single function Wrapper that only FIFO mode I2C. It replaces the fixed-function QUP Wrapper found on older SoCs. The geni-se.h containing the generic GENI Serial Engine registers defines is imported from Linux. Only FIFO mode is implemented, neither SE DMA nor GPI DMA are implemented. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23phy: qcom: snps-femto-v2: drop clocksCaleb Connolly1-14/+0
There is a clock associated with this phy, but it's always from the rpmhcc and isn't actually needed for the hardware to work. Drop all the clock handling from the driver. Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23iommu: qcom-smmu: add qcom generic compatibleCaleb Connolly1-0/+1
With the exception of SDM845, most other Qualcomm SoCs have the Qualcomm specific (but not SoC) specific SMMU compatible string. Add it here so we can match those without having to add individual SoCs to the list here. Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23gpio: qcom_pmic: add pm8150lCaleb Connolly1-0/+1
This is used for the volume keys on some SM8150/SM8250 devices. Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23gpio: qcom_pmic: add pm6125Caleb Connolly1-0/+1
As with some other modern PMICs, writing to the GPIOs seems to make the device reset. Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23spmi: msm: support controller version 7Neil Armstrong1-4/+29
Add the defines and support for SPMI arbiters version 7, which can handle up to 1024 peripherals, and can also drive a secondary bus which is not implemented yet. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Acked-by: Caleb Connolly <caleb.connolly@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23spmi: msm: handle peripheral ownershipNeil Armstrong1-4/+29
The cnfg registers provides the owner id for each peripheral, so we can use this id to check if we're allowed to write register to each peripherals. Since the v5 can handle more peripherals, add the max_channels to scan more starting from version 5, make the channel_map store 32bit values and introduce the SPMI_CHANNEL_READ_ONLY flag to mark a peripheral as read-only. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Acked-by: Caleb Connolly <caleb.connolly@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23spmi: msm: properly format commandNeil Armstrong1-20/+55
Since version 2, the cmd format has changed, takes helpers from Linux driver and use a switch/case to handle all versions in msm_spmi_write/read() command. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Acked-by: Caleb Connolly <caleb.connolly@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23spmi: msm: fix version 5 supportNeil Armstrong1-10/+9
Properly use ch_offset in msm_spmi_write() reg access. Fixes: f5a2d6b4b03 ("spmi: msm: add arbiter version 5 support") Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Acked-by: Caleb Connolly <caleb.connolly@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23pinctrl: qcom: apq8016: Add GPIO pinctrl functionSumit Garg1-0/+1
Add GPIO pinctrl function to enable driving GPIO pins as output low or high. Signed-off-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23pinctrl: qcom: Add support for driving GPIO pins outputSumit Garg1-5/+20
Add support for driving the GPIO pins as output low or high. Signed-off-by: Sumit Garg <sumit.garg@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23serial_msm: Enable RS232 flow controlSumit Garg1-4/+6
SE HMIBSC board debug console requires RS232 flow control, so enable corresponding support if RS232 gpios are present. Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Signed-off-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23apq8016: Add support for UART1 clocks and pinmuxSumit Garg3-14/+35
SE HMIBSC board uses UART1 as the main debug console, so add corresponding clocks and pinmux support. Along with that update instructions to enable clocks for debug UART support. Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Signed-off-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23pinctrl: qcom: ipq4019: support all pin functionsRobert Marko1-13/+293
Currently, IPQ4019 pinctrl driver supports only a very limited number of pin functions and is not fully DT compatible with Linux pinctrl nodes. IPQ40xx SoC-s sometimes use different pin function numbers for the same function depending on the pin number, so for example I2C0 on GPIO58 uses function number 3 while on GPIO59 it uses function number 2. So, in order to make the driver compatible with upstream DTS to avoid the need to patch the pinctrl nodes in U-Boot and support all of the missing pin functions lets rework the driver based on upstream Linux IPQ4019 pinctrl driver and the pending SM8150 U-Boot pinctrl driver which also uses different function numbers pased on the exact pin number. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23pinctrl: qcom: ipq4019: enable DM_FLAG_PRE_RELOCRobert Marko1-0/+1
If compiled with logging and debug UART support, the following is printed: serial_msm serial@78af000: pinctrl_select_state_full: uclass_get_device_by_phandle_id: err=-19 This is due to the fact that IPQ4019 pinctrl driver is not available prior to relocation and thus MSM serial will fail probing as pinctrl provider is not available. So, lets enable DM_FLAG_PRE_RELOC for IPQ4019 pinctrl to fix this. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23pinctrl: qcom: ipq4019: adapt pin name lookup to upstream DTSRobert Marko1-1/+1
We want to use OF_UPSTREAM on IPQ40XX as its well supported upstream, so as a preparation update pinctrl driver to look for the upstream pin format. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23pinctrl: qcom: allow selecting with ARCH_IPQ40XXRobert Marko1-1/+1
IPQ4019 pinctrl driver was moved to the dedicated Qualcomm pinctrl directory, but the KConfig depends on ARCH_SNAPDRAGON only and thus PINCTRL_QCOM_IPQ4019 cannot be selected when ARCH_IPQ40XX is used. Fixes: 24d2908e987a ("pinctrl: qcom: move ipq4019 driver from mach-ipq40xx") Signed-off-by: Robert Marko <robert.marko@sartura.hr> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23serial: msm: calculate bit clock dividerCaleb Connolly1-17/+70
The driver currently requires the bit clock divider be hardcoded in devicetree (or use the hardcoded default from apq8016). The bit clock divider is used to derive the baud rate from the core clock: baudrate = clk_rate / csr_div clk_rate is the actual programmed core clock rate which is returned by clk_set_rate(), and this UART driver only supports a baudrate of 115200. We can therefore determine the appropriate value for UARTDM_CSR by iterating over the possible values and finding the one where the equation above holds true for a baudrate of 115200. Implement this logic and drop the non-standard DT bindings for this driver. Tested on dragonboard410c. Tested-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23clk/qcom: ipq4019: return valid rate when setting UART clockCaleb Connolly1-1/+1
clk_set_rate() should return the clock rate that was set. The IPQ4019 clock driver doesn't set any rates yet but it should still return the expected value so that drivers can work properly. For a baud rate of 115200 with an expected bit clock divisor of 16, the clock rate should be 1843200 so return that frequency. Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23clk/qcom: apq8016: return valid rate when setting UART clockCaleb Connolly1-2/+2
The clk_init_uart() helper always returns 0, but we're meant to return a real clock rate. Given that we hardcode 115200 baud, just return the clock rate that we set. Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23serial: msm_serial: remove .clk_rate from debug UARTRobert Marko1-1/+0
MSM serial in DEBUG UART mode is trying to set .clk_rate, but the msm_serial_data structure does not have such property at all, so lets remove it as otherwise it will fail compiling. Fixes: 90023bdfe979 ("serial: msm: add debug UART") Signed-off-by: Robert Marko <robert.marko@sartura.hr> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23serial: allow selecting MSM debug UART with ARCH_IPQ40XXRobert Marko1-1/+1
Currently, DEBUG_UART_MSM depends on ARCH_SNAPDRAGON only, but IPQ40XX devices also use the same UART HW so they can also use the debug UART. So, allow selecting DEBUG_UART_MSM when using ARCH_IPQ40XX as well. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23mmc: msm_sdhci: fix vendor_spec_cap0 registersCaleb Connolly1-2/+2
The addresses were mistakenly swapped. Put them right. Reported-by: Sumit Garg <sumit.garg@linaro.org> Fixes: a737d8962cae ("mmc: msm_sdhci: correct vendor_spec_cap0 register for v5") Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23clk: qcom: Add SM8650 clock driverNeil Armstrong3-0/+341
Add the GCC and TCSRCC clock driver for the SM8650 SoC. The GCC driver uses the clk-qcom infrastructure to support GDSCs, Resets and gates. While the TCSRCC is a simpler clock driver which only supports gates. The GCC enable and set_rate callbacks contains some tweaks to setup clocks for Debug UART, SDCard controller and USB. The TCSRCC gates returns the XO frequency, which is used by the Synopsys eUSB2 driver to determine the PHY configuration. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23clk: qcom: Add SM8550 clock driverNeil Armstrong3-0/+343
Add the GCC and TCSRCC clock driver for the SM8550 SoC. The GCC driver uses the clk-qcom infrastructure to support GDSCs, Resets and gates. While the TCSRCC is a simpler clock driver which only supports gates. The GCC enable and set_rate callbacks contains some tweaks to setup clocks for Debug UART, SDCard controller and USB. The TCSRCC gates returns the XO frequency, which is used by the Synopsys eUSB2 driver to determine the PHY configuration. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23pinctrl: qcom: sdm845: add special pin namesCaleb Connolly1-1/+12
Adjust sdm845_get_pin_name() to return the correct names for the special pins. This fixes a non-fatal -ENOSYS error when probing MMC. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23clk/qcom: sdm845: enable SDCC2 core clockCaleb Connolly2-0/+18
Allow setting the clock rate for the SD card core clock. This is required for SD card support on SDM845 devices. Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23mmc: msm_sdhci: use a more sensible default clock rateCaleb Connolly1-1/+1
We currently default to the lowest rate but this actually doesn't work on most platforms. Default to the HS400 speed instead which is most common on Qualcomm platforms. Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23mmc: msm_sdhci: print core versionCaleb Connolly1-0/+2
This is useful for debugging. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23mmc: msm_sdhci: use modern DT handlingCaleb Connolly1-9/+19
using fdtdec_* functions is incompatible with OF_LIVE and generally offers a less friendly interface. Update to use dev_read_* functions instead. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
generated by cgit v1.1 at 2024-10-13 18:02:57 +0000