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2021-02-10generic-phy: add configure opNeil Armstrong1-0/+11
Add the PHY configure op callback to the generic PHY uclass to permit configuring the PHY. It's useful for MIPI DSI PHYs to setup the link timings. Signed-off-by:Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2021-02-10phy: dphy: Add configuration helpersNeil Armstrong3-0/+167
The MIPI D-PHY spec defines default values and boundaries for most of the parameters it defines. Introduce helpers to help drivers get meaningful values based on their current parameters, and validate the boundaries of these parameters if needed. These helpers and header are taken from Linux commit 9123e3a74ec7 ("Linux 5.9-rc1"). Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2021-02-08Merge git://git.denx.de/u-boot-marvellWIP/08Feb2021Tom Rini2-39/+31
- Espressobin: Set default env values at runtime (Pali) - Espressobin: Set the maximum slave SPI speed to 40MHz (Pali) - theadorable: PCIe test code enhancement and early deemphasis enabling (Stefan) - pci_mvebu: Disable config access to PCI host bridge ports (Stefan) - mv_sdhci: parse device-tree entry (Baruch)
2021-02-08Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini8-84/+89
Layerscape: Enable gpio Bug fixes & updates related to dspi, qspi, pciep, SVR mask, stream-id, env variables, mdio for LAyerscape Platforms Add SATA, network variant 1, 2 support on sl28 powerpc: T1042: drop CONFIG_VIDEO, Add kmcent2 board supporrt, keymile Bug fixes and updates for keymile, Kontron
2021-02-08gpio: mpc8xxx_gpio: Fix for litte endianBiwen Li1-39/+8
Update gpio driver to use same logic for big-endian and little-endian Signed-off-by: Biwen Li <biwen.li@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-02-08pci: kconfig: layerscape: Change LX2162A PCIe node compatible stringHou Zhiqiang1-2/+3
LX2162A is not like LX2160A which has different PCIe controller in rev1 and rev2 silicon. It supports only one configuration of PCIe controller, which is same as LS2088A. So update PCIe compatible string same as LS2088A. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Wasim Khan <wasim.khan@nxp.com> Tested-by: Wasim Khan <wasim.khan@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-02-08pci: layerscape: Remove the shadow SVR definitionsHou Zhiqiang1-10/+2
This patch moves the SVR definitions to a new svr.h for Layerscape armv7 and armv8 platforms respectively, so that the PCIe driver can reuse them. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Wasim Khan <wasim.khan@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-02-08spi: fsl_qspi: apply the same settings for LS1088 as LS208xMathew McBride1-9/+1
The LS1088 requires the same QUADSPI_QURIK_BASE_INTERNAL workaround as the LS208x and also has a 64 byte TX buffer. With the previous settings SPI-NAND reads over AHB were corrupted. Fixes: 91afd36f3802 ("spi: Transform the FSL QuadSPI driver to use the SPI MEM API") Signed-off-by: Mathew McBride <matt@traverse.com.au> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-02-08spi: fsl_qspi: Ensure width is respected in spi-mem operationsMathew McBride1-1/+1
Adapted from kernel commit b0177aca7aea From: Michael Walle <michael@walle.cc> Make use of a core helper to ensure the desired width is respected when calling spi-mem operators. Otherwise only the SPI controller will be matched with the flash chip, which might lead to wrong widths. Also consider the width specified by the user in the device tree. Fixes: 91afd36f38 ("spi: Add a driver for the Freescale/NXP QuadSPI controller") Signed-off-by: Michael Walle <michael@walle.cc> Link: https://lore.kernel.org/r/20200114154613.8195-1-michael@walle.cc Signed-off-by: Mark Brown <broonie@kernel.org> Signed-off-by: Mathew McBride <matt@traverse.com.au> [adapt for U-Boot] Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-02-08net: eqos: Reduce the MDIO wait timeYe Li1-1/+1
Current MDIO wait time is too long, which introduce long delay when PHY negotiation register checking. Reduce it to 10us Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Fugang Duan <Fugang.duan@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-02-08net: memac_phy: add a timeout to MDIO operationsIoana Ciornei1-18/+58
We have encountered circumstances when a board design does not include pull-up resistors on the external MDIO buses which are not used. This leads to the MDIO data line not being pulled-up, thus the MDIO controller will always see the line as busy. Without a timeout in the MDIO bus driver, the execution is stuck in an infinite loop when any access is initiated on that external bus. Add a timeout in the driver so that we are protected in this circumstance. This is similar to what is being done in the Linux xgmac_mdio driver. Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> Reviewed-by: Madalin Bucur <madalin.bucur@oss.nxp.com> [Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-02-08mtd: spi-nor: add unlock all config optionMichael Walle2-4/+15
Provide an explicit configuration option to disable default "unlock all" of any flash chip which supports locking. It doesn't make sense to automatically unprotect the entire flash on each u-boot startup if the block protection bits are actually used. Traditionally, the unlock was there to be able to write to flash devices which powered-up with the block protection bits set. Over time this feature creeped into all flash devices which support locking. For a more detailed description and discussion see: https://lore.kernel.org/linux-mtd/20201203162959.29589-8-michael@walle.cc/ Keep things simple in u-boot and just provide a configration option to disable this behavior which can be set per board. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-02-08mmc: mv_sdhci: parse device-tree entryBaruch Siach1-0/+4
Call mmc_of_parse() so that generic DT properties like 'non-removable' are taken into account. This fixes boot on Clearfog with eMMC on SOM that requires the non-removable property. Reported-by: Thorsten Spille <thorsten_spille@netcor.de> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Marek Behún <marek.behun@nic.cz>
2021-02-08pci: pci_mvebu: Disable config access to PCI host bridge portsStefan Roese1-39/+27
This patch changes the PCI config routines in the Armada XP / 38x driver to not allow access to the PCIe root ports. While updating the Armada XP based theadorable to the latest mainline and testing it with the DM PCI driver I noticed, that the PCI root bridge was being configured incorrectly. Resulting in the PCIe Intel WiFi was not working correctly in Linux. With this patch applied, all PCIe devices work without any issues in Linux again. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Marek Behún <marek.behun@nic.cz> Cc: Phil Sutter <phil@nwl.cc> Cc: Mario Six <mario.six@gdsys.cc>
2021-02-07fastboot: reinit partition after storing GPT or MBRRoman Stratiienko1-0/+2
In case MMC has MBR system and fastboot writes GPT, MMC is still recognized as MBR. Invoke part_init() to purge cached data and update information about partition table type. Signed-off-by: Roman Stratiienko <r.stratiienko@gmail.com>
2021-02-07fastboot: add command to select the eMMC boot configurationPatrick Delaunay2-0/+43
Add command oem bootbus which executes the command ``mmc bootbus <id> <arg>`` on the current fastboot mmc device (<i> = CONFIG_FASTBOOT_FLASH_MMC_DEV) to set the eMMC boot configuration on first update, with <arg> = boot_bus_width reset_boot_bus_width boot_mode $> fastboot oem bootbus:<boot_bus_width> <reset_boot_bus_width> <boot_mode> Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-02-07fastboot: add command to select the default emmc hwpart for bootPatrick Delaunay2-0/+43
Add fastboot command oem partconf which executes the command ``mmc partconf <id> <arg> 0`` on the current <id> mmc device to configure the eMMC boot partition with <arg>: boot_ack boot_partition, so the command is: $> fastboot oem partconf:<boot_ack> <boot_partition> The partition_access argument is forced to 0 (userdata) Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> [lukma - Kconfig adjustments after merging this patch]
2021-02-07fastboot: mmc: extend flash/erase for both emmc hwpart 1 and 2Patrick Delaunay2-24/+49
Update the code and the configs for eMMC boot and userdata partitions acces - FASTBOOT_MMC_BOOT_SUPPORT: boot partition 1 and 2 (erase/write) - FASTBOOT_MMC_BOOT1_NAME: boot partition 1, default name="mmc0boot0" - FASTBOOT_MMC_BOOT2_NAME: boot partition 2, default name="mmc0boot1" This patch also removes the unnecessary dependency with ARCH_MEDIATEK and EFI_PARTITION. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-02-07fastboot: mmc: Add CONFIG_FASTBOOT_MMC_USER_SUPPORTPatrick Delaunay2-8/+23
Split userdata and boot partition support for eMMC update and correct the description (update is supported). The new configuration CONFIG_FASTBOOT_MMC_USER_SUPPORT allows to activate support of userdata partition update, based on target name=CONFIG_FASTBOOT_MMC_USER_NAME This patch also removes the unnecessary dependency with ARCH_MEDIATEK and EFI_PARTITION. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-02-07fastboot: Implement generic fastboot_set_reboot_flagRoman Kovalivskyi1-1/+15
It is possible to implement fastboot_set_reboot_flag in a generic way if BCB commands are turned on for a target. Using bcb_set_reboot_reason allows to do this by simply passing string with correct reboot reason that should be handled during next boot process. If BCB are turned off, then bcb_set_reboot_reason would simply return error, so it won't introduce any new behaviour for such targets. Signed-off-by: Roman Kovalivskyi <roman.kovalivskyi@globallogic.com>
2021-02-07Revert "fastboot: Add default fastboot_set_reboot_flag implementation"Roman Kovalivskyi3-56/+0
This reverts commit 0ebf9842e56c5b8cb7cb1f990bb452cc14af6225. Current generic implementation of fastboot_set_reboot_flag is somewhat messy and requires some additional configuration option to be enabled besides CMD_BCB, so it reverts that implementtion in order to bring a new cleaner one. Next commit introduces new generic implementation of fastboot_set_reboot_flag. Signed-off-by: Roman Kovalivskyi <roman.kovalivskyi@globallogic.com>
2021-02-07dfu: dfu_sf: use correct print codeHeinrich Schuchardt1-1/+1
For printing unsigned int %u has to be used. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2021-02-05Merge tag 'ti-v2021.04-rc2' of ↵WIP/05Feb2021Tom Rini4-112/+376
https://gitlab.denx.de/u-boot/custodians/u-boot-ti - Sync DTS from Linux kernel for all K3 platforms - Add MMC higher speed nodes for AM65x, J721e, J7200 - Convert Nokia RX-51 to use CONFIG_DM_MMC - Minor fixes for LEGO MINDSTORMS
2021-02-04mmc: am654_sdhci: Use sdhci_set_control_reg()Faiz Abbas1-16/+2
Use the generic sdhci_set_control_reg() instead of duplicating in platform driver. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-02-04mmc: am654_sdhci: Fix HISPD bit configuration in some lower speed modesFaiz Abbas2-2/+24
According to the AM654x Data Manual[1], the setup timing in lower speed modes can only be met if the controller uses a falling edge data launch. To ensure this, the HIGH_SPEED_ENA (HOST_CONTROL[2]) bit should be cleared in default speed, SD high speed, MMC high speed, SDR12 and SDR25 speed modes. Use the sdhci writeb callback to implement this condition. [1] http://www.ti.com/lit/gpn/am6546 Section 5.10.5.16.1 Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-02-04mmc: am654_sdhci: Add support for software tuningFaiz Abbas1-0/+45
With the new SW tuning App note[1], a custom tuning algorithm is required for eMMC HS200, HS400 and SD card UHS modes. The algorithm involves running through the 32 possible input tap delay values and sending the appropriate tuning command (CMD19/21) for each of them to get a fail or pass result for each of the values. Typically, the range will have a small contiguous failing window. Considering the tuning range as a circular buffer, the algorithm then sets a final tuned value directly opposite to the failing window. [1] https://www.ti.com/lit/pdf/spract9 Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-02-04mmc: am654_sdhci: Add support for writing to clkbuf_selFaiz Abbas1-0/+11
Add support for writing new clock buffer select property for both the am654x and j721e 4 bit IPs Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-02-04mmc: am654_sdhci: Add support for input tap delayFaiz Abbas1-80/+161
DLL need only be enabled for speed modes and clock frequencies at or above 50 MHz. For speed modes that don't enable the DLL, we need to configure a static input delay value. This involves reading an optional itap-del-sel-* value from the device tree and configuring it for the appropriate speed mode. Therefore, move all dll configurations to their own functions and gate it with 50 MHz speed and a minimum mode. If both these conditions are not satisfied then configure delay chain modes. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-02-04mmc: am654_sdhci: Add support for AM65x SR2.0Faiz Abbas1-0/+30
Add Support for AM65x PG2.0. Use the SoC bus framework to fixup the platform data and do DLL calibration if the revision is 1.0 Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-02-04mmc: am654_sdhci: Add flag for PHY calibrationFaiz Abbas1-12/+14
Not all controllers need calibration for the PHY DLL. Add a DLL_CALIB flag to indicate the same. Also move the write of trm_icp and driver strength to the set_clock() function to match the kernel configuration flow. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-02-04mmc: am654_sdhci: Convert flag fields to BIT macroFaiz Abbas1-4/+4
Convert the flags field defines to use the BIT() macro. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-02-04mmc: am654_sdhci: Unconditionally switch off DLL in the beginning of ios_post()Faiz Abbas1-9/+1
There are some speed modes that work without switching the dll on. Unconditionally switch off the DLL before setting clock frequency to support this case. The software will automatically enable DLL for speed modes that require it. This also means the dll_on priv data member is no longer required. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-02-04mmc: sdhci: Add helper functions for UHS modesFaiz Abbas1-0/+95
Add a set_voltage() function which handles the switch from 3.3V to 1.8V for SD card UHS modes. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-02-04remoteproc: k3_r5: Sync to upstreamed kernel DT property namesSuman Anna1-4/+4
The K3 R5F remoteproc driver in U-Boot was upstreamed prior to the equivalent remoteproc driver in the Linux kernel. Some of the DT properties used in U-Boot got upstreamed using different names in Linux kernel. The modified property names include the R5F cluster mode configuration property "lockstep-mode"; and three different individual R5F core config properties - "atcm-enable", "btcm-enable" and "loczrama". The property names were updated as follows: lockstep-mode => ti,cluster-mode atcm-enable => ti,atcm-enable btcm-enable => ti,btcm-enable loczrama => ti,loczrama Update the K3 R5F remoteproc driver, the corresponding binding, and all the existing usage in AM65x, J721E and J7200 dts files all at once to use the new properties and to not break any bisectability. Signed-off-by: Suman Anna <s-anna@ti.com>
2021-02-03firmware: smci: possible NULL dereferenceHeinrich Schuchardt1-0/+3
sandbox_scmi_devices_ctx() may return NULL. We should not dereference this value in sandbox_scmi_devices_remove(). The problem was indicated by 'gcc-11 -fanalyzer'. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-02-03net: ftmac100: Cast priv->iobase with uintptr_tBin Meng1-5/+5
priv->iobase was declared as phys_addr_t which is now a 64-bit address. In a 32-bit build, this causes the following warning seen when building ftmac100.c: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] Cast priv->iobase with uintptr_t. Signed-off-by: Bin Meng <bin.meng@windriver.com>
2021-02-03serial: sifive: Cast dev_read_addr() with uintptr_tBin Meng1-1/+1
dev_read_addr() returns fdt_addr_t which is now a 64-bit address. In a 32-bit build, this causes the following warning seen when building serial_sifive.c: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] Cast the return value with uintptr_t. Signed-off-by: Bin Meng <bin.meng@windriver.com>
2021-02-03dm: core: Add late driver remove optionMarek Vasut2-8/+33
Add another flag to the DM core which could be assigned to drivers and which makes those drivers call their remove callbacks last, just before booting OS and after all the other drivers finished with their remove callbacks. This is necessary for things like clock drivers, where the other drivers might depend on the clock driver in their remove callbacks. Prime example is the mmc subsystem, which can reconfigure a card from HS mode to slower modes in the remove callback and for that it needs to reconfigure the controller clock. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Signed-off-by: Simon Glass <sjg@chromium.org>
2021-02-03dm: core: Avoid partially removing devicesSimon Glass1-19/+40
At present if device_remove() decides that the device should not actually be removed, it still calls the uclass pre_remove() method and powers the device down. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-02-03dm: core: Remove children before advising uclassSimon Glass1-9/+3
At present the uclass pre-remove method is called before the children are removed. But the children may refused to be removed, in whch case the uclass is in a tricky situation. At present we handle this by calling the uclass' post_probe() method. But it seems better to avoid doing anything with the uclass in this case. Switch the ordering so that we make sure the children can be removed before advising the uclass. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-02-03dm: pci: Correct use of wrong flag nameSimon Glass1-1/+1
Update a driver that uses the incorrect flag. Add a comment to hopefully prevent furture mistakes. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-02-03dm: Rename DM_FLAG_REMOVE_WITH_PD_ONSimon Glass3-3/+3
This flag has the word 'REMOVE' in it which means it conflicts with the DM_REMOVE flags. Rename it to DM_FLAG_LEAVE_PD_ON which seems to indicate its purpose well enough. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-02-03nand: brcmnand: Don't use -EPROBE_DEFERSimon Glass1-4/+1
This has no useful meaning in U-Boot and will never be returned. We want to reserve this flag for internal driver model use. Drop the code. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-02-03smem: Don't use -EPROBE_DEFERSimon Glass1-3/+3
This has no useful meaning in U-Boot. Use -ENOMEM since that appears to be what has gone wrong in this case. We want to reserve this flag for internal driver model use. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-02-01Merge https://gitlab.denx.de/u-boot/custodians/u-boot-x86WIP/01Feb2021Tom Rini1-1/+1
- Fix CMD_ACPI dependency in Kconfig - Correct overflow in __udelay() in TSC timer driver - Add a devicetree node for eMMC for Coral - Minor improvements on image loading - Reduce size of Samus image
2021-02-01x86: tsc_timer: Correct overflow in __udelay()Simon Glass1-1/+1
At present long delays such as msleep(2000) can cause an overflow in this function. There is no need for this, since it already uses a 64-bit int. Add a cast to correct this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-01-31Merge https://gitlab.denx.de/u-boot/custodians/u-boot-sunxiWIP/31Jan2021Tom Rini2-30/+37
- Allwinner H616 Ethernet support - sunxi ata debug fix
2021-01-31ata: sunxi: fix debug messagesDario Binacchi1-4/+4
It is useless and misleading to print the ret variable that is not set by the dev_read_addr routine. Also, move the '\n' character after the round bracket that contains the error code. Signed-off-by: Dario Binacchi <dariobin@libero.it> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-01-31net: sun8i-emac: Determine pinmux based on SoC, not EMAC typeAndre Przywara1-8/+20
The pinmux choice for the RMII/RGMII pins the EMAC is connected to is not dependent on the EMAC IP, but on the SoC it is integrated in. Deriving the pinmux from the DT compatible string (as we do at the moment) will thus cause problems with certain EMAC IP / SoC combinations. To avoid this exact issue with the H616, let's use our Kconfig MACH symbols to choose the correct pinmux setup. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net>
2021-01-31net: sun8i-emac: Always clear syscon EPHY registerAndre Przywara1-18/+13
At the moment we only consider the EPHY register for those SoCs were we actually have an internal PHY to configure. However even other SoCs have this register, an expect the EPHY select bit to be cleared for proper operation with an external PHY. Rework sun8i_emac_set_syscon_ephy() to be called regardless of the EMAC model, and clear the H3_EPHY_SELECT bit if no internal PHY is used. We get away without it so far because SoCs like the A64 clear this bit on reset, but we need to explicitly clear it on the H616, for instance. The Linux driver does so as well. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net>