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2017-06-05Merge git://git.denx.de/u-boot-usbTom Rini2-1/+3
2017-06-05drivers: ram: stm32: fix compilation issuePatrice Chotard1-1/+1
If CONFIG_CLK flag is not set, compilation raises the following error message: drivers/ram/stm32_sdram.c: In function 'stm32_fmc_probe': drivers/ram/stm32_sdram.c:154:2: error: 'ret' undeclared (first use in this function) ret = stm32_sdram_init(dev); Signed-off-by: Patrice Chotard <patrice.chotard@st.com> cc: Vikas Manocha <vikas.manocha@st.com>
2017-06-05reset: sti: add deassert counter in reset channel descriptorPatrice Chotard1-11/+30
This deassert counter allow to manage "shared" reset lines encountered in some specific case. On STiH410 SoC, DWC3, EHCI and OHCI are all using a respective PHY, but all of these PHYs shared a "global" reset. Currently, during command "usb stop", all host controller are stopped (XHCI, EHCI and OHCI). XHCI is first shutdowned, which means that PHY global reset is asserted. Then EHCI is shutdowned, but its PHY reset has already been asserted which make handshake() call failed in ehci_shutdown(). This counter allows to really assert a reset lines only when the "last" user is asserting it. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-06-05common: arm: freescale: layerscape: Move header files out of common.hSimon Glass5-5/+10
We should not have an arch-specific header file in common.h. Adjust the board files a little so it is not needed, and drop it. Signed-off-by: Simon Glass <sjg@chromium.org>
2017-06-05common: freescale: Move arch-specific declarationsSimon Glass9-0/+24
The declarations should not be in common.h. Move them to the arch-specific headers. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Fixup thinko defined(FSL_LSCH3) -> defined(CONFIG_FSL_LSCH3)] Signed-off-by: Tom Rini <trini@konsulko.com>
2017-06-05arm: Add explicit include of <asm/mach-types.h>Simon Glass1-0/+1
Rather than relying on common.h to provide this include, which is going away at some point, include it explicitly in each file. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2017-06-05samsung: Drop more references fo s3c24x0Simon Glass3-13/+0
This is dead code now. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org>
2017-06-05samsung: nand: Drop s3c2410_nand driverSimon Glass2-176/+0
This is not used anymore. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org>
2017-06-05samsung: usb: Drop ohci-s3c24xx driverSimon Glass3-2098/+0
This is not used anymore. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org>
2017-06-05samsung: mmc: Drop s3c_sdi driverSimon Glass2-324/+0
This is no-longer used in U-Boot. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2017-06-05gpio: samsung: Drop s3c2440_gpio driverSimon Glass2-89/+0
This is no longer used in U-Boot. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org>
2017-06-05common: Drop inclusion of pci.hSimon Glass1-0/+1
This should not be in common.h - remove it and update the only file that needs it. Signed-off-by: Simon Glass <sjg@chromium.org>
2017-06-05ehci-pci: Prepare for usage of readl()/writel() accessorsAlexey Brodkin1-0/+1
We used to have opencoded ehci_readl()/writel() which required no external functions to be called. Now with attempt to switch to generic readl()/writel() accessors we see a missing declaration of those accessors in ehci-ppc4xx. Something like that happens if applied http://patchwork.ozlabs.org/patch/726714/: --------------------------------->8--------------------------- CC drivers/usb/host/ehci-pci.o In file included from drivers/usb/host/ehci-pci.c:14:0: drivers/usb/host/ehci-pci.c: In function 'ehci_pci_init': drivers/usb/host/ehci.h:108:36: warning: implicit declaration of function 'readl' [-Wimplicit-function-declaration] #define ehci_readl(x) cpu_to_le32(readl(x)) ^ drivers/usb/host/ehci.h:23:26: note: in definition of macro 'HC_LENGTH' #define HC_LENGTH(p) (((p) >> 0) & 0x00ff) ^ include/linux/byteorder/generic.h:89:21: note: in expansion of macro '__cpu_to_le32' #define cpu_to_le32 __cpu_to_le32 ^~~~~~~~~~~~~ drivers/usb/host/ehci-pci.c:33:14: note: in expansion of macro 'ehci_readl' HC_LENGTH(ehci_readl(&hccr->cr_capbase))); ^~~~~~~~~~ --------------------------------->8--------------------------- This the same fix as we have for "ehci-ppc4xx" in 83cb46c286b "ehci-ppc4xx: Prepare for usage of readl()/writel() accessors". Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com> Cc: Marek Vasut <marex@denx.de> Cc: Stefan Roese <sr@denx.de>
2017-06-03Merge git://git.denx.de/u-boot-netTom Rini11-61/+207
2017-06-03Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini2-64/+246
2017-06-03dfu: dfu_sf: Fix read offsetPhil Edworthy1-1/+2
The offset was applied to write, but not read, now its applied to both. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
2017-06-02net: pch_gbe: Add cache maintenancePaul Burton1-0/+12
On MIPS systems DMA isn't coherent with the CPU caches unless an IOCU is present. When there is no IOCU we need to writeback or invalidate the data caches at appropriate points. Perform this cache maintenance in the pch_gbe driver which is used on the MIPS Boston development board. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-06-02net: pch_gbe: CPU accessible addresses are virtualPaul Burton1-12/+13
Use the virt_to_bus & bus_to_virt functions rather than phys_to_bus & bus_to_phys, since the addresses accessed by the CPU will be virtual rather than physical. On MIPS physical & virtual addresses differ as we use virtual addresses in kseg0, and attempting to use physical addresses directly caused problems as they're in the user segment which would be mapped via the uninitialised TLB. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-06-02net: pch_gbe: Fix rx descriptor buffer addressesPaul Burton1-2/+2
The loop to set up buffer addresses in rx descriptors always operated on descriptor 0, rather than on each descriptor sequentially. Fix this in order to setup correct buffer addresses for each descriptor. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-06-02net: pch_gbe: Reset during probePaul Burton1-0/+5
Using the EG20T gigabit ethernet controller on the MIPS Boston board, we find that we have to reset the controller in order for the RGMII link to the PHY to become functional. Without doing so we constantly time out in pch_gbe_mdio_ready. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-06-02net: zynq_gem: Dont flush dummy descriptorsSiva Durga Prasad Paladugu1-4/+0
Dont flush dummy descriptors as they are already allocated from a region with dcache off. Tested this on Zynq(zc702) and ZynqMP(zcu102) boards. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-06-02net: zynq_gem: Use wait_for_bit with non breakableSiva Durga Prasad Paladugu1-2/+2
Use wait_for_bit to be non breakable as using it with breakable causes issue of un interruptible auto negotiation. This is due to the ctrlc pressed will taken for wait_for_bit() abort during phy_read() and hence not coming out of auto negotiation. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-06-02net: phy: marvell 88e151x: Fix handling of RGMII interface typesPhil Edworthy1-1/+44
The 88E1518 code is programming the wrong registers for rgmii-id, rgmii-txid and rgmii-rxid interfaces. Since the PHY defaults to rgmii-id, it would appear that the code was previously only used with sgmii and rgmii-id interfaces. Tested on 88E1512 PHY in rgmii-id mode which is from the same family as 88E1518. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-06-02drivers: net: cpsw: abort init() on aneg timeoutSekhar Nori1-12/+22
Abort CPSW driver init when auto-negotiation of link times out. Currently, the code ignores return status of phy_startup(), and goes ahead with network operation (like DHCP) even though the link may be down. Instead, abort init process if link is down or if there is another error, so phy_startup() can easily be retried again. This also helps quick fallback to next network interface (like USB RNDIS) without inordinate delay. Tested on AM571x IDK and AM335x BeagleBone black. Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-06-02net: macb: Fix GMAC not work when enable DM_ETHWenyou Yang1-5/+2
Always search the PHY to determine the macb->phy_addr before using the PHY to fix "No PHY present" error. Fix the wrong test of the GMAC's phy interface mode, it should be PHY_INTERFACE_MODE_RGMII. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-06-02net: mvpp2.c: Enable 10G support for port 0 (SFI)Stefan Chulski1-15/+40
This patch fixes some remaining issues in the mvpp2 driver for the 10GB support on port 0. These changes are: - Incorrect PCS configuration - Skip PHY configuration when no PHY is connected - Skip GMAC configurations if 10G SFI mode set Signed-off-by: Stefan Chulski <stefanc@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-06-02armv8/ls1046a: RGMII PHY requires internal delay on TxMadalin Bucur1-2/+2
Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-06-02armv8/ls1043a: RGMII PHY requires internal delay on TxMadalin Bucur1-2/+2
Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-06-02net: zynq_gem: Do not return -ENOSYS on successOlliver Schinagl1-5/+3
The .read_rom_hwaddr net_ops hook does not check the return value, which is why it was never caught that we are currently returning 0 if the read_rom_hwaddr function return -ENOSYS and -ENOSYS otherwise. In this case we can simplify this by just returning the result of the function. Signed-off-by: Olliver Schinagl <oliver@schinagl.nl> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Michal Simek <michal.simek@xilinx.com>
2017-06-02net: designware: Add phy supply supportJacob Chen1-0/+17
Some board need a regulator for gmac phy, so add this code to handle it. Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-06-02net: Kconfig:make PHY_GIGE and individual Micrel PHYs selectablePhilipp Tomsich2-0/+42
This change migrate the following configuration options for Kconfig: * PHY_GIGE, indicates that a controller (with an appropriate PHY) is Gigabit capable and enables extra support in the miiutil for parsing the status of Gigabit PHYs * adds configuration options for Micrel KSZ9021 and KSZ9031 GbE PHYs, which previously had to enabled through a board-specific config file Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-06-01QE: add QE support on SD bootZhao Qiang1-1/+35
modify u_qe_init to upload QE firmware from SD card when it is SD boot Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-06-01drivers: net: fsl-mc: Include MAC addr fixup to DPLBogdan Purcareata1-63/+195
Previous to MC v10.x, port mac address was specified via DPL. Since newer MC versions are compatible with old style DPLs, make the u-boot env mac addresses visible there. This applies only to DPLs that have an older version. DPLs use 32 bit values for specifying MAC addresses. U-boot environment variables take precedence over the MAC addresses already visible in the DPL/DPC. Signed-off-by: Bogdan Purcareata <bogdan.purcareata@nxp.com> Signed-off-by: Heinz Wrobel <heinz.wrobel@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-06-01drivers: net: fsl-mc: Link MC boot to PHY_RESET_RBogdan Purcareata1-0/+16
DPAA2 platforms boot the Management Complex based on the u-boot env variable "mcinitcmd". Instead of doing this step on each platform individually, define a single mc_env_boot function in the MC driver, since it's semantically tied to it. Call the function in a per-board reset_phy hook, as it gets called at a later moment, when all board PHY devices have been initialized. Signed-off-by: Bogdan Purcareata <bogdan.purcareata@nxp.com> Signed-off-by: Heinz Wrobel <heinz.wrobel@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-06-01dm: gpio: power: Convert pm8916 drivers to livetreeSimon Glass2-6/+4
This PMIC driver (power and GPIO) is used by the sandbox SPMI tests. Update the drivers to support a live device tree so that the tests pass. Signed-off-by: Simon Glass <sjg@chromium.org>
2017-06-01dm: sandbox: sysreset: Convert driver to livetreeSimon Glass1-1/+1
Update this driver to support a live device tree. Signed-off-by: Simon Glass <sjg@chromium.org>
2017-06-01dm: sandbox: spi: Convert driver to support livetreeSimon Glass1-4/+2
Update this driver to support a live device tree. Signed-off-by: Simon Glass <sjg@chromium.org>
2017-06-01dm: spi-flash: Convert uclass to livetreeSimon Glass1-4/+3
Update the SPI flash uclass to support a live device tree. Signed-off-by: Simon Glass <sjg@chromium.org>
2017-06-01dm: sandbox: i2c_rtc: Drop fdtdec.h headerSimon Glass1-1/+0
This is not needed in this driver. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org>
2017-06-01dm: sandbox: i2c: Drop fdtdec.h headerSimon Glass1-1/+0
This is not needed in this driver. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org>
2017-06-01dm: spi: Convert uclass to livetreeSimon Glass1-17/+14
Update the SPI uclass to support a live device tree. Also adjust spi_slave_ofdata_to_platdata() to accept a device instead of a blob and offset. Signed-off-by: Simon Glass <sjg@chromium.org>
2017-06-01cros_ec: Update the cros_ec keyboard driver to livetreeSimon Glass3-24/+22
Update this driver and key_matrix to support a live device tree. Signed-off-by: Simon Glass <sjg@chromium.org>
2017-06-01dm: Update the I2C eeprom driver for livetreeSimon Glass1-5/+2
Update this driver so that it works with livetree. Signed-off-by: Simon Glass <sjg@chromium.org>
2017-06-01dm: pci: Update uclass to support livetreeSimon Glass1-14/+12
Update the PCI uclass to support livetree. This mostly involves fixing the address decoding from the device tree. Signed-off-by: Simon Glass <sjg@chromium.org>
2017-06-01dm: reset: Update uclass to support livetreeSimon Glass1-11/+10
Update the reset domain uclass to support livetree. Fix the xlate() method which has no callers. Signed-off-by: Simon Glass <sjg@chromium.org>
2017-06-01dm: power-domain: Update uclass to support livetreeSimon Glass1-11/+8
Update the power domain uclass to support livetree. Fix the xlate() method which has no callers. Signed-off-by: Simon Glass <sjg@chromium.org>
2017-06-01sandbox: phy: Update driver for livetreeSimon Glass1-2/+1
Update the sandbox phy driver to support livetree. Signed-off-by: Simon Glass <sjg@chromium.org>
2017-06-01dm: phy: Update uclass to support livetreeSimon Glass1-12/+9
Update the phy uclass to support livetree. Fix the xlate() method which has no callers. Signed-off-by: Simon Glass <sjg@chromium.org>
2017-06-01dm: mailbox: Update uclass to support livetreeSimon Glass2-13/+9
Update the mailbox uclass to support livetree. Fix the xlate() method in all callers. Signed-off-by: Simon Glass <sjg@chromium.org>
2017-06-01dm: clk: fixed: Update to support livetreeSimon Glass1-3/+2
Update the fixed-rate clock driver to support a live device tree. Signed-off-by: Simon Glass <sjg@chromium.org>
generated by cgit v1.1 at 2024-07-30 22:04:37 +0000