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2020-08-31Merge tag 'ti-v2020.10-rc4' of ↵Tom Rini1-59/+3
https://gitlab.denx.de/u-boot/custodians/u-boot-ti - Update to ABI 3.0 - Fix i2c write in eeprom driver
2020-08-31arm64: a37xx: pci: Depends on DM_GPIOPali Rohár2-8/+3
For proper initialization of aardvark pci driver it is required to de-assert reset GPIO. So depeneds on DM_GPIO option. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Andre Heider <a.heider@gmail.com>
2020-08-31mmc: xenon: set signal voltage and max base clockEvan Wang1-1/+78
- The SDIO signal voltage and max base clock frequency setting are missing in driver, which causes SDIO not working. - The patch adds SDIO signal voltage switch support, which is based on regulator-gpio of vqmmc-supply, and sets the max base clock frequency. - Fix the zero clock value in call to sdhci_setup_cfg() function. Change-Id: I79c8860c65b8db166f4f70db56ede4097f71f1fa Signed-off-by: Evan Wang <xswang@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/53589 Reviewed-by: Hua Jing <jinghua@marvell.com> Tested-by: Hua Jing <jinghua@marvell.com> [pali: Amended fixup patch] Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Andre Heider <a.heider@gmail.com>
2020-08-31arm64: a37xx: pci: Assert PERST# signal when unloading driverPali Rohár1-6/+21
This change ensures that PCIe card is put into reset state when U-Boot stops using it. DM_FLAG_OS_PREPARE ensures that U-Boot executes driver's remove callback prior booting Linux kernel. Linux kernel pci-aardvark driver needs to reset PCIe card via PERST# signal prior initializing it. If it does not issue reset then some PCIe cards (specially Compex WiFi cards) are not detected at all. Putting PCIe card into reset state prior booting Linux kernel would ensure that card would be properly reset at time when Linux kernel starts initializing pci-aardvark driver. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Konstantin Porotchkin <kostap@marvell.com> Tested-by: Andre Heider <a.heider@gmail.com>
2020-08-31arm64: a37xx: pci: Make PCIe Reset GPIO DT compatible with Linux kernel DTPali Rohár1-3/+3
Change active-high to active-low and change DT property name from reset-gpio to reset-gpios. This format of gpio reset is used by pci-aardvark driver in Linux kernel. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Konstantin Porotchkin <kostap@marvell.com> Tested-by: Andre Heider <a.heider@gmail.com>
2020-08-31firmware: ti_sci: Drop unused structure ti_sci_rm_type_mapLokesh Vutla1-49/+3
struct ti_sci_rm_type_map is no longer used. Drop its definition and its declarations. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-08-31firmware: ti_sci: drop the device ids to resource id translation tableLokesh Vutla1-11/+1
With ABI 3.0, sysfw deprecated special resource types used for AM65x SoC. Instead started using device id as resource type similar to the convention used in J721E SOC. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-08-27pci: kconfig: Setup proper dependency for PCIE_ROCKCHIPMichal Simek1-0/+1
There is missing dependency for PCIE_ROCKCHIP which selects PHY_ROCKCHIP_PCIE which directly depends on ARCH_ROCKCHIP. WARNING: unmet direct dependencies detected for PHY_ROCKCHIP_PCIE Depends on [n]: ARCH_ROCKCHIP [=n] Selected by [y]: - PCIE_ROCKCHIP [=y] && PCI [=y] Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2020-08-27drivers: usb: Fix config indentationRuben Di Battista1-6/+6
The indentation was messing up with the scripts/build-whitelist.sh that was marking SYS_USB_EVENT_POLL_VIA_INT_QUEUE (and probably also the other indented options) erroneously as ad-hoc configure option with the following error: ``` Error: You must add new CONFIG options using Kconfig The following new ad-hoc CONFIG options were detected: CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE ```
2020-08-25Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvellTom Rini13-42/+4871
- Add basic Marvell/Cavium OcteonTX/TX2 support (Suneel) - Infrastructure changes to PCI uclass to support these SoC's (Suneel) - Add PCI, MMC & watchdog driver drivers for OcteonTX/TX2 (Suneel) - Increase CONFIG_SYS_MALLOC_F_LEN for qemu-x86 (Stefan)
2020-08-25Merge tag 'i2c-bugfixes-for-v2020.10' of ↵Tom Rini3-35/+28
https://gitlab.denx.de/u-boot/custodians/u-boot-i2c i2c bugfixes for v2020.10 - fix some issues with octeon_i2c driver on ARM Octeon TX2 - fix link failure with CONFIG_SPL and CONFIG_I2C_MUX_PCA954x
2020-08-25Merge https://gitlab.denx.de/u-boot/custodians/u-boot-riscvTom Rini1-2/+2
- Sipeed Maix support S-mode. - Provide command sbi. - Use fdtdec_get_addr_size_auto_parent to get fu540 cache base address. - Fix a compiler error with CONFIG_SPL_SMP=n. - Fix sifive ram driver 32 compiler warnings. - Fix kendryte/pll.h redefine nop() warning.
2020-08-25watchdog: Add reset support for OcteonTX / TX2Suneel Garapati3-0/+77
Adds support for Core 0 watchdog poke on OcteonTX and OcteonTX2 platforms. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-08-25mmc: Add MMC controller driver for OcteonTX / TX2Suneel Garapati4-0/+4114
Adds support for MMC controllers found on OcteonTX or OcteonTX2 SoC platforms. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Peng Fan <peng.fan@nxp.com>
2020-08-25pci: Add PCI controller driver for OcteonTX / TX2Suneel Garapati3-0/+373
Adds support for PCI ECAM/PEM controllers found on OcteonTX or OcteonTX2 SoC platforms. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
2020-08-25ata: ahci: Add BAR index quirk for Cavium PCI SATA deviceSuneel Garapati1-0/+15
For SATA controller found on OcteonTX SoC's, use non-standard PCI BAR0 instead of BAR5. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-08-25pci: pci-uclass: Check validity of ofnodeSuneel Garapati1-3/+7
Add check if the referenced ofnode is valid. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
2020-08-25pci: pci-uclass: Add support for Alternate-RoutingID capabilitySuneel Garapati2-0/+35
If ARI capability is found on device, use it to update next function number in bus scan and also helps to skip unnecessary bdf scans. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
2020-08-25pci: pci-uclass: Add VF BAR map support for Enhanced AllocationSuneel Garapati1-5/+62
Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
2020-08-25pci: pci-uclass: Add support for Single-Root I/O VirtualizationSuneel Garapati2-0/+124
SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
2020-08-25pci: pci-uclass: Add support for Enhanced Allocation in BridgesSuneel Garapati1-6/+18
If Enhanced Allocation capability is present in bridges, use it to read the fixed sub-ordinate bus number. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
2020-08-25pci: pci-uclass: Add multi entry support for memory regionsSuneel Garapati2-3/+16
Enable PCI memory regions in ranges property to be of multiple entry. This helps to add support for SoC's like OcteonTX/TX2 where every peripheral is on PCI bus. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
2020-08-25Link failure with CONFIG_SPL and CONFIG_I2C_MUX_PCA954xTrommel, Kees (Contractor)2-2/+2
Fix for the case of a U-Boot configuration with CONFIG_SPL, CONFIG_I2C_MUX, CONFIG_I2C_MUX_PCA954x, no CONFIG_SPL_DM and no CONFIG_SPL_I2C_MUX. Without this fix linking of pca954x fails because dm_write_i2c does not exist because CONFIG_SPL_DM is not defined. Signed-off-by: Kees Trommel <kees.trommel.contractor@draeger.com> Cc: Heiko Schocher <hs@denx.de>
2020-08-25i2c: octeon_i2c: Misc fixes for ARM Octeon TX2 supportStefan Roese1-33/+26
This patch fixes a few issues noticed, when testing this new driver on ARM Octeon TX2 again. Here the details: - Remove "common.h" header inclusion - Use correct THP define on Octeon TX2 - Octeon TX2 uses the same compatible as Octeon TX. We can't distinguish both platforms this way. Remove the unused "cavium,thunder2-99xx-twsi" compatible and add a check to the Octeon TX2 specific "cavium,thunderx-i2c" so that the correct driver data is selected. - Removed "struct pci_device_id" definition and U_BOOT_PCI_DEVICE() as its not needed for the PCI based probing on Octeon TX2 Signed-off-by: Stefan Roese <sr@denx.de> Cc: Heiko Schocher <hs@denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Suneel Garapati <sgarapati@marvell.com> Cc: Aaron Williams <awilliams@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Heiko Schocher <hs@denx.de>
2020-08-25pci: pci-uclass: Make DT subnode parse optionalSuneel Garapati1-1/+2
Parse subnode DT properties only if parent node is valid. Otherwise, assert is triggered on ofnode_valid in ofnode_first_subnode from dev_for_each_subnode. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
2020-08-25pci: pci-uclass: Fix incorrect argument in map_physmemSuneel Garapati1-2/+2
Fix argument ordering for map_physmem() called in dm_pci_map_ea_bar(). Additinally minor spelling correction. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
2020-08-25pci: pci-uclass: Dynamically allocate the PCI regionsStefan Roese1-6/+8
Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
2020-08-25pci: pci-uclass: Remove #ifdef CONFIG_NR_DRAM_BANKS as its always setStefan Roese1-16/+1
Since the migration to Kconfig, CONFIG_NR_DRAM_BANKS is configured for all boards. Hence we can remove the conditional compilation and the code path that will never get compiled. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com> Cc: Bin Meng <bmeng.cn@gmail.com>
2020-08-25dm: core: Add API to read PCI bus-range propertyStefan Roese1-0/+17
Add dev_read_pci_bus_range() to read bus-range property values Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-08-25ram: sifive: Fix compiler warnings for 32-bitBin Meng1-2/+2
priv->info.size is of type 'size_t' but the length modifier is l. Fix this by casting priv->info.size. Note 'z' cannot be used as the modifier as SPL does not support that. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Rick Chen <rick@andestech.com> Reviewed-by: Pragnesh Patel <pragnesh.patel@openfive.com>
2020-08-24xen: Code style conformityAnastasiia Lukianenko2-7/+8
Cleaning up the following: ERROR: do not use assignment in if condition #281: FILE: drivers/xen/pvblock.c:260: + if ((err = xenbus_switch_state(XBT_NIL, nodename, CHECK:COMPARISON_TO_NULL: Comparison to NULL could be written "err" #52: FILE: drivers/xen/pvblock.c:298: + if (err != NULL) { ERROR: do not use assignment in if condition #176: FILE: drivers/xen/gnttab.c:103: + if ((flags = nflags) & (GTF_reading | GTF_writing)) { WARNING: Missing or malformed SPDX-License-Identifier tag in line 1 #329: FILE: include/xen/gnttab.h:1: +/* WARNING: Misplaced SPDX-License-Identifier tag - use line 1 instead #330: FILE: include/xen/gnttab.h:2: + * SPDX-License-Identifier: GPL-2.0 ERROR: do not use assignment in if condition #630: FILE: lib/sscanf.c:558: + if ((n = inr) < width) { Signed-off-by: Anastasiia Lukianenko <anastasiia_lukianenko@epam.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-08-24clk: mt7622: add needed clocks for ssusb-nodeFrank Wunderlich1-0/+42
MT7622 needs additional clock definitions to work properly Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
2020-08-24ahci: mediatek: fix copyright and author-linesFrank Wunderlich1-4/+2
after review of sam copyright should be on one line and link should not between author lines just remove the link and put ryder first as he is author of linux-driver Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
2020-08-24reset: drop unnecessary comment for pciesysFrank Wunderlich1-1/+0
after review from sam this comment should be removed Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
2020-08-24phy: mtk-tphy: make shared reg optional for v1Frank Wunderlich1-3/+2
make the shared reg optional when version is v1 for sata Suggested-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
2020-08-24virtio_blk: set log2blksz correctlyAKASHI Takahiro1-0/+1
'log2blksz' in blk_desc structure must always be initialized, otherwise it will cause a lot of weird failures in file operations. For example, fs_set_blk_dev[_with_part]() examines a block device against every file system with its probe function. In particular, ext4 file system's ext4_probe() will calls fs_devread() to fetch a super block. If log2blksz is 0, the actual 'read' size, i.e. block_len >> log2blksz, is much bigger than a buffer's size, and it can end up with memory corruption. Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org> Fixes: f4802209e59d ("virtio: Add block driver support") Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-08-24firmware: psci: Do not bind driver if U-Boot runs in EL3Michal Simek1-0/+6
There is no reason to bind psci driver if U-Boot runs in EL3 because SMC/HVC instructions can't be called. That's why detect this state and don't let user to crash from prompt by performing reset or poweroff commands (if enabled). Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-08-24Merge tag 'u-boot-clk-24Aug2020' of ↵Tom Rini10-13/+88
https://gitlab.denx.de/u-boot/custodians/u-boot-clk - Add CCF clocks definitions for iMX6Q enet (ETH) - Several fixes for CCF framework - the most notable is the one, which adds get_rate helper to clk-mux.c - Improvements for clk command - better visibility and alignment.
2020-08-24clk: ccf: Add missing #include <dm/uclass.h> to clk-mux.cLukasz Majewski1-0/+1
After adding custom get_rate helper function it was necessary to include <dm/uclass.h> to avoid warnings about missing uclass_get_device_by_name. Signed-off-by: Lukasz Majewski <lukma@denx.de> Series-to: u-boot
2020-08-24clk: ccf: mux: change the get_rate helperDario Binacchi1-1/+25
The previous version of the get_rate helper does not work if the mux clock parent is changed after the probe. This error has not been detected because this condition has not been tested. The error occurs because the set_parent helper does not change the parent of the clock device but only the clock selection register. Since changing the parent of a probed device can be tricky, the new version of the get_rate helper provides the rate of the selected clock and not that of the parent. Signed-off-by: Dario Binacchi <dariobin@libero.it>
2020-08-24clk: ccf: mux: fix access to the sandbox registerDario Binacchi1-0/+8
The tests developed for the mux clock are run on the sandbox. They don't call the clk_mux_set_parent routine and therefore they do not detect this error. Signed-off-by: Dario Binacchi <dariobin@libero.it>
2020-08-24clk: ccf: mux: fix typoDario Binacchi1-1/+1
Close the opening bracket. Signed-off-by: Dario Binacchi <dariobin@libero.it>
2020-08-24clk: ccf: mux: change include orderDario Binacchi1-4/+4
Apply u-boot coding style on include files order. Signed-off-by: Dario Binacchi <dariobin@libero.it>
2020-08-24clk: fix the console output of clk_registerDario Binacchi1-5/+5
The parent->name variable can be used only in case the uclass_get_device_by_name routine returns successfully. Signed-off-by: Dario Binacchi <dariobin@libero.it>
2020-08-24clk: set flags in the ccf registration routinesDario Binacchi6-1/+7
The top-level framework flags are passed as parameter to the common clock framework (ccf) registration routines without being used. Checks of the flags setting added by the patch have been added in the ccf test. Signed-off-by: Dario Binacchi <dariobin@libero.it>
2020-08-24dm: test: clk: add the test for the ccf gated clockDario Binacchi1-0/+4
Unlike the other clock types, in the case of the gated clock, a new driver has been developed which does not use the registering routine provided by the common clock framework. The addition of the ecspi0 clock to sandbox therefore allows testing the ccf gate clock. Signed-off-by: Dario Binacchi <dariobin@libero.it> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-08-24clk: imx6: Add definition for IMX6QDL_CLK_ENET_REF clockLukasz Majewski1-0/+7
After commit 673f6597321d ("net: fec_mxc: support i.MX8M with CLK_CCF") all NXP boards, which are not IMX8 and in the same time are supporting CCF need to provide PTP clock. On the i.MX6Q this clock is provided with IMX6QDL_CLK_ENET_REF in the Linux kernel's CCF. Code in this change models the simplest case when enet reference clock is generated from 'osc' clock. Signed-off-by: Lukasz Majewski <lukma@denx.de>
2020-08-24clk: imx: Add support for pllv3 enet clockLukasz Majewski1-0/+25
This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
2020-08-24clk: imx6: Add definition for IMX6QDL_CLK_ENET clockLukasz Majewski1-0/+1
After commit 673f6597321d ("net: fec_mxc: support i.MX8M with CLK_CCF") all NXP boards, which are not IMX8 and in the same time are supporting CCF need to provide IMX6QDL_CLK_ENET. This change defines the missing clock in i.MX6Q's CCF. Signed-off-by: Lukasz Majewski <lukma@denx.de>
2020-08-24clk: ICS8N3QV01 remove superfluous codeHeinrich Schuchardt1-1/+0
Do not calculate a unused value of n which is overwritten in both branches of the subsequent if statement. Identified by cppcheck. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Lukasz Majewski <lukma@denx.de>
generated by cgit v1.1 at 2024-07-15 12:40:03 +0000