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2015-12-01dm: tegra: pci: Move CONFIG_PCI_TEGRA to KconfigSimon Glass1-0/+10
Move this option to Kconfig and fix up all users. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Stephen Warren <swarren@nvidia.com>
2015-12-01x86: tsc: Move tsc_timer.c to drivers/timerBin Meng3-0/+397
To group all dm timer drivers together, move tsc timer to drivers/timer directory. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-12-01dm: timer: Support 64-bit counterBin Meng3-6/+15
There are timers with a 64-bit counter value but current timer uclass driver assumes a 32-bit one. Modify timer_get_count() to ask timer driver to always return a 64-bit counter value, and provide an inline helper function timer_conv_64() to handle the 32-bit/64-bit conversion automatically. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
2015-12-01timer: sandbox: Use device tree to pass the clock frequencyBin Meng1-4/+0
We should use device tree to pass the clock frequency of the timer instead of hardcoded in the driver codes. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-12-01timer: altera: Remove the codes to get clock frequencyBin Meng1-6/+0
Since we have timer uclass to get clock frequency for us, remove the custom version in the altera timer driver. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Simon Glass <sjg@chromium.org>
2015-12-01dm: timer: Implement pre_probe()Bin Meng1-0/+13
Every timer device needs to have a valid clock frequency and it can be specified in the device tree. Use pre_probe() to get this in the timer uclass driver. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Simon Glass <sjg@chromium.org>
2015-12-01dm: timer: Fix several nitsBin Meng2-8/+8
This changes 'Timer' to 'timer' at several places. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Simon Glass <sjg@chromium.org>
2015-11-30Merge branch 'master' of git://git.denx.de/u-boot-atmelTom Rini3-0/+308
2015-11-30gpio: atmel: Add the PIO4 driver supportWenyou Yang3-0/+308
The PIO4 is introduced from SAMA5D2, as a new version for Atmel PIO controller. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
2015-11-30Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini18-285/+1357
2015-11-30net: phy: added aquantia PHY AQR405 supportShaohui Xie1-0/+15
The phy can share driver with other aquantia PHYs, so we only add PHY ID. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30drivers/ddr/fsl: Fix typo in BIST test for DDR4York Sun1-12/+12
BIST test code has a typo, resulting the binding registers not maintained as expected. This typo results BIST runs twice on the covered memory. Signed-off-by: York Sun <yorksun@freescale.com> Reported-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
2015-11-30drivers/ddr/fsl: Enable detection of one DDR controller operation for LSCH3York Sun2-0/+41
Freescale LSCH3 platforms use two DDR controlers interleaving mode out of reset. It can be configured to disable one controller. To support this operation, the driver needs to detect and skip the disabled controller. Signed-off-by: York Sun <yorksun@freescale.com>
2015-11-30pci/layerscape: add support for LS1043A PCIe LUT register accessMingkai Hu1-7/+7
The endian and base address of PEX LUT register region is different between Chassis 2 and Chassis 3, so move the base address definition to chassis specific header file and add pex_lut_* functions to access LUT register. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30armv8: ls2085a: Add support of LS2085A SoCPrabhakar Kushwaha3-3/+4
Freescale's LS2085A is a another personality of LS2080A SoC with support of AIOP and DP-DDR. This Patch adds support of LS2085A Personality. Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> [York Sun: Updated MAINTAINERS files Dropped #ifdef in cpu.h Add CONFIG_SYS_NS16550=y in defconfig] Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30armv8: LS2080A: Rename LS2085A to reflect LS2080APrabhakar Kushwaha5-5/+8
LS2080A is a prime personality of Freescale’s LS2085A. It is a non-AIOP personality without support of DP-DDR, L2 switch, 1588, PCIe endpoint etc. So renaming existing LS2085A code base to reflect LS2080A (Prime personality) Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> [York Sun: Dropped #ifdef in cpu.c for cpu_type_list] Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30driver: net: ldpaa: Fix Rx buffer alignmentPrabhakar Kushwaha2-6/+11
MC 0.7.1.2 enforces limitation i.e.: "Packets may be corrupted in several combinations of buffer size and frame offsets. Workaround: Use buffers that are of size that is a multiple of 256, and frame offset that is a multiple of 256" Updating the DPNI Eth driver to comply with the restriction. Signed-off-by: Bogdan Hamciuc <bogdan.hamciuc@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30driver: net: ldpaa: Add debug informationPrabhakar Kushwaha1-0/+123
Add following debug information in the driver - Get various DPNI counter values - Get link status of DPNI objects - Get information of both ends of connection (DPMAC - DPNI) Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30driver: net: ldpaa: Use DPMAC as net devicePrabhakar Kushwaha3-44/+142
As per current implementation of DPAA2 ethernet driver DPNI is used as net device. DPNI is tangible objects can be multiple connected to same physical lane. Use DPMAC as net device where it represents physical lane. Below modification done in driver - Use global DPNI object - Connect DPMAC to DPNI - Create and destroy DPMAC Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30driver: net: fsl-mc: Create DPAA2 object at run-timePrabhakar Kushwaha2-36/+435
Freescale's DPAA2 ethernet driver depends upon the static DPL for the DPRC, DPNI, DPBP, DPIO objects. Instead of static objects, Create DPNI, DPBP, DPIO objects at run-time. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30driver: net: fsl-mc: Add DPAA2 commands to manage MCPrabhakar Kushwaha1-198/+184
Management complex Firmware, DPL and DPC are depolyed during u-boot boot sequence. Add new DPAA2 commands to manage Management Complex (MC) i.e. start mc, aiop and apply DPL from u-boot command prompt. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30driver: net: fsl-mc: Increase MC command timeoutPrabhakar Kushwaha1-1/+1
dpni_create API take takes more time as comapred to existing supported APIs of MC Flib. So increase MC command timeout. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30driver: ldpaa: Add api to return linked PHY ID of DPMACPrabhakar Kushwaha1-0/+12
DPMAC represents physical line on the board. This physical line eventually asscociate with on-board PHY. So Add an api to return linked PHY ID of DPMAC object. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30driver: net: fsl-mc: Add APIs for DPMAC objects in FLIBPrabhakar Kushwaha2-1/+224
DPMAC object of Management complex controls Physical MAC and MDIO controller. It provides APIs for MDIO and link state updates. It also provides APIs for PHY/link configuration. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30driver: net: fsl-mc: Add create, destroy APIs in flibsPrabhakar Kushwaha4-0/+167
Current Management Complex Flibs does not support APIs for adding and destroying the objects. Add APIs to create and destroy objects for DPBP, DPIO, DPNI and DPRC. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30armv8: lsch3: Fix lane protocol parsing logicPrabhakar Kushwaha1-8/+7
Current implementation only consider SGMIIs for dpmac initialization. XFI serdes protocols also uses dpmac. Also, fix lane protocol parsing logic to consider both XFIs and SGMIIs. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30Merge git://git.denx.de/u-boot-socfpgaTom Rini1-8/+21
2015-11-30mmc: socfpga_dw_mmc: Move drvsel and smplsel to dtsChin Liang See1-8/+21
socfpga_dw_mmc driver will obtain the drvsel and smplsel value from device tree instead of definition in config header file. Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Dinh Nguyen <dinh.linux@gmail.com> Cc: Pavel Machek <pavel@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Pantelis Antoniou <pantelis.antoniou@konsulko.com> Cc: Simon Glass <sjg@chromium.org> Cc: Jaehoon Chung <jh80.chung@samsung.com> Acked-by: Marek Vasut <marex@denx.de>
2015-11-30Merge branch 'master' of git://git.denx.de/u-boot-videoTom Rini2-1/+2
2015-11-30video: ipu: fix out of bounds accessPeng Fan2-1/+2
We need to access reg stp_rep9, but not stp_rep[(9 - 1) / 2]. If using "__raw_writel(0, DI_STP_REP(disp, 9))", this will exceeds the size of stp_rep array. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Acked-by: Liu Ying <Ying.Liu@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Anatolij Gustschin <agust@denx.de>
2015-11-23pci: fix address range check in __pci_hose_phys_to_bus()Marcel Ziswiler1-1/+1
The address range check may overflow if the memory region is located at the top of the 32-bit address space. This can e.g. be seen on TK1 if using the E1000 gigabit Ethernet driver where start and size are both 0x80000000 leading to the following messages: Apalis TK1 # tftpboot $loadaddr test_file Using e1000#0 device TFTP from server 192.168.10.1; our IP address is 192.168.10.2 Filename 'test_file'. Load address: 0x80408000 Loading: pci_hose_phys_to_bus: invalid physical address This patch fixes this by changing the order of the addition vs. subtraction in the range check just like already done in __pci_hose_bus_to_phys(). Reported-by: Ivan Mercier <ivan.mercier@nexvision.fr> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-11-23i2c, avr32: fix compiler warning "input is not relaxable"Heiko Schocher1-1/+1
compiling U-Boot for avr32 boards shows since commit 3d1957f0ea01 "dm: i2c: Add support for multiplexed I2C buses" this warning: Building current source for 4 boards (4 threads, 8 jobs per thread) avr32: + atstk1002 +(atstk1002) drivers/i2c/built-in.o: warning: input is not relaxable avr32: + grasshopper +(grasshopper) drivers/i2c/built-in.o: warning: input is not relaxable avr32: + atngw100 +(atngw100) drivers/i2c/built-in.o: warning: input is not relaxable avr32: + atngw100mkii +(atngw100mkii) drivers/i2c/built-in.o: warning: input is not relaxable 0 4 0 /4 0:00:16 : atngw100mkii Fix it. Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Roger Meier <r.meier@siemens.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
2015-11-22Merge branch 'master' of http://git.denx.de/u-boot-sunxiTom Rini2-2/+15
2015-11-22sunxi: Add basic H3 supportJens Kuske1-2/+3
Add initial sun8i H3 support, only uart + mmc are supported for now. Signed-off-by: Jens Kuske <jenskuske@gmail.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2015-11-22sunxi: musb: Implement dfu_usb_get_reset()Siarhei Siamashka1-0/+12
This is necessary to distinguish between the "dfu-util --detach" and the "dfu-util --reset" requests. The default weak implementation of dfu_usb_get_reset() unconditionally reboots the device, but we want to be able to continue the boot.scr execution after writing the kernel, fdt and ramdisk to RAM via DFU. Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2015-11-21ns16550: move CONFIG_SYS_NS16550 to KconfigThomas Chou1-0/+10
Move CONFIG_SYS_NS16550 to Kconfig, and run moveconfig.py. Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
2015-11-21ns16550: zap CONFIG_NS16550_SERIALThomas Chou2-16/+0
Zap CONFIG_NS16550_SERIAL, as the unification of ns16550 drivers is completed. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-11-21ns16550: unify serial_omapThomas Chou2-55/+0
Unify serial_omap, and use the generic binding. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-11-21ns16550: unify serial_tegraThomas Chou2-55/+0
Unify serial_tegra, and use the generic binding. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-11-21ns16550: unify serial_dwThomas Chou2-40/+0
Unify serial_dw, and use the generic binding. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-11-21ns16550: unify serial_keystoneThomas Chou2-49/+0
Unify serial_keystone, and use the generic binding. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-11-21ns16550: unify serial_rockchipThomas Chou3-54/+1
Unify serial_rockchip, and use the generic binding. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Tom Rini <trini@konsulko.com> Tested-by: Ariel D'Alessandro <ariel@vanguardiasur.com.ar> Acked-by: Simon Glass <sjg@chromium.org>
2015-11-21ns16550: unify serial_ppcThomas Chou3-42/+1
Unify serial_ppc, and use the generic binding. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Tom Rini <trini@konsulko.com> [trini: Add TODO comment] Signed-off-by: Tom Rini <trini@konsulko.com>
2015-11-20ns16550: unify serial_x86Thomas Chou3-55/+1
Unify serial_x86, and use the generic binding. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-11-20ns16550: add generic binding to unify the driversThomas Chou2-0/+55
Add generic binding to unify ns16550 drivers. There are several drivers using almost the same code, such as serial_dw, serial_keystone, serial_omap, serial_ppc, serial_rockchip, serial_tegra.c, and serial_x86. But each is platform specific. The key difference between these drivers is the way to get input clock frequency. With this unified approach, fixed clock frequency should be extracted from "clock-frequency" property of device tree blob. If this property is not available, the macro CONFIG_SYS_NS16550_CLK will be used. It can be a constant or a function to get clock, eg, get_serial_clock(). Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Heiko Schocher <hs@denx.de> Acked-by: Simon Glass <sjg@chromium.org>
2015-11-20ns16550: change map_sysmem to map_physmemThomas Chou1-3/+2
Change map_sysmem() to map_physmem(,,MAP_NOCACHE). Though map_sysmem() can be used to map system memory, it might be wrong to use it for I/O ports. The map_physmem() serves the same purpose to translate physical address to virtual address with the additional flag to take care of cache property. Most drivers use map_physmem() since I/O ports access should be uncached. As ns16550 is a driver, it should use map_physmem() rather than map_sysmem(). Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Simon Glass <sjg@chromium.org>
2015-11-20debug_uart: restore ns16550 as defaultThomas Chou1-0/+1
Since commit 220e8021af96 ("nios2: convert altera_jtag_uart to driver model"), the default debug uart was changed. Most people use ns16550 UART, so restore it as default. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reported-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar> Reported-by: Ariel D'Alessandro <ariel@vanguardiasur.com.ar> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Heiko Schocher <hs@denx.de> Acked-by: Simon Glass <sjg@chromium.org>
2015-11-19usb: sandbox: Add a USB emulation driverSimon Glass2-0/+242
Add a simple USB keyboard driver for sandbox. It provides a function to 'load' it with input data, which it will then stream through to the normal U-Boot input subsystem. When the input data is exhausted, the keyboard stops providing data. Signed-off-by: Simon Glass <sjg@chromium.org>
2015-11-19usb: sandbox: Add support for interrupt operationsSimon Glass2-0/+31
Allow USB device emulation to support interrupt URBs so that we can use USB keyboards with sandbox. Signed-off-by: Simon Glass <sjg@chromium.org>
2015-11-19dm: usb: Remove inactive children after a bus scanSimon Glass1-0/+23
Each scan of the USB bus may return different results. Existing driver-model devices are reused when found, but if a device no longer exists it will stay around, de-activated, but bound. Detect these devices and remove them after the scan completes. Signed-off-by: Simon Glass <sjg@chromium.org>
generated by cgit v1.1 at 2024-07-14 21:23:55 +0000