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2018-10-31Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini2-2/+2
2018-10-31arm: socfpga: fpga: fix type of local variableSimon Goldschmidt2-2/+2
The 'status' variable in 'socfpga_load()' for both gen5 and arria10 is of type 'unsigned long' while it is always used as 'int' only. Change it to 'int'. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2018-10-29powerpc: t1040: Correct RCW EC2 settingsBin Meng1-3/+0
Per T1040RM (Rev. 1, 08/2015), there are 2 issues with the RCW EC2 settings. - The value of FSL_CORENET_RCWSR13_EC2_FM1_GPIO is wrong and should be 0x04000000 (value of 1 in RCW bit [420:421]) - Value of 2/3 are reserved in RCW bit [420:421], hence there is no macro FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_MII. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Poonam Aggrwal <poonam.aggrwal@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-10-29fsl/usb: Workaround for USB erratum-A005275Chris Packham4-1/+50
Workaround makes FS as default mode on all affected socs. Add support to check erratum-A005275 validity for an soc. This info is required to determine whether a given soc is affected by this erratum. Add quirk for this erratum "has_fsl_erratum_a005275" . This quirk is used to enable workaround for the errata Force FS mode as default by: - making EPS as FS - setting PFSC bit to disable HS chirping This workaround can be disabled by mentioning "no_erratum_a005275" in hwconfig string Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-10-29Merge branch 'master' of git://git.denx.de/u-boot-sunxiTom Rini2-14/+20
2018-10-28drivers: cosmetic: Convert SPDX license tags to Linux Kernel stylePatrick Delaunay24-38/+32
Complete in the drivers directory the work started with commit 83d290c56fab ("SPDX: Convert all of our single license tags to Linux Kernel style"). Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2018-10-25Merge branch 'master' of git://git.denx.de/u-boot-netTom Rini6-25/+389
2018-10-25Merge tag 'u-boot-imx-20181025' of git://git.denx.de/u-boot-imxTom Rini24-142/+1795
Merged imx8 architecture, fix build for imx8 + warnings
2018-10-24net: fec_mxc: add support for i.MX8XAnatolij Gustschin3-4/+61
Add compatible property and enable the FEC ipg clock when probing on i.MX8X. Add specific function for reading FEC clock rate via clock driver when configuring MII speed register. Allow FEC_MXC selection for i.MX8. Signed-off-by: Anatolij Gustschin <agust@denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-24net: mvpp2: increase PHY reset pulseBaruch Siach1-1/+1
The default Linux PHY reset delay is 10ms. This is also the requirement for Marvell 88E151x PHYs, which are likely to be used with this Ethernet MAC. Cc: Stefan Chulski <stefanc@marvell.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Stefan Roese <sr@denx.de>
2018-10-24net: mvpp2: fix polarity of PHY reset signalBaruch Siach1-2/+2
The dm_gpio_set_value() call sets the logical level of the GPIO signal. That is, it takes the GPIO_ACTIVE_{LOW,HIGH} property into account. The driver needs to assert the reset, and then deassert it. Not the other way around. Cc: Stefan Chulski <stefanc@marvell.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Stefan Roese <sr@denx.de>
2018-10-24net: dm: fec: Obtain the transceiver type from the DTMartin Fuzzey1-1/+20
The DT property "phy-mode" already provides the transceiver type. Use it so that we do not have to also set CONFIG_FEC_XCV_TYPE Signed-off-by: Martin Fuzzey <martin.fuzzey@flowbird.group> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-24net: dm: fec: Support the phy-supply bindingMartin Fuzzey2-0/+23
Configure the phy regulator if defined by the "phy-supply" DT phandle. Signed-off-by: Martin Fuzzey <martin.fuzzey@flowbird.group> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-24net: dm: fec: Fix phy-reset-duration clamping and defaultsMartin Fuzzey1-11/+8
The DT binding says: - phy-reset-duration : Reset duration in milliseconds. Should present only if property "phy-reset-gpios" is available. Missing the property will have the duration be 1 millisecond. Numbers greater than 1000 are invalid and 1 millisecond will be used instead. However the current code: - clamps values greater than 1000ms to 1000ms rather than 1. - does not initialize the delay if the property does not exist (else clause mismatch) - returns an error if phy-reset-gpios is not defined Fix all this and simplify by using dev_read_u32_default() Signed-off-by: Martin Fuzzey <martin.fuzzey@flowbird.group> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-24net: dm: fec: Fix time unit error in phy-reset-durationMartin Fuzzey1-1/+1
The DT binding says that phy-reset-duration is in ms, but the driver currently uses udelay(). Switch to mdelay() to fix this. Signed-off-by: Martin Fuzzey <martin.fuzzey@flowbird.group> Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-24net: phy: aquantia: autodetect if firmware needs to be loadedJeremy Gebben1-6/+22
If the phy reports a valid firmware version and doesn't indicate a fault, skip loading the firmware. This allows the same image to be used on boards that have firmware storage and those that do not. Signed-off-by: Jeremy Gebben <jgebben@sweptlaser.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-24net: phy: aquantia: add firmware loading supportJeremy Gebben2-2/+256
Aquantia phys have firmware that can be loaded automatically from storage directly attached to the phy or via MDIO commands. Add support for loading firmware from either a file or a raw location on an MMC device. Signed-off-by: Jeremy Gebben <jgebben@sweptlaser.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-24configs: migrate CONFIG_PHY_AQUANTIA to KconfigJeremy Gebben2-4/+2
The aquantia driver requires both CONFIG_PHY_GIGE and CONFIG_PHYLIB_10G. Signed-off-by: Jeremy Gebben <jgebben@sweptlaser.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-24sunxi: display: Mark sunxi_rgb2yuv_coef array as constPriit Laes1-1/+1
sunxi_rgb2yuv_coef is readonly and never modified. Signed-off-by: Priit Laes <plaes@plaes.org> Acked-by: Anatolij Gustschin <agust@denx.de> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-10-24pwm: sunxi: choose best prescaler to improve PWM resolutionVasily Khoruzhick1-13/+19
Choose best prescaler to improve PWM resolution. Without this change driver chooses first prescaler that gives us period value within range, but it could be not the best one. Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com> Tested-by: Vagrant Cascadian <vagrant@debian.org> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-10-24pwm: sunxi: use new prescaler when configuring PWMVasily Khoruzhick1-1/+1
Looks like old prescaler was used when configuring PWM, fix it. Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-10-24pwm: sunxi: fix off-by-one that prevented PWM to use prescaler bypassVasily Khoruzhick1-1/+1
Fix off-by-one that prevented PWM driver to use prescaler bypass. Without this change prescaler is always enabled. Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-10-22Merge git://git.denx.de/u-boot-x86Tom Rini2-3/+16
2018-10-22serial: mxc: Add match string for i.mx6 quad/dual lite serialBernhard Messerklinger1-0/+1
Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com> Reviewed-by: Hannes Schmelzer <oe5hpm@oevsv.at> Tested-by: Hannes Schmelzer <oe5hpm@oevsv.at>
2018-10-22watchdog: aspeed: restore default value of reset_maskCédric Le Goater1-0/+1
This is required for the current Linux kernel to reboot. It should also probably be fixed in Linux. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-10-22nand: atmel: Initialize pmecc smu with correct sizeBin Meng1-1/+1
Currently in pmecc_get_sigma(), the code tries to clear the memory pointed by smu with wrong size 'sizeof(int16_t) * ARRAY_SIZE(smu)'. Since smu is actually a pointer, not an array, so ARRAY_SIZE(smu) does not generate correct size to be cleared. In fact, GCC 8.1.0 reports a warning against it: error: division 'sizeof (int16_t * {aka short int *}) / sizeof (int16_t {aka short int})' does not compute the number of array elements [-Werror=sizeof-pointer-div] Fix it by using the correct size. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
2018-10-22i2c: imx_lpi2c: fix typo and register base address formatAnatolij Gustschin1-2/+2
Output the register base address in hex notation. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Heiko Schocher <hs@denx.de>
2018-10-22Kconfig: Convert CONFIG_IMX_WATCHDOG to KconfigXiaoliang Yang1-0/+7
Move this option to Kconfig and tidy up the config file of eight boards which use it. Signed-off-by: Xiaoliang Yang <xiaoliang.yang_1@nxp.com>
2018-10-22mmc: fsl_esdhc: add uclass clk supportPeng Fan1-4/+22
When CONIFG_CLK is enabled, use uclass clk api to handle the clock. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Anatolij Gustschin <agust@denx.de> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Stefano Babic <sbabic@denx.de>
2018-10-22fsl_esdhc: Update usdhc driver to support i.MX8Ye Li1-4/+4
Add CONFIG_ARCH_IMX8 to use the 64bits support in usdhc driver. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Anatolij Gustschin <agust@denx.de> Cc: Jaehoon Chung <jh80.chung@samsung.com>
2018-10-22serial: lpuart: support uclass clk apiPeng Fan1-19/+76
Modify most APIs to use udevice as the first parameter, then it will be easy to get the clk reference by using udevice pointer. Use uclass api to get lpuart clk when CONFIG_CLK is enabled. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Anatolij Gustschin <agust@denx.de> Cc: Stefano Babic <sbabic@denx.de>
2018-10-22serial: lpuart: Enable RX and TX FIFOYe Li1-7/+26
Enable the RX and TX FIFO in LPUART driver to avoid the input lost during U-Boot boot up. Signed-off-by: Ye Li <ye.li@nxp.com> Acked-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Anatolij Gustschin <agust@denx.de> Cc: Stefano Babic <sbabic@denx.de>
2018-10-22serial_lpuart: Update lpuart driver to support i.MX8Peng Fan1-3/+12
Add i.MX8 compatible string and cpu type support to lpuart driver, to use little endian 32 bits configurations. Also, according to RM, the Receive FIFO Enable (RXFE) field in LPUART FIFO register is bit 3, so this definition should change to 0x08 (not 0x40) for i.MX8, otherwise the Receive FIFO is not disabled. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Anatolij Gustschin <agust@denx.de> Cc: Stefano Babic <sbabic@denx.de>
2018-10-22clk: imx: add clk driver for i.MX8QXPPeng Fan5-0/+406
Add clk driver for i.MX8QXP. This basic version supports clk enable/disable/get_rate/set_rate operations for I2C, ENET, SDHC0 and UART clocks. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Anatolij Gustschin <agust@denx.de> Cc: Stefano Babic <sbabic@denx.de>
2018-10-22power: Add power domain driver for i.MX8Peng Fan3-1/+323
Add the power domain DM driver for i.MX8, that it depends on the DTB power domain trees to generate the power domain provider devices. Users need to add power domain trees with property "compatible = "nxp,imx8-pd";" When power on a PD device, the driver will power on its ancestor PD devices in power domain tree. When power off a PD device, the driver will check its child PD devices first. Only if all child PD devices are off, then power off the current PD device. Then the driver checks sibling PD devices. If sibling PD devices are off, then it will power off parent PD device. There is no counter maintained in this driver, but a state to hold current on/off state. So the request and free functions are empty. The power domain implementation in i.MX8 DTB set the "#power-domain-cells" to 0, so there is no ID binding with each PD device. We don't use "id" variable in struct power_domain. At the same time, we have to set of_xlate to empty to bypass standard of_xlate in uclass driver. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Anatolij Gustschin <agust@denx.de> Cc: Stefano Babic <sbabic@denx.de>
2018-10-22pinctrl: Add pinctrl driver for i.MX8Peng Fan6-93/+258
Add pinctrl driver for i.MX8. The pads configuration is controlled by SCU, so need to ask SCU to configure pads through scfw API. Add pinctrl-scu to invoke sc_pad_set to configure pads. Add a new flag IMX8_USE_SCU to differentiate i.MX8 from other platforms which could directly configure pads from Acore side. Add CONFIG_PINCTRL_IMX8 as the built gate. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Anatolij Gustschin <agust@denx.de> Cc: Stefano Babic <sbabic@denx.de>
2018-10-22gpio: mxc_gpio: add support for i.MX8Peng Fan1-9/+21
Add i.MX8 support, there are 8 GPIO banks. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Anatolij Gustschin <agust@denx.de> Cc: Stefano Babic <sbabic@denx.de>
2018-10-22misc: imx8: add scfw api impementationPeng Fan2-1/+368
Add clk/misc/pad/pm/rm scfw api implementaion for different drivers to invoke. The low level code is using misc_call to invoke imx8_scu driver. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Anatolij Gustschin <agust@denx.de> Cc: Stefano Babic <sbabic@denx.de>
2018-10-22misc: add i.MX8 misc driverPeng Fan3-0/+270
Add i.MX8 MISC driver to handle the communication between A35 Core and SCU. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Anatolij Gustschin <agust@denx.de> Cc: Stefano Babic <sbabic@denx.de>
2018-10-22x86: tsc: Introduce config option for early timer frequencyBin Meng2-3/+13
So far the TSC timer driver supports trying hardware calibration first and using device tree as last resort for its running frequency as the normal timer. However when it is used as the early timer, it only supports hardware calibration and if it fails, the driver just panics. This introduces a new config option to specify the early timer frequency in MHz and it should be equal to the value described in the device tree. Without this patch, the travis-ci testing on QEMU x86_64 target fails each time after it finishes the 'bootefi selftest' as the test.py see an error was emitted on the console like this: TSC frequency is ZERO resetting ... ### ERROR ### Please RESET the board ### It's strange that this error is consistently seen on the travis-ci machine, but only occasionally seen on my local machine (maybe 1 out of 10). Since QEMU x86_64 target enables BOOTSTAGE support which uses early timer, with this fix it should work without any failure. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-10-22Enable CONFIG_TIMER_EARLY with bootstageSimon Glass1-0/+3
In initr_bootstage() we call bootstage_mark_name() which ends up calling timer_get_us(). This call happens before initr_dm(), which inits driver model. On x86 we set gd->timer to NULL in the transition from board_init_f() to board_init_r(). See board_init_f_r() for this assignment. So U-Boot knows there is no timer available in the period immediately after relocation. On x86 the timer_get_us() call is implemented as calls to get_ticks() and get_tbclk(). Both of these call dm_timer_init() to set up the timer, if gd->timer is NULL and the early timer is not available. However dm_timer_init() cannot succeed before initr_dm() is called. So it seems that on x86 if we want to use CONFIG_BOOTSTAGE we must enable CONFIG_TIMER_EARLY. Update the Kconfig to handle this. Note: On most architectures we can rely on the pre-relocation memory still being available, so that gd->timer pointers to a valid timer device and everything works correctly. Admittedly this is not strictly correct since the timer device is set up by pre-relocation U-Boot, but normally this is fine. On x86 the 'CAR' (cache-as-RAM) memory used by pre-relocation U-Boot disappears in board_init_f_r() and any attempt to access it will hang. This is the reason why we must mark the timer as invalid when we get to board_init_f_r(). Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-10-20pci: Support parsing PCI controller DT subnodesMarek Vasut1-3/+29
The PCI controller can have DT subnodes describing extra properties of particular PCI devices, ie. a PHY attached to an EHCI controller on a PCI bus. This patch parses those DT subnodes and assigns a node to the PCI device instance, so that the driver can extract details from that node and ie. configure the PHY using the PHY subsystem. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-10-19Convert CONFIG_FLASH_CFI_DRIVER et al to KconfigAdam Ford1-0/+38
This converts the following to Kconfig: CONFIG_FLASH_CFI_DRIVER CONFIG_SYS_FLASH_USE_BUFFER_WRITE CONFIG_FLASH_CFI_MTD CONFIG_SYS_FLASH_PROTECTION CONFIG_SYS_FLASH_CFI Signed-off-by: Adam Ford <aford173@gmail.com> [trini: Re-migrate] Signed-off-by: Tom Rini <trini@konsulko.com>
2018-10-19bootcount: Make bootcount magic configurableMarek Vasut5-12/+19
Add new Kconfig option, SYS_BOOTCOUNT_MAGIC, to select the boot counter magic word. This can be useful ie. in case the entire boot counter register is not usable. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com>
2018-10-16Merge git://git.denx.de/u-boot-microblazeTom Rini4-4/+8
Xilinx changes for v2018.11-rc2-v2 FPGA: - Fix SPL fpga loading from FIT ARM64: - Fix gic accesses in EL2/EL1 Xilinx: - Add dlc20 board support - Add Versal board support - Sync defconfigs - Enable MP via Kconfig - Add missing efuse node - Enable CDC for zcu100 cmd: - Fix kgdb Kconfig dependency
2018-10-16net: gem: Do not setup any clock for Xilinx SoC VersalMichal Simek1-0/+4
Xilinx SoC Versal is using fixed clock where setting rate is not supported. That's why workaround the driver till real clock driver is supported. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-10-16arm64: versal: Add support for new Xilinx Versal ACAPsMichal Simek3-4/+4
Xilinx is introducing Versal, an adaptive compute acceleration platform (ACAP), built on 7nm FinFET process technology. Versal ACAPs combine Scalar Processing Engines, Adaptable Hardware Engines, and Intelligent Engines with leading-edge memory and interfacing technologies to deliver powerful heterogeneous acceleration for any application. The Versal AI Core series has five devices, offering 128 to 400 AI Engines. The series includes dual-core Arm Cortex™-A72 application processors, dual-core Arm Cortex-R5 real-time processors, 256KB of on-chip memory with ECC, more than 1,900 DSP engines optimized for high-precision floating point with low latency. The patch is adding necessary infrastructure in place without enabling platform which is done in separate patch. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-10-16Merge branch 'master' of git://git.denx.de/u-boot-i2cTom Rini2-0/+8
2018-10-12Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini4-20/+39
2018-10-12ldpaa_eth.c: Fix warning when PHYLIB is not enabledTom Rini1-3/+7
We need to #ifdef some variables to avoid warning about them being unused. Fixes: 1a048cd65645 ("driver: net: fsl-mc: Add support of multiple phys for dpmac") Signed-off-by: Tom Rini <trini@konsulko.com>
generated by cgit v1.1 at 2024-07-13 21:56:35 +0000