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2021-07-19Merge tag 'ti-v2021.10-rc1' of ↵Tom Rini12-6/+795
https://source.denx.de/u-boot/custodians/u-boot-ti - Enabled distro boot for all TI platforms. - Cleanup for AM335x Guardian Board - PRUSS rproc on AM65 platform. - Add PMIC support for J7200 - Misc fixes for Nokia RX-51 # Conflicts: # arch/arm/mach-omap2/am33xx/Kconfig
2021-07-18pci: Require DM_PCITom Rini4-983/+5
As the migration deadline has passed, require that DM_PCI be used. Signed-off-by: Tom Rini <trini@konsulko.com>
2021-07-18usb: Enforce DM_USB migration for USB_HOST devices.Tom Rini9-25/+36
As the deadline for migration to DM_USB, when using a USB host controller has now gone two years past the deadline, enforce migration. This is done by: - Ensuring that all host controller options (other than the very legacy old MUSB ones) now select USB_HOST. USB_HOST now enforces DM_USB and OF_CONTROL. - Remove other parts of Kconfig logic that had platforms pick DM_USB. - To keep Kconfig happy, have some select statements test for USB_HOST as well. - Re-order some Kconfig entries and menus so that we can cleanly pick host or gadget roles. For the various HCD options that have platform glue options, group them together and update dependencies in some cases. - As SPL_DM_USB is not required, on platforms that had not yet enabled it, disable it. Cc: Marek Vasut <marex@denx.de> Cc: Icenowy Zheng <icenowy@aosc.io> Cc: Samuel Holland <samuel@sholland.org> Cc: FUKAUMI Naoki <naobsd@gmail.com> Cc: Andre Przywara <andre.przywara@arm.com> Cc: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Tom Rini <trini@konsulko.com>
2021-07-18m68k: Remove M54451EVB boardTom Rini1-6/+0
This board has not been converted to CONFIG_DM_MMC by the deadline. Remove it. As this is also the last in family remove the related support as well. Cc: Angelo Durgehello <angelo.dureghello@timesys.com> Signed-off-by: Tom Rini <trini@konsulko.com>
2021-07-18pci: msc01: convert to driver modelDaniel Schwierzeck1-1/+71
This driver is currently only used on MIPS Malta boards. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-07-18pci: gt64120: convert to driver modelDaniel Schwierzeck1-1/+73
This driver is currently only used on MIPS Malta boards. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-07-18dm: pci: add option to map virtual system memory base addressDaniel Schwierzeck2-3/+19
On MIPS the DRAM start address respectively CONFIG_SYS_SDRAM_BASE is still used as a virtual, CPU-mapped address instead of being used as physical address. Converting all MIPS boards and generic MIPS code to fix that is not trivial. Due to the approaching deadline for PCI DM conversion, this workaround is required for MIPS boards with PCI support until the CONFIG_SYS_SDRAM_BASE issue could be solved. Add a compile-time option to let the PCI uclass core optionally map the DRAM address to a physical address when adding the PCI region of type PCI_REGION_SYS_MEMORY. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
2021-07-17Merge tag 'u-boot-imx-20210717' of ↵WIP/17Jul2021Tom Rini14-31/+867
https://gitlab.denx.de/u-boot/custodians/u-boot-imx i.MX ---- - mx7ulp : fix WDOG - imx8 : Phytec - USB3 support for i.MX8 CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/8277
2021-07-17mx7ulp: wdog: Wait for WDOG unlock and reconfiguration to completeBreno Lima1-14/+25
According to i.MX7ULP Reference Manual we should wait for WDOG unlock and reconfiguration to complete. Section "59.5.3 Configure Watchdog" provides the following example: DisableInterrupts; //disable global interrupt WDOG_CNT = 0xD928C520; //unlock watchdog while(WDOG_CS[ULK]==0); //wait until registers are unlocked WDOG_TOVAL = 256; //set timeout value WDOG_CS = WDOG_CS_EN(1) | WDOG_CS_CLK(1) | WDOG_CS_INT(1) | WDOG_CS_WIN(0) | WDOG_CS_UPDATE(1); while(WDOG_CS[RCS]==0); //wait until new configuration takes effect EnableInterrupts; //enable global interrupt Update U-Boot WDOG driver to align with i.MX7ULP reference manual. Use 32 bits accessing to CS register. According to RM, the bits in this register only can write once after unlock. So using 8 bits access will cause problem. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Breno Lima <breno.lima@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-07-17mx7ulp: Update unlock and refresh sequences in sWDOG driverBreno Lima1-6/+12
According to i.MX7ULP Reference Manual the second word write for both UNLOCK and REFRESH operations must occur in maximum 16 bus clock. The current code is using writel() function which has a DMB barrier to order the memory access. The DMB between two words write may introduce some delay in certain circumstance, causing a WDOG timeout due to 16 bus clock window requirement. Replace writel() function by __raw_writel() to achieve a faster memory access and avoid such issue. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Breno Lima <breno.lima@nxp.com>
2021-07-17phy: phy-imx8mq-usb: Add USB PHY driver for i.MX8MQYe Li3-0/+205
Add the USB PHY driver for i.MX8MQ to work with DWC3 USB controller. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Patrick Wildt <patrick@blueri.se> Tested-by: Patrick Wildt <patrick@blueri.se>
2021-07-16Merge branch '2021-07-15-assorted-fixes'Tom Rini9-14/+27
- Large number of Coverity reported issues addressed - m41t62 bugfix - Support more Android image compression formats - FIT + DTO bugfix
2021-07-16Merge https://source.denx.de/u-boot/custodians/u-boot-marvellWIP/16Jul2021Tom Rini2-5/+16
- designware_wdt: reset watchdog in designware_wdt_stop() function (Meng) - socfpga_stratix10: enable wdt command (Meng) - wdt-uclass: Use IS_ENABLED for WATCHDOG_AUTOSTART (Teresa)
2021-07-16drivers: watchdog: wdt-uclass: Use IS_ENABLED for WATCHDOG_AUTOSTARTTeresa Remmet1-1/+1
There is no separate SPL/TPL config for WATCHDOG_AUTOSTART. So use IS_ENABLED instead of CONFIG_IS_ENABLED to make watchdog working in SPL again. Fixes: 830d29ac3721 ("watchdog: Allow to use CONFIG_WDT without starting watchdog") Signed-off-by: Teresa Remmet <t.remmet@phytec.de> Reviewed-by: Stefan Roese <sr@denx.de>
2021-07-16driver: watchdog: reset watchdog in designware_wdt_stop() functionMengLi1-4/+15
In uboot command line environment, watchdog is not able to be stopped with below commands: SOCFPGA_STRATIX10 # wdt dev watchdog@ffd00200 SOCFPGA_STRATIX10 # wdt stop Refer to watchdog driver in linux kernel, it is also need to reset watchdog after disable it so that the disable action takes effect. Signed-off-by: Meng Li <Meng.Li@windriver.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Sean Anderson <sean.anderson@seco.com>
2021-07-16clk: stm32mp1: add support of SYSCFG clockPatrick Delaunay1-0/+1
Add the support of SYSCFG clock used by syscon driver to prepare the clock management of STM32MP_SYSCON_SYSCFG. This clock is already defined in kernel device tree, stm32mp151.dtsi but not yet supported in the syscon driver: syscfg: syscon@50020000 { compatible = "st,stm32mp157-syscfg", "syscon"; reg = <0x50020000 0x400>; clocks = <&rcc SYSCFG>; }; It is safe to support this clock in U-Boot driver with RCC_MC_APB3ENSETR, Bit 11 SYSCFGEN: SYSCFG peripheral clocks enable. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-07-15rtc: m41t62: fix wrong register use for set/reset ST bitMax Yang1-2/+2
Fix wrong register use when set/reset ST bit. ST bit is in register M41T62_REG_SEC not in M41T62_REG_ALARM_HOUR. I have not actually tested this. But this seemed buggy from inspection. Fixes: 9bbe210512c4539 ("rtc: m41t62: add oscillator fail bit reset support") Signed-off-by: Max Yang <max.yang@deltaww.com>
2021-07-15clk: Detect failure to set defaultsSimon Glass1-1/+5
When the default clocks cannot be set, the clock is silently probed and the error is ignored. This is incorrect, since having the clocks at the correct speed may be important for operation of the system. Fix it by checking the return code. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-07-15pinctrl: Avoid coverity warning when checking widthSimon Glass1-0/+1
The width is set up in single_of_to_plat() and can only have three values, all of which result in a non-zero divisor. Add a comment. Signed-off-by: Simon Glass <sjg@chromium.org> Reported-by: Coverity (CID: 331154)
2021-07-15sandbox: cros_ec: Update error handling when reading matrixSimon Glass1-5/+7
At present the return value of ofnode_get_property() is not checked, which causes a coverity warning. While we are here, use logging for the errors. Signed-off-by: Simon Glass <sjg@chromium.org> Reported-by: Coverity (CID: 331157)
2021-07-15dm: core: Check uclass_get() return value when dumpingSimon Glass1-3/+4
Update dm_dump_drivers() to use the return value from uclass_get() to check the validity of uc. This is equivalent and should be more attractive to Coverity. Signed-off-by: Simon Glass <sjg@chromium.org> Reported-by: Coverity (CID: 316601)
2021-07-15reset: Avoid a warning in devm_regmap_init()Simon Glass1-0/+1
The devres_alloc() function is intended to avoid the need for freeing memory, although in practice it may not be enabled, thus leading to a true leak. Nevertheless this is intended. Add a comment. Signed-off-by: Simon Glass <sjg@chromium.org> Reported-by: Coverity (CID: 312951)
2021-07-15reset: Avoid a warning in devm_reset_bulk_get_by_node()Simon Glass1-0/+2
The devres_alloc() function is intended to avoid the need for freeing memory, although in practice it may not be enabled, thus leading to a true leak. Nevertheless this is intended. Add a comment to explain this. Signed-off-by: Simon Glass <sjg@chromium.org> Reported-by: Coverity (CID: 312952)
2021-07-15video: Check return value in pwm_backlight_of_to_plat()Simon Glass1-2/+4
This cannot actually fail, but check the value anyway to keep coverity happy. Signed-off-by: Simon Glass <sjg@chromium.org> Reported-by: Coverity (CID: 316351)
2021-07-15sandbox: net: Ensure host name is always a valid stringSimon Glass1-1/+1
At present if ifname is exactly IFNAMSIZ characters then it will result in an unterminated string. Fix this by using strlcpy() instead. Signed-off-by: Simon Glass <sjg@chromium.org> Reported-by: Coverity (CID: 316358) Acked-by: Ramon Fried <rfried.dev@gmail.com>
2021-07-15Merge https://source.denx.de/u-boot/custodians/u-boot-x86WIP/15Jul2021Tom Rini3-8/+37
- x86: various improvements made in getting Chromium OS verified boot running on top of coreboot, booting into U-Boot.
2021-07-15power: pmic: tps65941: Add compatible for LP876441Gowtham Tammana1-0/+1
TI J7200 EVM has lp876441 pmic that is similar to tps65941. Add support for same with existing driver with new compatible. Signed-off-by: Gowtham Tammana <g-tammana@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Acked-by: Jaehoon Chung <jh80.chung@samsung.com> Link: https://lore.kernel.org/r/20210714205300.17424-2-g-tammana@ti.com
2021-07-15remoteproc: pru: Add support for various PRU cores on K3 AM65x SoCsKeerthy3-0/+473
The K3 AM65x family of SoCs have the next generation of the PRU-ICSS processor subsystem, commonly referred to as ICSSG. Each ICSSG processor subsystem on AM65x SR1.0 contains two primary PRU cores and two new auxiliary PRU cores called RTUs. The AM65x SR2.0 SoCs have a revised ICSSG IP that is based off the subsequent IP revision used on J721E SoCs. This IP instance has two new custom auxiliary PRU cores called Transmit PRUs (Tx_PRUs) in addition to the existing PRUs and RTUs. Each RTU and Tx_PRU cores have their own dedicated IRAM (smaller than a PRU), Control and debug feature sets, but is different in terms of sub-modules integrated around it and does not have the full capabilities associated with a PRU core. The RTU core is typically used to aid a PRU core in accelerating data transfers, while the Tx_PRU cores is normally used to control the TX L2 FIFO if enabled in Ethernet applications. Both can also be used to run independent applications. The RTU and Tx_PRU cores though share the same Data RAMs as the PRU cores, so the memories have to be partitioned carefully between different applications. The new cores also support a new sub-module called Task Manager to support two different context thread executions. The driver currently supports the AM65xx SoC Signed-off-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210622063431.3151-3-lokeshvutla@ti.com
2021-07-15soc: ti: pruss: Add a platform driver for PRUSS in TI SoCsKeerthy3-0/+229
The Programmable Real-Time Unit - Industrial Communication Subsystem (PRU-ICSS) is present of various TI SoCs such as AM335x or AM437x or the AM654x family. Each SoC can have one or more PRUSS instances that may or may not be identical. The PRUSS consists of dual 32-bit RISC cores called the Programmable Real-Time Units (PRUs), some shared, data and instruction memories, some internal peripheral modules, and an interrupt controller. The programmable nature of the PRUs provide flexibility to implement custom peripheral interfaces, fast real-time responses, or specialized data handling. Add support for pruss driver. Currently am654x family is supported. Signed-off-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210622063431.3151-2-lokeshvutla@ti.com
2021-07-15am335x, guardian: software update available status is stored in AM3352 RTC ↵Gireesh Hiremath3-3/+89
scracth register RTC second scratch register[32-bit]: -zero byte hold boot count value -first byte hold update available state -second byte hold version -third byte hold magic number Signed-off-by: Gireesh Hiremath <Gireesh.Hiremath@in.bosch.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210611161350.2141-17-Gireesh.Hiremath@in.bosch.com Gbp-Pq: Topic apertis/guardian Gbp-Pq: Name am335x-guardian-software-update-available-status-is-store.patch
2021-07-15drivers: video: hx8238 fix build bugGireesh Hiremath2-3/+3
update panel driver hx8238 fix build bug Signed-off-by: Gireesh Hiremath <Gireesh.Hiremath@in.bosch.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210611161350.2141-15-Gireesh.Hiremath@in.bosch.com
2021-07-15tpm: cr50: Drop unnecessary coral headersSimon Glass1-2/+0
These headers are not actually used. Drop them so that this driver can be used by other boards, e.g. coreboot. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-07-15spi: ich: Don't require the PCHSimon Glass1-2/+2
When booting from coreboot we may not have a PCH driver available. The SPI driver can operate without the PCH but currently complains in this case. Update it to continue to work normally. The only missing feature is memory-mapping of SPI-flash contents, which is not essential. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2021-07-15x86: pci: Allow binding of some devices before relocationSimon Glass1-1/+32
At present only bridge devices are bound before relocation, to save space in pre-relocation memory. In some cases we do actually want to bind a device, e.g. because it provides the console UART. Add a devicetree binding to support this. Use the PCI_VENDEV() macro to encode the cell value. This is present in U-Boot but not used, so move it to the binding header-file. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-07-15pci: Use const for pci_find_device_id() etc.Simon Glass1-3/+3
These functions don't modify the device-ID struct that is passed in, so mark the argument as const, so the data structure can be declared that way. This allows it to be placed in the rodata section. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-07-15mmc: mmc_get_op_cond: Allow quiet detection of eMMCPali Rohár1-3/+4
Add a new 'quiet' argument to mmc_get_op_cond() function which avoids printing error message when SD/eMMC card is not detected. Espressobin and mx6cuboxi boards use this function for detecting presence of eMMC and therefore it is expected and normal that eMMC does not have to be connected. So error message "Card did not respond to voltage select!" should be skipped in this case as it is not an error. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de> Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-07-15arm: mvebu: armada-3720: remove unused config optionMarek Behún1-0/+1
The config option CONFIG_DEBUG_UART_CLOCK is not used by Armada 3720's serial driver (it wasn't even before the recent update of that driver). Even if it was used, the value was incorrect (the frequency of the clock is 25 MHz, not 25.8048 MHz). Remove it from config files and set the default value to 0. Signed-off-by: Marek Behún <marek.behun@nic.cz> Cc: Stefan Roese <sr@denx.de> Cc: Pali Rohár <pali@kernel.org> Reviewed-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
2021-07-15arm: a37xx: pci: Fix typo in commentPali Rohár1-1/+1
Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-by: Stefan Roese <sr@denx.de>
2021-07-15arm: a37xx: pci: Extend validation for PCIe resources and oubound windowsPali Rohár1-3/+4
Remapped address of PCIe outbound window may have set only bits from the mask. Add additional check that remapped address which is calculated from PCIe bus address specified in DTS file is valid. Remove also useless clearing of low 16 bits in win_mask. As win_size is power of two and is at least 0x10000 it means that it always has zero low 16 bits. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-by: Stefan Roese <sr@denx.de>
2021-07-14lib: move rtc-lib.c to libHeinrich Schuchardt2-78/+0
Function rtc_to_tm() is needed for FAT file system support even if we don't have a real time clock. So move it from drivers/ to lib/. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-07-14usb: musb-new: Add glue driver for ST-Ericsson Ux500Stephan Gerhold4-2/+191
The ST-Ericsson DB8500 SoC contains a MUSB OTG controller which supports both host and gadget mode. For some reason there is nothing special about it - add a simple glue driver for Ux500 that literally just sets up MUSB together with a generic PHY. There are no SoC-specific registers etc needed to make USB work. The new Ux500 glue driver is only tested to work with DM_USB and DM_USB_GADGET. Both host and gadget mode work fine on the u8500 "stemmy" board that is already present in U-Boot. Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
2021-07-14phy: Add driver for ST-Ericsson AB8500 USB PHYStephan Gerhold3-0/+59
The AB8500 PMIC contains an USB PHY that needs to be set up in device or host mode to make USB work properly. Add a simple driver for the generic PHY uclass that allows enabling it. The if (CONFIG_IS_ENABLED(USB_MUSB_HOST)) might be a bit strange. The USB PHY must be configured in either host or device mode and somehow the USB PHY driver must be made aware of the mode. Actually, the MUSB driver used together with this PHY does not support dynamic selection of host/device mode in U-Boot at the moment. Therefore, one very simple approach that works fine is to select the mode to configure at compile time. When the MUSB driver is configured in host mode the PHY is configured in host mode, and similarly when the MUSB driver is configured in device/gadget mode. Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-07-14power: pmic: Add driver for ST-Ericsson AB8500 via PRCMUStephan Gerhold3-0/+279
All devices based on ST-Ericsson Ux500 use a PMIC similar to AB8500 (Analog Baseband). There is AB8500, AB8505, AB9540 and AB8540 although in practice only AB8500 and AB8505 are relevant since the platforms with AB9540 and AB8540 were cancelled and never used in production. In general, the AB8500 PMIC uses I2C as control interface, where the different register banks are represented as separate I2C devices. However, in practice AB8500 is always connected to a special I2C bus on the DB8500 SoC that is controlled by the power/reset/clock management unit (PRCMU) firmware. Add a simple driver that allows reading/writing registers of the AB8500 PMIC. The driver directly accesses registers from the PRCMU parent device (represented by syscon in U-Boot). Abstracting it further (e.g. with the i2c uclass) would not provide any advantage because the PRCMU I2C bus is always just connected to AB8500 and vice-versa. The ab8500.h header is mostly taken as-is from Linux (with some minor adjustments) to allow using similar code in both Linux and U-Boot. Cc: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-07-14pci: uniphier: Add UniPhier PCIe controller driverKunihiko Hayashi3-0/+435
Add PCIe driver for UniPhier SoCs. This PCIe controller is based on Synopsys DesignWare Core IP. This version doesn't apply common DW functions because supported controller doesn't have unroll version of iATU. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
2021-07-14phy: socionext: Add UniPhier PCIe PHY driverKunihiko Hayashi5-0/+80
Add PCIe PHY driver support for Pro5, LD20 and PXs3 SoCs. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
2021-07-14reset: uniphier: Add PCIe reset entryKunihiko Hayashi1-0/+3
Add reset control for PCIe controller on each SoC. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
2021-07-14clk: uniphier: Add PCIe clock entryKunihiko Hayashi1-0/+3
Add clock control for PCIe controller on each SoC. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
2021-07-14misc: i2c_eeprom: Add atmel,24c01 to the listMarek Vasut1-0/+1
Linux kernel binding is using atmel,24c01 compatible string. On the other hand there is atmel,24c01a which is not listed in the kernel. Add compatible string without "a" suffix to be compatible with Linux kernel binding. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Heiko Schocher <hs@denx.de> Cc: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Heiko Schocher <hs@denx.de>
2021-07-14timer: nomadik-mtu: Use dev_read_addr_ptr()Stephan Gerhold1-5/+2
Simplify the code a bit by using dev_read_addr_ptr() instead of dev_read_addr(). This avoids having to cast explicitly to the struct nomadik_mtu_regs. Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
2021-07-14gpio: Add driver for Nomadik GPIOStephan Gerhold3-0/+134
Nomadik GPIO is a fairly simple GPIO module used in the ST-Ericsson Ux500 SoCs (and some older Nomadik SoCs). It uses registers where each GPIO is represented as a single bit, plus "set" and "clear" registers that allow updating the state without having to read the existing state. The driver implements support for it for use together with DM_GPIO and the existing ste-dbx5x0.dtsi device tree. Cc: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
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