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2021-05-17Merge https://source.denx.de/u-boot/custodians/u-boot-marvellWIP/17May2021Tom Rini2-17/+87
- Add base support for Marvell OcteonTX2 CN9130 DB (mostly done by Kostya) - Sync Armada 8k MMU setup with Marvell version (misc Marvell authors) - spi: kirkwood: Some fixes especially for baudrate generation (misc Marvell authors) - mvebu: x530: Reduce SPL image size (Stefan) - Rename "rx_training" to "mvebu_comphy_rx_training" (Stefan)
2021-05-16usb: dwc3-generic: Disable host driver definition if gadget onlyKunihiko Hayashi1-1/+2
Even if only USB gadget is defined, dwc3 generic driver enables a definition and probe/remove functions for host driver. This enables the definition if USB_HOST is enabled only. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
2021-05-16usb: musb-new: Extend and move Allwinner quirk into KconfigAndre Przywara2-2/+11
All newer Allwinner SoCs (since about 2013) miss the CONFIGDATA register in their MUSB implementation, so they need a quirk to hardcode this. Currently this quirk depends on listing the SoCs affected in musb_reg.h, which means that this list needs to grow with every new chip. Move the quirk feature into Kconfig, next to PIO_ONLY, and change the default to y (for Allwinner builds), while listing the early implementations as exceptions. This fixes USB peripheral operation on some newer SoCs, which were not explicitly listed before. Tested on H6, H616, R40 (which were broken before), and also on the H5 and A20, for regressions. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-05-16pcie: designware: mvebu: do not configure ATU for IO when not usedMarcin Wojtas1-12/+25
The pcie_dw_mvebu configure ATU regions for memory, configuration and IO space types. However the latter is not obligatory and when not specified in the device tree, causes wrong ATU configuration. Fix that by adding a dependency on the detected PCIE regions count. Signed-off-by: Marcin Wojtas <mw@semihalf.com> Reviewed-on: https://sj1git1.cavium.com/18136 Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Tested-by: Kostya Porotchkin <kostap@marvell.com>
2021-05-16spi: kirkwood: prevent limiting speed to 0Grzegorz Jaszczyk1-1/+1
After commit 1fe929ed497bcc8975be8d37383ebafd22b99dd2 ("spi: kirkwood: prevent configuring speed exceeding max controller freq") the spi frequency could be set to 0 on platform where spi-max-frequency is not defined (e.g. on armada-388-gp). Prevent limiting speed in mentioned cases. Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Tested-by: Kostya Porotchkin <kostap@marvell.com> Reviewed-by: Marcin Wojtas <marcin@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2021-05-16spi: kirkwood: prevent configuring speed exceeding max controller freqMarcin Wojtas1-0/+7
This patch adds a limitation in the kirkwood_spi driver set_speed hook, which prevents setting too high transfer speed. Signed-off-by: Marcin Wojtas <mw@semihalf.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Tested-by: Kostya Porotchkin <kostap@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2021-05-16spi: kirkwood: support extended baud ratesKen Ma1-5/+55
The Armada SoC family implementation of this SPI hardware module has extended the configuration register to allow for a wider range of SPI clock rates. Specifically the Serial Baud Rate Pre-selection bits in the SPI Interface Configuration Register now also use bits 6 and 7 as well. Modify the baud rate calculation to handle these differences for the Armada case. Potentially a baud rate can be setup using a number of different pre-scalar and scalar combinations. This code tries all possible pre-scalar divisors (8 in total) to try and find the most accurate set. Signed-off-by: Ken Ma <make@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2021-05-14Merge tag 'u-boot-amlogic-20210514' of ↵Tom Rini2-5/+21
https://source.denx.de/u-boot/custodians/u-boot-amlogic - dts: add missing -u-boot.dtsi to enable HDMI on Beelink GTKing/King-Pro - usb: dwc3-meson-g12a: skip phy on -ENODATA aswell - net: dwmac_meson8b: do not set TX delay in TXID & RXID - net: designware: meson8b: add g12a compatible
2021-05-14net: designware: meson8b: add g12a compatibleNeil Armstrong1-0/+1
Add support for the Meson G12A dwmac glue compatible needed after Linux 5.12 sync. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2021-05-14net: dwmac_meson8b: do not set TX delay in TXID & RXIDNeil Armstrong1-4/+19
When the PHY interface is set as TXID & RXID, the delays should be taken from DT, but first they should not be hardcoded since the PHY driver will set them. Fixes: 798424e857 ("net: designware: add Amlogic Meson8b & later glue driver") Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-05-14usb: dwc3-meson-g12a: skip phy on -ENODATA aswellNeil Armstrong1-1/+1
If the PHY isn't specified in the DT, -ENODATA means it should be skipped, handle it like -ENOENT. With that, devices without USB3 supported can have USB working (Odroid-HC4). Fixes: adb049abf7 ("usb: dwc3: Add Meson G12A USB Glue") Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2021-05-14pwm: sifive: make set_config() and set_enable() work properlyVincent Chen1-10/+11
The pwm_sifive_set_config() and pwm_sifive_set_enable() cannot work properly due to the wrong implementations. It will cause the u-boot PWM command to not work as expected. The bugs will be resolved in this patch. Signed-off-by: Vincent Chen <vincent.chen@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
2021-05-14clk: Add support for the k210 clock driver pre-relocationSean Anderson1-4/+10
Variables which had previously been stored in .bss are moved to .data. In addition, probed needs to be reset when the clock driver is re-bound post-relocation. Signed-off-by: Sean Anderson <seanga2@gmail.com>
2021-05-14clk: k210: Move the clint clock to under aclkSean Anderson1-1/+1
No other (real) clocks have the cpu clock as their parent; instead they are children of aclk. Move the clint clock under aclk to match them. Signed-off-by: Sean Anderson <seanga2@gmail.com>
2021-05-14clk: k210: Remove k210_register_pllSean Anderson2-28/+3
This simplifies the PLL creation process, since we don't have to pass all the parameters individually. Signed-off-by: Sean Anderson <seanga2@gmail.com>
2021-05-14clk: k210: Fix PLL enable always getting takenSean Anderson1-1/+2
This conditional always evaluated as false, regardless of the value of reg. Fix it so that it properly tests the bits in the PLL register. Also test PLL_EN, now that we set it. Reported-by: Damien Le Moal <Damien.LeMoal@wdc.com> Signed-off-by: Sean Anderson <seanga2@gmail.com>
2021-05-14clk: k210: Fix PLLs not being enabledSean Anderson1-0/+2
After starting or setting the rate of a PLL, the enable bit must be set. This fixes a bug where the AI ram would not be accessible, because it requires PLL1 to be running. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Damien Le Moal <damien.lemoal@wdc.com>
2021-05-14clk: Warn on failure to assign rateSean Anderson1-4/+7
If the user/dev explicitly requests a clock be assigned a certain rate, then we should warn them if we can't do it. This makes it clear if the clock is running at the default rate. Signed-off-by: Sean Anderson <seanga2@gmail.com>
2021-05-13w1: replace dt detection by automatic detectionKory Maincent4-33/+87
This patch changes the functioning of the detection of w1 devices. The old way was a comparison between detected w1 and the ones described in the device tree. Now it will just look for the driver matching the family id of the w1 detected. The patch is inspired from Maxime Ripard code. Signed-off-by: Kory Maincent <kory.maincent@bootlin.com> Reviewed-by: Maxime Ripard <maxime@cerno.tech>
2021-05-12Merge tag 'ti-v2021.07-rc3' of ↵WIP/12May2021Tom Rini83-23478/+47964
https://source.denx.de/u-boot/custodians/u-boot-ti - Initial support for AM64 EVM and SK - K3 DDR driver unification for J7 and AM64 platforms. - Minor fixes for TI clock driver
2021-05-12net: ti: am65-cpsw-nuss: Add a new compatible for AM64Vignesh Raghavendra1-0/+1
Add a new compatible to support AM64 SoC Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2021-05-12net: ti: am65-cpsw-nuss: Don't cache disabled port IDVignesh Raghavendra1-1/+1
Currently driver may end up caching disabled port ID as active interface. Fix this by bailing out earlier in case port is marked disabled in the DT. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2021-05-12net: ti: am65-cpsw-nuss: Prepare to support non primary ext portVignesh Raghavendra1-1/+1
CPSW NUSS IP on K3 SoCs can have more than one external port (upto 8) Therefore increase AM65_CPSW_CPSWNU_MAX_PORTS to 9 (8 ext + 1 Root port) as preparation to allow any one of the 8 ports to be used as ethernet interface in U-Boot. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2021-05-12dma: ti: k3-udma: Add BCDMA and PKTDMA supportVignesh Raghavendra1-64/+939
Sync BCDMA and PKTDMA support from Kernel for AM64 SoC Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2021-05-12dma: ti: k3-psil-am64: Add AM64 PSIL endpoint dataVignesh Raghavendra4-0/+160
Add AM64 SoC specific channel mapping and endpoint data. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2021-05-12dma: ti: k3-psil: Extend PSIL EP data extension for AM64Vignesh Raghavendra1-0/+16
Extend PSIL EP data to include AM64 DMA specific information Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2021-05-12dma: ti: k3-psil-am654: Drop unused PSIL EP static dataVignesh Raghavendra1-25/+7
ICSSG Ethernet driver uses two src threads per port (one per slice). Similarly CPSW uses one src thread. Drop PSIL EP static data for other src threads in order to reduce R5 SPL footprint. This makes AM65x board bootable again. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2021-05-12soc: ti: k3-navss-ringacc: Remove unused ring modesVignesh Raghavendra1-304/+7
With AM64x supporting only K3_NAV_RINGACC_RING_MODE_RING or the exposed ring mode, all other K3 SoCs have also been moved to this common baseline. Therefore drop other modes such as K3_NAV_RINGACC_RING_MODE_MESSAGE (and proxy) to save on SPL footprint. There is a saving of ~800 bytes with this change for am65x_evm_r5_defconfig. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
2021-05-12soc: ti: k3-navss-ringacc: Add AM64 ringacc supportVignesh Raghavendra1-5/+268
AM64 dual mode rings are modeled as pair of Rings objects which has common configuration and memory buffer, but separate real-time control register sets for each direction mem2dev (forward) and dev2mem (reverse). AM64 rings must be requested only using k3_ringacc_request_rings_pair(), and forward ring must always be initialized/configured. After this any other Ringacc APIs can be used without any callers changes. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2021-05-12firmware: ti_sci: Update ti_sci_cmd_rm_udmap_tx_ch_cfg() API to the latestVignesh Raghavendra2-0/+21
Update struct ti_sci_msg_rm_udmap_tx_ch_cfg_req to latest ABI to support AM64x BCDMA Block copy channels. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2021-05-12soc: ti: k3-socinfo: Add entry for AM64X SoC familyLokesh Vutla1-0/+4
Add support for AM64 SoC identification. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2021-05-12ram: k3-ddrss: Enable vtt regulator if presentLokesh Vutla1-0/+14
Attempt to get and enable a vtt regulator if one is provided from the dts. If we do not find one, continue as not all platforms have this. Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12ram: k3-ddrss: Introduce support for AM642 SoCsDave Gerlach20-0/+23490
Introduce support for the AM64 DDRSS controller which uses the 16bit variation of the controller. This controller shares much functionality with the existing J721e support, so this patch introduces only the new code needed for am64 specific support from "_16bit_" files with headers under "16bit/" include path/. Also add a CONFIG_K3_AM64_DDRSS option to the choice required for use with CONFIG_K3_DDRSS to allow selecting AM64 support. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12ram: k3-ddrss: Introduce common driver with J7 SoC supportDave Gerlach27-3849/+3675
Introduce a new version of the ddr driver which has the ability to support different variations of the controller. Also introduce support for the 32bit variation of the controller which is what was already supported by the previous version used for J721e and J7200. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12ram: k3-ddrss: Introduce top-level CONFIG_K3_DDRSSDave Gerlach2-2/+11
Create a new CONFIG_K3_DDRSS option to select the common parts of the k3-ddrss driver. Also introduce a choice that depends on the top level option to select CONFIG_K3_J721E_DDRSS for j721e support, and update corresponding Kconfig as required. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12ram: k3-j721e: Rename to k3-ddrssDave Gerlach20-1/+1
Rename the k3-j721e folder under drivers/ram to k3-ddrss in preparation of introducing additional support for other platforms to the same driver. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12ram: k3-j721e: lpddr4_ctl_regs: Fix checkpatch issue for typesDave Gerlach1-1514/+1514
Use Linux style u32 instead of uint32_t. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12ram: k3-j721e: lpddr4_pi_macros: Fix indentation issuesDave Gerlach1-2801/+2801
Fix the indentation for certain macros to be consistent with the other macros in the file, as the existing indentation does not make sense in many places. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12ram: k3-j721e: lpddr4_phy_core_macros: Fix indentation issuesDave Gerlach1-694/+694
Fix the indentation for certain macros to be consistent with the other macros in the file, as the existing indentation does not make sense in many places. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12ram: k3-j721e: lpddr4_ddr_controller_macros: Fix indentation issuesDave Gerlach1-3681/+3681
Fix the indentation for certain macros to be consistent with the other macros in the file, as the existing indentation does not make sense in many places. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12ram: k3-j721e: lpddr4_data_slice_3_macros: Fix indentation issuesDave Gerlach1-677/+677
Fix the indentation for certain macros to be consistent with the other macros in the file, as the existing indentation does not make sense in many places. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12ram: k3-j721e: lpddr4_data_slice_2_macros: Fix indentation issuesDave Gerlach1-677/+677
Fix the indentation for certain macros to be consistent with the other macros in the file, as the existing indentation does not make sense in many places. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12ram: k3-j721e: lpddr4_data_slice_1_macros: Fix indentation issuesDave Gerlach1-677/+677
Fix the indentation for certain macros to be consistent with the other macros in the file, as the existing indentation does not make sense in many places. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12ram: k3-j721e: lpddr4_data_slice_0_macros: Fix indentation issuesDave Gerlach1-717/+717
Fix the indentation for certain macros to be consistent with the other macros in the file, as the existing indentation does not make sense in many places. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12ram: k3-j721e: lpddr4_address_slice_0_macros: Fix indentation issuesDave Gerlach1-167/+167
Fix the indentation for certain macros to be consistent with the other macros in the file, as the existing indentation does not make sense in many places. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12mailbox: k3-sec-proxy: Extend valid thread IDsDave Gerlach1-9/+1
AM64x uses a different thread mapping that existing K3 SoCs, so update the valid thread ID list to include those used for AM64x. Also remove the comment identifying the purpose of each thread ID. The purpose of the thread ID is specified when describing the threads in the device tree and the same ID can mean different things on different SoCs, so the comment is not useful. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12mmc: sdhci_am654: Add Support for TI's AM642 SoCDave Gerlach1-0/+18
Add support for the controller present on the AM642 SoC. There are instances: sdhci0: 8bit bus width, max 400 MBps sdhci1: 4bit bus width, max 100 MBps Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12Revert "fdt: translate address if #size-cells = <0>"Dario Binacchi5-24/+13
This reverts commit d64b9cdcd475eb7f07b49741ded87e24dae4a5fc. As pointed by [1] and [2], the reverted patch made every DT 'reg' property translatable. What the patch was trying to fix was fixed in a different way from previously submitted patches which instead of correcting the generic address translation function fixed the issue with appropriate platform code. [1] https://patchwork.ozlabs.org/project/uboot/patch/1614324949-61314-1-git-send-email-bmeng.cn@gmail.com/ [2] https://lore.kernel.org/linux-clk/20210402192054.7934-1-dariobin@libero.it/T/ Signed-off-by: Dario Binacchi <dariobin@libero.it> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-05-12clk: ti: am3-dpll: use custom API for memory accessDario Binacchi1-33/+53
Using the custom TI functions required not only replacing common memory access functions but also rewriting the routines used to set bypass and lock states. As for readl() and writel(), they also required the address of the register to be accessed, a parameter that is hidden by the TI clk module. Signed-off-by: Dario Binacchi <dariobin@libero.it>
2021-05-12clk: ti: gate: use custom API for memory accessDario Binacchi1-11/+12
Replaces the common memory access functions used by the driver with the ones exported from the TI clk module. Signed-off-by: Dario Binacchi <dariobin@libero.it>
generated by cgit v1.1 at 2024-08-12 09:30:18 +0000