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2022-04-09scsi: call device_probe() after scanningAKASHI Takahiro1-0/+5
Every time a scsi bus/port is scanned and a new block device is detected, we want to call device_probe() as it will give us a chance to run additional post-processings for some purposes. In particular, support for creating partitions on a device will be added. Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-04-08arm: Remove unused ep93xx codeTom Rini5-819/+0
There are no platforms for this architecture anymore, remove unused code. Signed-off-by: Tom Rini <trini@konsulko.com>
2022-04-08net: Remove uli526x driverTom Rini2-997/+0
This driver is not enabled by any board and not converted to DM_ETH. Remove. Signed-off-by: Tom Rini <trini@konsulko.com>
2022-04-08net: Remove ns8382x driverTom Rini2-855/+0
This driver is not enabled by any board and not converted to DM_ETH. Remove. Signed-off-by: Tom Rini <trini@konsulko.com>
2022-04-08net: Remove natsemi driverTom Rini2-884/+0
This driver is not enabled by any board and not converted to DM_ETH. Remove. Signed-off-by: Tom Rini <trini@konsulko.com>
2022-04-08net: Remove lan91c96 driverTom Rini3-1416/+0
This driver is not enabled by any board and not converted to DM_ETH. Remove. Signed-off-by: Tom Rini <trini@konsulko.com>
2022-04-08net: Remove ftmac110 driverTom Rini3-667/+0
This driver is not enabled by any board and not converted to DM_ETH. Remove. Signed-off-by: Tom Rini <trini@konsulko.com>
2022-04-08net: Remove dnet driverTom Rini3-562/+0
This driver is not enabled by any board and not converted to DM_ETH. Remove. Signed-off-by: Tom Rini <trini@konsulko.com>
2022-04-08net: Remove cs8900 driverTom Rini3-569/+0
This driver is not enabled by any board and not converted to DM_ETH. Remove. Signed-off-by: Tom Rini <trini@konsulko.com>
2022-04-08net: Remove ax88180 driverTom Rini3-1152/+0
This driver is not enabled by any board and not converted to DM_ETH. Remove. Signed-off-by: Tom Rini <trini@konsulko.com>
2022-04-08net: Remove armada100_fec driverTom Rini3-948/+0
This driver is not enabled by any board and not converted to DM_ETH. Remove. Signed-off-by: Tom Rini <trini@konsulko.com>
2022-04-08Convert CONFIG_DIMM_SLOTS_PER_CTLR to KconfigTom Rini1-0/+4
This converts the following to Kconfig: CONFIG_DIMM_SLOTS_PER_CTLR Signed-off-by: Tom Rini <trini@konsulko.com>
2022-04-08spi: cadence_qspi: Migrate CONFIG_CQSPI_REF_CLK to KconfigTom Rini3-1/+12
This is a little tricky since SoCFPGA has code to determine this as runtime. Introduce a guard variable for platforms to select if they have a static value to use. Then for ARCH_SOCFPGA, call cm_get_qspi_controller_clk_hz() and otherwise continue the previous behavior. Cc: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Tom Rini <trini@konsulko.com>
2022-04-08Convert CONFIG_SH_SCIF_CLK_FREQ to KconfigTom Rini1-0/+5
This converts the following to Kconfig: CONFIG_SH_SCIF_CLK_FREQ Signed-off-by: Tom Rini <trini@konsulko.com>
2022-04-08Convert CONFIG_CONS_SCIF0 et al to KconfigTom Rini1-0/+21
This converts the following to Kconfig: CONFIG_CONS_SCIF0 CONFIG_CONS_SCIF1 CONFIG_CONS_SCIF2 CONFIG_CONS_SCIF4 CONFIG_CONS_SCIFA0 Signed-off-by: Tom Rini <trini@konsulko.com>
2022-04-06dm: blk: Expand iteration and add testsWIP/2022-04-06-various-verified-boot-bugfixesSimon Glass1-0/+24
Add some functions which support iteration before probing. Also add tests for the functions. Signed-off-by: Simon Glass <sjg@chromium.org>
2022-04-06spi: Avoid checking console in SPLSimon Glass1-1/+1
When SPI flash is used in SPL there is no console, so ctrlc() cannot be called. Add a condition to fix this. Signed-off-by: Simon Glass <sjg@chromium.org>
2022-04-05power: pmic: Provide DM_PMIC support for tps65217 driverLukasz Majewski1-0/+82
The tps65217 PMIC driver is used with am335x SoC based designs. It is used in the SPL (MLO) as well, so the DM conversion only is for u-boot proper. This driver only allows simple reading/writing/dumping of the content of its registers and requires the DM_I2C for proper operation. Signed-off-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2022-04-05power: Rename CONFIG_POWER_TPS65217 with CONFIG_PMIC_TPS65217Lukasz Majewski2-1/+9
Up till now the CONFIG_POWER_TPS65217 has been defined in several header files for am335x SoC. This patch renames it to CONFIG_PMIC_TPS65217, which better reflects the role of this IC circuit. Moreover, new CONFIG_PMIC_TPS65217 has been introduced in Kconfig to be used with boards, which both support DM_PMIC and DM_I2C. Signed-off-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> [trini: Migrate all other platforms as well] Signed-off-by: Tom Rini <trini@konsulko.com>
2022-04-05Merge branch '2022-04-04-platform-updates'Tom Rini3-8/+198
- Updates for exynos78x0 and TI K3 platforms
2022-04-05Merge tag 'xilinx-for-v2022.07-rc1-v2' of ↵WIP/05Apr2022Tom Rini12-38/+427
https://source.denx.de/u-boot/custodians/u-boot-microblaze Xilinx changes for v2022.07-rc1 v2 xilinx: - Allow booting bigger kernels till 100MB zynqmp: - DT updates (reset IDs) - Remove unneeded low level uart initialization from psu_init* - Enable PWM features - Add support for 1EG device serial_zynq: - Change fifo behavior in DEBUG mode zynq_sdhci: - Fix BASECLK setting calculation clk_zynqmp: - Add support for showing video clock gpio: - Update slg driver to handle DT flags net: - Update ethernet_id code to support also DM_ETH_PHY - Add support for DM_ETH_PHY in gem driver - Enable dynamic mode for SGMII config in gem driver pwm: - Add driver for cadence PWM versal: - Add support for reserved memory firmware: - Handle PD enabling for SPL - Add support for IOUSLCR SGMII configurations include: - Sync phy.h with Linux - Update xilinx power domain dt binding headers
2022-04-05net: zynq_gem: Add SGMII dynamic config supportT Karthik Reddy1-0/+46
Add support for SGMII dynamic configuration which will takes care of configuring SGMII in the GEM secure (GEM_CLK_CTRL) configuration register. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/a8915186e44015959978d080a31de652f544cd4a.1648631275.git.michal.simek@xilinx.com
2022-04-05firmware: firmware-zynqmp: Add zynqmp_pm_set_gem_config apiT Karthik Reddy1-0/+13
Add zynqmp_pm_set_gem_config() api to configure GEM secure registers. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/f69e32355c6a6be7d2780663353c52757530207d.1648631275.git.michal.simek@xilinx.com
2022-04-05gpio: slg7xl45106: Update gpio desc flags from DTT Karthik Reddy1-0/+2
In current slg7xl45106 gpio driver xlate() function we are not updating gpio flags from DT. Read the given flag from DT and update the gpio desc flags variable with required gpio direction state. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/a8d7b4799337bd99f61ace509889f02b192a9414.1648631275.git.michal.simek@xilinx.com
2022-04-05net: zynq_gem: Move ethernet info print statementT Karthik Reddy1-4/+4
As we are not reading the PHY address in case of CONFIG_ETH_PHY in plat function, phy address always prints as -1. So move the ethernet info print statement to probe function, to display proper phy address. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/f6efc6719d767b1bebe65987c22c6d52329f4225.1648631275.git.michal.simek@xilinx.com
2022-04-05net: phy: Avoid phy gpio reset sequence if DM_ETH_PHY is enabledT Karthik Reddy1-19/+26
If DM_ETH_PHY config is enabled PHY gpio reset is taken care by the eth-phy-uclass driver, so use the PHY gpio reset functionality from ethernet_id file when this config is disabled to reset the PHY. Use debug() print instead of dev_err() to avoid warning incase if phy-id compatible string is not present. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/4d0fd3f9f886c1d943776025e5efb5438b0eb389.1648631275.git.michal.simek@xilinx.com
2022-04-05net: zynq_gem: Use shared MDIO bus support for zynqmpMichal Simek1-9/+23
CONFIG_ETH_PHY enables support to utilize generic ethernet phy framework. Though if ethernet PHY node is in other ethernet node, it will use shared MDIO to access the PHY of other ethernet. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Link: https://lore.kernel.org/r/337b1a38ba36cde1951739af62fb3d2736d97f53.1648631275.git.michal.simek@xilinx.com
2022-04-05net: phy: Fix rgmii-id phy reset timeout issueT Karthik Reddy2-3/+3
While creating a phy device using phy_device_create(), we need to provide a valid phyaddr instead of 0 causing phy address being registered as 0 with mdio bus and shows mdio phy list as below ZynqMP> mdio list eth0: 0 - TI DP83867 <--> ethernet@ff0b0000 eth1: 0 - TI DP83867 <--> ethernet@ff0c0000 Also PHY soft reset is being requested on 0 instead of valid address causing "PHY reset timed out" error. So add phyaddr argument to phy_connect_phy_id() and to its prototype to create phy device with valid phyaddress. Fixes: a744a284e354 ("net: phy: Add support for ethernet-phy-id with gpio reset") Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Link: https://lore.kernel.org/r/fe35fddb9faa5af577ffdfabaec6879c935a30f8.1648562755.git.michal.simek@xilinx.com
2022-04-05clk: zynqmp: Add support for for DP audio/video clocksMichal Simek1-0/+7
Add support for getting rate for DP audio and video clocks. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/8792efe1fd9715f7c8a2e1e24f0454fb5b25d833.1648552434.git.michal.simek@xilinx.com
2022-04-05Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sunxiTom Rini12-355/+1085
A big part is the DM pinctrl driver, which allows us to get rid of quite some custom pinmux code and make the whole port much more robust. Many thanks to Samuel for that nice contribution! There are some more or less cosmetic warnings about missing clocks right now, I will send the trivial fixes for that later. Another big chunk is the mkimage upgrade, which adds RISC-V and TOC0 (secure images) support. Both features are unused at the moment, but I have an always-secure board that will use that once the DT lands in the kernel. On top of those big things we have some smaller fixes, improving the I2C DM support, fixing some H6/H616 early clock setup and improving the eMMC boot partition support. The gitlab CI completed successfully, including the build test for all 161 sunxi boards. I also boot tested on a A64, A20, H3, H6, and F1C100 board. USB, SD card, eMMC, and Ethernet all work there (where applicable).
2022-04-04ram: k3-am654: Make VTT regulator optionalChristian Gmeiner1-3/+2
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2022-04-04ram: k3-am654: Write all configuration valuesDominic Rath1-0/+10
Makes it possible to use 16-bit DDR memory. Signed-off-by: Dominic Rath <rath@ibv-augsburg.net> Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2022-04-04ram: k3-ddrss: Introduce ECC Functionality for full memory spaceDave Gerlach1-0/+133
Introduce ECC Functionality for full memory space as implemented in the DDRSS. The following is done to accomplish this: * Introduce a memory region "ss" to allow dt to provide DDRSS region, which is not the same as "ctl" which is the controller region. * Introduce a "ti,ecc-enable" flag which allows a memorycontroller instance to enable ecc. * Introduce functionality to properly program the DDRSS registers to enable ECC for the full DDR memory space if enabled with above flag. * Expose a k3_ddrss_ddr_fdt_fixup call to allow fixup of fdt blob to account from DDR memory that must be reserved for ECC operation. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2022-04-04ram: k3-ddrss: Rename ddrss_ss_regs to ddrss_ctl_regsDave Gerlach1-2/+3
The current address being read from dt actually represents the ddrss_ctl memory region, while ddrss_ss region is something else. Introduce ddrss_ctl_regs and use it to free up ddrss_ss_regs for its proper purpose later so that we can avoid confusion. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2022-04-04misc: k3_esm: Add functionality to set and route error events within K3SoCHari Nagalla1-3/+50
Add functionality to enable, set priority to the input events and to route to MCU ESM. On AM64x/AM62x devices, it is possible to route Main ESM0 error events to MCU ESM. When these error events are routed to MCU ESM high output, it can trigger the reset logic to reset the device, when CTRLMMR_MCU_RST_CTRL:MCU_ESM_ERROR_RESET_EN_Z is set to '0'. K3 based J7 devices (ex: J721e) also have ESM modules, and the changes to the driver does not impact those devices. Signed-off-by: Hari Nagalla <hnagalla@ti.com> Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2022-04-04i2c: sun8i_rsb: Add support for DM clocks and resetsSamuel Holland1-0/+12
Currently, clock/reset setup for this device is handled by a platform-specific function and is intermixed with non-DM pinctrl setup. Use the devicetree to get clocks/resets, which disentagles it from the pinctrl setup in preparation for moving to DM_PINCTRL. This also has the added benefit of picking the right clock/reset bits for H6 and new SoCs that have a rearranged PRCM MMIO space. Signed-off-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-04-04i2c: sun8i_rsb: Initialize chips in .child_pre_probeSamuel Holland1-1/+2
Chips attached to the RSB bus require an initialization command before they can be used. (Specifically, this command programs the chip's runtime address.) The driver does this in its .probe_chip hook, under the assumption that .probe_chip is called during child probe. This is not the case; .probe_chip is only called by dm_i2c_probe, which is intended for use by board-level code, not for chips with OF nodes. Since this initialization command must be run before a child chip can be used, do it before probing each child. Signed-off-by: Samuel Holland <samuel@sholland.org> Acked-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-04-04i2c: sun6i_p2wi: Add support for DM clocks and resetsSamuel Holland1-0/+12
Currently, clock/reset setup for this device is handled by a platform-specific function and is intermixed with non-DM pinctrl setup. Use the devicetree to get clocks/resets, which disentagles it from the pinctrl setup in preparation for moving to DM_PINCTRL. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-04-04i2c: sun6i_p2wi: Initialize chips in .child_pre_probeSamuel Holland1-1/+2
Chips attached to the P2WI bus require an initialization command before they can be used. (Specifically, this switches the chip from I2C mode to P2WI mode.) The driver does this in its .probe_chip hook, under the assumption that .probe_chip is called during child probe. This is not the case; .probe_chip is only called by dm_i2c_probe, which is intended for use by board-level code, not for chips with OF nodes. Since this initialization command must be run before a child chip can be used, do it before probing each child. Signed-off-by: Samuel Holland <samuel@sholland.org> Acked-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-04-04spi: sun4i_spi: Remove non-DM pin setupSamuel Holland1-84/+0
This is now handled automatically by the pinctrl driver. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-04-04pinctrl: sunxi: Add SPI0 pinmuxesSamuel Holland1-0/+15
Pin lists and mux values were taken from the Linux drivers. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-04-04pwm: sunxi: Remove non-DM pin setupSamuel Holland1-11/+0
This is now handled automatically by the pinctrl driver. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-04-04pinctrl: sunxi: Add the A64 PWM pinmuxSamuel Holland1-0/+1
This is the only possible mux setting for the A64's PWM peripheral. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-04-04pinctrl: sunxi: Add MMC pinmuxesSamuel Holland1-0/+54
Pin lists and mux values were taken from the Linux drivers. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-04-04i2c: sun8i_rsb: Only do non-DM pin setup for non-DM I2CSamuel Holland1-27/+19
When the DM_I2C driver is loaded, the pin setup is done automatically from the device tree by the pinctrl driver. Clean up the code in the process: remove #ifdefs and recognize that the pin configuration is the same for all sun8i/sun50i SoCs, not just those which select CONFIG_MACH_SUN8I. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-04-04i2c: sun6i_p2wi: Only do non-DM pin setup for non-DM I2CSamuel Holland1-6/+6
When the DM_I2C driver is loaded, the pin setup is done automatically from the device tree by the pinctrl driver. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-04-04pinctrl: sunxi: Add I2C pinmuxesSamuel Holland1-0/+37
Where multiple options were available, the one matching board.c and the device trees was chosen. Pin lists and mux values were taken from the Linux drivers. Signed-off-by: Samuel Holland <samuel@sholland.org> [Andre: fixup H5 I2C1 pinmux] Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-04-04net: sun8i_emac: Remove non-DM pin setupSamuel Holland1-90/+0
This is now handled automatically by the pinctrl driver. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-04-04pinctrl: sunxi: Add sun8i EMAC pinmuxesSamuel Holland1-0/+7
Pin lists and mux values were taken from the Linux drivers. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-04-04pinctrl: sunxi: Add sunxi GMAC pinmuxesSamuel Holland1-0/+3
Pin lists and mux values were taken from the Linux drivers. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
generated by cgit v1.1 at 2024-09-17 10:38:39 +0000